root / hw / sparc32_dma.c @ 338b922e
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1 | 67e999be | bellard | /*
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2 | 67e999be | bellard | * QEMU Sparc32 DMA controller emulation
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3 | 67e999be | bellard | *
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4 | 67e999be | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 67e999be | bellard | *
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6 | 6f57bbf4 | Artyom Tarasenko | * Modifications:
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7 | 6f57bbf4 | Artyom Tarasenko | * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
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8 | 6f57bbf4 | Artyom Tarasenko | *
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9 | 67e999be | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 67e999be | bellard | * of this software and associated documentation files (the "Software"), to deal
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11 | 67e999be | bellard | * in the Software without restriction, including without limitation the rights
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12 | 67e999be | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 67e999be | bellard | * copies of the Software, and to permit persons to whom the Software is
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14 | 67e999be | bellard | * furnished to do so, subject to the following conditions:
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15 | 67e999be | bellard | *
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16 | 67e999be | bellard | * The above copyright notice and this permission notice shall be included in
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17 | 67e999be | bellard | * all copies or substantial portions of the Software.
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18 | 67e999be | bellard | *
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19 | 67e999be | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 67e999be | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 67e999be | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 67e999be | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 67e999be | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 67e999be | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 67e999be | bellard | * THE SOFTWARE.
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26 | 67e999be | bellard | */
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27 | 6f6260c7 | Blue Swirl | |
28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
30 | 87ecb68b | pbrook | #include "sun4m.h" |
31 | 6f6260c7 | Blue Swirl | #include "sysbus.h" |
32 | 67e999be | bellard | |
33 | 67e999be | bellard | /* debug DMA */
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34 | 67e999be | bellard | //#define DEBUG_DMA
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35 | 67e999be | bellard | |
36 | 67e999be | bellard | /*
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37 | 67e999be | bellard | * This is the DMA controller part of chip STP2000 (Master I/O), also
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38 | 67e999be | bellard | * produced as NCR89C100. See
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39 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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40 | 67e999be | bellard | * and
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41 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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42 | 67e999be | bellard | */
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43 | 67e999be | bellard | |
44 | 67e999be | bellard | #ifdef DEBUG_DMA
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45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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46 | 001faf32 | Blue Swirl | do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0) |
47 | 67e999be | bellard | #else
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48 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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49 | 67e999be | bellard | #endif
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50 | 67e999be | bellard | |
51 | 5aca8c3b | blueswir1 | #define DMA_REGS 4 |
52 | 5aca8c3b | blueswir1 | #define DMA_SIZE (4 * sizeof(uint32_t)) |
53 | 09723aa1 | blueswir1 | /* We need the mask, because one instance of the device is not page
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54 | 09723aa1 | blueswir1 | aligned (ledma, start address 0x0010) */
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55 | 09723aa1 | blueswir1 | #define DMA_MASK (DMA_SIZE - 1) |
56 | 67e999be | bellard | |
57 | 67e999be | bellard | #define DMA_VER 0xa0000000 |
58 | 67e999be | bellard | #define DMA_INTR 1 |
59 | 67e999be | bellard | #define DMA_INTREN 0x10 |
60 | 67e999be | bellard | #define DMA_WRITE_MEM 0x100 |
61 | 73d74342 | Blue Swirl | #define DMA_EN 0x200 |
62 | 67e999be | bellard | #define DMA_LOADED 0x04000000 |
63 | 5aca8c3b | blueswir1 | #define DMA_DRAIN_FIFO 0x40 |
64 | 67e999be | bellard | #define DMA_RESET 0x80 |
65 | 67e999be | bellard | |
66 | 65899fe3 | Artyom Tarasenko | /* XXX SCSI and ethernet should have different read-only bit masks */
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67 | 65899fe3 | Artyom Tarasenko | #define DMA_CSR_RO_MASK 0xfe000007 |
68 | 65899fe3 | Artyom Tarasenko | |
69 | 67e999be | bellard | typedef struct DMAState DMAState; |
70 | 67e999be | bellard | |
71 | 67e999be | bellard | struct DMAState {
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72 | 6f6260c7 | Blue Swirl | SysBusDevice busdev; |
73 | 67e999be | bellard | uint32_t dmaregs[DMA_REGS]; |
74 | 5aca8c3b | blueswir1 | qemu_irq irq; |
75 | 2d069bab | blueswir1 | void *iommu;
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76 | 73d74342 | Blue Swirl | qemu_irq gpio[2];
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77 | 73d74342 | Blue Swirl | }; |
78 | 73d74342 | Blue Swirl | |
79 | 73d74342 | Blue Swirl | enum {
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80 | 73d74342 | Blue Swirl | GPIO_RESET = 0,
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81 | 73d74342 | Blue Swirl | GPIO_DMA, |
82 | 67e999be | bellard | }; |
83 | 67e999be | bellard | |
84 | 9b94dc32 | bellard | /* Note: on sparc, the lance 16 bit bus is swapped */
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85 | c227f099 | Anthony Liguori | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
86 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
87 | 67e999be | bellard | { |
88 | 67e999be | bellard | DMAState *s = opaque; |
89 | 9b94dc32 | bellard | int i;
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90 | 67e999be | bellard | |
91 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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92 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
93 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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94 | 9b94dc32 | bellard | if (do_bswap) {
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95 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
96 | 9b94dc32 | bellard | } else {
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97 | 9b94dc32 | bellard | addr &= ~1;
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98 | 9b94dc32 | bellard | len &= ~1;
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99 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
100 | 9b94dc32 | bellard | for(i = 0; i < len; i += 2) { |
101 | 9b94dc32 | bellard | bswap16s((uint16_t *)(buf + i)); |
102 | 9b94dc32 | bellard | } |
103 | 9b94dc32 | bellard | } |
104 | 67e999be | bellard | } |
105 | 67e999be | bellard | |
106 | c227f099 | Anthony Liguori | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
107 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
108 | 67e999be | bellard | { |
109 | 67e999be | bellard | DMAState *s = opaque; |
110 | 9b94dc32 | bellard | int l, i;
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111 | 9b94dc32 | bellard | uint16_t tmp_buf[32];
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112 | 67e999be | bellard | |
113 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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114 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
115 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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116 | 9b94dc32 | bellard | if (do_bswap) {
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117 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, buf, len); |
118 | 9b94dc32 | bellard | } else {
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119 | 9b94dc32 | bellard | addr &= ~1;
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120 | 9b94dc32 | bellard | len &= ~1;
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121 | 9b94dc32 | bellard | while (len > 0) { |
122 | 9b94dc32 | bellard | l = len; |
123 | 9b94dc32 | bellard | if (l > sizeof(tmp_buf)) |
124 | 9b94dc32 | bellard | l = sizeof(tmp_buf);
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125 | 9b94dc32 | bellard | for(i = 0; i < l; i += 2) { |
126 | 9b94dc32 | bellard | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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127 | 9b94dc32 | bellard | } |
128 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); |
129 | 9b94dc32 | bellard | len -= l; |
130 | 9b94dc32 | bellard | buf += l; |
131 | 9b94dc32 | bellard | addr += l; |
132 | 9b94dc32 | bellard | } |
133 | 9b94dc32 | bellard | } |
134 | 67e999be | bellard | } |
135 | 67e999be | bellard | |
136 | 70c0de96 | blueswir1 | static void dma_set_irq(void *opaque, int irq, int level) |
137 | 67e999be | bellard | { |
138 | 67e999be | bellard | DMAState *s = opaque; |
139 | 70c0de96 | blueswir1 | if (level) {
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140 | 70c0de96 | blueswir1 | s->dmaregs[0] |= DMA_INTR;
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141 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTREN) { |
142 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Raise IRQ\n");
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143 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_raise(s->irq); |
144 | 6f57bbf4 | Artyom Tarasenko | } |
145 | 70c0de96 | blueswir1 | } else {
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146 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTR) { |
147 | 6f57bbf4 | Artyom Tarasenko | s->dmaregs[0] &= ~DMA_INTR;
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148 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTREN) { |
149 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Lower IRQ\n");
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150 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_lower(s->irq); |
151 | 6f57bbf4 | Artyom Tarasenko | } |
152 | 6f57bbf4 | Artyom Tarasenko | } |
153 | 70c0de96 | blueswir1 | } |
154 | 67e999be | bellard | } |
155 | 67e999be | bellard | |
156 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
157 | 67e999be | bellard | { |
158 | 67e999be | bellard | DMAState *s = opaque; |
159 | 67e999be | bellard | |
160 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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161 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
162 | 67e999be | bellard | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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163 | 67e999be | bellard | s->dmaregs[1] += len;
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164 | 67e999be | bellard | } |
165 | 67e999be | bellard | |
166 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
167 | 67e999be | bellard | { |
168 | 67e999be | bellard | DMAState *s = opaque; |
169 | 67e999be | bellard | |
170 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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171 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
172 | 67e999be | bellard | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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173 | 67e999be | bellard | s->dmaregs[1] += len;
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174 | 67e999be | bellard | } |
175 | 67e999be | bellard | |
176 | c227f099 | Anthony Liguori | static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) |
177 | 67e999be | bellard | { |
178 | 67e999be | bellard | DMAState *s = opaque; |
179 | 67e999be | bellard | uint32_t saddr; |
180 | 67e999be | bellard | |
181 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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182 | 5aca8c3b | blueswir1 | DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr, |
183 | 5aca8c3b | blueswir1 | s->dmaregs[saddr]); |
184 | 67e999be | bellard | |
185 | 67e999be | bellard | return s->dmaregs[saddr];
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186 | 67e999be | bellard | } |
187 | 67e999be | bellard | |
188 | c227f099 | Anthony Liguori | static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
189 | 67e999be | bellard | { |
190 | 67e999be | bellard | DMAState *s = opaque; |
191 | 67e999be | bellard | uint32_t saddr; |
192 | 67e999be | bellard | |
193 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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194 | 5aca8c3b | blueswir1 | DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr, |
195 | 5aca8c3b | blueswir1 | s->dmaregs[saddr], val); |
196 | 67e999be | bellard | switch (saddr) {
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197 | 67e999be | bellard | case 0: |
198 | 6f57bbf4 | Artyom Tarasenko | if (val & DMA_INTREN) {
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199 | 65899fe3 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTR) { |
200 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Raise IRQ\n");
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201 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_raise(s->irq); |
202 | 6f57bbf4 | Artyom Tarasenko | } |
203 | 6f57bbf4 | Artyom Tarasenko | } else {
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204 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { |
205 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Lower IRQ\n");
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206 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_lower(s->irq); |
207 | 6f57bbf4 | Artyom Tarasenko | } |
208 | d537cf6c | pbrook | } |
209 | 67e999be | bellard | if (val & DMA_RESET) {
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210 | 73d74342 | Blue Swirl | qemu_irq_raise(s->gpio[GPIO_RESET]); |
211 | 73d74342 | Blue Swirl | qemu_irq_lower(s->gpio[GPIO_RESET]); |
212 | 5aca8c3b | blueswir1 | } else if (val & DMA_DRAIN_FIFO) { |
213 | 5aca8c3b | blueswir1 | val &= ~DMA_DRAIN_FIFO; |
214 | 67e999be | bellard | } else if (val == 0) |
215 | 5aca8c3b | blueswir1 | val = DMA_DRAIN_FIFO; |
216 | 73d74342 | Blue Swirl | |
217 | 73d74342 | Blue Swirl | if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) { |
218 | 73d74342 | Blue Swirl | DPRINTF("Raise DMA enable\n");
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219 | 73d74342 | Blue Swirl | qemu_irq_raise(s->gpio[GPIO_DMA]); |
220 | 73d74342 | Blue Swirl | } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) { |
221 | 73d74342 | Blue Swirl | DPRINTF("Lower DMA enable\n");
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222 | 73d74342 | Blue Swirl | qemu_irq_lower(s->gpio[GPIO_DMA]); |
223 | 73d74342 | Blue Swirl | } |
224 | 73d74342 | Blue Swirl | |
225 | 65899fe3 | Artyom Tarasenko | val &= ~DMA_CSR_RO_MASK; |
226 | 67e999be | bellard | val |= DMA_VER; |
227 | 65899fe3 | Artyom Tarasenko | s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; |
228 | 67e999be | bellard | break;
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229 | 67e999be | bellard | case 1: |
230 | 67e999be | bellard | s->dmaregs[0] |= DMA_LOADED;
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231 | 65899fe3 | Artyom Tarasenko | /* fall through */
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232 | 67e999be | bellard | default:
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233 | 65899fe3 | Artyom Tarasenko | s->dmaregs[saddr] = val; |
234 | 67e999be | bellard | break;
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235 | 67e999be | bellard | } |
236 | 67e999be | bellard | } |
237 | 67e999be | bellard | |
238 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const dma_mem_read[3] = { |
239 | 7c560456 | blueswir1 | NULL,
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240 | 7c560456 | blueswir1 | NULL,
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241 | 67e999be | bellard | dma_mem_readl, |
242 | 67e999be | bellard | }; |
243 | 67e999be | bellard | |
244 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const dma_mem_write[3] = { |
245 | 7c560456 | blueswir1 | NULL,
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246 | 7c560456 | blueswir1 | NULL,
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247 | 67e999be | bellard | dma_mem_writel, |
248 | 67e999be | bellard | }; |
249 | 67e999be | bellard | |
250 | 49ef6c90 | Blue Swirl | static void dma_reset(DeviceState *d) |
251 | 67e999be | bellard | { |
252 | 49ef6c90 | Blue Swirl | DMAState *s = container_of(d, DMAState, busdev.qdev); |
253 | 67e999be | bellard | |
254 | 5aca8c3b | blueswir1 | memset(s->dmaregs, 0, DMA_SIZE);
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255 | 67e999be | bellard | s->dmaregs[0] = DMA_VER;
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256 | 67e999be | bellard | } |
257 | 67e999be | bellard | |
258 | 75c497dc | Blue Swirl | static const VMStateDescription vmstate_dma = { |
259 | 75c497dc | Blue Swirl | .name ="sparc32_dma",
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260 | 75c497dc | Blue Swirl | .version_id = 2,
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261 | 75c497dc | Blue Swirl | .minimum_version_id = 2,
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262 | 75c497dc | Blue Swirl | .minimum_version_id_old = 2,
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263 | 75c497dc | Blue Swirl | .fields = (VMStateField []) { |
264 | 75c497dc | Blue Swirl | VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS), |
265 | 75c497dc | Blue Swirl | VMSTATE_END_OF_LIST() |
266 | 75c497dc | Blue Swirl | } |
267 | 75c497dc | Blue Swirl | }; |
268 | 67e999be | bellard | |
269 | 81a322d4 | Gerd Hoffmann | static int sparc32_dma_init1(SysBusDevice *dev) |
270 | 6f6260c7 | Blue Swirl | { |
271 | 6f6260c7 | Blue Swirl | DMAState *s = FROM_SYSBUS(DMAState, dev); |
272 | 6f6260c7 | Blue Swirl | int dma_io_memory;
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273 | 67e999be | bellard | |
274 | 6f6260c7 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
275 | 67e999be | bellard | |
276 | 1eed09cb | Avi Kivity | dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); |
277 | 6f6260c7 | Blue Swirl | sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); |
278 | 67e999be | bellard | |
279 | 6f6260c7 | Blue Swirl | qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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280 | 73d74342 | Blue Swirl | qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
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281 | 49ef6c90 | Blue Swirl | |
282 | 81a322d4 | Gerd Hoffmann | return 0; |
283 | 6f6260c7 | Blue Swirl | } |
284 | 67e999be | bellard | |
285 | 6f6260c7 | Blue Swirl | static SysBusDeviceInfo sparc32_dma_info = {
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286 | 6f6260c7 | Blue Swirl | .init = sparc32_dma_init1, |
287 | 6f6260c7 | Blue Swirl | .qdev.name = "sparc32_dma",
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288 | 6f6260c7 | Blue Swirl | .qdev.size = sizeof(DMAState),
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289 | 49ef6c90 | Blue Swirl | .qdev.vmsd = &vmstate_dma, |
290 | 49ef6c90 | Blue Swirl | .qdev.reset = dma_reset, |
291 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
292 | 3180d772 | Gerd Hoffmann | DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
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293 | 3180d772 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
294 | 6f6260c7 | Blue Swirl | } |
295 | 6f6260c7 | Blue Swirl | }; |
296 | 6f6260c7 | Blue Swirl | |
297 | 6f6260c7 | Blue Swirl | static void sparc32_dma_register_devices(void) |
298 | 6f6260c7 | Blue Swirl | { |
299 | 6f6260c7 | Blue Swirl | sysbus_register_withprop(&sparc32_dma_info); |
300 | 67e999be | bellard | } |
301 | 6f6260c7 | Blue Swirl | |
302 | 6f6260c7 | Blue Swirl | device_init(sparc32_dma_register_devices) |