root / hw / realview_gic.c @ 33f00271
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/*
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* ARM RealView Emulation Baseboard Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "primecell.h" |
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#define GIC_NIRQ 96 |
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#define NCPU 1 |
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/* Only a single "CPU" interface is present. */
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static inline int |
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gic_get_current_cpu(void)
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{ |
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return 0; |
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} |
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#include "arm_gic.c" |
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static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) |
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{ |
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gic_state *s = (gic_state *)opaque; |
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offset -= s->base; |
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return gic_cpu_read(s, gic_get_current_cpu(), offset);
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} |
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static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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gic_state *s = (gic_state *)opaque; |
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offset -= s->base; |
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gic_cpu_write(s, gic_get_current_cpu(), offset, value); |
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} |
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static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
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realview_gic_cpu_read, |
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realview_gic_cpu_read, |
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realview_gic_cpu_read |
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}; |
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static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
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realview_gic_cpu_write, |
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realview_gic_cpu_write, |
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realview_gic_cpu_write |
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}; |
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qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq) |
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{ |
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gic_state *s; |
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int iomemtype;
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s = gic_init(base, &parent_irq); |
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if (!s)
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return NULL; |
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iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
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realview_gic_cpu_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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return s->in;
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} |