root / target-mips / machine.c @ 344b983d
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1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
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2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 8dd3dca3 | aurel32 | |
4 | 33a84765 | ths | #include "exec-all.h" |
5 | 33a84765 | ths | |
6 | 33a84765 | ths | static void save_tc(QEMUFile *f, TCState *tc) |
7 | 33a84765 | ths | { |
8 | 33a84765 | ths | int i;
|
9 | 33a84765 | ths | |
10 | 33a84765 | ths | /* Save active TC */
|
11 | 33a84765 | ths | for(i = 0; i < 32; i++) |
12 | 33a84765 | ths | qemu_put_betls(f, &tc->gpr[i]); |
13 | 33a84765 | ths | qemu_put_betls(f, &tc->PC); |
14 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
15 | 33a84765 | ths | qemu_put_betls(f, &tc->HI[i]); |
16 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
17 | 33a84765 | ths | qemu_put_betls(f, &tc->LO[i]); |
18 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
19 | 33a84765 | ths | qemu_put_betls(f, &tc->ACX[i]); |
20 | 33a84765 | ths | qemu_put_betls(f, &tc->DSPControl); |
21 | 33a84765 | ths | qemu_put_sbe32s(f, &tc->CP0_TCStatus); |
22 | 33a84765 | ths | qemu_put_sbe32s(f, &tc->CP0_TCBind); |
23 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCHalt); |
24 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCContext); |
25 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCSchedule); |
26 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCScheFBack); |
27 | 33a84765 | ths | qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); |
28 | 33a84765 | ths | } |
29 | 33a84765 | ths | |
30 | 33a84765 | ths | static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) |
31 | 33a84765 | ths | { |
32 | 33a84765 | ths | int i;
|
33 | 33a84765 | ths | |
34 | 33a84765 | ths | for(i = 0; i < 32; i++) |
35 | 33a84765 | ths | qemu_put_be64s(f, &fpu->fpr[i].d); |
36 | 33a84765 | ths | qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); |
37 | 33a84765 | ths | qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); |
38 | 33a84765 | ths | qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); |
39 | 33a84765 | ths | qemu_put_be32s(f, &fpu->fcr0); |
40 | 33a84765 | ths | qemu_put_be32s(f, &fpu->fcr31); |
41 | 33a84765 | ths | } |
42 | 33a84765 | ths | |
43 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
44 | 8dd3dca3 | aurel32 | { |
45 | 33a84765 | ths | CPUState *env = opaque; |
46 | 33a84765 | ths | int i;
|
47 | 33a84765 | ths | |
48 | 33a84765 | ths | /* Save active TC */
|
49 | 33a84765 | ths | save_tc(f, &env->active_tc); |
50 | 33a84765 | ths | |
51 | 33a84765 | ths | /* Save active FPU */
|
52 | 33a84765 | ths | save_fpu(f, &env->active_fpu); |
53 | 33a84765 | ths | |
54 | 33a84765 | ths | /* Save MVP */
|
55 | 33a84765 | ths | qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); |
56 | 33a84765 | ths | qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); |
57 | 33a84765 | ths | qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); |
58 | 33a84765 | ths | |
59 | 33a84765 | ths | /* Save TLB */
|
60 | 33a84765 | ths | qemu_put_be32s(f, &env->tlb->nb_tlb); |
61 | 33a84765 | ths | qemu_put_be32s(f, &env->tlb->tlb_in_use); |
62 | 33a84765 | ths | for(i = 0; i < MIPS_TLB_MAX; i++) { |
63 | 33a84765 | ths | uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
|
64 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
|
65 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
|
66 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
|
67 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
|
68 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
|
69 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].D1 << 0));
|
70 | 95bed643 | Blue Swirl | uint8_t asid; |
71 | 33a84765 | ths | |
72 | 33a84765 | ths | qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); |
73 | 33a84765 | ths | qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); |
74 | 95bed643 | Blue Swirl | asid = env->tlb->mmu.r4k.tlb[i].ASID; |
75 | 95bed643 | Blue Swirl | qemu_put_8s(f, &asid); |
76 | 33a84765 | ths | qemu_put_be16s(f, &flags); |
77 | 33a84765 | ths | qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
|
78 | 33a84765 | ths | qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
|
79 | 33a84765 | ths | } |
80 | 33a84765 | ths | |
81 | 33a84765 | ths | /* Save CPU metastate */
|
82 | 33a84765 | ths | qemu_put_be32s(f, &env->current_tc); |
83 | 33a84765 | ths | qemu_put_be32s(f, &env->current_fpu); |
84 | 33a84765 | ths | qemu_put_sbe32s(f, &env->error_code); |
85 | 33a84765 | ths | qemu_put_be32s(f, &env->hflags); |
86 | 33a84765 | ths | qemu_put_betls(f, &env->btarget); |
87 | 1ba74fb8 | aurel32 | i = env->bcond; |
88 | 1ba74fb8 | aurel32 | qemu_put_sbe32s(f, &i); |
89 | 33a84765 | ths | |
90 | 33a84765 | ths | /* Save remaining CP1 registers */
|
91 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Index); |
92 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Random); |
93 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEControl); |
94 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEConf0); |
95 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEConf1); |
96 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_YQMask); |
97 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_VPESchedule); |
98 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_VPEScheFBack); |
99 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEOpt); |
100 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EntryLo0); |
101 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EntryLo1); |
102 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_Context); |
103 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_PageMask); |
104 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_PageGrain); |
105 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Wired); |
106 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf0); |
107 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf1); |
108 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf2); |
109 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf3); |
110 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf4); |
111 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_HWREna); |
112 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_BadVAddr); |
113 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Count); |
114 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EntryHi); |
115 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Compare); |
116 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Status); |
117 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_IntCtl); |
118 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSCtl); |
119 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSMap); |
120 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Cause); |
121 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EPC); |
122 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_PRid); |
123 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_EBase); |
124 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config0); |
125 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config1); |
126 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config2); |
127 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config3); |
128 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config6); |
129 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config7); |
130 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_LLAddr); |
131 | 33a84765 | ths | for(i = 0; i < 8; i++) |
132 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_WatchLo[i]); |
133 | 33a84765 | ths | for(i = 0; i < 8; i++) |
134 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); |
135 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_XContext); |
136 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Framemask); |
137 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Debug); |
138 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_DEPC); |
139 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Performance0); |
140 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_TagLo); |
141 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_DataLo); |
142 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_TagHi); |
143 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_DataHi); |
144 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_ErrorEPC); |
145 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_DESAVE); |
146 | 33a84765 | ths | |
147 | 33a84765 | ths | /* Save inactive TC state */
|
148 | 33a84765 | ths | for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) |
149 | 33a84765 | ths | save_tc(f, &env->tcs[i]); |
150 | 33a84765 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |
151 | 33a84765 | ths | save_fpu(f, &env->fpus[i]); |
152 | 33a84765 | ths | } |
153 | 33a84765 | ths | |
154 | 33a84765 | ths | static void load_tc(QEMUFile *f, TCState *tc) |
155 | 33a84765 | ths | { |
156 | 33a84765 | ths | int i;
|
157 | 33a84765 | ths | |
158 | 33a84765 | ths | /* Save active TC */
|
159 | 33a84765 | ths | for(i = 0; i < 32; i++) |
160 | 33a84765 | ths | qemu_get_betls(f, &tc->gpr[i]); |
161 | 33a84765 | ths | qemu_get_betls(f, &tc->PC); |
162 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
163 | 33a84765 | ths | qemu_get_betls(f, &tc->HI[i]); |
164 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
165 | 33a84765 | ths | qemu_get_betls(f, &tc->LO[i]); |
166 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
167 | 33a84765 | ths | qemu_get_betls(f, &tc->ACX[i]); |
168 | 33a84765 | ths | qemu_get_betls(f, &tc->DSPControl); |
169 | 33a84765 | ths | qemu_get_sbe32s(f, &tc->CP0_TCStatus); |
170 | 33a84765 | ths | qemu_get_sbe32s(f, &tc->CP0_TCBind); |
171 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCHalt); |
172 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCContext); |
173 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCSchedule); |
174 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCScheFBack); |
175 | 33a84765 | ths | qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); |
176 | 33a84765 | ths | } |
177 | 33a84765 | ths | |
178 | 33a84765 | ths | static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) |
179 | 33a84765 | ths | { |
180 | 33a84765 | ths | int i;
|
181 | 33a84765 | ths | |
182 | 33a84765 | ths | for(i = 0; i < 32; i++) |
183 | 33a84765 | ths | qemu_get_be64s(f, &fpu->fpr[i].d); |
184 | 33a84765 | ths | qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); |
185 | 33a84765 | ths | qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); |
186 | 33a84765 | ths | qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); |
187 | 33a84765 | ths | qemu_get_be32s(f, &fpu->fcr0); |
188 | 33a84765 | ths | qemu_get_be32s(f, &fpu->fcr31); |
189 | 8dd3dca3 | aurel32 | } |
190 | 8dd3dca3 | aurel32 | |
191 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
192 | 8dd3dca3 | aurel32 | { |
193 | 33a84765 | ths | CPUState *env = opaque; |
194 | 33a84765 | ths | int i;
|
195 | 33a84765 | ths | |
196 | 33a84765 | ths | if (version_id != 3) |
197 | 33a84765 | ths | return -EINVAL;
|
198 | 33a84765 | ths | |
199 | 33a84765 | ths | /* Load active TC */
|
200 | 33a84765 | ths | load_tc(f, &env->active_tc); |
201 | 33a84765 | ths | |
202 | 33a84765 | ths | /* Load active FPU */
|
203 | 33a84765 | ths | load_fpu(f, &env->active_fpu); |
204 | 33a84765 | ths | |
205 | 33a84765 | ths | /* Load MVP */
|
206 | 33a84765 | ths | qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); |
207 | 33a84765 | ths | qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); |
208 | 33a84765 | ths | qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); |
209 | 33a84765 | ths | |
210 | 33a84765 | ths | /* Load TLB */
|
211 | 33a84765 | ths | qemu_get_be32s(f, &env->tlb->nb_tlb); |
212 | 33a84765 | ths | qemu_get_be32s(f, &env->tlb->tlb_in_use); |
213 | 33a84765 | ths | for(i = 0; i < MIPS_TLB_MAX; i++) { |
214 | 33a84765 | ths | uint16_t flags; |
215 | 95bed643 | Blue Swirl | uint8_t asid; |
216 | 33a84765 | ths | |
217 | 33a84765 | ths | qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); |
218 | 33a84765 | ths | qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); |
219 | 95bed643 | Blue Swirl | qemu_get_8s(f, &asid); |
220 | 95bed643 | Blue Swirl | env->tlb->mmu.r4k.tlb[i].ASID = asid; |
221 | 33a84765 | ths | qemu_get_be16s(f, &flags); |
222 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; |
223 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; |
224 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; |
225 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; |
226 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; |
227 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; |
228 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; |
229 | 33a84765 | ths | qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
|
230 | 33a84765 | ths | qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
|
231 | 33a84765 | ths | } |
232 | 33a84765 | ths | |
233 | 33a84765 | ths | /* Load CPU metastate */
|
234 | 33a84765 | ths | qemu_get_be32s(f, &env->current_tc); |
235 | 33a84765 | ths | qemu_get_be32s(f, &env->current_fpu); |
236 | 33a84765 | ths | qemu_get_sbe32s(f, &env->error_code); |
237 | 33a84765 | ths | qemu_get_be32s(f, &env->hflags); |
238 | 33a84765 | ths | qemu_get_betls(f, &env->btarget); |
239 | 1ba74fb8 | aurel32 | qemu_get_sbe32s(f, &i); |
240 | 1ba74fb8 | aurel32 | env->bcond = i; |
241 | 33a84765 | ths | |
242 | 33a84765 | ths | /* Load remaining CP1 registers */
|
243 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Index); |
244 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Random); |
245 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEControl); |
246 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEConf0); |
247 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEConf1); |
248 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_YQMask); |
249 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_VPESchedule); |
250 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_VPEScheFBack); |
251 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEOpt); |
252 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EntryLo0); |
253 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EntryLo1); |
254 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_Context); |
255 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_PageMask); |
256 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_PageGrain); |
257 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Wired); |
258 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf0); |
259 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf1); |
260 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf2); |
261 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf3); |
262 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf4); |
263 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_HWREna); |
264 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_BadVAddr); |
265 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Count); |
266 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EntryHi); |
267 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Compare); |
268 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Status); |
269 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_IntCtl); |
270 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSCtl); |
271 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSMap); |
272 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Cause); |
273 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EPC); |
274 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_PRid); |
275 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_EBase); |
276 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config0); |
277 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config1); |
278 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config2); |
279 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config3); |
280 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config6); |
281 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config7); |
282 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_LLAddr); |
283 | 33a84765 | ths | for(i = 0; i < 8; i++) |
284 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_WatchLo[i]); |
285 | 33a84765 | ths | for(i = 0; i < 8; i++) |
286 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); |
287 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_XContext); |
288 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Framemask); |
289 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Debug); |
290 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_DEPC); |
291 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Performance0); |
292 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_TagLo); |
293 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_DataLo); |
294 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_TagHi); |
295 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_DataHi); |
296 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_ErrorEPC); |
297 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_DESAVE); |
298 | 33a84765 | ths | |
299 | 33a84765 | ths | /* Load inactive TC state */
|
300 | 33a84765 | ths | for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) |
301 | 33a84765 | ths | load_tc(f, &env->tcs[i]); |
302 | 33a84765 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |
303 | 33a84765 | ths | load_fpu(f, &env->fpus[i]); |
304 | 33a84765 | ths | |
305 | 33a84765 | ths | /* XXX: ensure compatiblity for halted bit ? */
|
306 | 33a84765 | ths | tlb_flush(env, 1);
|
307 | 8dd3dca3 | aurel32 | return 0; |
308 | 8dd3dca3 | aurel32 | } |