Revision 3475187d target-sparc/helper.c
| b/target-sparc/helper.c | ||
|---|---|---|
| 43 | 43 |
int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
| 44 | 44 |
int is_user, int is_softmmu) |
| 45 | 45 |
{
|
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env->mmuregs[4] = address; |
|
| 47 | 46 |
if (rw & 2) |
| 48 | 47 |
env->exception_index = TT_TFAULT; |
| 49 | 48 |
else |
| ... | ... | |
| 102 | 101 |
env = saved_env; |
| 103 | 102 |
} |
| 104 | 103 |
|
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#ifndef TARGET_SPARC64 |
|
| 105 | 105 |
static const int access_table[8][8] = {
|
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
|
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
|
| ... | ... | |
| 268 | 268 |
return 1; |
| 269 | 269 |
} |
| 270 | 270 |
} |
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#else |
|
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static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
|
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int *access_index, target_ulong address, int rw, |
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int is_user) |
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{
|
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target_ulong mask; |
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unsigned int i; |
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|
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if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
|
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*physical = address & 0xffffffff; |
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*prot = PAGE_READ | PAGE_WRITE; |
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return 0; |
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} |
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|
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for (i = 0; i < 64; i++) {
|
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
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switch (env->dtlb_tte[i] >> 60) {
|
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default: |
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case 0x4: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x5: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x6: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x7: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
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// ctx match, vaddr match? |
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if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
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(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
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// access ok? |
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if (((env->dtlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) || |
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
|
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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*physical = env->dtlb_tte[i] & 0xffffe000; |
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*prot = PAGE_READ; |
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if (env->dtlb_tte[i] & 0x2) |
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*prot |= PAGE_WRITE; |
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return 0; |
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} |
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} |
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} |
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
|
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int *access_index, target_ulong address, int rw, |
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int is_user) |
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{
|
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target_ulong mask; |
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unsigned int i; |
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|
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if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
|
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*physical = address & 0xffffffff; |
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*prot = PAGE_READ; |
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return 0; |
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} |
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for (i = 0; i < 64; i++) {
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
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switch (env->itlb_tte[i] >> 60) {
|
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default: |
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case 0x4: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x5: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x6: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x7: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
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// ctx match, vaddr match? |
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if (env->immuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
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(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
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// access ok? |
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if ((env->itlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) {
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env->exception_index = TT_TFAULT; |
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return 1; |
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} |
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*physical = env->itlb_tte[i] & 0xffffe000; |
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*prot = PAGE_READ; |
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return 0; |
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} |
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} |
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} |
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env->exception_index = TT_TFAULT; |
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return 1; |
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} |
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|
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int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int is_user) |
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{
|
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if (rw == 2) |
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return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user); |
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else |
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return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user); |
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} |
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|
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/* Perform address translation */ |
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
|
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int is_user, int is_softmmu) |
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{
|
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target_ulong virt_addr; |
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target_phys_addr_t paddr; |
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unsigned long vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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|
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
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if (error_code == 0) {
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virt_addr = address & TARGET_PAGE_MASK; |
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vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); |
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
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return ret; |
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} |
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// XXX |
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return 1; |
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} |
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|
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#endif |
|
| 271 | 401 |
#endif |
| 272 | 402 |
|
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void memcpy32(target_ulong *dst, const target_ulong *src) |
| ... | ... | |
| 292 | 422 |
if (new_cwp == (NWINDOWS - 1)) |
| 293 | 423 |
memcpy32(env->regbase + NWINDOWS * 16, env->regbase); |
| 294 | 424 |
env->regwptr = env->regbase + (new_cwp * 16); |
| 425 |
REGWPTR = env->regwptr; |
|
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} |
| 296 | 427 |
|
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void cpu_set_cwp(CPUState *env1, int new_cwp) |
| 298 | 429 |
{
|
| 299 | 430 |
CPUState *saved_env; |
| 431 |
#ifdef reg_REGWPTR |
|
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target_ulong *saved_regwptr; |
|
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#endif |
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|
|
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saved_env = env; |
| 436 |
#ifdef reg_REGWPTR |
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saved_regwptr = REGWPTR; |
|
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#endif |
|
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env = env1; |
| 302 | 440 |
set_cwp(new_cwp); |
| 303 | 441 |
env = saved_env; |
| 442 |
#ifdef reg_REGWPTR |
|
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REGWPTR = saved_regwptr; |
|
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#endif |
|
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} |
| 305 | 446 |
|
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#ifdef TARGET_SPARC64 |
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void do_interrupt(int intno) |
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{
|
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#ifdef DEBUG_PCALL |
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if (loglevel & CPU_LOG_INT) {
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static int count; |
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fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n", |
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count, intno, |
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env->pc, |
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env->npc, env->regwptr[6]); |
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cpu_dump_state(env, logfile, fprintf, 0); |
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#if 0 |
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{
|
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int i; |
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uint8_t *ptr; |
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|
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fprintf(logfile, " code="); |
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ptr = (uint8_t *)env->pc; |
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for(i = 0; i < 16; i++) {
|
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fprintf(logfile, " %02x", ldub(ptr + i)); |
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} |
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fprintf(logfile, "\n"); |
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} |
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#endif |
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count++; |
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} |
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#endif |
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#if !defined(CONFIG_USER_ONLY) |
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if (env->pstate & PS_IE) {
|
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cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index); |
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return; |
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} |
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#endif |
|
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env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
|
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((env->pstate & 0xfff) << 8) | (env->cwp & 0xff); |
|
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env->tpc[env->tl] = env->pc; |
|
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env->tnpc[env->tl] = env->npc; |
|
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env->tt[env->tl] = intno; |
|
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env->tbr = env->tbr | (env->tl > 1) ? 1 << 14 : 0 | (intno << 4); |
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env->tl++; |
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env->pc = env->tbr; |
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env->npc = env->pc + 4; |
|
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env->exception_index = 0; |
|
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} |
|
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#else |
|
| 306 | 492 |
void do_interrupt(int intno) |
| 307 | 493 |
{
|
| 308 | 494 |
int cwp; |
| ... | ... | |
| 448 | 634 |
printf("MMU dump ends\n");
|
| 449 | 635 |
} |
| 450 | 636 |
#endif |
| 637 |
#endif |
|
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