Revision 352367e8

b/target-openrisc/translate.c
904 904
    case 0x27:    /* l.addi */
905 905
        LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
906 906
        {
907
            int lab = gen_new_label();
908
            TCGv_i64 ta = tcg_temp_new_i64();
909
            TCGv_i64 td = tcg_temp_local_new_i64();
910
            TCGv_i32 res = tcg_temp_local_new_i32();
911
            TCGv_i32 sr_ove = tcg_temp_local_new_i32();
912
            tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
913
            tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
914
            tcg_gen_trunc_i64_i32(res, td);
915
            tcg_gen_shri_i64(td, td, 32);
916
            tcg_gen_andi_i64(td, td, 0x3);
917
            /* Jump to lab when no overflow.  */
918
            tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
919
            tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
920
            tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
921
            tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
922
            tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
923
            gen_exception(dc, EXCP_RANGE);
924
            gen_set_label(lab);
925
            tcg_gen_mov_i32(cpu_R[rd], res);
926
            tcg_temp_free_i64(ta);
927
            tcg_temp_free_i64(td);
928
            tcg_temp_free_i32(res);
929
            tcg_temp_free_i32(sr_ove);
907
            if (I16 == 0) {
908
                tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
909
            } else {
910
                int lab = gen_new_label();
911
                TCGv_i64 ta = tcg_temp_new_i64();
912
                TCGv_i64 td = tcg_temp_local_new_i64();
913
                TCGv_i32 res = tcg_temp_local_new_i32();
914
                TCGv_i32 sr_ove = tcg_temp_local_new_i32();
915
                tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
916
                tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
917
                tcg_gen_trunc_i64_i32(res, td);
918
                tcg_gen_shri_i64(td, td, 32);
919
                tcg_gen_andi_i64(td, td, 0x3);
920
                /* Jump to lab when no overflow.  */
921
                tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
922
                tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
923
                tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
924
                tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
925
                tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
926
                gen_exception(dc, EXCP_RANGE);
927
                gen_set_label(lab);
928
                tcg_gen_mov_i32(cpu_R[rd], res);
929
                tcg_temp_free_i64(ta);
930
                tcg_temp_free_i64(td);
931
                tcg_temp_free_i32(res);
932
                tcg_temp_free_i32(sr_ove);
933
            }
930 934
        }
931 935
        break;
932 936

  

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