root / target-i386 / machine.c @ 3523e4bd
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#include "hw/hw.h" |
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#include "hw/boards.h" |
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#include "hw/i386/pc.h" |
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#include "hw/isa/isa.h" |
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|
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#include "cpu.h" |
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#include "sysemu/kvm.h" |
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|
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static const VMStateDescription vmstate_segment = { |
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.name = "segment",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
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VMSTATE_UINT32(selector, SegmentCache), |
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VMSTATE_UINTTL(base, SegmentCache), |
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VMSTATE_UINT32(limit, SegmentCache), |
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VMSTATE_UINT32(flags, SegmentCache), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_SEGMENT(_field, _state) { \
|
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.name = (stringify(_field)), \ |
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.size = sizeof(SegmentCache), \
|
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.vmsd = &vmstate_segment, \ |
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.flags = VMS_STRUCT, \ |
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.offset = offsetof(_state, _field) \ |
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+ type_check(SegmentCache,typeof_field(_state, _field)) \ |
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} |
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|
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#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
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|
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static const VMStateDescription vmstate_xmm_reg = { |
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.name = "xmm_reg",
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
|
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
|
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_XMM_REGS(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
|
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|
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/* YMMH format is the same as XMM */
|
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static const VMStateDescription vmstate_ymmh_reg = { |
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.name = "ymmh_reg",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
|
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg) |
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|
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static const VMStateDescription vmstate_mtrr_var = { |
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.name = "mtrr_var",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
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VMSTATE_UINT64(base, MTRRVar), |
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VMSTATE_UINT64(mask, MTRRVar), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) |
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|
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static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size) |
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{ |
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fprintf(stderr, "call put_fpreg() with invalid arguments\n");
|
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exit(0);
|
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} |
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|
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/* XXX: add that in a FPU generic layer */
|
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union x86_longdouble {
|
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uint64_t mant; |
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uint16_t exp; |
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}; |
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|
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#define MANTD1(fp) (fp & ((1LL << 52) - 1)) |
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#define EXPBIAS1 1023 |
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#define EXPD1(fp) ((fp >> 52) & 0x7FF) |
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#define SIGND1(fp) ((fp >> 32) & 0x80000000) |
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|
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static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp) |
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{ |
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int e;
|
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/* mantissa */
|
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p->mant = (MANTD1(temp) << 11) | (1LL << 63); |
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/* exponent + sign */
|
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e = EXPD1(temp) - EXPBIAS1 + 16383;
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e |= SIGND1(temp) >> 16;
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p->exp = e; |
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} |
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|
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static int get_fpreg(QEMUFile *f, void *opaque, size_t size) |
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{ |
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FPReg *fp_reg = opaque; |
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uint64_t mant; |
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uint16_t exp; |
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|
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qemu_get_be64s(f, &mant); |
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qemu_get_be16s(f, &exp); |
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fp_reg->d = cpu_set_fp80(mant, exp); |
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return 0; |
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} |
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|
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static void put_fpreg(QEMUFile *f, void *opaque, size_t size) |
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{ |
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FPReg *fp_reg = opaque; |
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uint64_t mant; |
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uint16_t exp; |
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/* we save the real CPU data (in case of MMX usage only 'mant'
|
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contains the MMX register */
|
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cpu_get_fp80(&mant, &exp, fp_reg->d); |
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qemu_put_be64s(f, &mant); |
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qemu_put_be16s(f, &exp); |
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} |
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|
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static const VMStateInfo vmstate_fpreg = { |
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.name = "fpreg",
|
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.get = get_fpreg, |
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.put = put_fpreg, |
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}; |
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|
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static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size) |
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{ |
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union x86_longdouble *p = opaque;
|
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uint64_t mant; |
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|
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qemu_get_be64s(f, &mant); |
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p->mant = mant; |
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p->exp = 0xffff;
|
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return 0; |
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} |
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|
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static const VMStateInfo vmstate_fpreg_1_mmx = { |
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.name = "fpreg_1_mmx",
|
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.get = get_fpreg_1_mmx, |
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.put = put_fpreg_error, |
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}; |
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|
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static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size) |
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{ |
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union x86_longdouble *p = opaque;
|
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uint64_t mant; |
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|
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qemu_get_be64s(f, &mant); |
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fp64_to_fp80(p, mant); |
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return 0; |
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} |
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|
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static const VMStateInfo vmstate_fpreg_1_no_mmx = { |
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.name = "fpreg_1_no_mmx",
|
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.get = get_fpreg_1_no_mmx, |
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.put = put_fpreg_error, |
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}; |
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|
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static bool fpregs_is_0(void *opaque, int version_id) |
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{ |
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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|
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return (env->fpregs_format_vmstate == 0); |
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} |
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|
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static bool fpregs_is_1_mmx(void *opaque, int version_id) |
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{ |
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int guess_mmx;
|
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|
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guess_mmx = ((env->fptag_vmstate == 0xff) &&
|
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(env->fpus_vmstate & 0x3800) == 0); |
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return (guess_mmx && (env->fpregs_format_vmstate == 1)); |
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} |
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|
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static bool fpregs_is_1_no_mmx(void *opaque, int version_id) |
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{ |
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int guess_mmx;
|
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|
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guess_mmx = ((env->fptag_vmstate == 0xff) &&
|
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(env->fpus_vmstate & 0x3800) == 0); |
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return (!guess_mmx && (env->fpregs_format_vmstate == 1)); |
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} |
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|
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#define VMSTATE_FP_REGS(_field, _state, _n) \
|
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \ |
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \ |
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg) |
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|
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static bool version_is_5(void *opaque, int version_id) |
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{ |
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return version_id == 5; |
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} |
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|
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#ifdef TARGET_X86_64
|
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static bool less_than_7(void *opaque, int version_id) |
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{ |
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return version_id < 7; |
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} |
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|
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static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) |
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{ |
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uint64_t *v = pv; |
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*v = qemu_get_be32(f); |
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return 0; |
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} |
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|
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static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) |
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{ |
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uint64_t *v = pv; |
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qemu_put_be32(f, *v); |
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} |
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|
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static const VMStateInfo vmstate_hack_uint64_as_uint32 = { |
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.name = "uint64_as_uint32",
|
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.get = get_uint64_as_uint32, |
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.put = put_uint64_as_uint32, |
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}; |
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|
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#define VMSTATE_HACK_UINT32(_f, _s, _t) \
|
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VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
|
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#endif
|
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|
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static void cpu_pre_save(void *opaque) |
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{ |
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int i;
|
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|
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/* FPU */
|
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env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
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env->fptag_vmstate = 0;
|
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for(i = 0; i < 8; i++) { |
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env->fptag_vmstate |= ((!env->fptags[i]) << i); |
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} |
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|
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env->fpregs_format_vmstate = 0;
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|
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/*
|
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* Real mode guest segments register DPL should be zero.
|
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* Older KVM version were setting it wrongly.
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* Fixing it will allow live migration to host with unrestricted guest
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* support (otherwise the migration will fail with invalid guest state
|
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* error).
|
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*/
|
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if (!(env->cr[0] & CR0_PE_MASK) && |
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(env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { |
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env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); |
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env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); |
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env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); |
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env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); |
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env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); |
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env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); |
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} |
272 |
|
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} |
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|
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static int cpu_post_load(void *opaque, int version_id) |
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{ |
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int i;
|
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|
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/*
|
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* Real mode guest segments register DPL should be zero.
|
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* Older KVM version were setting it wrongly.
|
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* Fixing it will allow live migration from such host that don't have
|
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* restricted guest support to a host with unrestricted guest support
|
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* (otherwise the migration will fail with invalid guest state
|
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* error).
|
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*/
|
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if (!(env->cr[0] & CR0_PE_MASK) && |
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(env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { |
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env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); |
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env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); |
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env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); |
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env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); |
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env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); |
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env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); |
297 |
} |
298 |
|
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/* XXX: restore FPU round state */
|
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env->fpstt = (env->fpus_vmstate >> 11) & 7; |
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env->fpus = env->fpus_vmstate & ~0x3800;
|
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env->fptag_vmstate ^= 0xff;
|
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for(i = 0; i < 8; i++) { |
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env->fptags[i] = (env->fptag_vmstate >> i) & 1;
|
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} |
306 |
|
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cpu_breakpoint_remove_all(env, BP_CPU); |
308 |
cpu_watchpoint_remove_all(env, BP_CPU); |
309 |
for (i = 0; i < DR7_MAX_BP; i++) { |
310 |
hw_breakpoint_insert(env, i); |
311 |
} |
312 |
tlb_flush(env, 1);
|
313 |
|
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return 0; |
315 |
} |
316 |
|
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static bool async_pf_msr_needed(void *opaque) |
318 |
{ |
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X86CPU *cpu = opaque; |
320 |
|
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return cpu->env.async_pf_en_msr != 0; |
322 |
} |
323 |
|
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static bool pv_eoi_msr_needed(void *opaque) |
325 |
{ |
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X86CPU *cpu = opaque; |
327 |
|
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return cpu->env.pv_eoi_en_msr != 0; |
329 |
} |
330 |
|
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static bool steal_time_msr_needed(void *opaque) |
332 |
{ |
333 |
X86CPU *cpu = opaque; |
334 |
|
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return cpu->env.steal_time_msr != 0; |
336 |
} |
337 |
|
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static const VMStateDescription vmstate_steal_time_msr = { |
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.name = "cpu/steal_time_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
344 |
VMSTATE_UINT64(env.steal_time_msr, X86CPU), |
345 |
VMSTATE_END_OF_LIST() |
346 |
} |
347 |
}; |
348 |
|
349 |
static const VMStateDescription vmstate_async_pf_msr = { |
350 |
.name = "cpu/async_pf_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
353 |
.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
355 |
VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), |
356 |
VMSTATE_END_OF_LIST() |
357 |
} |
358 |
}; |
359 |
|
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static const VMStateDescription vmstate_pv_eoi_msr = { |
361 |
.name = "cpu/async_pv_eoi_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
364 |
.minimum_version_id_old = 1,
|
365 |
.fields = (VMStateField []) { |
366 |
VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), |
367 |
VMSTATE_END_OF_LIST() |
368 |
} |
369 |
}; |
370 |
|
371 |
static bool fpop_ip_dp_needed(void *opaque) |
372 |
{ |
373 |
X86CPU *cpu = opaque; |
374 |
CPUX86State *env = &cpu->env; |
375 |
|
376 |
return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; |
377 |
} |
378 |
|
379 |
static const VMStateDescription vmstate_fpop_ip_dp = { |
380 |
.name = "cpu/fpop_ip_dp",
|
381 |
.version_id = 1,
|
382 |
.minimum_version_id = 1,
|
383 |
.minimum_version_id_old = 1,
|
384 |
.fields = (VMStateField []) { |
385 |
VMSTATE_UINT16(env.fpop, X86CPU), |
386 |
VMSTATE_UINT64(env.fpip, X86CPU), |
387 |
VMSTATE_UINT64(env.fpdp, X86CPU), |
388 |
VMSTATE_END_OF_LIST() |
389 |
} |
390 |
}; |
391 |
|
392 |
static bool tsc_adjust_needed(void *opaque) |
393 |
{ |
394 |
X86CPU *cpu = opaque; |
395 |
CPUX86State *env = &cpu->env; |
396 |
|
397 |
return env->tsc_adjust != 0; |
398 |
} |
399 |
|
400 |
static const VMStateDescription vmstate_msr_tsc_adjust = { |
401 |
.name = "cpu/msr_tsc_adjust",
|
402 |
.version_id = 1,
|
403 |
.minimum_version_id = 1,
|
404 |
.minimum_version_id_old = 1,
|
405 |
.fields = (VMStateField[]) { |
406 |
VMSTATE_UINT64(env.tsc_adjust, X86CPU), |
407 |
VMSTATE_END_OF_LIST() |
408 |
} |
409 |
}; |
410 |
|
411 |
static bool tscdeadline_needed(void *opaque) |
412 |
{ |
413 |
X86CPU *cpu = opaque; |
414 |
CPUX86State *env = &cpu->env; |
415 |
|
416 |
return env->tsc_deadline != 0; |
417 |
} |
418 |
|
419 |
static const VMStateDescription vmstate_msr_tscdeadline = { |
420 |
.name = "cpu/msr_tscdeadline",
|
421 |
.version_id = 1,
|
422 |
.minimum_version_id = 1,
|
423 |
.minimum_version_id_old = 1,
|
424 |
.fields = (VMStateField []) { |
425 |
VMSTATE_UINT64(env.tsc_deadline, X86CPU), |
426 |
VMSTATE_END_OF_LIST() |
427 |
} |
428 |
}; |
429 |
|
430 |
static bool misc_enable_needed(void *opaque) |
431 |
{ |
432 |
X86CPU *cpu = opaque; |
433 |
CPUX86State *env = &cpu->env; |
434 |
|
435 |
return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
|
436 |
} |
437 |
|
438 |
static bool feature_control_needed(void *opaque) |
439 |
{ |
440 |
X86CPU *cpu = opaque; |
441 |
CPUX86State *env = &cpu->env; |
442 |
|
443 |
return env->msr_ia32_feature_control != 0; |
444 |
} |
445 |
|
446 |
static const VMStateDescription vmstate_msr_ia32_misc_enable = { |
447 |
.name = "cpu/msr_ia32_misc_enable",
|
448 |
.version_id = 1,
|
449 |
.minimum_version_id = 1,
|
450 |
.minimum_version_id_old = 1,
|
451 |
.fields = (VMStateField []) { |
452 |
VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), |
453 |
VMSTATE_END_OF_LIST() |
454 |
} |
455 |
}; |
456 |
|
457 |
static const VMStateDescription vmstate_msr_ia32_feature_control = { |
458 |
.name = "cpu/msr_ia32_feature_control",
|
459 |
.version_id = 1,
|
460 |
.minimum_version_id = 1,
|
461 |
.minimum_version_id_old = 1,
|
462 |
.fields = (VMStateField []) { |
463 |
VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), |
464 |
VMSTATE_END_OF_LIST() |
465 |
} |
466 |
}; |
467 |
|
468 |
static bool pmu_enable_needed(void *opaque) |
469 |
{ |
470 |
X86CPU *cpu = opaque; |
471 |
CPUX86State *env = &cpu->env; |
472 |
int i;
|
473 |
|
474 |
if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
|
475 |
env->msr_global_status || env->msr_global_ovf_ctrl) { |
476 |
return true; |
477 |
} |
478 |
for (i = 0; i < MAX_FIXED_COUNTERS; i++) { |
479 |
if (env->msr_fixed_counters[i]) {
|
480 |
return true; |
481 |
} |
482 |
} |
483 |
for (i = 0; i < MAX_GP_COUNTERS; i++) { |
484 |
if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
|
485 |
return true; |
486 |
} |
487 |
} |
488 |
|
489 |
return false; |
490 |
} |
491 |
|
492 |
static const VMStateDescription vmstate_msr_architectural_pmu = { |
493 |
.name = "cpu/msr_architectural_pmu",
|
494 |
.version_id = 1,
|
495 |
.minimum_version_id = 1,
|
496 |
.minimum_version_id_old = 1,
|
497 |
.fields = (VMStateField []) { |
498 |
VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), |
499 |
VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), |
500 |
VMSTATE_UINT64(env.msr_global_status, X86CPU), |
501 |
VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), |
502 |
VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS), |
503 |
VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), |
504 |
VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), |
505 |
VMSTATE_END_OF_LIST() |
506 |
} |
507 |
}; |
508 |
|
509 |
const VMStateDescription vmstate_x86_cpu = {
|
510 |
.name = "cpu",
|
511 |
.version_id = 12,
|
512 |
.minimum_version_id = 3,
|
513 |
.minimum_version_id_old = 3,
|
514 |
.pre_save = cpu_pre_save, |
515 |
.post_load = cpu_post_load, |
516 |
.fields = (VMStateField []) { |
517 |
VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), |
518 |
VMSTATE_UINTTL(env.eip, X86CPU), |
519 |
VMSTATE_UINTTL(env.eflags, X86CPU), |
520 |
VMSTATE_UINT32(env.hflags, X86CPU), |
521 |
/* FPU */
|
522 |
VMSTATE_UINT16(env.fpuc, X86CPU), |
523 |
VMSTATE_UINT16(env.fpus_vmstate, X86CPU), |
524 |
VMSTATE_UINT16(env.fptag_vmstate, X86CPU), |
525 |
VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), |
526 |
VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
|
527 |
|
528 |
VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
|
529 |
VMSTATE_SEGMENT(env.ldt, X86CPU), |
530 |
VMSTATE_SEGMENT(env.tr, X86CPU), |
531 |
VMSTATE_SEGMENT(env.gdt, X86CPU), |
532 |
VMSTATE_SEGMENT(env.idt, X86CPU), |
533 |
|
534 |
VMSTATE_UINT32(env.sysenter_cs, X86CPU), |
535 |
#ifdef TARGET_X86_64
|
536 |
/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
|
537 |
VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7), |
538 |
VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7), |
539 |
VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
|
540 |
VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
|
541 |
#else
|
542 |
VMSTATE_UINTTL(env.sysenter_esp, X86CPU), |
543 |
VMSTATE_UINTTL(env.sysenter_eip, X86CPU), |
544 |
#endif
|
545 |
|
546 |
VMSTATE_UINTTL(env.cr[0], X86CPU),
|
547 |
VMSTATE_UINTTL(env.cr[2], X86CPU),
|
548 |
VMSTATE_UINTTL(env.cr[3], X86CPU),
|
549 |
VMSTATE_UINTTL(env.cr[4], X86CPU),
|
550 |
VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
|
551 |
/* MMU */
|
552 |
VMSTATE_INT32(env.a20_mask, X86CPU), |
553 |
/* XMM */
|
554 |
VMSTATE_UINT32(env.mxcsr, X86CPU), |
555 |
VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS), |
556 |
|
557 |
#ifdef TARGET_X86_64
|
558 |
VMSTATE_UINT64(env.efer, X86CPU), |
559 |
VMSTATE_UINT64(env.star, X86CPU), |
560 |
VMSTATE_UINT64(env.lstar, X86CPU), |
561 |
VMSTATE_UINT64(env.cstar, X86CPU), |
562 |
VMSTATE_UINT64(env.fmask, X86CPU), |
563 |
VMSTATE_UINT64(env.kernelgsbase, X86CPU), |
564 |
#endif
|
565 |
VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
|
566 |
|
567 |
VMSTATE_UINT64_V(env.pat, X86CPU, 5),
|
568 |
VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
|
569 |
|
570 |
VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5), |
571 |
VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
|
572 |
VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
|
573 |
VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
|
574 |
VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
|
575 |
VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
|
576 |
VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
|
577 |
VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
|
578 |
VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
|
579 |
VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
|
580 |
VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
|
581 |
/* MTRRs */
|
582 |
VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8), |
583 |
VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
|
584 |
VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8), |
585 |
/* KVM-related states */
|
586 |
VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
|
587 |
VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
|
588 |
VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
|
589 |
VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
|
590 |
VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
|
591 |
VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
|
592 |
VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
|
593 |
VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
|
594 |
VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
|
595 |
/* MCE */
|
596 |
VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
|
597 |
VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
|
598 |
VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
|
599 |
VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10), |
600 |
/* rdtscp */
|
601 |
VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
|
602 |
/* KVM pvclock msr */
|
603 |
VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
|
604 |
VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
|
605 |
/* XSAVE related fields */
|
606 |
VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
|
607 |
VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
|
608 |
VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
|
609 |
VMSTATE_END_OF_LIST() |
610 |
/* The above list is not sorted /wrt version numbers, watch out! */
|
611 |
}, |
612 |
.subsections = (VMStateSubsection []) { |
613 |
{ |
614 |
.vmsd = &vmstate_async_pf_msr, |
615 |
.needed = async_pf_msr_needed, |
616 |
} , { |
617 |
.vmsd = &vmstate_pv_eoi_msr, |
618 |
.needed = pv_eoi_msr_needed, |
619 |
} , { |
620 |
.vmsd = &vmstate_steal_time_msr, |
621 |
.needed = steal_time_msr_needed, |
622 |
} , { |
623 |
.vmsd = &vmstate_fpop_ip_dp, |
624 |
.needed = fpop_ip_dp_needed, |
625 |
}, { |
626 |
.vmsd = &vmstate_msr_tsc_adjust, |
627 |
.needed = tsc_adjust_needed, |
628 |
}, { |
629 |
.vmsd = &vmstate_msr_tscdeadline, |
630 |
.needed = tscdeadline_needed, |
631 |
}, { |
632 |
.vmsd = &vmstate_msr_ia32_misc_enable, |
633 |
.needed = misc_enable_needed, |
634 |
}, { |
635 |
.vmsd = &vmstate_msr_ia32_feature_control, |
636 |
.needed = feature_control_needed, |
637 |
}, { |
638 |
.vmsd = &vmstate_msr_architectural_pmu, |
639 |
.needed = pmu_enable_needed, |
640 |
} , { |
641 |
/* empty */
|
642 |
} |
643 |
} |
644 |
}; |