root / hw / acpi_piix4.c @ 355bf2e5
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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "apm.h" |
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#include "pm_smbus.h" |
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#include "pci.h" |
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#include "acpi.h" |
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#include "sysemu.h" |
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#include "range.h" |
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#include "ioport.h" |
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0) |
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#endif
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#define ACPI_DBG_IO_ADDR 0xb044 |
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#define GPE_BASE 0xafe0 |
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#define GPE_LEN 4 |
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#define PCI_BASE 0xae00 |
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#define PCI_EJ_BASE 0xae08 |
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#define PCI_RMV_BASE 0xae0c |
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#define PIIX4_PCI_HOTPLUG_STATUS 2 |
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struct pci_status {
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uint32_t up; |
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uint32_t down; |
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}; |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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IORange ioport; |
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ACPIREGS ar; |
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APMState apm; |
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PMSMBus smb; |
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uint32_t smb_io_base; |
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qemu_irq irq; |
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qemu_irq smi_irq; |
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int kvm_enabled;
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Notifier machine_ready; |
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/* for pci hotplug */
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struct pci_status pci0_status;
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uint32_t pci0_hotplug_enable; |
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} PIIX4PMState; |
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->ar, s->ar.tmr.overflow_time); |
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sci_level = (((pmsts & s->ar.pm1.evt.en) & |
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(ACPI_BITMASK_RT_CLOCK_ENABLE | |
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ACPI_BITMASK_POWER_BUTTON_ENABLE | |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
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ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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(((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
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& PIIX4_PCI_HOTPLUG_STATUS) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
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!(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
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} |
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static void pm_tmr_timer(ACPIREGS *ar) |
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{ |
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PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
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pm_update_sci(s); |
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} |
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static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
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uint64_t val) |
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{ |
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PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
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if (width != 2) { |
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PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
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(unsigned)addr, width, (unsigned)val); |
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} |
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switch(addr) {
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case 0x00: |
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acpi_pm1_evt_write_sts(&s->ar, val); |
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pm_update_sci(s); |
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break;
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case 0x02: |
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s->ar.pm1.evt.en = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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acpi_pm1_cnt_write(&s->ar, val); |
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break;
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default:
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break;
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} |
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PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
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(unsigned int)val); |
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} |
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static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
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uint64_t *data) |
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{ |
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PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
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uint32_t val; |
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switch(addr) {
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case 0x00: |
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val = acpi_pm1_evt_get_sts(&s->ar, s->ar.tmr.overflow_time); |
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break;
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case 0x02: |
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val = s->ar.pm1.evt.en; |
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break;
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case 0x04: |
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val = s->ar.pm1.cnt.cnt; |
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break;
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case 0x08: |
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val = acpi_pm_tmr_get(&s->ar); |
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break;
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default:
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val = 0;
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break;
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} |
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PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
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*data = val; |
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} |
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static const IORangeOps pm_iorange_ops = { |
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.read = pm_ioport_read, |
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.write = pm_ioport_write, |
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}; |
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static void apm_ctrl_changed(uint32_t val, void *arg) |
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{ |
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PIIX4PMState *s = arg; |
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
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} |
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static void pm_io_space_update(PIIX4PMState *s) |
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{ |
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uint32_t pm_io_base; |
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if (s->dev.config[0x80] & 1) { |
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
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ioport_register(&s->ioport); |
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} |
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} |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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pci_default_write_config(d, address, val, len); |
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if (range_covers_byte(address, len, 0x80)) |
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pm_io_space_update((PIIX4PMState *)d); |
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} |
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \ |
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.name = (stringify(_field)), \ |
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.version_id = 0, \
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.num = GPE_LEN, \ |
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.info = &vmstate_info_uint16, \ |
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.size = sizeof(uint16_t), \
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.flags = VMS_ARRAY | VMS_POINTER, \ |
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
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} |
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static const VMStateDescription vmstate_gpe = { |
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.name = "gpe",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
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VMSTATE_GPE_ARRAY(en, ACPIGPE), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_pci_status = { |
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.name = "pci_status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_UINT32(up, struct pci_status),
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VMSTATE_UINT32(down, struct pci_status),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_acpi = { |
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.name = "piix4_pm",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), |
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
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VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
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VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
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VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
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struct pci_status),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void piix4_update_hotplug(PIIX4PMState *s) |
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{ |
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PCIDevice *dev = &s->dev; |
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BusState *bus = qdev_get_parent_bus(&dev->qdev); |
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DeviceState *qdev, *next; |
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s->pci0_hotplug_enable = ~0;
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QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
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PCIDevice *pdev = PCI_DEVICE(qdev); |
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); |
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int slot = PCI_SLOT(pdev->devfn);
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if (pc->no_hotplug) {
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s->pci0_hotplug_enable &= ~(1 << slot);
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} |
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} |
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} |
289 |
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static void piix4_reset(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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uint8_t *pci_conf = s->dev.config; |
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pci_conf[0x58] = 0; |
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pci_conf[0x59] = 0; |
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pci_conf[0x5a] = 0; |
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pci_conf[0x5b] = 0; |
299 |
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02; |
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} |
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piix4_update_hotplug(s); |
305 |
} |
306 |
|
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static void piix4_powerdown(void *opaque, int irq, int power_failing) |
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{ |
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PIIX4PMState *s = opaque; |
310 |
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assert(s != NULL);
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acpi_pm1_evt_power_down(&s->ar); |
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} |
314 |
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static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
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{ |
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PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); |
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uint8_t *pci_conf; |
319 |
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pci_conf = s->dev.config; |
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pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; |
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pci_conf[0x63] = 0x60; |
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pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | |
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(isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); |
325 |
|
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} |
327 |
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static int piix4_pm_initfn(PCIDevice *dev) |
329 |
{ |
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PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
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uint8_t *pci_conf; |
332 |
|
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pci_conf = s->dev.config; |
334 |
pci_conf[0x06] = 0x80; |
335 |
pci_conf[0x07] = 0x02; |
336 |
pci_conf[0x09] = 0x00; |
337 |
pci_conf[0x3d] = 0x01; // interrupt pin 1 |
338 |
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pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
340 |
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/* APM */
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apm_init(&s->apm, apm_ctrl_changed, s); |
343 |
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
345 |
|
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if (s->kvm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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348 |
* support SMM mode. */
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349 |
pci_conf[0x5B] = 0x02; |
350 |
} |
351 |
|
352 |
/* XXX: which specification is used ? The i82731AB has different
|
353 |
mappings */
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pci_conf[0x90] = s->smb_io_base | 1; |
355 |
pci_conf[0x91] = s->smb_io_base >> 8; |
356 |
pci_conf[0xd2] = 0x09; |
357 |
register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
358 |
register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); |
359 |
|
360 |
acpi_pm_tmr_init(&s->ar, pm_tmr_timer); |
361 |
acpi_gpe_init(&s->ar, GPE_LEN); |
362 |
|
363 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
|
364 |
|
365 |
pm_smbus_init(&s->dev.qdev, &s->smb); |
366 |
s->machine_ready.notify = piix4_pm_machine_ready; |
367 |
qemu_add_machine_init_done_notifier(&s->machine_ready); |
368 |
qemu_register_reset(piix4_reset, s); |
369 |
piix4_acpi_system_hot_add_init(dev->bus, s); |
370 |
|
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return 0; |
372 |
} |
373 |
|
374 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
375 |
qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, |
376 |
int kvm_enabled)
|
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{ |
378 |
PCIDevice *dev; |
379 |
PIIX4PMState *s; |
380 |
|
381 |
dev = pci_create(bus, devfn, "PIIX4_PM");
|
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qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
383 |
|
384 |
s = DO_UPCAST(PIIX4PMState, dev, dev); |
385 |
s->irq = sci_irq; |
386 |
acpi_pm1_cnt_init(&s->ar, cmos_s3); |
387 |
s->smi_irq = smi_irq; |
388 |
s->kvm_enabled = kvm_enabled; |
389 |
|
390 |
qdev_init_nofail(&dev->qdev); |
391 |
|
392 |
return s->smb.smbus;
|
393 |
} |
394 |
|
395 |
static Property piix4_pm_properties[] = {
|
396 |
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), |
397 |
DEFINE_PROP_END_OF_LIST(), |
398 |
}; |
399 |
|
400 |
static void piix4_pm_class_init(ObjectClass *klass, void *data) |
401 |
{ |
402 |
DeviceClass *dc = DEVICE_CLASS(klass); |
403 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
404 |
|
405 |
k->no_hotplug = 1;
|
406 |
k->init = piix4_pm_initfn; |
407 |
k->config_write = pm_write_config; |
408 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
409 |
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; |
410 |
k->revision = 0x03;
|
411 |
k->class_id = PCI_CLASS_BRIDGE_OTHER; |
412 |
dc->desc = "PM";
|
413 |
dc->no_user = 1;
|
414 |
dc->vmsd = &vmstate_acpi; |
415 |
dc->props = piix4_pm_properties; |
416 |
} |
417 |
|
418 |
static TypeInfo piix4_pm_info = {
|
419 |
.name = "PIIX4_PM",
|
420 |
.parent = TYPE_PCI_DEVICE, |
421 |
.instance_size = sizeof(PIIX4PMState),
|
422 |
.class_init = piix4_pm_class_init, |
423 |
}; |
424 |
|
425 |
static void piix4_pm_register_types(void) |
426 |
{ |
427 |
type_register_static(&piix4_pm_info); |
428 |
} |
429 |
|
430 |
type_init(piix4_pm_register_types) |
431 |
|
432 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
433 |
{ |
434 |
PIIX4PMState *s = opaque; |
435 |
uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
436 |
|
437 |
PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
|
438 |
return val;
|
439 |
} |
440 |
|
441 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
442 |
{ |
443 |
PIIX4PMState *s = opaque; |
444 |
|
445 |
acpi_gpe_ioport_writeb(&s->ar, addr, val); |
446 |
pm_update_sci(s); |
447 |
|
448 |
PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
|
449 |
} |
450 |
|
451 |
static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
452 |
{ |
453 |
uint32_t val = 0;
|
454 |
struct pci_status *g = opaque;
|
455 |
switch (addr) {
|
456 |
case PCI_BASE:
|
457 |
val = g->up; |
458 |
break;
|
459 |
case PCI_BASE + 4: |
460 |
val = g->down; |
461 |
break;
|
462 |
default:
|
463 |
break;
|
464 |
} |
465 |
|
466 |
PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
|
467 |
return val;
|
468 |
} |
469 |
|
470 |
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
471 |
{ |
472 |
struct pci_status *g = opaque;
|
473 |
switch (addr) {
|
474 |
case PCI_BASE:
|
475 |
g->up = val; |
476 |
break;
|
477 |
case PCI_BASE + 4: |
478 |
g->down = val; |
479 |
break;
|
480 |
} |
481 |
|
482 |
PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
|
483 |
} |
484 |
|
485 |
static uint32_t pciej_read(void *opaque, uint32_t addr) |
486 |
{ |
487 |
PIIX4_DPRINTF("pciej read %x\n", addr);
|
488 |
return 0; |
489 |
} |
490 |
|
491 |
static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
492 |
{ |
493 |
BusState *bus = opaque; |
494 |
DeviceState *qdev, *next; |
495 |
int slot = ffs(val) - 1; |
496 |
|
497 |
QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
498 |
PCIDevice *dev = PCI_DEVICE(qdev); |
499 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
500 |
if (PCI_SLOT(dev->devfn) == slot && !pc->no_hotplug) {
|
501 |
qdev_free(qdev); |
502 |
} |
503 |
} |
504 |
|
505 |
|
506 |
PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
|
507 |
} |
508 |
|
509 |
static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
510 |
{ |
511 |
PIIX4PMState *s = opaque; |
512 |
|
513 |
return s->pci0_hotplug_enable;
|
514 |
} |
515 |
|
516 |
static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val) |
517 |
{ |
518 |
return;
|
519 |
} |
520 |
|
521 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
522 |
PCIHotplugState state); |
523 |
|
524 |
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
525 |
{ |
526 |
struct pci_status *pci0_status = &s->pci0_status;
|
527 |
|
528 |
register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
|
529 |
register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s);
|
530 |
acpi_gpe_blk(&s->ar, GPE_BASE); |
531 |
|
532 |
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); |
533 |
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); |
534 |
|
535 |
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); |
536 |
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); |
537 |
|
538 |
register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s); |
539 |
register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); |
540 |
|
541 |
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
542 |
} |
543 |
|
544 |
static void enable_device(PIIX4PMState *s, int slot) |
545 |
{ |
546 |
s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
547 |
s->pci0_status.up |= (1 << slot);
|
548 |
} |
549 |
|
550 |
static void disable_device(PIIX4PMState *s, int slot) |
551 |
{ |
552 |
s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
553 |
s->pci0_status.down |= (1 << slot);
|
554 |
} |
555 |
|
556 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
557 |
PCIHotplugState state) |
558 |
{ |
559 |
int slot = PCI_SLOT(dev->devfn);
|
560 |
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
561 |
PCI_DEVICE(qdev)); |
562 |
|
563 |
/* Don't send event when device is enabled during qemu machine creation:
|
564 |
* it is present on boot, no hotplug event is necessary. We do send an
|
565 |
* event when the device is disabled later. */
|
566 |
if (state == PCI_COLDPLUG_ENABLED) {
|
567 |
return 0; |
568 |
} |
569 |
|
570 |
s->pci0_status.up = 0;
|
571 |
s->pci0_status.down = 0;
|
572 |
if (state == PCI_HOTPLUG_ENABLED) {
|
573 |
enable_device(s, slot); |
574 |
} else {
|
575 |
disable_device(s, slot); |
576 |
} |
577 |
|
578 |
pm_update_sci(s); |
579 |
|
580 |
return 0; |
581 |
} |