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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | a541f297 | bellard | *
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4 | a541f297 | bellard | * Copyright (c) 2003-2004 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 9a64fbe4 | bellard | #include "vl.h" |
25 | 9fddaa0c | bellard | |
26 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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27 | a541f297 | bellard | //#define DEBUG_PPC_IO
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28 | 9a64fbe4 | bellard | |
29 | 64201201 | bellard | #define KERNEL_LOAD_ADDR 0x01000000; |
30 | 64201201 | bellard | #define INITRD_LOAD_ADDR 0x01800000; |
31 | 64201201 | bellard | |
32 | 9a64fbe4 | bellard | extern int loglevel; |
33 | 9a64fbe4 | bellard | extern FILE *logfile;
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34 | 9a64fbe4 | bellard | |
35 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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36 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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37 | 9a64fbe4 | bellard | #endif
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38 | 9a64fbe4 | bellard | |
39 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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40 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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41 | 9a64fbe4 | bellard | do { \
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42 | 9a64fbe4 | bellard | if (loglevel > 0) { \ |
43 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
44 | 9a64fbe4 | bellard | } else { \
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45 | 9a64fbe4 | bellard | printf("%s : " fmt, __func__ , ##args); \ |
46 | 9a64fbe4 | bellard | } \ |
47 | 9a64fbe4 | bellard | } while (0) |
48 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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49 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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50 | 9a64fbe4 | bellard | do { \
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51 | 9a64fbe4 | bellard | if (loglevel > 0) { \ |
52 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
53 | 9a64fbe4 | bellard | } \ |
54 | 9a64fbe4 | bellard | } while (0) |
55 | 9a64fbe4 | bellard | #else
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56 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
57 | 9a64fbe4 | bellard | #endif
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58 | 9a64fbe4 | bellard | |
59 | a541f297 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
60 | 64201201 | bellard | /* Constants for devices init */
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61 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
62 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
63 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
64 | a541f297 | bellard | |
65 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
66 | a541f297 | bellard | |
67 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
68 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
69 | 9a64fbe4 | bellard | |
70 | 64201201 | bellard | //static PITState *pit;
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71 | 64201201 | bellard | |
72 | 64201201 | bellard | /* ISA IO ports bridge */
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73 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
74 | 9a64fbe4 | bellard | |
75 | 64201201 | bellard | /* Speaker port 0x61 */
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76 | 64201201 | bellard | int speaker_data_on;
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77 | 64201201 | bellard | int dummy_refresh_clock;
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78 | 64201201 | bellard | |
79 | 64201201 | bellard | static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80 | 9a64fbe4 | bellard | { |
81 | a541f297 | bellard | #if 0
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82 | 64201201 | bellard | speaker_data_on = (val >> 1) & 1;
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83 | 64201201 | bellard | pit_set_gate(pit, 2, val & 1);
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84 | a541f297 | bellard | #endif
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85 | 9a64fbe4 | bellard | } |
86 | 9a64fbe4 | bellard | |
87 | 64201201 | bellard | static uint32_t speaker_ioport_read(void *opaque, uint32_t addr) |
88 | 9a64fbe4 | bellard | { |
89 | a541f297 | bellard | #if 0
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90 | 64201201 | bellard | int out;
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91 | 64201201 | bellard | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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92 | 64201201 | bellard | dummy_refresh_clock ^= 1;
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93 | 64201201 | bellard | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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94 | 64201201 | bellard | (dummy_refresh_clock << 4);
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95 | a541f297 | bellard | #endif
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96 | 64201201 | bellard | return 0; |
97 | 9a64fbe4 | bellard | } |
98 | 9a64fbe4 | bellard | |
99 | 64201201 | bellard | /* PCI intack register */
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100 | 64201201 | bellard | /* Read-only register (?) */
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101 | a4193c8a | bellard | static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) |
102 | 64201201 | bellard | { |
103 | 64201201 | bellard | // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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104 | 64201201 | bellard | } |
105 | 64201201 | bellard | |
106 | 64201201 | bellard | static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) |
107 | 64201201 | bellard | { |
108 | 64201201 | bellard | uint32_t retval = 0;
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109 | 64201201 | bellard | |
110 | 64201201 | bellard | if (addr == 0xBFFFFFF0) |
111 | 64201201 | bellard | retval = pic_intack_read(NULL);
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112 | 64201201 | bellard | // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
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113 | 64201201 | bellard | |
114 | 64201201 | bellard | return retval;
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115 | 64201201 | bellard | } |
116 | 64201201 | bellard | |
117 | a4193c8a | bellard | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
118 | 64201201 | bellard | { |
119 | 64201201 | bellard | return _PPC_intack_read(addr);
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120 | 64201201 | bellard | } |
121 | 64201201 | bellard | |
122 | a4193c8a | bellard | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
123 | 9a64fbe4 | bellard | { |
124 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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125 | 64201201 | bellard | return bswap16(_PPC_intack_read(addr));
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126 | 64201201 | bellard | #else
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127 | 64201201 | bellard | return _PPC_intack_read(addr);
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128 | f658b4db | bellard | #endif
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129 | 9a64fbe4 | bellard | } |
130 | 9a64fbe4 | bellard | |
131 | a4193c8a | bellard | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
132 | 9a64fbe4 | bellard | { |
133 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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134 | 64201201 | bellard | return bswap32(_PPC_intack_read(addr));
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135 | 64201201 | bellard | #else
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136 | 64201201 | bellard | return _PPC_intack_read(addr);
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137 | f658b4db | bellard | #endif
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138 | 9a64fbe4 | bellard | } |
139 | 9a64fbe4 | bellard | |
140 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_intack_write[] = {
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141 | 64201201 | bellard | &_PPC_intack_write, |
142 | 64201201 | bellard | &_PPC_intack_write, |
143 | 64201201 | bellard | &_PPC_intack_write, |
144 | 64201201 | bellard | }; |
145 | 64201201 | bellard | |
146 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_intack_read[] = {
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147 | 64201201 | bellard | &PPC_intack_readb, |
148 | 64201201 | bellard | &PPC_intack_readw, |
149 | 64201201 | bellard | &PPC_intack_readl, |
150 | 64201201 | bellard | }; |
151 | 64201201 | bellard | |
152 | 64201201 | bellard | /* PowerPC control and status registers */
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153 | 64201201 | bellard | #if 0 // Not used
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154 | 64201201 | bellard | static struct {
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155 | 64201201 | bellard | /* IDs */
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156 | 64201201 | bellard | uint32_t veni_devi;
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157 | 64201201 | bellard | uint32_t revi;
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158 | 64201201 | bellard | /* Control and status */
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159 | 64201201 | bellard | uint32_t gcsr;
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160 | 64201201 | bellard | uint32_t xcfr;
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161 | 64201201 | bellard | uint32_t ct32;
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162 | 64201201 | bellard | uint32_t mcsr;
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163 | 64201201 | bellard | /* General purpose registers */
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164 | 64201201 | bellard | uint32_t gprg[6];
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165 | 64201201 | bellard | /* Exceptions */
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166 | 64201201 | bellard | uint32_t feen;
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167 | 64201201 | bellard | uint32_t fest;
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168 | 64201201 | bellard | uint32_t fema;
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169 | 64201201 | bellard | uint32_t fecl;
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170 | 64201201 | bellard | uint32_t eeen;
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171 | 64201201 | bellard | uint32_t eest;
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172 | 64201201 | bellard | uint32_t eecl;
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173 | 64201201 | bellard | uint32_t eeint;
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174 | 64201201 | bellard | uint32_t eemck0;
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175 | 64201201 | bellard | uint32_t eemck1;
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176 | 64201201 | bellard | /* Error diagnostic */
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177 | 64201201 | bellard | } XCSR;
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178 | 64201201 | bellard | #endif
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179 | 64201201 | bellard | |
180 | a4193c8a | bellard | static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
181 | 64201201 | bellard | { |
182 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
183 | 64201201 | bellard | } |
184 | 64201201 | bellard | |
185 | a4193c8a | bellard | static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
186 | 9a64fbe4 | bellard | { |
187 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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188 | 64201201 | bellard | value = bswap16(value); |
189 | f658b4db | bellard | #endif
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190 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
191 | 9a64fbe4 | bellard | } |
192 | 9a64fbe4 | bellard | |
193 | a4193c8a | bellard | static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
194 | 9a64fbe4 | bellard | { |
195 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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196 | 64201201 | bellard | value = bswap32(value); |
197 | f658b4db | bellard | #endif
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198 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
199 | 9a64fbe4 | bellard | } |
200 | 9a64fbe4 | bellard | |
201 | a4193c8a | bellard | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
202 | 64201201 | bellard | { |
203 | 64201201 | bellard | uint32_t retval = 0;
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204 | 9a64fbe4 | bellard | |
205 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
206 | 9a64fbe4 | bellard | |
207 | 64201201 | bellard | return retval;
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208 | 64201201 | bellard | } |
209 | 64201201 | bellard | |
210 | a4193c8a | bellard | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
211 | 9a64fbe4 | bellard | { |
212 | 64201201 | bellard | uint32_t retval = 0;
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213 | 64201201 | bellard | |
214 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
215 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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216 | 64201201 | bellard | retval = bswap16(retval); |
217 | 64201201 | bellard | #endif
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218 | 64201201 | bellard | |
219 | 64201201 | bellard | return retval;
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220 | 9a64fbe4 | bellard | } |
221 | 9a64fbe4 | bellard | |
222 | a4193c8a | bellard | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
223 | 9a64fbe4 | bellard | { |
224 | 9a64fbe4 | bellard | uint32_t retval = 0;
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225 | 9a64fbe4 | bellard | |
226 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
227 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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228 | 64201201 | bellard | retval = bswap32(retval); |
229 | 64201201 | bellard | #endif
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230 | 9a64fbe4 | bellard | |
231 | 9a64fbe4 | bellard | return retval;
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232 | 9a64fbe4 | bellard | } |
233 | 9a64fbe4 | bellard | |
234 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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235 | 64201201 | bellard | &PPC_XCSR_writeb, |
236 | 64201201 | bellard | &PPC_XCSR_writew, |
237 | 64201201 | bellard | &PPC_XCSR_writel, |
238 | 9a64fbe4 | bellard | }; |
239 | 9a64fbe4 | bellard | |
240 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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241 | 64201201 | bellard | &PPC_XCSR_readb, |
242 | 64201201 | bellard | &PPC_XCSR_readw, |
243 | 64201201 | bellard | &PPC_XCSR_readl, |
244 | 9a64fbe4 | bellard | }; |
245 | 9a64fbe4 | bellard | |
246 | 64201201 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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247 | 64201201 | bellard | typedef struct sysctrl_t { |
248 | 64201201 | bellard | m48t59_t *nvram; |
249 | 64201201 | bellard | uint8_t state; |
250 | 64201201 | bellard | uint8_t syscontrol; |
251 | 64201201 | bellard | uint8_t fake_io[2];
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252 | 64201201 | bellard | } sysctrl_t; |
253 | 9a64fbe4 | bellard | |
254 | 64201201 | bellard | enum {
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255 | 64201201 | bellard | STATE_HARDFILE = 0x01,
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256 | 9a64fbe4 | bellard | }; |
257 | 9a64fbe4 | bellard | |
258 | 64201201 | bellard | static sysctrl_t *sysctrl;
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259 | 9a64fbe4 | bellard | |
260 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
261 | 9a64fbe4 | bellard | { |
262 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
263 | 64201201 | bellard | |
264 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
265 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398] = val;
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266 | 9a64fbe4 | bellard | } |
267 | 9a64fbe4 | bellard | |
268 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
269 | 9a64fbe4 | bellard | { |
270 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
271 | 9a64fbe4 | bellard | |
272 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, |
273 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398]);
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274 | 64201201 | bellard | return sysctrl->fake_io[addr - 0x0398]; |
275 | 64201201 | bellard | } |
276 | 9a64fbe4 | bellard | |
277 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
278 | 9a64fbe4 | bellard | { |
279 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
280 | 64201201 | bellard | |
281 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
282 | 9a64fbe4 | bellard | switch (addr) {
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283 | 9a64fbe4 | bellard | case 0x0092: |
284 | 9a64fbe4 | bellard | /* Special port 92 */
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285 | 9a64fbe4 | bellard | /* Check soft reset asked */
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286 | 64201201 | bellard | if (val & 0x01) { |
287 | 64201201 | bellard | // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
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288 | 9a64fbe4 | bellard | } |
289 | 9a64fbe4 | bellard | /* Check LE mode */
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290 | 64201201 | bellard | if (val & 0x02) { |
291 | 9a64fbe4 | bellard | printf("Little Endian mode isn't supported (yet ?)\n");
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292 | 9a64fbe4 | bellard | abort(); |
293 | 9a64fbe4 | bellard | } |
294 | 9a64fbe4 | bellard | break;
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295 | 64201201 | bellard | case 0x0800: |
296 | 64201201 | bellard | /* Motorola CPU configuration register : read-only */
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297 | 64201201 | bellard | break;
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298 | 64201201 | bellard | case 0x0802: |
299 | 64201201 | bellard | /* Motorola base module feature register : read-only */
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300 | 64201201 | bellard | break;
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301 | 64201201 | bellard | case 0x0803: |
302 | 64201201 | bellard | /* Motorola base module status register : read-only */
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303 | 64201201 | bellard | break;
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304 | 9a64fbe4 | bellard | case 0x0808: |
305 | 64201201 | bellard | /* Hardfile light register */
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306 | 64201201 | bellard | if (val & 1) |
307 | 64201201 | bellard | sysctrl->state |= STATE_HARDFILE; |
308 | 64201201 | bellard | else
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309 | 64201201 | bellard | sysctrl->state &= ~STATE_HARDFILE; |
310 | 9a64fbe4 | bellard | break;
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311 | 9a64fbe4 | bellard | case 0x0810: |
312 | 9a64fbe4 | bellard | /* Password protect 1 register */
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313 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
314 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 1);
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315 | 9a64fbe4 | bellard | break;
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316 | 9a64fbe4 | bellard | case 0x0812: |
317 | 9a64fbe4 | bellard | /* Password protect 2 register */
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318 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
319 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 2);
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320 | 9a64fbe4 | bellard | break;
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321 | 9a64fbe4 | bellard | case 0x0814: |
322 | 64201201 | bellard | /* L2 invalidate register */
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323 | 64201201 | bellard | // tlb_flush(cpu_single_env, 1);
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324 | 9a64fbe4 | bellard | break;
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325 | 9a64fbe4 | bellard | case 0x081C: |
326 | 9a64fbe4 | bellard | /* system control register */
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327 | 64201201 | bellard | sysctrl->syscontrol = val & 0x0F;
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328 | 9a64fbe4 | bellard | break;
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329 | 9a64fbe4 | bellard | case 0x0850: |
330 | 9a64fbe4 | bellard | /* I/O map type register */
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331 | 64201201 | bellard | if (!(val & 0x01)) { |
332 | 9a64fbe4 | bellard | printf("No support for non-continuous I/O map mode\n");
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333 | 9a64fbe4 | bellard | abort(); |
334 | 9a64fbe4 | bellard | } |
335 | 9a64fbe4 | bellard | break;
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336 | 9a64fbe4 | bellard | default:
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337 | 64201201 | bellard | printf("ERROR: unaffected IO port write: %04lx => %02x\n",
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338 | 64201201 | bellard | (long)addr, val);
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339 | 9a64fbe4 | bellard | break;
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340 | 9a64fbe4 | bellard | } |
341 | 9a64fbe4 | bellard | } |
342 | 9a64fbe4 | bellard | |
343 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
344 | 9a64fbe4 | bellard | { |
345 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
346 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
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347 | 9a64fbe4 | bellard | |
348 | 9a64fbe4 | bellard | switch (addr) {
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349 | 9a64fbe4 | bellard | case 0x0092: |
350 | 9a64fbe4 | bellard | /* Special port 92 */
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351 | 64201201 | bellard | retval = 0x00;
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352 | 64201201 | bellard | break;
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353 | 64201201 | bellard | case 0x0800: |
354 | 64201201 | bellard | /* Motorola CPU configuration register */
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355 | 64201201 | bellard | retval = 0xEF; /* MPC750 */ |
356 | 64201201 | bellard | break;
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357 | 64201201 | bellard | case 0x0802: |
358 | 64201201 | bellard | /* Motorola Base module feature register */
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359 | 64201201 | bellard | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
360 | 64201201 | bellard | break;
|
361 | 64201201 | bellard | case 0x0803: |
362 | 64201201 | bellard | /* Motorola base module status register */
|
363 | 64201201 | bellard | retval = 0xE0; /* Standard MPC750 */ |
364 | 9a64fbe4 | bellard | break;
|
365 | 9a64fbe4 | bellard | case 0x080C: |
366 | 9a64fbe4 | bellard | /* Equipment present register:
|
367 | 9a64fbe4 | bellard | * no L2 cache
|
368 | 9a64fbe4 | bellard | * no upgrade processor
|
369 | 9a64fbe4 | bellard | * no cards in PCI slots
|
370 | 9a64fbe4 | bellard | * SCSI fuse is bad
|
371 | 9a64fbe4 | bellard | */
|
372 | 64201201 | bellard | retval = 0x3C;
|
373 | 64201201 | bellard | break;
|
374 | 64201201 | bellard | case 0x0810: |
375 | 64201201 | bellard | /* Motorola base module extended feature register */
|
376 | 64201201 | bellard | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
377 | 9a64fbe4 | bellard | break;
|
378 | 9a64fbe4 | bellard | case 0x0818: |
379 | 9a64fbe4 | bellard | /* Keylock */
|
380 | 9a64fbe4 | bellard | retval = 0x00;
|
381 | 9a64fbe4 | bellard | break;
|
382 | 9a64fbe4 | bellard | case 0x081C: |
383 | 9a64fbe4 | bellard | /* system control register
|
384 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
|
385 | 9a64fbe4 | bellard | */
|
386 | 64201201 | bellard | retval = sysctrl->syscontrol; |
387 | 9a64fbe4 | bellard | break;
|
388 | 9a64fbe4 | bellard | case 0x0823: |
389 | 9a64fbe4 | bellard | /* */
|
390 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
391 | 9a64fbe4 | bellard | break;
|
392 | 9a64fbe4 | bellard | case 0x0850: |
393 | 9a64fbe4 | bellard | /* I/O map type register */
|
394 | 64201201 | bellard | retval = 0x01;
|
395 | 9a64fbe4 | bellard | break;
|
396 | 9a64fbe4 | bellard | default:
|
397 | 64201201 | bellard | printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); |
398 | 9a64fbe4 | bellard | break;
|
399 | 9a64fbe4 | bellard | } |
400 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval); |
401 | 9a64fbe4 | bellard | |
402 | 9a64fbe4 | bellard | return retval;
|
403 | 9a64fbe4 | bellard | } |
404 | 9a64fbe4 | bellard | |
405 | a541f297 | bellard | extern CPUPPCState *global_env;
|
406 | a541f297 | bellard | |
407 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
408 | a541f297 | bellard | |
409 | 26aa7d72 | bellard | /* PowerPC PREP hardware initialisation */
|
410 | a541f297 | bellard | void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, |
411 | a541f297 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
412 | a541f297 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
413 | a541f297 | bellard | const char *initrd_filename) |
414 | a541f297 | bellard | { |
415 | a541f297 | bellard | char buf[1024]; |
416 | 64201201 | bellard | // void *openpic;
|
417 | 64201201 | bellard | m48t59_t *nvram; |
418 | a541f297 | bellard | int PPC_io_memory;
|
419 | 64201201 | bellard | int ret, linux_boot, i, nb_nics1, fd;
|
420 | 64201201 | bellard | unsigned long bios_offset; |
421 | 64201201 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
422 | 64201201 | bellard | |
423 | 64201201 | bellard | sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
424 | 64201201 | bellard | if (sysctrl == NULL) |
425 | 64201201 | bellard | return;
|
426 | a541f297 | bellard | |
427 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
428 | a541f297 | bellard | |
429 | a541f297 | bellard | /* allocate RAM */
|
430 | 64201201 | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
431 | 64201201 | bellard | |
432 | 64201201 | bellard | /* allocate and load BIOS */
|
433 | 64201201 | bellard | bios_offset = ram_size + vga_ram_size; |
434 | 64201201 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
435 | 64201201 | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
436 | 64201201 | bellard | if (ret != BIOS_SIZE) {
|
437 | 64201201 | bellard | fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
438 | 64201201 | bellard | exit(1);
|
439 | 64201201 | bellard | } |
440 | 64201201 | bellard | cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), |
441 | 64201201 | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
442 | 64201201 | bellard | cpu_single_env->nip = 0xfffffffc;
|
443 | 26aa7d72 | bellard | |
444 | a541f297 | bellard | if (linux_boot) {
|
445 | 64201201 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
446 | a541f297 | bellard | /* now we can load the kernel */
|
447 | 64201201 | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
448 | 64201201 | bellard | if (kernel_size < 0) { |
449 | a541f297 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
450 | a541f297 | bellard | kernel_filename); |
451 | a541f297 | bellard | exit(1);
|
452 | a541f297 | bellard | } |
453 | a541f297 | bellard | /* load initrd */
|
454 | a541f297 | bellard | if (initrd_filename) {
|
455 | 64201201 | bellard | initrd_base = INITRD_LOAD_ADDR; |
456 | 64201201 | bellard | initrd_size = load_image(initrd_filename, |
457 | 64201201 | bellard | phys_ram_base + initrd_base); |
458 | a541f297 | bellard | if (initrd_size < 0) { |
459 | a541f297 | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
460 | a541f297 | bellard | initrd_filename); |
461 | a541f297 | bellard | exit(1);
|
462 | a541f297 | bellard | } |
463 | 64201201 | bellard | } else {
|
464 | 64201201 | bellard | initrd_base = 0;
|
465 | 64201201 | bellard | initrd_size = 0;
|
466 | a541f297 | bellard | } |
467 | 64201201 | bellard | boot_device = 'm';
|
468 | a541f297 | bellard | } else {
|
469 | 64201201 | bellard | kernel_base = 0;
|
470 | 64201201 | bellard | kernel_size = 0;
|
471 | 64201201 | bellard | initrd_base = 0;
|
472 | 64201201 | bellard | initrd_size = 0;
|
473 | a541f297 | bellard | } |
474 | a541f297 | bellard | |
475 | a2a444d6 | bellard | /* Register CPU as a 74x/75x */
|
476 | a2a444d6 | bellard | cpu_ppc_register(cpu_single_env, 0x00080000);
|
477 | a2a444d6 | bellard | /* Set time-base frequency to 100 Mhz */
|
478 | 9fddaa0c | bellard | cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL); |
479 | 9fddaa0c | bellard | |
480 | 64201201 | bellard | isa_mem_base = 0xc0000000;
|
481 | 64201201 | bellard | pci_prep_init(); |
482 | 64201201 | bellard | /* Register 64 KB of ISA IO space */
|
483 | a4193c8a | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
484 | 64201201 | bellard | cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory); |
485 | 64201201 | bellard | |
486 | a541f297 | bellard | /* init basic PC hardware */
|
487 | a541f297 | bellard | vga_initialize(ds, phys_ram_base + ram_size, ram_size, |
488 | 64201201 | bellard | vga_ram_size, 1);
|
489 | a541f297 | bellard | rtc_init(0x70, 8); |
490 | 64201201 | bellard | // openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
491 | 64201201 | bellard | // pic_init(openpic);
|
492 | a541f297 | bellard | pic_init(); |
493 | 64201201 | bellard | // pit = pit_init(0x40, 0);
|
494 | a541f297 | bellard | |
495 | a541f297 | bellard | fd = serial_open_device(); |
496 | a541f297 | bellard | serial_init(0x3f8, 4, fd); |
497 | a541f297 | bellard | nb_nics1 = nb_nics; |
498 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
499 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
500 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
501 | 69b91039 | bellard | isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
502 | a541f297 | bellard | } |
503 | a541f297 | bellard | |
504 | a541f297 | bellard | for(i = 0; i < 2; i++) { |
505 | 69b91039 | bellard | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
506 | 69b91039 | bellard | bs_table[2 * i], bs_table[2 * i + 1]); |
507 | a541f297 | bellard | } |
508 | a541f297 | bellard | kbd_init(); |
509 | a541f297 | bellard | DMA_init(); |
510 | 64201201 | bellard | // AUD_init();
|
511 | a541f297 | bellard | // SB16_init();
|
512 | a541f297 | bellard | |
513 | a541f297 | bellard | fdctrl_init(6, 2, 0, 0x3f0, fd_table); |
514 | a541f297 | bellard | |
515 | 64201201 | bellard | /* Register speaker port */
|
516 | 64201201 | bellard | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
517 | 64201201 | bellard | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
518 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
519 | 64201201 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
520 | 64201201 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
521 | a541f297 | bellard | /* System control ports */
|
522 | 64201201 | bellard | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
523 | 64201201 | bellard | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
524 | 64201201 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
525 | 64201201 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
526 | 64201201 | bellard | /* PCI intack location */
|
527 | 64201201 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
528 | a4193c8a | bellard | PPC_intack_write, NULL);
|
529 | a541f297 | bellard | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
530 | 64201201 | bellard | /* PowerPC control and status register group */
|
531 | a4193c8a | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL); |
532 | 64201201 | bellard | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
533 | a541f297 | bellard | |
534 | 64201201 | bellard | nvram = m48t59_init(8, 0x0074, NVRAM_SIZE); |
535 | 64201201 | bellard | if (nvram == NULL) |
536 | 64201201 | bellard | return;
|
537 | 64201201 | bellard | sysctrl->nvram = nvram; |
538 | 64201201 | bellard | |
539 | 64201201 | bellard | /* Initialise NVRAM */
|
540 | 64201201 | bellard | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
|
541 | 64201201 | bellard | kernel_base, kernel_size, |
542 | 64201201 | bellard | (uint32_t)(long)kernel_cmdline,
|
543 | 64201201 | bellard | strlen(kernel_cmdline), |
544 | 64201201 | bellard | initrd_base, initrd_size, |
545 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
546 | 64201201 | bellard | 0
|
547 | 64201201 | bellard | ); |
548 | 64201201 | bellard | |
549 | 64201201 | bellard | /* Special port to get debug messages from Open-Firmware */
|
550 | 64201201 | bellard | register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL); |
551 | 64201201 | bellard | register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL); |
552 | 64201201 | bellard | |
553 | 64201201 | bellard | pci_ppc_bios_init(); |
554 | a541f297 | bellard | } |