root / hw / arm_gic.c @ 35ef81d6
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1 | 5fafdf24 | ths | /*
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2 | 9ee6e8bb | pbrook | * ARM Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 9ee6e8bb | pbrook | /* This file contains implementation code for the RealView EB interrupt
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11 | 9ee6e8bb | pbrook | controller, MPCore distributed interrupt controller and ARMv7-M
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12 | 9ee6e8bb | pbrook | Nested Vectored Interrupt Controller. */
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13 | e69954b9 | pbrook | |
14 | e69954b9 | pbrook | //#define DEBUG_GIC
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15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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17 | e69954b9 | pbrook | #define DPRINTF(fmt, args...) \
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18 | df628ff1 | pbrook | do { printf("arm_gic: " fmt , ##args); } while (0) |
19 | e69954b9 | pbrook | #else
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20 | e69954b9 | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
21 | e69954b9 | pbrook | #endif
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22 | e69954b9 | pbrook | |
23 | 9ee6e8bb | pbrook | #ifdef NVIC
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24 | 9ee6e8bb | pbrook | static const uint8_t gic_id[] = |
25 | 9ee6e8bb | pbrook | { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; |
26 | 9ee6e8bb | pbrook | /* The NVIC has 16 internal vectors. However these are not exposed
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27 | 9ee6e8bb | pbrook | through the normal GIC interface. */
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28 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 32 |
29 | 9ee6e8bb | pbrook | #else
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30 | e69954b9 | pbrook | static const uint8_t gic_id[] = |
31 | e69954b9 | pbrook | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
32 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 0 |
33 | 9ee6e8bb | pbrook | #endif
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34 | e69954b9 | pbrook | |
35 | e69954b9 | pbrook | typedef struct gic_irq_state |
36 | e69954b9 | pbrook | { |
37 | 9ee6e8bb | pbrook | /* ??? The documentation seems to imply the enable bits are global, even
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38 | 9ee6e8bb | pbrook | for per-cpu interrupts. This seems strange. */
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39 | e69954b9 | pbrook | unsigned enabled:1; |
40 | 9ee6e8bb | pbrook | unsigned pending:NCPU;
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41 | 9ee6e8bb | pbrook | unsigned active:NCPU;
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42 | e69954b9 | pbrook | unsigned level:1; |
43 | 9ee6e8bb | pbrook | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
44 | e69954b9 | pbrook | unsigned trigger:1; /* nonzero = edge triggered. */ |
45 | e69954b9 | pbrook | } gic_irq_state; |
46 | e69954b9 | pbrook | |
47 | 9ee6e8bb | pbrook | #define ALL_CPU_MASK ((1 << NCPU) - 1) |
48 | 9ee6e8bb | pbrook | |
49 | e69954b9 | pbrook | #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 |
50 | e69954b9 | pbrook | #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 |
51 | e69954b9 | pbrook | #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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52 | 9ee6e8bb | pbrook | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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53 | 9ee6e8bb | pbrook | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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54 | 9ee6e8bb | pbrook | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
55 | 9ee6e8bb | pbrook | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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56 | 9ee6e8bb | pbrook | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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57 | 9ee6e8bb | pbrook | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
58 | e69954b9 | pbrook | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
59 | e69954b9 | pbrook | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
60 | e69954b9 | pbrook | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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61 | 9ee6e8bb | pbrook | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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62 | 9ee6e8bb | pbrook | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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63 | 57d69a91 | balrog | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
64 | e69954b9 | pbrook | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
65 | e69954b9 | pbrook | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
66 | e69954b9 | pbrook | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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67 | 9ee6e8bb | pbrook | #define GIC_GET_PRIORITY(irq, cpu) \
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68 | 9ee6e8bb | pbrook | (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32]) |
69 | 9ee6e8bb | pbrook | #ifdef NVIC
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70 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) 1 |
71 | 9ee6e8bb | pbrook | #else
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72 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) s->irq_target[irq]
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73 | 9ee6e8bb | pbrook | #endif
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74 | e69954b9 | pbrook | |
75 | e69954b9 | pbrook | typedef struct gic_state |
76 | e69954b9 | pbrook | { |
77 | 9ee6e8bb | pbrook | qemu_irq parent_irq[NCPU]; |
78 | e69954b9 | pbrook | int enabled;
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79 | 9ee6e8bb | pbrook | int cpu_enabled[NCPU];
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80 | e69954b9 | pbrook | |
81 | e69954b9 | pbrook | gic_irq_state irq_state[GIC_NIRQ]; |
82 | 9ee6e8bb | pbrook | #ifndef NVIC
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83 | e69954b9 | pbrook | int irq_target[GIC_NIRQ];
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84 | 9ee6e8bb | pbrook | #endif
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85 | 9ee6e8bb | pbrook | int priority1[32][NCPU]; |
86 | 9ee6e8bb | pbrook | int priority2[GIC_NIRQ - 32]; |
87 | 9ee6e8bb | pbrook | int last_active[GIC_NIRQ][NCPU];
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88 | 9ee6e8bb | pbrook | |
89 | 9ee6e8bb | pbrook | int priority_mask[NCPU];
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90 | 9ee6e8bb | pbrook | int running_irq[NCPU];
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91 | 9ee6e8bb | pbrook | int running_priority[NCPU];
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92 | 9ee6e8bb | pbrook | int current_pending[NCPU];
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93 | 9ee6e8bb | pbrook | |
94 | 9ee6e8bb | pbrook | qemu_irq *in; |
95 | 9ee6e8bb | pbrook | #ifdef NVIC
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96 | 9ee6e8bb | pbrook | void *nvic;
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97 | 9ee6e8bb | pbrook | #endif
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98 | e69954b9 | pbrook | } gic_state; |
99 | e69954b9 | pbrook | |
100 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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101 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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102 | e69954b9 | pbrook | static void gic_update(gic_state *s) |
103 | e69954b9 | pbrook | { |
104 | e69954b9 | pbrook | int best_irq;
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105 | e69954b9 | pbrook | int best_prio;
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106 | e69954b9 | pbrook | int irq;
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107 | 9ee6e8bb | pbrook | int level;
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108 | 9ee6e8bb | pbrook | int cpu;
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109 | 9ee6e8bb | pbrook | int cm;
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110 | 9ee6e8bb | pbrook | |
111 | 9ee6e8bb | pbrook | for (cpu = 0; cpu < NCPU; cpu++) { |
112 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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113 | 9ee6e8bb | pbrook | s->current_pending[cpu] = 1023;
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114 | 9ee6e8bb | pbrook | if (!s->enabled || !s->cpu_enabled[cpu]) {
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115 | 9ee6e8bb | pbrook | qemu_irq_lower(s->parent_irq[cpu]); |
116 | 9ee6e8bb | pbrook | return;
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117 | 9ee6e8bb | pbrook | } |
118 | 9ee6e8bb | pbrook | best_prio = 0x100;
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119 | 9ee6e8bb | pbrook | best_irq = 1023;
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120 | 9ee6e8bb | pbrook | for (irq = 0; irq < GIC_NIRQ; irq++) { |
121 | 9ee6e8bb | pbrook | if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq, cm)) {
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122 | 9ee6e8bb | pbrook | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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123 | 9ee6e8bb | pbrook | best_prio = GIC_GET_PRIORITY(irq, cpu); |
124 | 9ee6e8bb | pbrook | best_irq = irq; |
125 | 9ee6e8bb | pbrook | } |
126 | e69954b9 | pbrook | } |
127 | e69954b9 | pbrook | } |
128 | 9ee6e8bb | pbrook | level = 0;
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129 | 9ee6e8bb | pbrook | if (best_prio <= s->priority_mask[cpu]) {
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130 | 9ee6e8bb | pbrook | s->current_pending[cpu] = best_irq; |
131 | 9ee6e8bb | pbrook | if (best_prio < s->running_priority[cpu]) {
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132 | 9ee6e8bb | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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133 | 9ee6e8bb | pbrook | level = 1;
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134 | 9ee6e8bb | pbrook | } |
135 | e69954b9 | pbrook | } |
136 | 9ee6e8bb | pbrook | qemu_set_irq(s->parent_irq[cpu], level); |
137 | e69954b9 | pbrook | } |
138 | e69954b9 | pbrook | } |
139 | e69954b9 | pbrook | |
140 | 9ee6e8bb | pbrook | static void __attribute__((unused)) |
141 | 9ee6e8bb | pbrook | gic_set_pending_private(gic_state *s, int cpu, int irq) |
142 | 9ee6e8bb | pbrook | { |
143 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
144 | 9ee6e8bb | pbrook | |
145 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq, cm))
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146 | 9ee6e8bb | pbrook | return;
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147 | 9ee6e8bb | pbrook | |
148 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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149 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
150 | 9ee6e8bb | pbrook | gic_update(s); |
151 | 9ee6e8bb | pbrook | } |
152 | 9ee6e8bb | pbrook | |
153 | 9ee6e8bb | pbrook | /* Process a change in an external IRQ input. */
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154 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
155 | e69954b9 | pbrook | { |
156 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
157 | e69954b9 | pbrook | /* The first external input line is internal interrupt 32. */
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158 | e69954b9 | pbrook | irq += 32;
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159 | 9ee6e8bb | pbrook | if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
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160 | e69954b9 | pbrook | return;
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161 | e69954b9 | pbrook | |
162 | e69954b9 | pbrook | if (level) {
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163 | 9ee6e8bb | pbrook | GIC_SET_LEVEL(irq, ALL_CPU_MASK); |
164 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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165 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
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166 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, GIC_TARGET(irq)); |
167 | e69954b9 | pbrook | } |
168 | e69954b9 | pbrook | } else {
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169 | 9ee6e8bb | pbrook | GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK); |
170 | e69954b9 | pbrook | } |
171 | e69954b9 | pbrook | gic_update(s); |
172 | e69954b9 | pbrook | } |
173 | e69954b9 | pbrook | |
174 | 9ee6e8bb | pbrook | static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
175 | e69954b9 | pbrook | { |
176 | 9ee6e8bb | pbrook | s->running_irq[cpu] = irq; |
177 | 9ee6e8bb | pbrook | if (irq == 1023) { |
178 | 9ee6e8bb | pbrook | s->running_priority[cpu] = 0x100;
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179 | 9ee6e8bb | pbrook | } else {
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180 | 9ee6e8bb | pbrook | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
181 | 9ee6e8bb | pbrook | } |
182 | e69954b9 | pbrook | gic_update(s); |
183 | e69954b9 | pbrook | } |
184 | e69954b9 | pbrook | |
185 | 9ee6e8bb | pbrook | static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
186 | e69954b9 | pbrook | { |
187 | e69954b9 | pbrook | int new_irq;
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188 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
189 | 9ee6e8bb | pbrook | new_irq = s->current_pending[cpu]; |
190 | 9ee6e8bb | pbrook | if (new_irq == 1023 |
191 | 9ee6e8bb | pbrook | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
192 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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193 | e69954b9 | pbrook | return 1023; |
194 | e69954b9 | pbrook | } |
195 | 9ee6e8bb | pbrook | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
196 | 9ee6e8bb | pbrook | /* Clear pending flags for both level and edge triggered interrupts.
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197 | 9ee6e8bb | pbrook | Level triggered IRQs will be reasserted once they become inactive. */
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198 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
199 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, new_irq); |
200 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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201 | e69954b9 | pbrook | return new_irq;
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202 | e69954b9 | pbrook | } |
203 | e69954b9 | pbrook | |
204 | 9ee6e8bb | pbrook | static void gic_complete_irq(gic_state * s, int cpu, int irq) |
205 | e69954b9 | pbrook | { |
206 | e69954b9 | pbrook | int update = 0; |
207 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
208 | df628ff1 | pbrook | DPRINTF("EOI %d\n", irq);
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209 | 9ee6e8bb | pbrook | if (s->running_irq[cpu] == 1023) |
210 | e69954b9 | pbrook | return; /* No active IRQ. */ |
211 | e69954b9 | pbrook | if (irq != 1023) { |
212 | e69954b9 | pbrook | /* Mark level triggered interrupts as pending if they are still
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213 | e69954b9 | pbrook | raised. */
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214 | e69954b9 | pbrook | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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215 | 9ee6e8bb | pbrook | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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216 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, cm);
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217 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
218 | e69954b9 | pbrook | update = 1;
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219 | e69954b9 | pbrook | } |
220 | e69954b9 | pbrook | } |
221 | 9ee6e8bb | pbrook | if (irq != s->running_irq[cpu]) {
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222 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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223 | 9ee6e8bb | pbrook | int tmp = s->running_irq[cpu];
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224 | 9ee6e8bb | pbrook | while (s->last_active[tmp][cpu] != 1023) { |
225 | 9ee6e8bb | pbrook | if (s->last_active[tmp][cpu] == irq) {
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226 | 9ee6e8bb | pbrook | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
227 | e69954b9 | pbrook | break;
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228 | e69954b9 | pbrook | } |
229 | 9ee6e8bb | pbrook | tmp = s->last_active[tmp][cpu]; |
230 | e69954b9 | pbrook | } |
231 | e69954b9 | pbrook | if (update) {
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232 | e69954b9 | pbrook | gic_update(s); |
233 | e69954b9 | pbrook | } |
234 | e69954b9 | pbrook | } else {
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235 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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236 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
237 | e69954b9 | pbrook | } |
238 | e69954b9 | pbrook | } |
239 | e69954b9 | pbrook | |
240 | e69954b9 | pbrook | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
241 | e69954b9 | pbrook | { |
242 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
243 | e69954b9 | pbrook | uint32_t res; |
244 | e69954b9 | pbrook | int irq;
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245 | e69954b9 | pbrook | int i;
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246 | 9ee6e8bb | pbrook | int cpu;
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247 | 9ee6e8bb | pbrook | int cm;
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248 | 9ee6e8bb | pbrook | int mask;
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249 | e69954b9 | pbrook | |
250 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
251 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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252 | e69954b9 | pbrook | if (offset < 0x100) { |
253 | 9ee6e8bb | pbrook | #ifndef NVIC
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254 | e69954b9 | pbrook | if (offset == 0) |
255 | e69954b9 | pbrook | return s->enabled;
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256 | e69954b9 | pbrook | if (offset == 4) |
257 | 9ee6e8bb | pbrook | return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5); |
258 | e69954b9 | pbrook | if (offset < 0x08) |
259 | e69954b9 | pbrook | return 0; |
260 | 9ee6e8bb | pbrook | #endif
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261 | e69954b9 | pbrook | goto bad_reg;
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262 | e69954b9 | pbrook | } else if (offset < 0x200) { |
263 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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264 | e69954b9 | pbrook | if (offset < 0x180) |
265 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
266 | e69954b9 | pbrook | else
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267 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
268 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
269 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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270 | e69954b9 | pbrook | goto bad_reg;
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271 | e69954b9 | pbrook | res = 0;
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272 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
273 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i)) {
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274 | e69954b9 | pbrook | res |= (1 << i);
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275 | e69954b9 | pbrook | } |
276 | e69954b9 | pbrook | } |
277 | e69954b9 | pbrook | } else if (offset < 0x300) { |
278 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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279 | e69954b9 | pbrook | if (offset < 0x280) |
280 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
281 | e69954b9 | pbrook | else
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282 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
283 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
284 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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285 | e69954b9 | pbrook | goto bad_reg;
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286 | e69954b9 | pbrook | res = 0;
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287 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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288 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
289 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq + i, mask)) {
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290 | e69954b9 | pbrook | res |= (1 << i);
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291 | e69954b9 | pbrook | } |
292 | e69954b9 | pbrook | } |
293 | e69954b9 | pbrook | } else if (offset < 0x400) { |
294 | e69954b9 | pbrook | /* Interrupt Active. */
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295 | 9ee6e8bb | pbrook | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
296 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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297 | e69954b9 | pbrook | goto bad_reg;
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298 | e69954b9 | pbrook | res = 0;
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299 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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300 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
301 | 9ee6e8bb | pbrook | if (GIC_TEST_ACTIVE(irq + i, mask)) {
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302 | e69954b9 | pbrook | res |= (1 << i);
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303 | e69954b9 | pbrook | } |
304 | e69954b9 | pbrook | } |
305 | e69954b9 | pbrook | } else if (offset < 0x800) { |
306 | e69954b9 | pbrook | /* Interrupt Priority. */
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307 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
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308 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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309 | e69954b9 | pbrook | goto bad_reg;
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310 | 9ee6e8bb | pbrook | res = GIC_GET_PRIORITY(irq, cpu); |
311 | 9ee6e8bb | pbrook | #ifndef NVIC
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312 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
313 | e69954b9 | pbrook | /* Interrupt CPU Target. */
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314 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
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315 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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316 | e69954b9 | pbrook | goto bad_reg;
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317 | 9ee6e8bb | pbrook | if (irq >= 29 && irq <= 31) { |
318 | 9ee6e8bb | pbrook | res = cm; |
319 | 9ee6e8bb | pbrook | } else {
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320 | 9ee6e8bb | pbrook | res = GIC_TARGET(irq); |
321 | 9ee6e8bb | pbrook | } |
322 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
323 | e69954b9 | pbrook | /* Interrupt Configuration. */
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324 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
325 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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326 | e69954b9 | pbrook | goto bad_reg;
|
327 | e69954b9 | pbrook | res = 0;
|
328 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
329 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
|
330 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
331 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
|
332 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
333 | e69954b9 | pbrook | } |
334 | 9ee6e8bb | pbrook | #endif
|
335 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
336 | e69954b9 | pbrook | goto bad_reg;
|
337 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
338 | e69954b9 | pbrook | if (offset & 3) { |
339 | e69954b9 | pbrook | res = 0;
|
340 | e69954b9 | pbrook | } else {
|
341 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
342 | e69954b9 | pbrook | } |
343 | e69954b9 | pbrook | } |
344 | e69954b9 | pbrook | return res;
|
345 | e69954b9 | pbrook | bad_reg:
|
346 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset); |
347 | e69954b9 | pbrook | return 0; |
348 | e69954b9 | pbrook | } |
349 | e69954b9 | pbrook | |
350 | e69954b9 | pbrook | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
351 | e69954b9 | pbrook | { |
352 | e69954b9 | pbrook | uint32_t val; |
353 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
354 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
355 | e69954b9 | pbrook | return val;
|
356 | e69954b9 | pbrook | } |
357 | e69954b9 | pbrook | |
358 | e69954b9 | pbrook | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
359 | e69954b9 | pbrook | { |
360 | e69954b9 | pbrook | uint32_t val; |
361 | 9ee6e8bb | pbrook | #ifdef NVIC
|
362 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
363 | 9ee6e8bb | pbrook | uint32_t addr; |
364 | 8da3ff18 | pbrook | addr = offset; |
365 | 9ee6e8bb | pbrook | if (addr < 0x100 || addr > 0xd00) |
366 | 9ee6e8bb | pbrook | return nvic_readl(s->nvic, addr);
|
367 | 9ee6e8bb | pbrook | #endif
|
368 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
369 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
370 | e69954b9 | pbrook | return val;
|
371 | e69954b9 | pbrook | } |
372 | e69954b9 | pbrook | |
373 | e69954b9 | pbrook | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
374 | e69954b9 | pbrook | uint32_t value) |
375 | e69954b9 | pbrook | { |
376 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
377 | e69954b9 | pbrook | int irq;
|
378 | e69954b9 | pbrook | int i;
|
379 | 9ee6e8bb | pbrook | int cpu;
|
380 | e69954b9 | pbrook | |
381 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
382 | e69954b9 | pbrook | if (offset < 0x100) { |
383 | 9ee6e8bb | pbrook | #ifdef NVIC
|
384 | 9ee6e8bb | pbrook | goto bad_reg;
|
385 | 9ee6e8bb | pbrook | #else
|
386 | e69954b9 | pbrook | if (offset == 0) { |
387 | e69954b9 | pbrook | s->enabled = (value & 1);
|
388 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
389 | e69954b9 | pbrook | } else if (offset < 4) { |
390 | e69954b9 | pbrook | /* ignored. */
|
391 | e69954b9 | pbrook | } else {
|
392 | e69954b9 | pbrook | goto bad_reg;
|
393 | e69954b9 | pbrook | } |
394 | 9ee6e8bb | pbrook | #endif
|
395 | e69954b9 | pbrook | } else if (offset < 0x180) { |
396 | e69954b9 | pbrook | /* Interrupt Set Enable. */
|
397 | 9ee6e8bb | pbrook | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
398 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
399 | e69954b9 | pbrook | goto bad_reg;
|
400 | 9ee6e8bb | pbrook | if (irq < 16) |
401 | 9ee6e8bb | pbrook | value = 0xff;
|
402 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
403 | e69954b9 | pbrook | if (value & (1 << i)) { |
404 | 9ee6e8bb | pbrook | int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq); |
405 | e69954b9 | pbrook | if (!GIC_TEST_ENABLED(irq + i))
|
406 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
|
407 | e69954b9 | pbrook | GIC_SET_ENABLED(irq + i); |
408 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
|
409 | e69954b9 | pbrook | is as pending. */
|
410 | 9ee6e8bb | pbrook | if (GIC_TEST_LEVEL(irq + i, mask)
|
411 | 9ee6e8bb | pbrook | && !GIC_TEST_TRIGGER(irq + i)) { |
412 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
413 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, mask); |
414 | 9ee6e8bb | pbrook | } |
415 | e69954b9 | pbrook | } |
416 | e69954b9 | pbrook | } |
417 | e69954b9 | pbrook | } else if (offset < 0x200) { |
418 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
|
419 | 9ee6e8bb | pbrook | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
420 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
421 | e69954b9 | pbrook | goto bad_reg;
|
422 | 9ee6e8bb | pbrook | if (irq < 16) |
423 | 9ee6e8bb | pbrook | value = 0;
|
424 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
425 | e69954b9 | pbrook | if (value & (1 << i)) { |
426 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i))
|
427 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
428 | e69954b9 | pbrook | GIC_CLEAR_ENABLED(irq + i); |
429 | e69954b9 | pbrook | } |
430 | e69954b9 | pbrook | } |
431 | e69954b9 | pbrook | } else if (offset < 0x280) { |
432 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
433 | 9ee6e8bb | pbrook | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
434 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
435 | e69954b9 | pbrook | goto bad_reg;
|
436 | 9ee6e8bb | pbrook | if (irq < 16) |
437 | 9ee6e8bb | pbrook | irq = 0;
|
438 | 9ee6e8bb | pbrook | |
439 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
440 | e69954b9 | pbrook | if (value & (1 << i)) { |
441 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
442 | e69954b9 | pbrook | } |
443 | e69954b9 | pbrook | } |
444 | e69954b9 | pbrook | } else if (offset < 0x300) { |
445 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
446 | 9ee6e8bb | pbrook | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
447 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
448 | e69954b9 | pbrook | goto bad_reg;
|
449 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
450 | 9ee6e8bb | pbrook | /* ??? This currently clears the pending bit for all CPUs, even
|
451 | 9ee6e8bb | pbrook | for per-CPU interrupts. It's unclear whether this is the
|
452 | 9ee6e8bb | pbrook | corect behavior. */
|
453 | e69954b9 | pbrook | if (value & (1 << i)) { |
454 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
455 | e69954b9 | pbrook | } |
456 | e69954b9 | pbrook | } |
457 | e69954b9 | pbrook | } else if (offset < 0x400) { |
458 | e69954b9 | pbrook | /* Interrupt Active. */
|
459 | e69954b9 | pbrook | goto bad_reg;
|
460 | e69954b9 | pbrook | } else if (offset < 0x800) { |
461 | e69954b9 | pbrook | /* Interrupt Priority. */
|
462 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
463 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
464 | e69954b9 | pbrook | goto bad_reg;
|
465 | 9ee6e8bb | pbrook | if (irq < 32) { |
466 | 9ee6e8bb | pbrook | s->priority1[irq][cpu] = value; |
467 | 9ee6e8bb | pbrook | } else {
|
468 | 9ee6e8bb | pbrook | s->priority2[irq - 32] = value;
|
469 | 9ee6e8bb | pbrook | } |
470 | 9ee6e8bb | pbrook | #ifndef NVIC
|
471 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
472 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
473 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
474 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
475 | e69954b9 | pbrook | goto bad_reg;
|
476 | 9ee6e8bb | pbrook | if (irq < 29) |
477 | 9ee6e8bb | pbrook | value = 0;
|
478 | 9ee6e8bb | pbrook | else if (irq < 32) |
479 | 9ee6e8bb | pbrook | value = ALL_CPU_MASK; |
480 | 9ee6e8bb | pbrook | s->irq_target[irq] = value & ALL_CPU_MASK; |
481 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
482 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
483 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
484 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
485 | e69954b9 | pbrook | goto bad_reg;
|
486 | 9ee6e8bb | pbrook | if (irq < 32) |
487 | 9ee6e8bb | pbrook | value |= 0xaa;
|
488 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
489 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
490 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
491 | e69954b9 | pbrook | } else {
|
492 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
493 | e69954b9 | pbrook | } |
494 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
495 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
496 | e69954b9 | pbrook | } else {
|
497 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
498 | e69954b9 | pbrook | } |
499 | e69954b9 | pbrook | } |
500 | 9ee6e8bb | pbrook | #endif
|
501 | e69954b9 | pbrook | } else {
|
502 | 9ee6e8bb | pbrook | /* 0xf00 is only handled for 32-bit writes. */
|
503 | e69954b9 | pbrook | goto bad_reg;
|
504 | e69954b9 | pbrook | } |
505 | e69954b9 | pbrook | gic_update(s); |
506 | e69954b9 | pbrook | return;
|
507 | e69954b9 | pbrook | bad_reg:
|
508 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset); |
509 | e69954b9 | pbrook | } |
510 | e69954b9 | pbrook | |
511 | e69954b9 | pbrook | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
512 | e69954b9 | pbrook | uint32_t value) |
513 | e69954b9 | pbrook | { |
514 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
515 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
516 | e69954b9 | pbrook | } |
517 | e69954b9 | pbrook | |
518 | e69954b9 | pbrook | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
519 | e69954b9 | pbrook | uint32_t value) |
520 | e69954b9 | pbrook | { |
521 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
522 | 9ee6e8bb | pbrook | #ifdef NVIC
|
523 | 9ee6e8bb | pbrook | uint32_t addr; |
524 | 8da3ff18 | pbrook | addr = offset; |
525 | 9ee6e8bb | pbrook | if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
526 | 9ee6e8bb | pbrook | nvic_writel(s->nvic, addr, value); |
527 | 9ee6e8bb | pbrook | return;
|
528 | 9ee6e8bb | pbrook | } |
529 | 9ee6e8bb | pbrook | #endif
|
530 | 8da3ff18 | pbrook | if (offset == 0xf00) { |
531 | 9ee6e8bb | pbrook | int cpu;
|
532 | 9ee6e8bb | pbrook | int irq;
|
533 | 9ee6e8bb | pbrook | int mask;
|
534 | 9ee6e8bb | pbrook | |
535 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
536 | 9ee6e8bb | pbrook | irq = value & 0x3ff;
|
537 | 9ee6e8bb | pbrook | switch ((value >> 24) & 3) { |
538 | 9ee6e8bb | pbrook | case 0: |
539 | 9ee6e8bb | pbrook | mask = (value >> 16) & ALL_CPU_MASK;
|
540 | 9ee6e8bb | pbrook | break;
|
541 | 9ee6e8bb | pbrook | case 1: |
542 | 9ee6e8bb | pbrook | mask = 1 << cpu;
|
543 | 9ee6e8bb | pbrook | break;
|
544 | 9ee6e8bb | pbrook | case 2: |
545 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK ^ (1 << cpu);
|
546 | 9ee6e8bb | pbrook | break;
|
547 | 9ee6e8bb | pbrook | default:
|
548 | 9ee6e8bb | pbrook | DPRINTF("Bad Soft Int target filter\n");
|
549 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK; |
550 | 9ee6e8bb | pbrook | break;
|
551 | 9ee6e8bb | pbrook | } |
552 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, mask); |
553 | 9ee6e8bb | pbrook | gic_update(s); |
554 | 9ee6e8bb | pbrook | return;
|
555 | 9ee6e8bb | pbrook | } |
556 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
557 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
558 | e69954b9 | pbrook | } |
559 | e69954b9 | pbrook | |
560 | e69954b9 | pbrook | static CPUReadMemoryFunc *gic_dist_readfn[] = {
|
561 | e69954b9 | pbrook | gic_dist_readb, |
562 | e69954b9 | pbrook | gic_dist_readw, |
563 | e69954b9 | pbrook | gic_dist_readl |
564 | e69954b9 | pbrook | }; |
565 | e69954b9 | pbrook | |
566 | e69954b9 | pbrook | static CPUWriteMemoryFunc *gic_dist_writefn[] = {
|
567 | e69954b9 | pbrook | gic_dist_writeb, |
568 | e69954b9 | pbrook | gic_dist_writew, |
569 | e69954b9 | pbrook | gic_dist_writel |
570 | e69954b9 | pbrook | }; |
571 | e69954b9 | pbrook | |
572 | 9ee6e8bb | pbrook | #ifndef NVIC
|
573 | 9ee6e8bb | pbrook | static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) |
574 | e69954b9 | pbrook | { |
575 | e69954b9 | pbrook | switch (offset) {
|
576 | e69954b9 | pbrook | case 0x00: /* Control */ |
577 | 9ee6e8bb | pbrook | return s->cpu_enabled[cpu];
|
578 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
579 | 9ee6e8bb | pbrook | return s->priority_mask[cpu];
|
580 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
581 | e69954b9 | pbrook | /* ??? Not implemented. */
|
582 | e69954b9 | pbrook | return 0; |
583 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
584 | 9ee6e8bb | pbrook | return gic_acknowledge_irq(s, cpu);
|
585 | e69954b9 | pbrook | case 0x14: /* Runing Priority */ |
586 | 9ee6e8bb | pbrook | return s->running_priority[cpu];
|
587 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
588 | 9ee6e8bb | pbrook | return s->current_pending[cpu];
|
589 | e69954b9 | pbrook | default:
|
590 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
|
591 | 9ee6e8bb | pbrook | (int)offset);
|
592 | e69954b9 | pbrook | return 0; |
593 | e69954b9 | pbrook | } |
594 | e69954b9 | pbrook | } |
595 | e69954b9 | pbrook | |
596 | 9ee6e8bb | pbrook | static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
597 | e69954b9 | pbrook | { |
598 | e69954b9 | pbrook | switch (offset) {
|
599 | e69954b9 | pbrook | case 0x00: /* Control */ |
600 | 9ee6e8bb | pbrook | s->cpu_enabled[cpu] = (value & 1);
|
601 | e69954b9 | pbrook | DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis"); |
602 | e69954b9 | pbrook | break;
|
603 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
604 | 9ee6e8bb | pbrook | s->priority_mask[cpu] = (value & 0xff);
|
605 | e69954b9 | pbrook | break;
|
606 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
607 | e69954b9 | pbrook | /* ??? Not implemented. */
|
608 | e69954b9 | pbrook | break;
|
609 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
610 | 9ee6e8bb | pbrook | return gic_complete_irq(s, cpu, value & 0x3ff); |
611 | e69954b9 | pbrook | default:
|
612 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
|
613 | 9ee6e8bb | pbrook | (int)offset);
|
614 | e69954b9 | pbrook | return;
|
615 | e69954b9 | pbrook | } |
616 | e69954b9 | pbrook | gic_update(s); |
617 | e69954b9 | pbrook | } |
618 | 9ee6e8bb | pbrook | #endif
|
619 | e69954b9 | pbrook | |
620 | e69954b9 | pbrook | static void gic_reset(gic_state *s) |
621 | e69954b9 | pbrook | { |
622 | e69954b9 | pbrook | int i;
|
623 | e69954b9 | pbrook | memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); |
624 | 9ee6e8bb | pbrook | for (i = 0 ; i < NCPU; i++) { |
625 | 9ee6e8bb | pbrook | s->priority_mask[i] = 0xf0;
|
626 | 9ee6e8bb | pbrook | s->current_pending[i] = 1023;
|
627 | 9ee6e8bb | pbrook | s->running_irq[i] = 1023;
|
628 | 9ee6e8bb | pbrook | s->running_priority[i] = 0x100;
|
629 | 9ee6e8bb | pbrook | #ifdef NVIC
|
630 | 9ee6e8bb | pbrook | /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
631 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 1;
|
632 | 9ee6e8bb | pbrook | #else
|
633 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 0;
|
634 | 9ee6e8bb | pbrook | #endif
|
635 | 9ee6e8bb | pbrook | } |
636 | e57ec016 | pbrook | for (i = 0; i < 16; i++) { |
637 | e69954b9 | pbrook | GIC_SET_ENABLED(i); |
638 | e69954b9 | pbrook | GIC_SET_TRIGGER(i); |
639 | e69954b9 | pbrook | } |
640 | 9ee6e8bb | pbrook | #ifdef NVIC
|
641 | 9ee6e8bb | pbrook | /* The NVIC is always enabled. */
|
642 | 9ee6e8bb | pbrook | s->enabled = 1;
|
643 | 9ee6e8bb | pbrook | #else
|
644 | e69954b9 | pbrook | s->enabled = 0;
|
645 | 9ee6e8bb | pbrook | #endif
|
646 | e69954b9 | pbrook | } |
647 | e69954b9 | pbrook | |
648 | 23e39294 | pbrook | static void gic_save(QEMUFile *f, void *opaque) |
649 | 23e39294 | pbrook | { |
650 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
651 | 23e39294 | pbrook | int i;
|
652 | 23e39294 | pbrook | int j;
|
653 | 23e39294 | pbrook | |
654 | 23e39294 | pbrook | qemu_put_be32(f, s->enabled); |
655 | 23e39294 | pbrook | for (i = 0; i < NCPU; i++) { |
656 | 23e39294 | pbrook | qemu_put_be32(f, s->cpu_enabled[i]); |
657 | 23e39294 | pbrook | #ifndef NVIC
|
658 | 23e39294 | pbrook | qemu_put_be32(f, s->irq_target[i]); |
659 | 23e39294 | pbrook | #endif
|
660 | 23e39294 | pbrook | for (j = 0; j < 32; j++) |
661 | 23e39294 | pbrook | qemu_put_be32(f, s->priority1[j][i]); |
662 | 23e39294 | pbrook | for (j = 0; j < GIC_NIRQ; j++) |
663 | 23e39294 | pbrook | qemu_put_be32(f, s->last_active[j][i]); |
664 | 23e39294 | pbrook | qemu_put_be32(f, s->priority_mask[i]); |
665 | 23e39294 | pbrook | qemu_put_be32(f, s->running_irq[i]); |
666 | 23e39294 | pbrook | qemu_put_be32(f, s->running_priority[i]); |
667 | 23e39294 | pbrook | qemu_put_be32(f, s->current_pending[i]); |
668 | 23e39294 | pbrook | } |
669 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ - 32; i++) { |
670 | 23e39294 | pbrook | qemu_put_be32(f, s->priority2[i]); |
671 | 23e39294 | pbrook | } |
672 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ; i++) { |
673 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].enabled); |
674 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].pending); |
675 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].active); |
676 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].level); |
677 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].model); |
678 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].trigger); |
679 | 23e39294 | pbrook | } |
680 | 23e39294 | pbrook | } |
681 | 23e39294 | pbrook | |
682 | 23e39294 | pbrook | static int gic_load(QEMUFile *f, void *opaque, int version_id) |
683 | 23e39294 | pbrook | { |
684 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
685 | 23e39294 | pbrook | int i;
|
686 | 23e39294 | pbrook | int j;
|
687 | 23e39294 | pbrook | |
688 | 23e39294 | pbrook | if (version_id != 1) |
689 | 23e39294 | pbrook | return -EINVAL;
|
690 | 23e39294 | pbrook | |
691 | 23e39294 | pbrook | s->enabled = qemu_get_be32(f); |
692 | 23e39294 | pbrook | for (i = 0; i < NCPU; i++) { |
693 | 23e39294 | pbrook | s->cpu_enabled[i] = qemu_get_be32(f); |
694 | 23e39294 | pbrook | #ifndef NVIC
|
695 | 23e39294 | pbrook | s->irq_target[i] = qemu_get_be32(f); |
696 | 23e39294 | pbrook | #endif
|
697 | 23e39294 | pbrook | for (j = 0; j < 32; j++) |
698 | 23e39294 | pbrook | s->priority1[j][i] = qemu_get_be32(f); |
699 | 23e39294 | pbrook | for (j = 0; j < GIC_NIRQ; j++) |
700 | 23e39294 | pbrook | s->last_active[j][i] = qemu_get_be32(f); |
701 | 23e39294 | pbrook | s->priority_mask[i] = qemu_get_be32(f); |
702 | 23e39294 | pbrook | s->running_irq[i] = qemu_get_be32(f); |
703 | 23e39294 | pbrook | s->running_priority[i] = qemu_get_be32(f); |
704 | 23e39294 | pbrook | s->current_pending[i] = qemu_get_be32(f); |
705 | 23e39294 | pbrook | } |
706 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ - 32; i++) { |
707 | 23e39294 | pbrook | s->priority2[i] = qemu_get_be32(f); |
708 | 23e39294 | pbrook | } |
709 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ; i++) { |
710 | 23e39294 | pbrook | s->irq_state[i].enabled = qemu_get_byte(f); |
711 | 23e39294 | pbrook | s->irq_state[i].pending = qemu_get_byte(f); |
712 | 23e39294 | pbrook | s->irq_state[i].active = qemu_get_byte(f); |
713 | 23e39294 | pbrook | s->irq_state[i].level = qemu_get_byte(f); |
714 | 23e39294 | pbrook | s->irq_state[i].model = qemu_get_byte(f); |
715 | 23e39294 | pbrook | s->irq_state[i].trigger = qemu_get_byte(f); |
716 | 23e39294 | pbrook | } |
717 | 23e39294 | pbrook | |
718 | 23e39294 | pbrook | return 0; |
719 | 23e39294 | pbrook | } |
720 | 23e39294 | pbrook | |
721 | 8da3ff18 | pbrook | static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
|
722 | e69954b9 | pbrook | { |
723 | e69954b9 | pbrook | gic_state *s; |
724 | e69954b9 | pbrook | int iomemtype;
|
725 | 9ee6e8bb | pbrook | int i;
|
726 | e69954b9 | pbrook | |
727 | e69954b9 | pbrook | s = (gic_state *)qemu_mallocz(sizeof(gic_state));
|
728 | e69954b9 | pbrook | if (!s)
|
729 | e69954b9 | pbrook | return NULL; |
730 | 9ee6e8bb | pbrook | s->in = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ); |
731 | 9ee6e8bb | pbrook | for (i = 0; i < NCPU; i++) { |
732 | 9ee6e8bb | pbrook | s->parent_irq[i] = parent_irq[i]; |
733 | e69954b9 | pbrook | } |
734 | 9ee6e8bb | pbrook | iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
|
735 | 9ee6e8bb | pbrook | gic_dist_writefn, s); |
736 | 8da3ff18 | pbrook | cpu_register_physical_memory(dist_base, 0x00001000,
|
737 | 9ee6e8bb | pbrook | iomemtype); |
738 | e69954b9 | pbrook | gic_reset(s); |
739 | 23e39294 | pbrook | register_savevm("arm_gic", -1, 1, gic_save, gic_load, s); |
740 | 9ee6e8bb | pbrook | return s;
|
741 | e69954b9 | pbrook | } |