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1 | 5391d806 | bellard | /*
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2 | 38cdea7c | balrog | * QEMU IDE disk and CD/DVD-ROM Emulator
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3 | 5fafdf24 | ths | *
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4 | 5391d806 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 201a51fc | balrog | * Copyright (c) 2006 Openedhand Ltd.
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6 | 5fafdf24 | ths | *
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7 | 5391d806 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 5391d806 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 5391d806 | bellard | * in the Software without restriction, including without limitation the rights
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10 | 5391d806 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 5391d806 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 5391d806 | bellard | * furnished to do so, subject to the following conditions:
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13 | 5391d806 | bellard | *
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14 | 5391d806 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 5391d806 | bellard | * all copies or substantial portions of the Software.
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16 | 5391d806 | bellard | *
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17 | 5391d806 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 5391d806 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 5391d806 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 5391d806 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 5391d806 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 5391d806 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 5391d806 | bellard | * THE SOFTWARE.
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24 | 5391d806 | bellard | */
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25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 87ecb68b | pbrook | #include "scsi-disk.h" |
29 | 87ecb68b | pbrook | #include "pcmcia.h" |
30 | 87ecb68b | pbrook | #include "block.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 9596ebb7 | pbrook | #include "ppc_mac.h" |
34 | b79e1752 | aurel32 | #include "sh.h" |
35 | 5391d806 | bellard | |
36 | 5391d806 | bellard | /* debug IDE devices */
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37 | 5391d806 | bellard | //#define DEBUG_IDE
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38 | 5391d806 | bellard | //#define DEBUG_IDE_ATAPI
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39 | 8ccad811 | bellard | //#define DEBUG_AIO
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40 | 8ccad811 | bellard | #define USE_DMA_CDROM
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41 | 5391d806 | bellard | |
42 | 5391d806 | bellard | /* Bits of HD_STATUS */
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43 | 5391d806 | bellard | #define ERR_STAT 0x01 |
44 | 5391d806 | bellard | #define INDEX_STAT 0x02 |
45 | 5391d806 | bellard | #define ECC_STAT 0x04 /* Corrected error */ |
46 | 5391d806 | bellard | #define DRQ_STAT 0x08 |
47 | 5391d806 | bellard | #define SEEK_STAT 0x10 |
48 | 5391d806 | bellard | #define SRV_STAT 0x10 |
49 | 5391d806 | bellard | #define WRERR_STAT 0x20 |
50 | 5391d806 | bellard | #define READY_STAT 0x40 |
51 | 5391d806 | bellard | #define BUSY_STAT 0x80 |
52 | 5391d806 | bellard | |
53 | 5391d806 | bellard | /* Bits for HD_ERROR */
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54 | 5391d806 | bellard | #define MARK_ERR 0x01 /* Bad address mark */ |
55 | 5391d806 | bellard | #define TRK0_ERR 0x02 /* couldn't find track 0 */ |
56 | 5391d806 | bellard | #define ABRT_ERR 0x04 /* Command aborted */ |
57 | 5391d806 | bellard | #define MCR_ERR 0x08 /* media change request */ |
58 | 5391d806 | bellard | #define ID_ERR 0x10 /* ID field not found */ |
59 | 5391d806 | bellard | #define MC_ERR 0x20 /* media changed */ |
60 | 5391d806 | bellard | #define ECC_ERR 0x40 /* Uncorrectable ECC error */ |
61 | 5391d806 | bellard | #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */ |
62 | 5391d806 | bellard | #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ |
63 | 5391d806 | bellard | |
64 | 5391d806 | bellard | /* Bits of HD_NSECTOR */
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65 | 5391d806 | bellard | #define CD 0x01 |
66 | 5391d806 | bellard | #define IO 0x02 |
67 | 5391d806 | bellard | #define REL 0x04 |
68 | 5391d806 | bellard | #define TAG_MASK 0xf8 |
69 | 5391d806 | bellard | |
70 | 5391d806 | bellard | #define IDE_CMD_RESET 0x04 |
71 | 5391d806 | bellard | #define IDE_CMD_DISABLE_IRQ 0x02 |
72 | 5391d806 | bellard | |
73 | 5391d806 | bellard | /* ATA/ATAPI Commands pre T13 Spec */
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74 | 5391d806 | bellard | #define WIN_NOP 0x00 |
75 | 5391d806 | bellard | /*
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76 | 5391d806 | bellard | * 0x01->0x02 Reserved
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77 | 5391d806 | bellard | */
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78 | 5391d806 | bellard | #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */ |
79 | 5391d806 | bellard | /*
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80 | 5391d806 | bellard | * 0x04->0x07 Reserved
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81 | 5391d806 | bellard | */
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82 | 5391d806 | bellard | #define WIN_SRST 0x08 /* ATAPI soft reset command */ |
83 | 5391d806 | bellard | #define WIN_DEVICE_RESET 0x08 |
84 | 5391d806 | bellard | /*
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85 | 5391d806 | bellard | * 0x09->0x0F Reserved
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86 | 5391d806 | bellard | */
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87 | 5391d806 | bellard | #define WIN_RECAL 0x10 |
88 | 5391d806 | bellard | #define WIN_RESTORE WIN_RECAL
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89 | 5391d806 | bellard | /*
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90 | 5391d806 | bellard | * 0x10->0x1F Reserved
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91 | 5391d806 | bellard | */
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92 | 5391d806 | bellard | #define WIN_READ 0x20 /* 28-Bit */ |
93 | 5391d806 | bellard | #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */ |
94 | 5391d806 | bellard | #define WIN_READ_LONG 0x22 /* 28-Bit */ |
95 | 5391d806 | bellard | #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */ |
96 | 5391d806 | bellard | #define WIN_READ_EXT 0x24 /* 48-Bit */ |
97 | 5391d806 | bellard | #define WIN_READDMA_EXT 0x25 /* 48-Bit */ |
98 | 5391d806 | bellard | #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */ |
99 | 5391d806 | bellard | #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */ |
100 | 5391d806 | bellard | /*
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101 | 5391d806 | bellard | * 0x28
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102 | 5391d806 | bellard | */
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103 | 5391d806 | bellard | #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */ |
104 | 5391d806 | bellard | /*
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105 | 5391d806 | bellard | * 0x2A->0x2F Reserved
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106 | 5391d806 | bellard | */
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107 | 5391d806 | bellard | #define WIN_WRITE 0x30 /* 28-Bit */ |
108 | 5391d806 | bellard | #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */ |
109 | 5391d806 | bellard | #define WIN_WRITE_LONG 0x32 /* 28-Bit */ |
110 | 5391d806 | bellard | #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */ |
111 | 5391d806 | bellard | #define WIN_WRITE_EXT 0x34 /* 48-Bit */ |
112 | 5391d806 | bellard | #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */ |
113 | 5391d806 | bellard | #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */ |
114 | 5391d806 | bellard | #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */ |
115 | 5391d806 | bellard | #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */ |
116 | 5391d806 | bellard | #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */ |
117 | 5391d806 | bellard | /*
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118 | 5391d806 | bellard | * 0x3A->0x3B Reserved
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119 | 5391d806 | bellard | */
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120 | 5391d806 | bellard | #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */ |
121 | 5391d806 | bellard | /*
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122 | 5391d806 | bellard | * 0x3D->0x3F Reserved
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123 | 5391d806 | bellard | */
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124 | 5391d806 | bellard | #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */ |
125 | 5391d806 | bellard | #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */ |
126 | 5391d806 | bellard | #define WIN_VERIFY_EXT 0x42 /* 48-Bit */ |
127 | 5391d806 | bellard | /*
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128 | 5391d806 | bellard | * 0x43->0x4F Reserved
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129 | 5391d806 | bellard | */
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130 | 5391d806 | bellard | #define WIN_FORMAT 0x50 |
131 | 5391d806 | bellard | /*
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132 | 5391d806 | bellard | * 0x51->0x5F Reserved
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133 | 5391d806 | bellard | */
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134 | 5391d806 | bellard | #define WIN_INIT 0x60 |
135 | 5391d806 | bellard | /*
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136 | 5391d806 | bellard | * 0x61->0x5F Reserved
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137 | 5391d806 | bellard | */
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138 | 5391d806 | bellard | #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */ |
139 | 5391d806 | bellard | #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */ |
140 | 5391d806 | bellard | #define WIN_DIAGNOSE 0x90 |
141 | 5391d806 | bellard | #define WIN_SPECIFY 0x91 /* set drive geometry translation */ |
142 | 5391d806 | bellard | #define WIN_DOWNLOAD_MICROCODE 0x92 |
143 | 5391d806 | bellard | #define WIN_STANDBYNOW2 0x94 |
144 | 201a51fc | balrog | #define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */ |
145 | 5391d806 | bellard | #define WIN_STANDBY2 0x96 |
146 | 5391d806 | bellard | #define WIN_SETIDLE2 0x97 |
147 | 5391d806 | bellard | #define WIN_CHECKPOWERMODE2 0x98 |
148 | 5391d806 | bellard | #define WIN_SLEEPNOW2 0x99 |
149 | 5391d806 | bellard | /*
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150 | 5391d806 | bellard | * 0x9A VENDOR
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151 | 5391d806 | bellard | */
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152 | 5391d806 | bellard | #define WIN_PACKETCMD 0xA0 /* Send a packet command. */ |
153 | 5391d806 | bellard | #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */ |
154 | 5391d806 | bellard | #define WIN_QUEUED_SERVICE 0xA2 |
155 | 5391d806 | bellard | #define WIN_SMART 0xB0 /* self-monitoring and reporting */ |
156 | 201a51fc | balrog | #define CFA_ACCESS_METADATA_STORAGE 0xB8 |
157 | 201a51fc | balrog | #define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */ |
158 | 5391d806 | bellard | #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/ |
159 | 5391d806 | bellard | #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */ |
160 | 5391d806 | bellard | #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */ |
161 | 5391d806 | bellard | #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */ |
162 | 5391d806 | bellard | #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */ |
163 | 5391d806 | bellard | #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */ |
164 | 5391d806 | bellard | #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */ |
165 | 5391d806 | bellard | #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */ |
166 | 5391d806 | bellard | #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */ |
167 | 5391d806 | bellard | #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */ |
168 | 5fafdf24 | ths | #define WIN_GETMEDIASTATUS 0xDA |
169 | 5391d806 | bellard | #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */ |
170 | 5391d806 | bellard | #define WIN_POSTBOOT 0xDC |
171 | 5391d806 | bellard | #define WIN_PREBOOT 0xDD |
172 | 5391d806 | bellard | #define WIN_DOORLOCK 0xDE /* lock door on removable drives */ |
173 | 5391d806 | bellard | #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */ |
174 | 5391d806 | bellard | #define WIN_STANDBYNOW1 0xE0 |
175 | 5391d806 | bellard | #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */ |
176 | 5391d806 | bellard | #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ |
177 | 5391d806 | bellard | #define WIN_SETIDLE1 0xE3 |
178 | 5391d806 | bellard | #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */ |
179 | 5391d806 | bellard | #define WIN_CHECKPOWERMODE1 0xE5 |
180 | 5391d806 | bellard | #define WIN_SLEEPNOW1 0xE6 |
181 | 5391d806 | bellard | #define WIN_FLUSH_CACHE 0xE7 |
182 | 5391d806 | bellard | #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */ |
183 | 5391d806 | bellard | #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */ |
184 | 5391d806 | bellard | /* SET_FEATURES 0x22 or 0xDD */
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185 | 5391d806 | bellard | #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */ |
186 | 5391d806 | bellard | #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */ |
187 | 5391d806 | bellard | #define WIN_MEDIAEJECT 0xED |
188 | 5391d806 | bellard | #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */ |
189 | 5391d806 | bellard | #define WIN_SETFEATURES 0xEF /* set special drive features */ |
190 | 5391d806 | bellard | #define EXABYTE_ENABLE_NEST 0xF0 |
191 | 201a51fc | balrog | #define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */ |
192 | 5391d806 | bellard | #define WIN_SECURITY_SET_PASS 0xF1 |
193 | 5391d806 | bellard | #define WIN_SECURITY_UNLOCK 0xF2 |
194 | 5391d806 | bellard | #define WIN_SECURITY_ERASE_PREPARE 0xF3 |
195 | 5391d806 | bellard | #define WIN_SECURITY_ERASE_UNIT 0xF4 |
196 | 5391d806 | bellard | #define WIN_SECURITY_FREEZE_LOCK 0xF5 |
197 | 201a51fc | balrog | #define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */ |
198 | 5391d806 | bellard | #define WIN_SECURITY_DISABLE 0xF6 |
199 | 5391d806 | bellard | #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */ |
200 | 5391d806 | bellard | #define WIN_SET_MAX 0xF9 |
201 | 5391d806 | bellard | #define DISABLE_SEAGATE 0xFB |
202 | 5391d806 | bellard | |
203 | 5391d806 | bellard | /* set to 1 set disable mult support */
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204 | f66723fa | bellard | #define MAX_MULT_SECTORS 16 |
205 | 5391d806 | bellard | |
206 | 1d8cde5b | aurel32 | #define IDE_DMA_BUF_SECTORS 256 |
207 | 1d8cde5b | aurel32 | |
208 | 1d8cde5b | aurel32 | #if (IDE_DMA_BUF_SECTORS < MAX_MULT_SECTORS)
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209 | 1d8cde5b | aurel32 | #error "IDE_DMA_BUF_SECTORS must be bigger or equal to MAX_MULT_SECTORS" |
210 | 1d8cde5b | aurel32 | #endif
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211 | 1d8cde5b | aurel32 | |
212 | 5391d806 | bellard | /* ATAPI defines */
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213 | 5391d806 | bellard | |
214 | 5391d806 | bellard | #define ATAPI_PACKET_SIZE 12 |
215 | 5391d806 | bellard | |
216 | 5391d806 | bellard | /* The generic packet command opcodes for CD/DVD Logical Units,
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217 | 5391d806 | bellard | * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
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218 | 5391d806 | bellard | #define GPCMD_BLANK 0xa1 |
219 | 5391d806 | bellard | #define GPCMD_CLOSE_TRACK 0x5b |
220 | 5391d806 | bellard | #define GPCMD_FLUSH_CACHE 0x35 |
221 | 5391d806 | bellard | #define GPCMD_FORMAT_UNIT 0x04 |
222 | 5391d806 | bellard | #define GPCMD_GET_CONFIGURATION 0x46 |
223 | 5391d806 | bellard | #define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a |
224 | 5391d806 | bellard | #define GPCMD_GET_PERFORMANCE 0xac |
225 | 5391d806 | bellard | #define GPCMD_INQUIRY 0x12 |
226 | 5391d806 | bellard | #define GPCMD_LOAD_UNLOAD 0xa6 |
227 | 5391d806 | bellard | #define GPCMD_MECHANISM_STATUS 0xbd |
228 | 5391d806 | bellard | #define GPCMD_MODE_SELECT_10 0x55 |
229 | 5391d806 | bellard | #define GPCMD_MODE_SENSE_10 0x5a |
230 | 5391d806 | bellard | #define GPCMD_PAUSE_RESUME 0x4b |
231 | 5391d806 | bellard | #define GPCMD_PLAY_AUDIO_10 0x45 |
232 | 5391d806 | bellard | #define GPCMD_PLAY_AUDIO_MSF 0x47 |
233 | 5391d806 | bellard | #define GPCMD_PLAY_AUDIO_TI 0x48 |
234 | 5391d806 | bellard | #define GPCMD_PLAY_CD 0xbc |
235 | 5391d806 | bellard | #define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e |
236 | 5391d806 | bellard | #define GPCMD_READ_10 0x28 |
237 | 5391d806 | bellard | #define GPCMD_READ_12 0xa8 |
238 | 5391d806 | bellard | #define GPCMD_READ_CDVD_CAPACITY 0x25 |
239 | 5391d806 | bellard | #define GPCMD_READ_CD 0xbe |
240 | 5391d806 | bellard | #define GPCMD_READ_CD_MSF 0xb9 |
241 | 5391d806 | bellard | #define GPCMD_READ_DISC_INFO 0x51 |
242 | 5391d806 | bellard | #define GPCMD_READ_DVD_STRUCTURE 0xad |
243 | 5391d806 | bellard | #define GPCMD_READ_FORMAT_CAPACITIES 0x23 |
244 | 5391d806 | bellard | #define GPCMD_READ_HEADER 0x44 |
245 | 5391d806 | bellard | #define GPCMD_READ_TRACK_RZONE_INFO 0x52 |
246 | 5391d806 | bellard | #define GPCMD_READ_SUBCHANNEL 0x42 |
247 | 5391d806 | bellard | #define GPCMD_READ_TOC_PMA_ATIP 0x43 |
248 | 5391d806 | bellard | #define GPCMD_REPAIR_RZONE_TRACK 0x58 |
249 | 5391d806 | bellard | #define GPCMD_REPORT_KEY 0xa4 |
250 | 5391d806 | bellard | #define GPCMD_REQUEST_SENSE 0x03 |
251 | 5391d806 | bellard | #define GPCMD_RESERVE_RZONE_TRACK 0x53 |
252 | 5391d806 | bellard | #define GPCMD_SCAN 0xba |
253 | 5391d806 | bellard | #define GPCMD_SEEK 0x2b |
254 | 5391d806 | bellard | #define GPCMD_SEND_DVD_STRUCTURE 0xad |
255 | 5391d806 | bellard | #define GPCMD_SEND_EVENT 0xa2 |
256 | 5391d806 | bellard | #define GPCMD_SEND_KEY 0xa3 |
257 | 5391d806 | bellard | #define GPCMD_SEND_OPC 0x54 |
258 | 5391d806 | bellard | #define GPCMD_SET_READ_AHEAD 0xa7 |
259 | 5391d806 | bellard | #define GPCMD_SET_STREAMING 0xb6 |
260 | 5391d806 | bellard | #define GPCMD_START_STOP_UNIT 0x1b |
261 | 5391d806 | bellard | #define GPCMD_STOP_PLAY_SCAN 0x4e |
262 | 5391d806 | bellard | #define GPCMD_TEST_UNIT_READY 0x00 |
263 | 5391d806 | bellard | #define GPCMD_VERIFY_10 0x2f |
264 | 5391d806 | bellard | #define GPCMD_WRITE_10 0x2a |
265 | 5391d806 | bellard | #define GPCMD_WRITE_AND_VERIFY_10 0x2e |
266 | 5fafdf24 | ths | /* This is listed as optional in ATAPI 2.6, but is (curiously)
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267 | 5391d806 | bellard | * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
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268 | 5391d806 | bellard | * Table 377 as an MMC command for SCSi devices though... Most ATAPI
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269 | 5391d806 | bellard | * drives support it. */
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270 | 5391d806 | bellard | #define GPCMD_SET_SPEED 0xbb |
271 | 5fafdf24 | ths | /* This seems to be a SCSI specific CD-ROM opcode
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272 | 5391d806 | bellard | * to play data at track/index */
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273 | 5391d806 | bellard | #define GPCMD_PLAYAUDIO_TI 0x48 |
274 | 5391d806 | bellard | /*
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275 | 5391d806 | bellard | * From MS Media Status Notification Support Specification. For
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276 | 5391d806 | bellard | * older drives only.
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277 | 5391d806 | bellard | */
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278 | 5391d806 | bellard | #define GPCMD_GET_MEDIA_STATUS 0xda |
279 | d14049ea | ths | #define GPCMD_MODE_SENSE_6 0x1a |
280 | 5391d806 | bellard | |
281 | 5391d806 | bellard | /* Mode page codes for mode sense/set */
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282 | 5391d806 | bellard | #define GPMODE_R_W_ERROR_PAGE 0x01 |
283 | 5391d806 | bellard | #define GPMODE_WRITE_PARMS_PAGE 0x05 |
284 | 5391d806 | bellard | #define GPMODE_AUDIO_CTL_PAGE 0x0e |
285 | 5391d806 | bellard | #define GPMODE_POWER_PAGE 0x1a |
286 | 5391d806 | bellard | #define GPMODE_FAULT_FAIL_PAGE 0x1c |
287 | 5391d806 | bellard | #define GPMODE_TO_PROTECT_PAGE 0x1d |
288 | 5391d806 | bellard | #define GPMODE_CAPABILITIES_PAGE 0x2a |
289 | 5391d806 | bellard | #define GPMODE_ALL_PAGES 0x3f |
290 | 5391d806 | bellard | /* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
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291 | 5391d806 | bellard | * of MODE_SENSE_POWER_PAGE */
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292 | 5391d806 | bellard | #define GPMODE_CDROM_PAGE 0x0d |
293 | 5391d806 | bellard | |
294 | 38cdea7c | balrog | /*
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295 | 38cdea7c | balrog | * Based on values from <linux/cdrom.h> but extending CD_MINS
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296 | 38cdea7c | balrog | * to the maximum common size allowed by the Orange's Book ATIP
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297 | 38cdea7c | balrog | *
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298 | 38cdea7c | balrog | * 90 and 99 min CDs are also available but using them as the
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299 | 38cdea7c | balrog | * upper limit reduces the effectiveness of the heuristic to
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300 | 38cdea7c | balrog | * detect DVDs burned to less than 25% of their maximum capacity
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301 | 38cdea7c | balrog | */
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302 | 38cdea7c | balrog | |
303 | 38cdea7c | balrog | /* Some generally useful CD-ROM information */
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304 | 38cdea7c | balrog | #define CD_MINS 80 /* max. minutes per CD */ |
305 | 38cdea7c | balrog | #define CD_SECS 60 /* seconds per minute */ |
306 | 38cdea7c | balrog | #define CD_FRAMES 75 /* frames per second */ |
307 | 38cdea7c | balrog | #define CD_FRAMESIZE 2048 /* bytes per frame, "cooked" mode */ |
308 | 38cdea7c | balrog | #define CD_MAX_BYTES (CD_MINS * CD_SECS * CD_FRAMES * CD_FRAMESIZE)
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309 | 38cdea7c | balrog | #define CD_MAX_SECTORS (CD_MAX_BYTES / 512) |
310 | 38cdea7c | balrog | |
311 | 38cdea7c | balrog | /*
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312 | 38cdea7c | balrog | * The MMC values are not IDE specific and might need to be moved
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313 | 38cdea7c | balrog | * to a common header if they are also needed for the SCSI emulation
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314 | 38cdea7c | balrog | */
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315 | 38cdea7c | balrog | |
316 | 38cdea7c | balrog | /* Profile list from MMC-6 revision 1 table 91 */
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317 | 38cdea7c | balrog | #define MMC_PROFILE_NONE 0x0000 |
318 | 38cdea7c | balrog | #define MMC_PROFILE_CD_ROM 0x0008 |
319 | 38cdea7c | balrog | #define MMC_PROFILE_CD_R 0x0009 |
320 | 38cdea7c | balrog | #define MMC_PROFILE_CD_RW 0x000A |
321 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_ROM 0x0010 |
322 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_R_SR 0x0011 |
323 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RAM 0x0012 |
324 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RW_RO 0x0013 |
325 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RW_SR 0x0014 |
326 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_R_DL_SR 0x0015 |
327 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_R_DL_JR 0x0016 |
328 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RW_DL 0x0017 |
329 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_DDR 0x0018 |
330 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_RW 0x001A |
331 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_R 0x001B |
332 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_RW_DL 0x002A |
333 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_R_DL 0x002B |
334 | 38cdea7c | balrog | #define MMC_PROFILE_BD_ROM 0x0040 |
335 | 38cdea7c | balrog | #define MMC_PROFILE_BD_R_SRM 0x0041 |
336 | 38cdea7c | balrog | #define MMC_PROFILE_BD_R_RRM 0x0042 |
337 | 38cdea7c | balrog | #define MMC_PROFILE_BD_RE 0x0043 |
338 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_ROM 0x0050 |
339 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_R 0x0051 |
340 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_RAM 0x0052 |
341 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_RW 0x0053 |
342 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_R_DL 0x0058 |
343 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_RW_DL 0x005A |
344 | 38cdea7c | balrog | #define MMC_PROFILE_INVALID 0xFFFF |
345 | 38cdea7c | balrog | |
346 | 5391d806 | bellard | #define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */ |
347 | 5391d806 | bellard | #define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */ |
348 | 5391d806 | bellard | #define ATAPI_INT_REASON_REL 0x04 |
349 | 5391d806 | bellard | #define ATAPI_INT_REASON_TAG 0xf8 |
350 | 5391d806 | bellard | |
351 | 5391d806 | bellard | /* same constants as bochs */
|
352 | 7f777bf3 | bellard | #define ASC_ILLEGAL_OPCODE 0x20 |
353 | 5391d806 | bellard | #define ASC_LOGICAL_BLOCK_OOR 0x21 |
354 | 5391d806 | bellard | #define ASC_INV_FIELD_IN_CMD_PACKET 0x24 |
355 | 9118e7f0 | aliguori | #define ASC_MEDIUM_MAY_HAVE_CHANGED 0x28 |
356 | 8114e9e8 | ths | #define ASC_INCOMPATIBLE_FORMAT 0x30 |
357 | 5391d806 | bellard | #define ASC_MEDIUM_NOT_PRESENT 0x3a |
358 | 5391d806 | bellard | #define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39 |
359 | 5391d806 | bellard | |
360 | 201a51fc | balrog | #define CFA_NO_ERROR 0x00 |
361 | 201a51fc | balrog | #define CFA_MISC_ERROR 0x09 |
362 | 201a51fc | balrog | #define CFA_INVALID_COMMAND 0x20 |
363 | 201a51fc | balrog | #define CFA_INVALID_ADDRESS 0x21 |
364 | 201a51fc | balrog | #define CFA_ADDRESS_OVERFLOW 0x2f |
365 | 201a51fc | balrog | |
366 | 5391d806 | bellard | #define SENSE_NONE 0 |
367 | 5391d806 | bellard | #define SENSE_NOT_READY 2 |
368 | 5391d806 | bellard | #define SENSE_ILLEGAL_REQUEST 5 |
369 | 5391d806 | bellard | #define SENSE_UNIT_ATTENTION 6 |
370 | 5391d806 | bellard | |
371 | 5391d806 | bellard | struct IDEState;
|
372 | 5391d806 | bellard | |
373 | 5391d806 | bellard | typedef void EndTransferFunc(struct IDEState *); |
374 | 5391d806 | bellard | |
375 | caed8802 | bellard | /* NOTE: IDEState represents in fact one drive */
|
376 | 5391d806 | bellard | typedef struct IDEState { |
377 | 5391d806 | bellard | /* ide config */
|
378 | 5391d806 | bellard | int is_cdrom;
|
379 | 201a51fc | balrog | int is_cf;
|
380 | 5391d806 | bellard | int cylinders, heads, sectors;
|
381 | 5391d806 | bellard | int64_t nb_sectors; |
382 | 5391d806 | bellard | int mult_sectors;
|
383 | 94458802 | bellard | int identify_set;
|
384 | 94458802 | bellard | uint16_t identify_data[256];
|
385 | d537cf6c | pbrook | qemu_irq irq; |
386 | 34e538ae | bellard | PCIDevice *pci_dev; |
387 | 98087450 | bellard | struct BMDMAState *bmdma;
|
388 | aedf5382 | bellard | int drive_serial;
|
389 | 5391d806 | bellard | /* ide regs */
|
390 | 5391d806 | bellard | uint8_t feature; |
391 | 5391d806 | bellard | uint8_t error; |
392 | c2ff060f | bellard | uint32_t nsector; |
393 | 5391d806 | bellard | uint8_t sector; |
394 | 5391d806 | bellard | uint8_t lcyl; |
395 | 5391d806 | bellard | uint8_t hcyl; |
396 | c2ff060f | bellard | /* other part of tf for lba48 support */
|
397 | c2ff060f | bellard | uint8_t hob_feature; |
398 | c2ff060f | bellard | uint8_t hob_nsector; |
399 | c2ff060f | bellard | uint8_t hob_sector; |
400 | c2ff060f | bellard | uint8_t hob_lcyl; |
401 | c2ff060f | bellard | uint8_t hob_hcyl; |
402 | c2ff060f | bellard | |
403 | 5391d806 | bellard | uint8_t select; |
404 | 5391d806 | bellard | uint8_t status; |
405 | c2ff060f | bellard | |
406 | 5391d806 | bellard | /* 0x3f6 command, only meaningful for drive 0 */
|
407 | 5391d806 | bellard | uint8_t cmd; |
408 | c2ff060f | bellard | /* set for lba48 access */
|
409 | c2ff060f | bellard | uint8_t lba48; |
410 | 5391d806 | bellard | /* depends on bit 4 in select, only meaningful for drive 0 */
|
411 | 5fafdf24 | ths | struct IDEState *cur_drive;
|
412 | 5391d806 | bellard | BlockDriverState *bs; |
413 | 5391d806 | bellard | /* ATAPI specific */
|
414 | 5391d806 | bellard | uint8_t sense_key; |
415 | 5391d806 | bellard | uint8_t asc; |
416 | 5391d806 | bellard | int packet_transfer_size;
|
417 | 5391d806 | bellard | int elementary_transfer_size;
|
418 | 5391d806 | bellard | int io_buffer_index;
|
419 | 5391d806 | bellard | int lba;
|
420 | 98087450 | bellard | int cd_sector_size;
|
421 | 98087450 | bellard | int atapi_dma; /* true if dma is requested for the packet cmd */ |
422 | 98087450 | bellard | /* ATA DMA state */
|
423 | 98087450 | bellard | int io_buffer_size;
|
424 | 98087450 | bellard | /* PIO transfer handling */
|
425 | 5391d806 | bellard | int req_nb_sectors; /* number of sectors per interrupt */ |
426 | 5391d806 | bellard | EndTransferFunc *end_transfer_func; |
427 | 5391d806 | bellard | uint8_t *data_ptr; |
428 | 5391d806 | bellard | uint8_t *data_end; |
429 | 33f00271 | balrog | uint8_t *io_buffer; |
430 | 31c2a146 | ths | QEMUTimer *sector_write_timer; /* only used for win2k install hack */
|
431 | e774a278 | bellard | uint32_t irq_count; /* counts IRQs when using win2k install hack */
|
432 | 201a51fc | balrog | /* CF-ATA extended error */
|
433 | 201a51fc | balrog | uint8_t ext_error; |
434 | 201a51fc | balrog | /* CF-ATA metadata storage */
|
435 | 201a51fc | balrog | uint32_t mdata_size; |
436 | 201a51fc | balrog | uint8_t *mdata_storage; |
437 | 201a51fc | balrog | int media_changed;
|
438 | 5391d806 | bellard | } IDEState; |
439 | 5391d806 | bellard | |
440 | 8114e9e8 | ths | /* XXX: DVDs that could fit on a CD will be reported as a CD */
|
441 | 8114e9e8 | ths | static inline int media_present(IDEState *s) |
442 | 8114e9e8 | ths | { |
443 | 8114e9e8 | ths | return (s->nb_sectors > 0); |
444 | 8114e9e8 | ths | } |
445 | 8114e9e8 | ths | |
446 | 8114e9e8 | ths | static inline int media_is_dvd(IDEState *s) |
447 | 8114e9e8 | ths | { |
448 | 8114e9e8 | ths | return (media_present(s) && s->nb_sectors > CD_MAX_SECTORS);
|
449 | 8114e9e8 | ths | } |
450 | 8114e9e8 | ths | |
451 | 8114e9e8 | ths | static inline int media_is_cd(IDEState *s) |
452 | 8114e9e8 | ths | { |
453 | 8114e9e8 | ths | return (media_present(s) && s->nb_sectors <= CD_MAX_SECTORS);
|
454 | 8114e9e8 | ths | } |
455 | 8114e9e8 | ths | |
456 | 98087450 | bellard | #define BM_STATUS_DMAING 0x01 |
457 | 98087450 | bellard | #define BM_STATUS_ERROR 0x02 |
458 | 98087450 | bellard | #define BM_STATUS_INT 0x04 |
459 | 98087450 | bellard | |
460 | 98087450 | bellard | #define BM_CMD_START 0x01 |
461 | 98087450 | bellard | #define BM_CMD_READ 0x08 |
462 | 98087450 | bellard | |
463 | 5457c8ce | bellard | #define IDE_TYPE_PIIX3 0 |
464 | 5457c8ce | bellard | #define IDE_TYPE_CMD646 1 |
465 | afcc3cdf | ths | #define IDE_TYPE_PIIX4 2 |
466 | 5457c8ce | bellard | |
467 | 5457c8ce | bellard | /* CMD646 specific */
|
468 | 5457c8ce | bellard | #define MRDMODE 0x71 |
469 | 5457c8ce | bellard | #define MRDMODE_INTR_CH0 0x04 |
470 | 5457c8ce | bellard | #define MRDMODE_INTR_CH1 0x08 |
471 | 5457c8ce | bellard | #define MRDMODE_BLK_CH0 0x10 |
472 | 5457c8ce | bellard | #define MRDMODE_BLK_CH1 0x20 |
473 | 5457c8ce | bellard | #define UDIDETCR0 0x73 |
474 | 5457c8ce | bellard | #define UDIDETCR1 0x7B |
475 | 5457c8ce | bellard | |
476 | 98087450 | bellard | typedef struct BMDMAState { |
477 | 98087450 | bellard | uint8_t cmd; |
478 | 98087450 | bellard | uint8_t status; |
479 | 98087450 | bellard | uint32_t addr; |
480 | 3b46e624 | ths | |
481 | 5457c8ce | bellard | struct PCIIDEState *pci_dev;
|
482 | 98087450 | bellard | /* current transfer state */
|
483 | 8ccad811 | bellard | uint32_t cur_addr; |
484 | 8ccad811 | bellard | uint32_t cur_prd_last; |
485 | 8ccad811 | bellard | uint32_t cur_prd_addr; |
486 | 8ccad811 | bellard | uint32_t cur_prd_len; |
487 | 98087450 | bellard | IDEState *ide_if; |
488 | 8ccad811 | bellard | BlockDriverCompletionFunc *dma_cb; |
489 | 8ccad811 | bellard | BlockDriverAIOCB *aiocb; |
490 | 98087450 | bellard | } BMDMAState; |
491 | 98087450 | bellard | |
492 | 98087450 | bellard | typedef struct PCIIDEState { |
493 | 98087450 | bellard | PCIDevice dev; |
494 | 98087450 | bellard | IDEState ide_if[4];
|
495 | 98087450 | bellard | BMDMAState bmdma[2];
|
496 | 5457c8ce | bellard | int type; /* see IDE_TYPE_xxx */ |
497 | 98087450 | bellard | } PCIIDEState; |
498 | 98087450 | bellard | |
499 | 8ccad811 | bellard | static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb); |
500 | 5f12ab4b | ths | static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret); |
501 | 98087450 | bellard | |
502 | 5391d806 | bellard | static void padstr(char *str, const char *src, int len) |
503 | 5391d806 | bellard | { |
504 | 5391d806 | bellard | int i, v;
|
505 | 5391d806 | bellard | for(i = 0; i < len; i++) { |
506 | 5391d806 | bellard | if (*src)
|
507 | 5391d806 | bellard | v = *src++; |
508 | 5391d806 | bellard | else
|
509 | 5391d806 | bellard | v = ' ';
|
510 | 69b34976 | ths | str[i^1] = v;
|
511 | 5391d806 | bellard | } |
512 | 5391d806 | bellard | } |
513 | 5391d806 | bellard | |
514 | bd0d90b2 | bellard | static void padstr8(uint8_t *buf, int buf_size, const char *src) |
515 | bd0d90b2 | bellard | { |
516 | bd0d90b2 | bellard | int i;
|
517 | bd0d90b2 | bellard | for(i = 0; i < buf_size; i++) { |
518 | bd0d90b2 | bellard | if (*src)
|
519 | bd0d90b2 | bellard | buf[i] = *src++; |
520 | bd0d90b2 | bellard | else
|
521 | bd0d90b2 | bellard | buf[i] = ' ';
|
522 | bd0d90b2 | bellard | } |
523 | bd0d90b2 | bellard | } |
524 | bd0d90b2 | bellard | |
525 | 67b915a5 | bellard | static void put_le16(uint16_t *p, unsigned int v) |
526 | 67b915a5 | bellard | { |
527 | 0c4ad8dc | bellard | *p = cpu_to_le16(v); |
528 | 67b915a5 | bellard | } |
529 | 67b915a5 | bellard | |
530 | 5391d806 | bellard | static void ide_identify(IDEState *s) |
531 | 5391d806 | bellard | { |
532 | 5391d806 | bellard | uint16_t *p; |
533 | 5391d806 | bellard | unsigned int oldsize; |
534 | aedf5382 | bellard | char buf[20]; |
535 | 5391d806 | bellard | |
536 | 94458802 | bellard | if (s->identify_set) {
|
537 | 94458802 | bellard | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
|
538 | 94458802 | bellard | return;
|
539 | 94458802 | bellard | } |
540 | 94458802 | bellard | |
541 | 5391d806 | bellard | memset(s->io_buffer, 0, 512); |
542 | 5391d806 | bellard | p = (uint16_t *)s->io_buffer; |
543 | 67b915a5 | bellard | put_le16(p + 0, 0x0040); |
544 | 5fafdf24 | ths | put_le16(p + 1, s->cylinders);
|
545 | 67b915a5 | bellard | put_le16(p + 3, s->heads);
|
546 | 67b915a5 | bellard | put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ |
547 | 67b915a5 | bellard | put_le16(p + 5, 512); /* XXX: retired, remove ? */ |
548 | 5fafdf24 | ths | put_le16(p + 6, s->sectors);
|
549 | aedf5382 | bellard | snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial); |
550 | 60fe76f3 | ths | padstr((char *)(p + 10), buf, 20); /* serial number */ |
551 | 67b915a5 | bellard | put_le16(p + 20, 3); /* XXX: retired, remove ? */ |
552 | 67b915a5 | bellard | put_le16(p + 21, 512); /* cache size in sectors */ |
553 | 67b915a5 | bellard | put_le16(p + 22, 4); /* ecc bytes */ |
554 | 60fe76f3 | ths | padstr((char *)(p + 23), QEMU_VERSION, 8); /* firmware version */ |
555 | 60fe76f3 | ths | padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */ |
556 | 3b46e624 | ths | #if MAX_MULT_SECTORS > 1 |
557 | 67b915a5 | bellard | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
558 | 5391d806 | bellard | #endif
|
559 | 67b915a5 | bellard | put_le16(p + 48, 1); /* dword I/O */ |
560 | 94458802 | bellard | put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ |
561 | 67b915a5 | bellard | put_le16(p + 51, 0x200); /* PIO transfer cycle */ |
562 | 67b915a5 | bellard | put_le16(p + 52, 0x200); /* DMA transfer cycle */ |
563 | 94458802 | bellard | put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ |
564 | 67b915a5 | bellard | put_le16(p + 54, s->cylinders);
|
565 | 67b915a5 | bellard | put_le16(p + 55, s->heads);
|
566 | 67b915a5 | bellard | put_le16(p + 56, s->sectors);
|
567 | 5391d806 | bellard | oldsize = s->cylinders * s->heads * s->sectors; |
568 | 67b915a5 | bellard | put_le16(p + 57, oldsize);
|
569 | 67b915a5 | bellard | put_le16(p + 58, oldsize >> 16); |
570 | 5391d806 | bellard | if (s->mult_sectors)
|
571 | 67b915a5 | bellard | put_le16(p + 59, 0x100 | s->mult_sectors); |
572 | 67b915a5 | bellard | put_le16(p + 60, s->nb_sectors);
|
573 | 67b915a5 | bellard | put_le16(p + 61, s->nb_sectors >> 16); |
574 | d1b5c20d | ths | put_le16(p + 62, 0x07); /* single word dma0-2 supported */ |
575 | 94458802 | bellard | put_le16(p + 63, 0x07); /* mdma0-2 supported */ |
576 | 94458802 | bellard | put_le16(p + 65, 120); |
577 | 94458802 | bellard | put_le16(p + 66, 120); |
578 | 94458802 | bellard | put_le16(p + 67, 120); |
579 | 94458802 | bellard | put_le16(p + 68, 120); |
580 | 94458802 | bellard | put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ |
581 | 94458802 | bellard | put_le16(p + 81, 0x16); /* conforms to ata5 */ |
582 | 67b915a5 | bellard | put_le16(p + 82, (1 << 14)); |
583 | c2ff060f | bellard | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
|
584 | c2ff060f | bellard | put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); |
585 | 67b915a5 | bellard | put_le16(p + 84, (1 << 14)); |
586 | 67b915a5 | bellard | put_le16(p + 85, (1 << 14)); |
587 | c2ff060f | bellard | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
|
588 | c2ff060f | bellard | put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); |
589 | 67b915a5 | bellard | put_le16(p + 87, (1 << 14)); |
590 | 94458802 | bellard | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
591 | 94458802 | bellard | put_le16(p + 93, 1 | (1 << 14) | 0x2000); |
592 | c2ff060f | bellard | put_le16(p + 100, s->nb_sectors);
|
593 | c2ff060f | bellard | put_le16(p + 101, s->nb_sectors >> 16); |
594 | c2ff060f | bellard | put_le16(p + 102, s->nb_sectors >> 32); |
595 | c2ff060f | bellard | put_le16(p + 103, s->nb_sectors >> 48); |
596 | 94458802 | bellard | |
597 | 94458802 | bellard | memcpy(s->identify_data, p, sizeof(s->identify_data));
|
598 | 94458802 | bellard | s->identify_set = 1;
|
599 | 5391d806 | bellard | } |
600 | 5391d806 | bellard | |
601 | 5391d806 | bellard | static void ide_atapi_identify(IDEState *s) |
602 | 5391d806 | bellard | { |
603 | 5391d806 | bellard | uint16_t *p; |
604 | aedf5382 | bellard | char buf[20]; |
605 | 5391d806 | bellard | |
606 | 94458802 | bellard | if (s->identify_set) {
|
607 | 94458802 | bellard | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
|
608 | 94458802 | bellard | return;
|
609 | 94458802 | bellard | } |
610 | 94458802 | bellard | |
611 | 5391d806 | bellard | memset(s->io_buffer, 0, 512); |
612 | 5391d806 | bellard | p = (uint16_t *)s->io_buffer; |
613 | 5391d806 | bellard | /* Removable CDROM, 50us response, 12 byte packets */
|
614 | 67b915a5 | bellard | put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); |
615 | aedf5382 | bellard | snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial); |
616 | 60fe76f3 | ths | padstr((char *)(p + 10), buf, 20); /* serial number */ |
617 | 67b915a5 | bellard | put_le16(p + 20, 3); /* buffer type */ |
618 | 67b915a5 | bellard | put_le16(p + 21, 512); /* cache size in sectors */ |
619 | 67b915a5 | bellard | put_le16(p + 22, 4); /* ecc bytes */ |
620 | 60fe76f3 | ths | padstr((char *)(p + 23), QEMU_VERSION, 8); /* firmware version */ |
621 | 38cdea7c | balrog | padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */ |
622 | 67b915a5 | bellard | put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ |
623 | 8ccad811 | bellard | #ifdef USE_DMA_CDROM
|
624 | 8ccad811 | bellard | put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ |
625 | 8ccad811 | bellard | put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ |
626 | d1b5c20d | ths | put_le16(p + 62, 7); /* single word dma0-2 supported */ |
627 | 8ccad811 | bellard | put_le16(p + 63, 7); /* mdma0-2 supported */ |
628 | 8ccad811 | bellard | put_le16(p + 64, 0x3f); /* PIO modes supported */ |
629 | 8ccad811 | bellard | #else
|
630 | 67b915a5 | bellard | put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ |
631 | 67b915a5 | bellard | put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ |
632 | 67b915a5 | bellard | put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ |
633 | 67b915a5 | bellard | put_le16(p + 64, 1); /* PIO modes */ |
634 | 8ccad811 | bellard | #endif
|
635 | 67b915a5 | bellard | put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ |
636 | 67b915a5 | bellard | put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ |
637 | 67b915a5 | bellard | put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ |
638 | 67b915a5 | bellard | put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ |
639 | 94458802 | bellard | |
640 | 67b915a5 | bellard | put_le16(p + 71, 30); /* in ns */ |
641 | 67b915a5 | bellard | put_le16(p + 72, 30); /* in ns */ |
642 | 5391d806 | bellard | |
643 | 67b915a5 | bellard | put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ |
644 | 8ccad811 | bellard | #ifdef USE_DMA_CDROM
|
645 | 8ccad811 | bellard | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
646 | 8ccad811 | bellard | #endif
|
647 | 94458802 | bellard | memcpy(s->identify_data, p, sizeof(s->identify_data));
|
648 | 94458802 | bellard | s->identify_set = 1;
|
649 | 5391d806 | bellard | } |
650 | 5391d806 | bellard | |
651 | 201a51fc | balrog | static void ide_cfata_identify(IDEState *s) |
652 | 201a51fc | balrog | { |
653 | 201a51fc | balrog | uint16_t *p; |
654 | 201a51fc | balrog | uint32_t cur_sec; |
655 | 201a51fc | balrog | char buf[20]; |
656 | 201a51fc | balrog | |
657 | 201a51fc | balrog | p = (uint16_t *) s->identify_data; |
658 | 201a51fc | balrog | if (s->identify_set)
|
659 | 201a51fc | balrog | goto fill_buffer;
|
660 | 201a51fc | balrog | |
661 | 201a51fc | balrog | memset(p, 0, sizeof(s->identify_data)); |
662 | 201a51fc | balrog | |
663 | 201a51fc | balrog | cur_sec = s->cylinders * s->heads * s->sectors; |
664 | 201a51fc | balrog | |
665 | 201a51fc | balrog | put_le16(p + 0, 0x848a); /* CF Storage Card signature */ |
666 | 201a51fc | balrog | put_le16(p + 1, s->cylinders); /* Default cylinders */ |
667 | 201a51fc | balrog | put_le16(p + 3, s->heads); /* Default heads */ |
668 | 201a51fc | balrog | put_le16(p + 6, s->sectors); /* Default sectors per track */ |
669 | 201a51fc | balrog | put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ |
670 | 201a51fc | balrog | put_le16(p + 8, s->nb_sectors); /* Sectors per card */ |
671 | 201a51fc | balrog | snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial); |
672 | 60fe76f3 | ths | padstr((char *)(p + 10), buf, 20); /* Serial number in ASCII */ |
673 | 201a51fc | balrog | put_le16(p + 22, 0x0004); /* ECC bytes */ |
674 | 60fe76f3 | ths | padstr((char *) (p + 23), QEMU_VERSION, 8); /* Firmware Revision */ |
675 | 60fe76f3 | ths | padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */ |
676 | 201a51fc | balrog | #if MAX_MULT_SECTORS > 1 |
677 | 201a51fc | balrog | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
678 | 201a51fc | balrog | #else
|
679 | 201a51fc | balrog | put_le16(p + 47, 0x0000); |
680 | 201a51fc | balrog | #endif
|
681 | 201a51fc | balrog | put_le16(p + 49, 0x0f00); /* Capabilities */ |
682 | 201a51fc | balrog | put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ |
683 | 201a51fc | balrog | put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ |
684 | 201a51fc | balrog | put_le16(p + 53, 0x0003); /* Translation params valid */ |
685 | 201a51fc | balrog | put_le16(p + 54, s->cylinders); /* Current cylinders */ |
686 | 201a51fc | balrog | put_le16(p + 55, s->heads); /* Current heads */ |
687 | 201a51fc | balrog | put_le16(p + 56, s->sectors); /* Current sectors */ |
688 | 201a51fc | balrog | put_le16(p + 57, cur_sec); /* Current capacity */ |
689 | 201a51fc | balrog | put_le16(p + 58, cur_sec >> 16); /* Current capacity */ |
690 | 201a51fc | balrog | if (s->mult_sectors) /* Multiple sector setting */ |
691 | 201a51fc | balrog | put_le16(p + 59, 0x100 | s->mult_sectors); |
692 | 201a51fc | balrog | put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ |
693 | 201a51fc | balrog | put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ |
694 | 201a51fc | balrog | put_le16(p + 63, 0x0203); /* Multiword DMA capability */ |
695 | 201a51fc | balrog | put_le16(p + 64, 0x0001); /* Flow Control PIO support */ |
696 | 201a51fc | balrog | put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ |
697 | 201a51fc | balrog | put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ |
698 | 201a51fc | balrog | put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ |
699 | 201a51fc | balrog | put_le16(p + 82, 0x400c); /* Command Set supported */ |
700 | 201a51fc | balrog | put_le16(p + 83, 0x7068); /* Command Set supported */ |
701 | 201a51fc | balrog | put_le16(p + 84, 0x4000); /* Features supported */ |
702 | 201a51fc | balrog | put_le16(p + 85, 0x000c); /* Command Set enabled */ |
703 | 201a51fc | balrog | put_le16(p + 86, 0x7044); /* Command Set enabled */ |
704 | 201a51fc | balrog | put_le16(p + 87, 0x4000); /* Features enabled */ |
705 | 201a51fc | balrog | put_le16(p + 91, 0x4060); /* Current APM level */ |
706 | 201a51fc | balrog | put_le16(p + 129, 0x0002); /* Current features option */ |
707 | 201a51fc | balrog | put_le16(p + 130, 0x0005); /* Reassigned sectors */ |
708 | 201a51fc | balrog | put_le16(p + 131, 0x0001); /* Initial power mode */ |
709 | 201a51fc | balrog | put_le16(p + 132, 0x0000); /* User signature */ |
710 | 201a51fc | balrog | put_le16(p + 160, 0x8100); /* Power requirement */ |
711 | 201a51fc | balrog | put_le16(p + 161, 0x8001); /* CF command set */ |
712 | 201a51fc | balrog | |
713 | 201a51fc | balrog | s->identify_set = 1;
|
714 | 201a51fc | balrog | |
715 | 201a51fc | balrog | fill_buffer:
|
716 | 201a51fc | balrog | memcpy(s->io_buffer, p, sizeof(s->identify_data));
|
717 | 201a51fc | balrog | } |
718 | 201a51fc | balrog | |
719 | 5391d806 | bellard | static void ide_set_signature(IDEState *s) |
720 | 5391d806 | bellard | { |
721 | 5391d806 | bellard | s->select &= 0xf0; /* clear head */ |
722 | 5391d806 | bellard | /* put signature */
|
723 | 5391d806 | bellard | s->nsector = 1;
|
724 | 5391d806 | bellard | s->sector = 1;
|
725 | 5391d806 | bellard | if (s->is_cdrom) {
|
726 | 5391d806 | bellard | s->lcyl = 0x14;
|
727 | 5391d806 | bellard | s->hcyl = 0xeb;
|
728 | 5391d806 | bellard | } else if (s->bs) { |
729 | 5391d806 | bellard | s->lcyl = 0;
|
730 | 5391d806 | bellard | s->hcyl = 0;
|
731 | 5391d806 | bellard | } else {
|
732 | 5391d806 | bellard | s->lcyl = 0xff;
|
733 | 5391d806 | bellard | s->hcyl = 0xff;
|
734 | 5391d806 | bellard | } |
735 | 5391d806 | bellard | } |
736 | 5391d806 | bellard | |
737 | 5391d806 | bellard | static inline void ide_abort_command(IDEState *s) |
738 | 5391d806 | bellard | { |
739 | 5391d806 | bellard | s->status = READY_STAT | ERR_STAT; |
740 | 5391d806 | bellard | s->error = ABRT_ERR; |
741 | 5391d806 | bellard | } |
742 | 5391d806 | bellard | |
743 | 5604e090 | balrog | static inline void ide_dma_submit_check(IDEState *s, |
744 | 5604e090 | balrog | BlockDriverCompletionFunc *dma_cb, BMDMAState *bm) |
745 | 5604e090 | balrog | { |
746 | 5604e090 | balrog | if (bm->aiocb)
|
747 | 5604e090 | balrog | return;
|
748 | 5604e090 | balrog | dma_cb(bm, -1);
|
749 | 5604e090 | balrog | } |
750 | 5604e090 | balrog | |
751 | 5391d806 | bellard | static inline void ide_set_irq(IDEState *s) |
752 | 5391d806 | bellard | { |
753 | 98ff7d30 | bellard | BMDMAState *bm = s->bmdma; |
754 | 5391d806 | bellard | if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
|
755 | 5457c8ce | bellard | if (bm) {
|
756 | 98ff7d30 | bellard | bm->status |= BM_STATUS_INT; |
757 | 5457c8ce | bellard | } |
758 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
759 | 5391d806 | bellard | } |
760 | 5391d806 | bellard | } |
761 | 5391d806 | bellard | |
762 | 5391d806 | bellard | /* prepare data transfer and tell what to do after */
|
763 | 5fafdf24 | ths | static void ide_transfer_start(IDEState *s, uint8_t *buf, int size, |
764 | 5391d806 | bellard | EndTransferFunc *end_transfer_func) |
765 | 5391d806 | bellard | { |
766 | 5391d806 | bellard | s->end_transfer_func = end_transfer_func; |
767 | 5391d806 | bellard | s->data_ptr = buf; |
768 | 5391d806 | bellard | s->data_end = buf + size; |
769 | 7603d156 | ths | if (!(s->status & ERR_STAT))
|
770 | 7603d156 | ths | s->status |= DRQ_STAT; |
771 | 5391d806 | bellard | } |
772 | 5391d806 | bellard | |
773 | 5391d806 | bellard | static void ide_transfer_stop(IDEState *s) |
774 | 5391d806 | bellard | { |
775 | 5391d806 | bellard | s->end_transfer_func = ide_transfer_stop; |
776 | 5391d806 | bellard | s->data_ptr = s->io_buffer; |
777 | 5391d806 | bellard | s->data_end = s->io_buffer; |
778 | 5391d806 | bellard | s->status &= ~DRQ_STAT; |
779 | 5391d806 | bellard | } |
780 | 5391d806 | bellard | |
781 | 5391d806 | bellard | static int64_t ide_get_sector(IDEState *s)
|
782 | 5391d806 | bellard | { |
783 | 5391d806 | bellard | int64_t sector_num; |
784 | 5391d806 | bellard | if (s->select & 0x40) { |
785 | 5391d806 | bellard | /* lba */
|
786 | c2ff060f | bellard | if (!s->lba48) {
|
787 | c2ff060f | bellard | sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | |
788 | c2ff060f | bellard | (s->lcyl << 8) | s->sector;
|
789 | c2ff060f | bellard | } else {
|
790 | c2ff060f | bellard | sector_num = ((int64_t)s->hob_hcyl << 40) |
|
791 | c2ff060f | bellard | ((int64_t) s->hob_lcyl << 32) |
|
792 | c2ff060f | bellard | ((int64_t) s->hob_sector << 24) |
|
793 | c2ff060f | bellard | ((int64_t) s->hcyl << 16) |
|
794 | c2ff060f | bellard | ((int64_t) s->lcyl << 8) | s->sector;
|
795 | c2ff060f | bellard | } |
796 | 5391d806 | bellard | } else {
|
797 | 5391d806 | bellard | sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
798 | c2ff060f | bellard | (s->select & 0x0f) * s->sectors + (s->sector - 1); |
799 | 5391d806 | bellard | } |
800 | 5391d806 | bellard | return sector_num;
|
801 | 5391d806 | bellard | } |
802 | 5391d806 | bellard | |
803 | 5391d806 | bellard | static void ide_set_sector(IDEState *s, int64_t sector_num) |
804 | 5391d806 | bellard | { |
805 | 5391d806 | bellard | unsigned int cyl, r; |
806 | 5391d806 | bellard | if (s->select & 0x40) { |
807 | c2ff060f | bellard | if (!s->lba48) {
|
808 | c2ff060f | bellard | s->select = (s->select & 0xf0) | (sector_num >> 24); |
809 | c2ff060f | bellard | s->hcyl = (sector_num >> 16);
|
810 | c2ff060f | bellard | s->lcyl = (sector_num >> 8);
|
811 | c2ff060f | bellard | s->sector = (sector_num); |
812 | c2ff060f | bellard | } else {
|
813 | c2ff060f | bellard | s->sector = sector_num; |
814 | c2ff060f | bellard | s->lcyl = sector_num >> 8;
|
815 | c2ff060f | bellard | s->hcyl = sector_num >> 16;
|
816 | c2ff060f | bellard | s->hob_sector = sector_num >> 24;
|
817 | c2ff060f | bellard | s->hob_lcyl = sector_num >> 32;
|
818 | c2ff060f | bellard | s->hob_hcyl = sector_num >> 40;
|
819 | c2ff060f | bellard | } |
820 | 5391d806 | bellard | } else {
|
821 | 5391d806 | bellard | cyl = sector_num / (s->heads * s->sectors); |
822 | 5391d806 | bellard | r = sector_num % (s->heads * s->sectors); |
823 | 5391d806 | bellard | s->hcyl = cyl >> 8;
|
824 | 5391d806 | bellard | s->lcyl = cyl; |
825 | 1b8eb456 | bellard | s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); |
826 | 5391d806 | bellard | s->sector = (r % s->sectors) + 1;
|
827 | 5391d806 | bellard | } |
828 | 5391d806 | bellard | } |
829 | 5391d806 | bellard | |
830 | e162cfb0 | balrog | static void ide_rw_error(IDEState *s) { |
831 | e162cfb0 | balrog | ide_abort_command(s); |
832 | e162cfb0 | balrog | ide_set_irq(s); |
833 | e162cfb0 | balrog | } |
834 | e162cfb0 | balrog | |
835 | 5391d806 | bellard | static void ide_sector_read(IDEState *s) |
836 | 5391d806 | bellard | { |
837 | 5391d806 | bellard | int64_t sector_num; |
838 | 5391d806 | bellard | int ret, n;
|
839 | 5391d806 | bellard | |
840 | 5391d806 | bellard | s->status = READY_STAT | SEEK_STAT; |
841 | a136e5a8 | bellard | s->error = 0; /* not needed by IDE spec, but needed by Windows */ |
842 | 5391d806 | bellard | sector_num = ide_get_sector(s); |
843 | 5391d806 | bellard | n = s->nsector; |
844 | 5391d806 | bellard | if (n == 0) { |
845 | 5391d806 | bellard | /* no more sector to read from disk */
|
846 | 5391d806 | bellard | ide_transfer_stop(s); |
847 | 5391d806 | bellard | } else {
|
848 | 5391d806 | bellard | #if defined(DEBUG_IDE)
|
849 | 18c5f8ea | balrog | printf("read sector=%" PRId64 "\n", sector_num); |
850 | 5391d806 | bellard | #endif
|
851 | 5391d806 | bellard | if (n > s->req_nb_sectors)
|
852 | 5391d806 | bellard | n = s->req_nb_sectors; |
853 | 5391d806 | bellard | ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
854 | e162cfb0 | balrog | if (ret != 0) { |
855 | e162cfb0 | balrog | ide_rw_error(s); |
856 | e162cfb0 | balrog | return;
|
857 | e162cfb0 | balrog | } |
858 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
|
859 | 5391d806 | bellard | ide_set_irq(s); |
860 | 5391d806 | bellard | ide_set_sector(s, sector_num + n); |
861 | 5391d806 | bellard | s->nsector -= n; |
862 | 5391d806 | bellard | } |
863 | 5391d806 | bellard | } |
864 | 5391d806 | bellard | |
865 | e162cfb0 | balrog | static void ide_dma_error(IDEState *s) |
866 | e162cfb0 | balrog | { |
867 | e162cfb0 | balrog | ide_transfer_stop(s); |
868 | e162cfb0 | balrog | s->error = ABRT_ERR; |
869 | e162cfb0 | balrog | s->status = READY_STAT | ERR_STAT; |
870 | e162cfb0 | balrog | ide_set_irq(s); |
871 | e162cfb0 | balrog | } |
872 | e162cfb0 | balrog | |
873 | 8ccad811 | bellard | /* return 0 if buffer completed */
|
874 | 8ccad811 | bellard | static int dma_buf_rw(BMDMAState *bm, int is_write) |
875 | 98087450 | bellard | { |
876 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
877 | 8ccad811 | bellard | struct {
|
878 | 8ccad811 | bellard | uint32_t addr; |
879 | 8ccad811 | bellard | uint32_t size; |
880 | 8ccad811 | bellard | } prd; |
881 | 8ccad811 | bellard | int l, len;
|
882 | 98087450 | bellard | |
883 | 8ccad811 | bellard | for(;;) {
|
884 | 8ccad811 | bellard | l = s->io_buffer_size - s->io_buffer_index; |
885 | 5fafdf24 | ths | if (l <= 0) |
886 | 8ccad811 | bellard | break;
|
887 | 8ccad811 | bellard | if (bm->cur_prd_len == 0) { |
888 | 8ccad811 | bellard | /* end of table (with a fail safe of one page) */
|
889 | 8ccad811 | bellard | if (bm->cur_prd_last ||
|
890 | 8ccad811 | bellard | (bm->cur_addr - bm->addr) >= 4096)
|
891 | 8ccad811 | bellard | return 0; |
892 | 8ccad811 | bellard | cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
|
893 | 8ccad811 | bellard | bm->cur_addr += 8;
|
894 | 8ccad811 | bellard | prd.addr = le32_to_cpu(prd.addr); |
895 | 8ccad811 | bellard | prd.size = le32_to_cpu(prd.size); |
896 | 8ccad811 | bellard | len = prd.size & 0xfffe;
|
897 | 8ccad811 | bellard | if (len == 0) |
898 | 8ccad811 | bellard | len = 0x10000;
|
899 | 8ccad811 | bellard | bm->cur_prd_len = len; |
900 | 8ccad811 | bellard | bm->cur_prd_addr = prd.addr; |
901 | 8ccad811 | bellard | bm->cur_prd_last = (prd.size & 0x80000000);
|
902 | 8ccad811 | bellard | } |
903 | 8ccad811 | bellard | if (l > bm->cur_prd_len)
|
904 | 8ccad811 | bellard | l = bm->cur_prd_len; |
905 | 8ccad811 | bellard | if (l > 0) { |
906 | 8ccad811 | bellard | if (is_write) {
|
907 | 5fafdf24 | ths | cpu_physical_memory_write(bm->cur_prd_addr, |
908 | 8ccad811 | bellard | s->io_buffer + s->io_buffer_index, l); |
909 | 8ccad811 | bellard | } else {
|
910 | 5fafdf24 | ths | cpu_physical_memory_read(bm->cur_prd_addr, |
911 | 8ccad811 | bellard | s->io_buffer + s->io_buffer_index, l); |
912 | 8ccad811 | bellard | } |
913 | 8ccad811 | bellard | bm->cur_prd_addr += l; |
914 | 8ccad811 | bellard | bm->cur_prd_len -= l; |
915 | 8ccad811 | bellard | s->io_buffer_index += l; |
916 | 98087450 | bellard | } |
917 | 98087450 | bellard | } |
918 | 8ccad811 | bellard | return 1; |
919 | 8ccad811 | bellard | } |
920 | 8ccad811 | bellard | |
921 | 8ccad811 | bellard | static void ide_read_dma_cb(void *opaque, int ret) |
922 | 8ccad811 | bellard | { |
923 | 8ccad811 | bellard | BMDMAState *bm = opaque; |
924 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
925 | 8ccad811 | bellard | int n;
|
926 | 8ccad811 | bellard | int64_t sector_num; |
927 | 8ccad811 | bellard | |
928 | e162cfb0 | balrog | if (ret < 0) { |
929 | e162cfb0 | balrog | ide_dma_error(s); |
930 | e162cfb0 | balrog | return;
|
931 | e162cfb0 | balrog | } |
932 | e162cfb0 | balrog | |
933 | 8ccad811 | bellard | n = s->io_buffer_size >> 9;
|
934 | 8ccad811 | bellard | sector_num = ide_get_sector(s); |
935 | 8ccad811 | bellard | if (n > 0) { |
936 | 8ccad811 | bellard | sector_num += n; |
937 | 8ccad811 | bellard | ide_set_sector(s, sector_num); |
938 | 8ccad811 | bellard | s->nsector -= n; |
939 | 8ccad811 | bellard | if (dma_buf_rw(bm, 1) == 0) |
940 | 8ccad811 | bellard | goto eot;
|
941 | 8ccad811 | bellard | } |
942 | 8ccad811 | bellard | |
943 | 8ccad811 | bellard | /* end of transfer ? */
|
944 | 8ccad811 | bellard | if (s->nsector == 0) { |
945 | 98087450 | bellard | s->status = READY_STAT | SEEK_STAT; |
946 | 98087450 | bellard | ide_set_irq(s); |
947 | 8ccad811 | bellard | eot:
|
948 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
949 | 8ccad811 | bellard | bm->status |= BM_STATUS_INT; |
950 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
951 | 8ccad811 | bellard | bm->ide_if = NULL;
|
952 | 8ccad811 | bellard | bm->aiocb = NULL;
|
953 | 8ccad811 | bellard | return;
|
954 | 98087450 | bellard | } |
955 | 8ccad811 | bellard | |
956 | 8ccad811 | bellard | /* launch next transfer */
|
957 | 8ccad811 | bellard | n = s->nsector; |
958 | 1d8cde5b | aurel32 | if (n > IDE_DMA_BUF_SECTORS)
|
959 | 1d8cde5b | aurel32 | n = IDE_DMA_BUF_SECTORS; |
960 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
961 | 8ccad811 | bellard | s->io_buffer_size = n * 512;
|
962 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
963 | 8ccad811 | bellard | printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
|
964 | 8ccad811 | bellard | #endif
|
965 | 5fafdf24 | ths | bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n, |
966 | 8ccad811 | bellard | ide_read_dma_cb, bm); |
967 | 5604e090 | balrog | ide_dma_submit_check(s, ide_read_dma_cb, bm); |
968 | 98087450 | bellard | } |
969 | 98087450 | bellard | |
970 | 98087450 | bellard | static void ide_sector_read_dma(IDEState *s) |
971 | 98087450 | bellard | { |
972 | 8ccad811 | bellard | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
973 | 98087450 | bellard | s->io_buffer_index = 0;
|
974 | 98087450 | bellard | s->io_buffer_size = 0;
|
975 | 98087450 | bellard | ide_dma_start(s, ide_read_dma_cb); |
976 | 98087450 | bellard | } |
977 | 98087450 | bellard | |
978 | a09db21f | bellard | static void ide_sector_write_timer_cb(void *opaque) |
979 | a09db21f | bellard | { |
980 | a09db21f | bellard | IDEState *s = opaque; |
981 | a09db21f | bellard | ide_set_irq(s); |
982 | a09db21f | bellard | } |
983 | a09db21f | bellard | |
984 | 5391d806 | bellard | static void ide_sector_write(IDEState *s) |
985 | 5391d806 | bellard | { |
986 | 5391d806 | bellard | int64_t sector_num; |
987 | 31c2a146 | ths | int ret, n, n1;
|
988 | 5391d806 | bellard | |
989 | 5391d806 | bellard | s->status = READY_STAT | SEEK_STAT; |
990 | 5391d806 | bellard | sector_num = ide_get_sector(s); |
991 | 5391d806 | bellard | #if defined(DEBUG_IDE)
|
992 | 18c5f8ea | balrog | printf("write sector=%" PRId64 "\n", sector_num); |
993 | 5391d806 | bellard | #endif
|
994 | 5391d806 | bellard | n = s->nsector; |
995 | 5391d806 | bellard | if (n > s->req_nb_sectors)
|
996 | 5391d806 | bellard | n = s->req_nb_sectors; |
997 | 31c2a146 | ths | ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
998 | e162cfb0 | balrog | if (ret != 0) { |
999 | e162cfb0 | balrog | ide_rw_error(s); |
1000 | e162cfb0 | balrog | return;
|
1001 | e162cfb0 | balrog | } |
1002 | e162cfb0 | balrog | |
1003 | 5391d806 | bellard | s->nsector -= n; |
1004 | 5391d806 | bellard | if (s->nsector == 0) { |
1005 | 292eef5a | ths | /* no more sectors to write */
|
1006 | 5391d806 | bellard | ide_transfer_stop(s); |
1007 | 5391d806 | bellard | } else {
|
1008 | 5391d806 | bellard | n1 = s->nsector; |
1009 | 5391d806 | bellard | if (n1 > s->req_nb_sectors)
|
1010 | 5391d806 | bellard | n1 = s->req_nb_sectors; |
1011 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
|
1012 | 5391d806 | bellard | } |
1013 | 5391d806 | bellard | ide_set_sector(s, sector_num + n); |
1014 | 3b46e624 | ths | |
1015 | 31c2a146 | ths | #ifdef TARGET_I386
|
1016 | 31c2a146 | ths | if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { |
1017 | 31c2a146 | ths | /* It seems there is a bug in the Windows 2000 installer HDD
|
1018 | 31c2a146 | ths | IDE driver which fills the disk with empty logs when the
|
1019 | 31c2a146 | ths | IDE write IRQ comes too early. This hack tries to correct
|
1020 | 31c2a146 | ths | that at the expense of slower write performances. Use this
|
1021 | 31c2a146 | ths | option _only_ to install Windows 2000. You must disable it
|
1022 | 31c2a146 | ths | for normal use. */
|
1023 | 31c2a146 | ths | qemu_mod_timer(s->sector_write_timer, |
1024 | 31c2a146 | ths | qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
|
1025 | 31c2a146 | ths | } else
|
1026 | 31c2a146 | ths | #endif
|
1027 | 31c2a146 | ths | { |
1028 | 31c2a146 | ths | ide_set_irq(s); |
1029 | 31c2a146 | ths | } |
1030 | 5391d806 | bellard | } |
1031 | 5391d806 | bellard | |
1032 | 8ccad811 | bellard | static void ide_write_dma_cb(void *opaque, int ret) |
1033 | 98087450 | bellard | { |
1034 | 8ccad811 | bellard | BMDMAState *bm = opaque; |
1035 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
1036 | 8ccad811 | bellard | int n;
|
1037 | 98087450 | bellard | int64_t sector_num; |
1038 | 98087450 | bellard | |
1039 | e162cfb0 | balrog | if (ret < 0) { |
1040 | e162cfb0 | balrog | ide_dma_error(s); |
1041 | e162cfb0 | balrog | return;
|
1042 | e162cfb0 | balrog | } |
1043 | e162cfb0 | balrog | |
1044 | 8ccad811 | bellard | n = s->io_buffer_size >> 9;
|
1045 | 8ccad811 | bellard | sector_num = ide_get_sector(s); |
1046 | 8ccad811 | bellard | if (n > 0) { |
1047 | 8ccad811 | bellard | sector_num += n; |
1048 | 8ccad811 | bellard | ide_set_sector(s, sector_num); |
1049 | 8ccad811 | bellard | s->nsector -= n; |
1050 | 98087450 | bellard | } |
1051 | 98087450 | bellard | |
1052 | 8ccad811 | bellard | /* end of transfer ? */
|
1053 | 8ccad811 | bellard | if (s->nsector == 0) { |
1054 | 8ccad811 | bellard | s->status = READY_STAT | SEEK_STAT; |
1055 | 8ccad811 | bellard | ide_set_irq(s); |
1056 | 8ccad811 | bellard | eot:
|
1057 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
1058 | 8ccad811 | bellard | bm->status |= BM_STATUS_INT; |
1059 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
1060 | 8ccad811 | bellard | bm->ide_if = NULL;
|
1061 | 8ccad811 | bellard | bm->aiocb = NULL;
|
1062 | 8ccad811 | bellard | return;
|
1063 | 8ccad811 | bellard | } |
1064 | 8ccad811 | bellard | |
1065 | 8ccad811 | bellard | /* launch next transfer */
|
1066 | 98087450 | bellard | n = s->nsector; |
1067 | 1d8cde5b | aurel32 | if (n > IDE_DMA_BUF_SECTORS)
|
1068 | 1d8cde5b | aurel32 | n = IDE_DMA_BUF_SECTORS; |
1069 | 98087450 | bellard | s->io_buffer_index = 0;
|
1070 | 98087450 | bellard | s->io_buffer_size = n * 512;
|
1071 | 8ccad811 | bellard | |
1072 | 8ccad811 | bellard | if (dma_buf_rw(bm, 0) == 0) |
1073 | 8ccad811 | bellard | goto eot;
|
1074 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
1075 | 8ccad811 | bellard | printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
|
1076 | 8ccad811 | bellard | #endif
|
1077 | 5fafdf24 | ths | bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n, |
1078 | 8ccad811 | bellard | ide_write_dma_cb, bm); |
1079 | 5604e090 | balrog | ide_dma_submit_check(s, ide_write_dma_cb, bm); |
1080 | 8ccad811 | bellard | } |
1081 | 8ccad811 | bellard | |
1082 | 8ccad811 | bellard | static void ide_sector_write_dma(IDEState *s) |
1083 | 8ccad811 | bellard | { |
1084 | 8ccad811 | bellard | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
1085 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
1086 | 8ccad811 | bellard | s->io_buffer_size = 0;
|
1087 | 98087450 | bellard | ide_dma_start(s, ide_write_dma_cb); |
1088 | 98087450 | bellard | } |
1089 | 98087450 | bellard | |
1090 | 5391d806 | bellard | static void ide_atapi_cmd_ok(IDEState *s) |
1091 | 5391d806 | bellard | { |
1092 | 5391d806 | bellard | s->error = 0;
|
1093 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
1094 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1095 | 5391d806 | bellard | ide_set_irq(s); |
1096 | 5391d806 | bellard | } |
1097 | 5391d806 | bellard | |
1098 | 5391d806 | bellard | static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc) |
1099 | 5391d806 | bellard | { |
1100 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1101 | 5391d806 | bellard | printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
|
1102 | 5391d806 | bellard | #endif
|
1103 | 5391d806 | bellard | s->error = sense_key << 4;
|
1104 | 5391d806 | bellard | s->status = READY_STAT | ERR_STAT; |
1105 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1106 | 5391d806 | bellard | s->sense_key = sense_key; |
1107 | 5391d806 | bellard | s->asc = asc; |
1108 | 5391d806 | bellard | ide_set_irq(s); |
1109 | 5391d806 | bellard | } |
1110 | 5391d806 | bellard | |
1111 | 9118e7f0 | aliguori | static void ide_atapi_cmd_check_status(IDEState *s) |
1112 | 9118e7f0 | aliguori | { |
1113 | 9118e7f0 | aliguori | #ifdef DEBUG_IDE_ATAPI
|
1114 | 9118e7f0 | aliguori | printf("atapi_cmd_check_status\n");
|
1115 | 9118e7f0 | aliguori | #endif
|
1116 | 9118e7f0 | aliguori | s->error = MC_ERR | (SENSE_UNIT_ATTENTION << 4);
|
1117 | 9118e7f0 | aliguori | s->status = ERR_STAT; |
1118 | 9118e7f0 | aliguori | s->nsector = 0;
|
1119 | 9118e7f0 | aliguori | ide_set_irq(s); |
1120 | 9118e7f0 | aliguori | } |
1121 | 9118e7f0 | aliguori | |
1122 | 5391d806 | bellard | static inline void cpu_to_ube16(uint8_t *buf, int val) |
1123 | 5391d806 | bellard | { |
1124 | 5391d806 | bellard | buf[0] = val >> 8; |
1125 | 5391d806 | bellard | buf[1] = val;
|
1126 | 5391d806 | bellard | } |
1127 | 5391d806 | bellard | |
1128 | 5391d806 | bellard | static inline void cpu_to_ube32(uint8_t *buf, unsigned int val) |
1129 | 5391d806 | bellard | { |
1130 | 5391d806 | bellard | buf[0] = val >> 24; |
1131 | 5391d806 | bellard | buf[1] = val >> 16; |
1132 | 5391d806 | bellard | buf[2] = val >> 8; |
1133 | 5391d806 | bellard | buf[3] = val;
|
1134 | 5391d806 | bellard | } |
1135 | 5391d806 | bellard | |
1136 | 5391d806 | bellard | static inline int ube16_to_cpu(const uint8_t *buf) |
1137 | 5391d806 | bellard | { |
1138 | 5391d806 | bellard | return (buf[0] << 8) | buf[1]; |
1139 | 5391d806 | bellard | } |
1140 | 5391d806 | bellard | |
1141 | 5391d806 | bellard | static inline int ube32_to_cpu(const uint8_t *buf) |
1142 | 5391d806 | bellard | { |
1143 | 5391d806 | bellard | return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
1144 | 5391d806 | bellard | } |
1145 | 5391d806 | bellard | |
1146 | 98087450 | bellard | static void lba_to_msf(uint8_t *buf, int lba) |
1147 | 98087450 | bellard | { |
1148 | 98087450 | bellard | lba += 150;
|
1149 | 98087450 | bellard | buf[0] = (lba / 75) / 60; |
1150 | 98087450 | bellard | buf[1] = (lba / 75) % 60; |
1151 | 98087450 | bellard | buf[2] = lba % 75; |
1152 | 98087450 | bellard | } |
1153 | 98087450 | bellard | |
1154 | 8ccad811 | bellard | static void cd_data_to_raw(uint8_t *buf, int lba) |
1155 | 8ccad811 | bellard | { |
1156 | 8ccad811 | bellard | /* sync bytes */
|
1157 | 8ccad811 | bellard | buf[0] = 0x00; |
1158 | 8ccad811 | bellard | memset(buf + 1, 0xff, 10); |
1159 | 8ccad811 | bellard | buf[11] = 0x00; |
1160 | 8ccad811 | bellard | buf += 12;
|
1161 | 8ccad811 | bellard | /* MSF */
|
1162 | 8ccad811 | bellard | lba_to_msf(buf, lba); |
1163 | 8ccad811 | bellard | buf[3] = 0x01; /* mode 1 data */ |
1164 | 8ccad811 | bellard | buf += 4;
|
1165 | 8ccad811 | bellard | /* data */
|
1166 | 8ccad811 | bellard | buf += 2048;
|
1167 | 8ccad811 | bellard | /* XXX: ECC not computed */
|
1168 | 8ccad811 | bellard | memset(buf, 0, 288); |
1169 | 8ccad811 | bellard | } |
1170 | 8ccad811 | bellard | |
1171 | 5fafdf24 | ths | static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf, |
1172 | 98087450 | bellard | int sector_size)
|
1173 | 98087450 | bellard | { |
1174 | 66c6ef76 | bellard | int ret;
|
1175 | 66c6ef76 | bellard | |
1176 | 98087450 | bellard | switch(sector_size) {
|
1177 | 98087450 | bellard | case 2048: |
1178 | 66c6ef76 | bellard | ret = bdrv_read(bs, (int64_t)lba << 2, buf, 4); |
1179 | 98087450 | bellard | break;
|
1180 | 98087450 | bellard | case 2352: |
1181 | 66c6ef76 | bellard | ret = bdrv_read(bs, (int64_t)lba << 2, buf + 16, 4); |
1182 | 66c6ef76 | bellard | if (ret < 0) |
1183 | 66c6ef76 | bellard | return ret;
|
1184 | 8ccad811 | bellard | cd_data_to_raw(buf, lba); |
1185 | 98087450 | bellard | break;
|
1186 | 98087450 | bellard | default:
|
1187 | 66c6ef76 | bellard | ret = -EIO; |
1188 | 98087450 | bellard | break;
|
1189 | 98087450 | bellard | } |
1190 | 66c6ef76 | bellard | return ret;
|
1191 | 66c6ef76 | bellard | } |
1192 | 66c6ef76 | bellard | |
1193 | 66c6ef76 | bellard | static void ide_atapi_io_error(IDEState *s, int ret) |
1194 | 66c6ef76 | bellard | { |
1195 | 66c6ef76 | bellard | /* XXX: handle more errors */
|
1196 | 66c6ef76 | bellard | if (ret == -ENOMEDIUM) {
|
1197 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1198 | 66c6ef76 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1199 | 66c6ef76 | bellard | } else {
|
1200 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1201 | 66c6ef76 | bellard | ASC_LOGICAL_BLOCK_OOR); |
1202 | 66c6ef76 | bellard | } |
1203 | 98087450 | bellard | } |
1204 | 98087450 | bellard | |
1205 | 5391d806 | bellard | /* The whole ATAPI transfer logic is handled in this function */
|
1206 | 5391d806 | bellard | static void ide_atapi_cmd_reply_end(IDEState *s) |
1207 | 5391d806 | bellard | { |
1208 | 66c6ef76 | bellard | int byte_count_limit, size, ret;
|
1209 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1210 | 5fafdf24 | ths | printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
|
1211 | 5391d806 | bellard | s->packet_transfer_size, |
1212 | 5391d806 | bellard | s->elementary_transfer_size, |
1213 | 5391d806 | bellard | s->io_buffer_index); |
1214 | 5391d806 | bellard | #endif
|
1215 | 5391d806 | bellard | if (s->packet_transfer_size <= 0) { |
1216 | 5391d806 | bellard | /* end of transfer */
|
1217 | 5391d806 | bellard | ide_transfer_stop(s); |
1218 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
1219 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1220 | 5391d806 | bellard | ide_set_irq(s); |
1221 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1222 | 5391d806 | bellard | printf("status=0x%x\n", s->status);
|
1223 | 5391d806 | bellard | #endif
|
1224 | 5391d806 | bellard | } else {
|
1225 | 5391d806 | bellard | /* see if a new sector must be read */
|
1226 | 98087450 | bellard | if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) { |
1227 | 66c6ef76 | bellard | ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size); |
1228 | 66c6ef76 | bellard | if (ret < 0) { |
1229 | 66c6ef76 | bellard | ide_transfer_stop(s); |
1230 | 66c6ef76 | bellard | ide_atapi_io_error(s, ret); |
1231 | 66c6ef76 | bellard | return;
|
1232 | 66c6ef76 | bellard | } |
1233 | 5391d806 | bellard | s->lba++; |
1234 | 5391d806 | bellard | s->io_buffer_index = 0;
|
1235 | 5391d806 | bellard | } |
1236 | 5391d806 | bellard | if (s->elementary_transfer_size > 0) { |
1237 | 5391d806 | bellard | /* there are some data left to transmit in this elementary
|
1238 | 5391d806 | bellard | transfer */
|
1239 | 98087450 | bellard | size = s->cd_sector_size - s->io_buffer_index; |
1240 | 5391d806 | bellard | if (size > s->elementary_transfer_size)
|
1241 | 5391d806 | bellard | size = s->elementary_transfer_size; |
1242 | 5fafdf24 | ths | ide_transfer_start(s, s->io_buffer + s->io_buffer_index, |
1243 | 5391d806 | bellard | size, ide_atapi_cmd_reply_end); |
1244 | 5391d806 | bellard | s->packet_transfer_size -= size; |
1245 | 5391d806 | bellard | s->elementary_transfer_size -= size; |
1246 | 5391d806 | bellard | s->io_buffer_index += size; |
1247 | 5391d806 | bellard | } else {
|
1248 | 5391d806 | bellard | /* a new transfer is needed */
|
1249 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
|
1250 | 5391d806 | bellard | byte_count_limit = s->lcyl | (s->hcyl << 8);
|
1251 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1252 | 5391d806 | bellard | printf("byte_count_limit=%d\n", byte_count_limit);
|
1253 | 5391d806 | bellard | #endif
|
1254 | 5391d806 | bellard | if (byte_count_limit == 0xffff) |
1255 | 5391d806 | bellard | byte_count_limit--; |
1256 | 5391d806 | bellard | size = s->packet_transfer_size; |
1257 | 5391d806 | bellard | if (size > byte_count_limit) {
|
1258 | 5391d806 | bellard | /* byte count limit must be even if this case */
|
1259 | 5391d806 | bellard | if (byte_count_limit & 1) |
1260 | 5391d806 | bellard | byte_count_limit--; |
1261 | 5391d806 | bellard | size = byte_count_limit; |
1262 | 5391d806 | bellard | } |
1263 | a136e5a8 | bellard | s->lcyl = size; |
1264 | a136e5a8 | bellard | s->hcyl = size >> 8;
|
1265 | 5391d806 | bellard | s->elementary_transfer_size = size; |
1266 | 5391d806 | bellard | /* we cannot transmit more than one sector at a time */
|
1267 | 5391d806 | bellard | if (s->lba != -1) { |
1268 | 98087450 | bellard | if (size > (s->cd_sector_size - s->io_buffer_index))
|
1269 | 98087450 | bellard | size = (s->cd_sector_size - s->io_buffer_index); |
1270 | 5391d806 | bellard | } |
1271 | 5fafdf24 | ths | ide_transfer_start(s, s->io_buffer + s->io_buffer_index, |
1272 | 5391d806 | bellard | size, ide_atapi_cmd_reply_end); |
1273 | 5391d806 | bellard | s->packet_transfer_size -= size; |
1274 | 5391d806 | bellard | s->elementary_transfer_size -= size; |
1275 | 5391d806 | bellard | s->io_buffer_index += size; |
1276 | 5391d806 | bellard | ide_set_irq(s); |
1277 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1278 | 5391d806 | bellard | printf("status=0x%x\n", s->status);
|
1279 | 5391d806 | bellard | #endif
|
1280 | 5391d806 | bellard | } |
1281 | 5391d806 | bellard | } |
1282 | 5391d806 | bellard | } |
1283 | 5391d806 | bellard | |
1284 | 5391d806 | bellard | /* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
|
1285 | 5391d806 | bellard | static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size) |
1286 | 5391d806 | bellard | { |
1287 | 5391d806 | bellard | if (size > max_size)
|
1288 | 5391d806 | bellard | size = max_size; |
1289 | 5391d806 | bellard | s->lba = -1; /* no sector read */ |
1290 | 5391d806 | bellard | s->packet_transfer_size = size; |
1291 | 5f12ab4b | ths | s->io_buffer_size = size; /* dma: send the reply data as one chunk */
|
1292 | 5391d806 | bellard | s->elementary_transfer_size = 0;
|
1293 | 5391d806 | bellard | s->io_buffer_index = 0;
|
1294 | 5391d806 | bellard | |
1295 | 5f12ab4b | ths | if (s->atapi_dma) {
|
1296 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT | DRQ_STAT; |
1297 | 5f12ab4b | ths | ide_dma_start(s, ide_atapi_cmd_read_dma_cb); |
1298 | 5f12ab4b | ths | } else {
|
1299 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
1300 | 5f12ab4b | ths | ide_atapi_cmd_reply_end(s); |
1301 | 5f12ab4b | ths | } |
1302 | 5391d806 | bellard | } |
1303 | 5391d806 | bellard | |
1304 | 5391d806 | bellard | /* start a CD-CDROM read command */
|
1305 | 98087450 | bellard | static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors, |
1306 | 98087450 | bellard | int sector_size)
|
1307 | 5391d806 | bellard | { |
1308 | 5391d806 | bellard | s->lba = lba; |
1309 | 98087450 | bellard | s->packet_transfer_size = nb_sectors * sector_size; |
1310 | 5391d806 | bellard | s->elementary_transfer_size = 0;
|
1311 | 98087450 | bellard | s->io_buffer_index = sector_size; |
1312 | 98087450 | bellard | s->cd_sector_size = sector_size; |
1313 | 5391d806 | bellard | |
1314 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
1315 | 5391d806 | bellard | ide_atapi_cmd_reply_end(s); |
1316 | 5391d806 | bellard | } |
1317 | 5391d806 | bellard | |
1318 | 98087450 | bellard | /* ATAPI DMA support */
|
1319 | 8ccad811 | bellard | |
1320 | 8ccad811 | bellard | /* XXX: handle read errors */
|
1321 | 8ccad811 | bellard | static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret) |
1322 | 98087450 | bellard | { |
1323 | 8ccad811 | bellard | BMDMAState *bm = opaque; |
1324 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
1325 | 8ccad811 | bellard | int data_offset, n;
|
1326 | 8ccad811 | bellard | |
1327 | 66c6ef76 | bellard | if (ret < 0) { |
1328 | 66c6ef76 | bellard | ide_atapi_io_error(s, ret); |
1329 | 66c6ef76 | bellard | goto eot;
|
1330 | 66c6ef76 | bellard | } |
1331 | 66c6ef76 | bellard | |
1332 | 8ccad811 | bellard | if (s->io_buffer_size > 0) { |
1333 | 5f12ab4b | ths | /*
|
1334 | 5f12ab4b | ths | * For a cdrom read sector command (s->lba != -1),
|
1335 | 5f12ab4b | ths | * adjust the lba for the next s->io_buffer_size chunk
|
1336 | 5f12ab4b | ths | * and dma the current chunk.
|
1337 | 5f12ab4b | ths | * For a command != read (s->lba == -1), just transfer
|
1338 | 5f12ab4b | ths | * the reply data.
|
1339 | 5f12ab4b | ths | */
|
1340 | 5f12ab4b | ths | if (s->lba != -1) { |
1341 | 5f12ab4b | ths | if (s->cd_sector_size == 2352) { |
1342 | 5f12ab4b | ths | n = 1;
|
1343 | 5f12ab4b | ths | cd_data_to_raw(s->io_buffer, s->lba); |
1344 | 5f12ab4b | ths | } else {
|
1345 | 5f12ab4b | ths | n = s->io_buffer_size >> 11;
|
1346 | 5f12ab4b | ths | } |
1347 | 5f12ab4b | ths | s->lba += n; |
1348 | 5f12ab4b | ths | } |
1349 | 8ccad811 | bellard | s->packet_transfer_size -= s->io_buffer_size; |
1350 | 8ccad811 | bellard | if (dma_buf_rw(bm, 1) == 0) |
1351 | 8ccad811 | bellard | goto eot;
|
1352 | 98087450 | bellard | } |
1353 | 8ccad811 | bellard | |
1354 | 98087450 | bellard | if (s->packet_transfer_size <= 0) { |
1355 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
1356 | 98087450 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1357 | 98087450 | bellard | ide_set_irq(s); |
1358 | 8ccad811 | bellard | eot:
|
1359 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
1360 | 8ccad811 | bellard | bm->status |= BM_STATUS_INT; |
1361 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
1362 | 8ccad811 | bellard | bm->ide_if = NULL;
|
1363 | 8ccad811 | bellard | bm->aiocb = NULL;
|
1364 | 8ccad811 | bellard | return;
|
1365 | 8ccad811 | bellard | } |
1366 | 3b46e624 | ths | |
1367 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
1368 | 8ccad811 | bellard | if (s->cd_sector_size == 2352) { |
1369 | 8ccad811 | bellard | n = 1;
|
1370 | 8ccad811 | bellard | s->io_buffer_size = s->cd_sector_size; |
1371 | 8ccad811 | bellard | data_offset = 16;
|
1372 | 8ccad811 | bellard | } else {
|
1373 | 8ccad811 | bellard | n = s->packet_transfer_size >> 11;
|
1374 | 1d8cde5b | aurel32 | if (n > (IDE_DMA_BUF_SECTORS / 4)) |
1375 | 1d8cde5b | aurel32 | n = (IDE_DMA_BUF_SECTORS / 4);
|
1376 | 8ccad811 | bellard | s->io_buffer_size = n * 2048;
|
1377 | 8ccad811 | bellard | data_offset = 0;
|
1378 | 98087450 | bellard | } |
1379 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
1380 | 8ccad811 | bellard | printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
|
1381 | 8ccad811 | bellard | #endif
|
1382 | 5fafdf24 | ths | bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2,
|
1383 | 5fafdf24 | ths | s->io_buffer + data_offset, n * 4,
|
1384 | 8ccad811 | bellard | ide_atapi_cmd_read_dma_cb, bm); |
1385 | 66c6ef76 | bellard | if (!bm->aiocb) {
|
1386 | 66c6ef76 | bellard | /* Note: media not present is the most likely case */
|
1387 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1388 | 66c6ef76 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1389 | 66c6ef76 | bellard | goto eot;
|
1390 | 66c6ef76 | bellard | } |
1391 | 98087450 | bellard | } |
1392 | 98087450 | bellard | |
1393 | 98087450 | bellard | /* start a CD-CDROM read command with DMA */
|
1394 | 98087450 | bellard | /* XXX: test if DMA is available */
|
1395 | 98087450 | bellard | static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors, |
1396 | 98087450 | bellard | int sector_size)
|
1397 | 98087450 | bellard | { |
1398 | 98087450 | bellard | s->lba = lba; |
1399 | 98087450 | bellard | s->packet_transfer_size = nb_sectors * sector_size; |
1400 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
1401 | 8ccad811 | bellard | s->io_buffer_size = 0;
|
1402 | 98087450 | bellard | s->cd_sector_size = sector_size; |
1403 | 98087450 | bellard | |
1404 | 8ccad811 | bellard | /* XXX: check if BUSY_STAT should be set */
|
1405 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
1406 | 98087450 | bellard | ide_dma_start(s, ide_atapi_cmd_read_dma_cb); |
1407 | 98087450 | bellard | } |
1408 | 98087450 | bellard | |
1409 | 5fafdf24 | ths | static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors, |
1410 | 98087450 | bellard | int sector_size)
|
1411 | 98087450 | bellard | { |
1412 | 98087450 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1413 | 5f12ab4b | ths | printf("read %s: LBA=%d nb_sectors=%d\n", s->atapi_dma ? "dma" : "pio", |
1414 | 5f12ab4b | ths | lba, nb_sectors); |
1415 | 98087450 | bellard | #endif
|
1416 | 98087450 | bellard | if (s->atapi_dma) {
|
1417 | 98087450 | bellard | ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size); |
1418 | 98087450 | bellard | } else {
|
1419 | 98087450 | bellard | ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size); |
1420 | 98087450 | bellard | } |
1421 | 98087450 | bellard | } |
1422 | 98087450 | bellard | |
1423 | 38cdea7c | balrog | static inline uint8_t ide_atapi_set_profile(uint8_t *buf, uint8_t *index, |
1424 | 38cdea7c | balrog | uint16_t profile) |
1425 | 38cdea7c | balrog | { |
1426 | 38cdea7c | balrog | uint8_t *buf_profile = buf + 12; /* start of profiles */ |
1427 | 38cdea7c | balrog | |
1428 | 38cdea7c | balrog | buf_profile += ((*index) * 4); /* start of indexed profile */ |
1429 | 38cdea7c | balrog | cpu_to_ube16 (buf_profile, profile); |
1430 | 38cdea7c | balrog | buf_profile[2] = ((buf_profile[0] == buf[6]) && (buf_profile[1] == buf[7])); |
1431 | 38cdea7c | balrog | |
1432 | 38cdea7c | balrog | /* each profile adds 4 bytes to the response */
|
1433 | 38cdea7c | balrog | (*index)++; |
1434 | 38cdea7c | balrog | buf[11] += 4; /* Additional Length */ |
1435 | 38cdea7c | balrog | |
1436 | 38cdea7c | balrog | return 4; |
1437 | 38cdea7c | balrog | } |
1438 | 38cdea7c | balrog | |
1439 | 8114e9e8 | ths | static int ide_dvd_read_structure(IDEState *s, int format, |
1440 | 8114e9e8 | ths | const uint8_t *packet, uint8_t *buf)
|
1441 | 8114e9e8 | ths | { |
1442 | 8114e9e8 | ths | switch (format) {
|
1443 | 8114e9e8 | ths | case 0x0: /* Physical format information */ |
1444 | 8114e9e8 | ths | { |
1445 | 8114e9e8 | ths | int layer = packet[6]; |
1446 | 8114e9e8 | ths | uint64_t total_sectors; |
1447 | 8114e9e8 | ths | |
1448 | 8114e9e8 | ths | if (layer != 0) |
1449 | 8114e9e8 | ths | return -ASC_INV_FIELD_IN_CMD_PACKET;
|
1450 | 8114e9e8 | ths | |
1451 | 8114e9e8 | ths | bdrv_get_geometry(s->bs, &total_sectors); |
1452 | 8114e9e8 | ths | total_sectors >>= 2;
|
1453 | 8114e9e8 | ths | if (total_sectors == 0) |
1454 | 8114e9e8 | ths | return -ASC_MEDIUM_NOT_PRESENT;
|
1455 | 8114e9e8 | ths | |
1456 | 8114e9e8 | ths | buf[4] = 1; /* DVD-ROM, part version 1 */ |
1457 | 8114e9e8 | ths | buf[5] = 0xf; /* 120mm disc, minimum rate unspecified */ |
1458 | 8114e9e8 | ths | buf[6] = 1; /* one layer, read-only (per MMC-2 spec) */ |
1459 | 8114e9e8 | ths | buf[7] = 0; /* default densities */ |
1460 | 8114e9e8 | ths | |
1461 | 8114e9e8 | ths | /* FIXME: 0x30000 per spec? */
|
1462 | 8114e9e8 | ths | cpu_to_ube32(buf + 8, 0); /* start sector */ |
1463 | 8114e9e8 | ths | cpu_to_ube32(buf + 12, total_sectors - 1); /* end sector */ |
1464 | 8114e9e8 | ths | cpu_to_ube32(buf + 16, total_sectors - 1); /* l0 end sector */ |
1465 | 8114e9e8 | ths | |
1466 | 8114e9e8 | ths | /* Size of buffer, not including 2 byte size field */
|
1467 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)buf, 2048 + 2); |
1468 | 8114e9e8 | ths | |
1469 | 8114e9e8 | ths | /* 2k data + 4 byte header */
|
1470 | 8114e9e8 | ths | return (2048 + 4); |
1471 | 8114e9e8 | ths | } |
1472 | 8114e9e8 | ths | |
1473 | 8114e9e8 | ths | case 0x01: /* DVD copyright information */ |
1474 | 8114e9e8 | ths | buf[4] = 0; /* no copyright data */ |
1475 | 8114e9e8 | ths | buf[5] = 0; /* no region restrictions */ |
1476 | 8114e9e8 | ths | |
1477 | 8114e9e8 | ths | /* Size of buffer, not including 2 byte size field */
|
1478 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)buf, 4 + 2); |
1479 | 8114e9e8 | ths | |
1480 | 8114e9e8 | ths | /* 4 byte header + 4 byte data */
|
1481 | 8114e9e8 | ths | return (4 + 4); |
1482 | 8114e9e8 | ths | |
1483 | 8114e9e8 | ths | case 0x03: /* BCA information - invalid field for no BCA info */ |
1484 | 8114e9e8 | ths | return -ASC_INV_FIELD_IN_CMD_PACKET;
|
1485 | 8114e9e8 | ths | |
1486 | 8114e9e8 | ths | case 0x04: /* DVD disc manufacturing information */ |
1487 | 8114e9e8 | ths | /* Size of buffer, not including 2 byte size field */
|
1488 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)buf, 2048 + 2); |
1489 | 8114e9e8 | ths | |
1490 | 8114e9e8 | ths | /* 2k data + 4 byte header */
|
1491 | 8114e9e8 | ths | return (2048 + 4); |
1492 | 8114e9e8 | ths | |
1493 | 8114e9e8 | ths | case 0xff: |
1494 | 8114e9e8 | ths | /*
|
1495 | 8114e9e8 | ths | * This lists all the command capabilities above. Add new ones
|
1496 | 8114e9e8 | ths | * in order and update the length and buffer return values.
|
1497 | 8114e9e8 | ths | */
|
1498 | 8114e9e8 | ths | |
1499 | 8114e9e8 | ths | buf[4] = 0x00; /* Physical format */ |
1500 | 8114e9e8 | ths | buf[5] = 0x40; /* Not writable, is readable */ |
1501 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)(buf + 6), 2048 + 4); |
1502 | 8114e9e8 | ths | |
1503 | 8114e9e8 | ths | buf[8] = 0x01; /* Copyright info */ |
1504 | 8114e9e8 | ths | buf[9] = 0x40; /* Not writable, is readable */ |
1505 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)(buf + 10), 4 + 4); |
1506 | 8114e9e8 | ths | |
1507 | 8114e9e8 | ths | buf[12] = 0x03; /* BCA info */ |
1508 | 8114e9e8 | ths | buf[13] = 0x40; /* Not writable, is readable */ |
1509 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)(buf + 14), 188 + 4); |
1510 | 8114e9e8 | ths | |
1511 | 8114e9e8 | ths | buf[16] = 0x04; /* Manufacturing info */ |
1512 | 8114e9e8 | ths | buf[17] = 0x40; /* Not writable, is readable */ |
1513 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)(buf + 18), 2048 + 4); |
1514 | 8114e9e8 | ths | |
1515 | 8114e9e8 | ths | /* Size of buffer, not including 2 byte size field */
|
1516 | 8114e9e8 | ths | cpu_to_be16wu((uint16_t *)buf, 16 + 2); |
1517 | 8114e9e8 | ths | |
1518 | 8114e9e8 | ths | /* data written + 4 byte header */
|
1519 | 8114e9e8 | ths | return (16 + 4); |
1520 | 8114e9e8 | ths | |
1521 | 8114e9e8 | ths | default: /* TODO: formats beyond DVD-ROM requires */ |
1522 | 8114e9e8 | ths | return -ASC_INV_FIELD_IN_CMD_PACKET;
|
1523 | 8114e9e8 | ths | } |
1524 | 8114e9e8 | ths | } |
1525 | 8114e9e8 | ths | |
1526 | 5391d806 | bellard | static void ide_atapi_cmd(IDEState *s) |
1527 | 5391d806 | bellard | { |
1528 | 5391d806 | bellard | const uint8_t *packet;
|
1529 | 5391d806 | bellard | uint8_t *buf; |
1530 | 5391d806 | bellard | int max_len;
|
1531 | 5391d806 | bellard | |
1532 | 5391d806 | bellard | packet = s->io_buffer; |
1533 | 5391d806 | bellard | buf = s->io_buffer; |
1534 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1535 | 5391d806 | bellard | { |
1536 | 5391d806 | bellard | int i;
|
1537 | 5391d806 | bellard | printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8)); |
1538 | 5391d806 | bellard | for(i = 0; i < ATAPI_PACKET_SIZE; i++) { |
1539 | 5391d806 | bellard | printf(" %02x", packet[i]);
|
1540 | 5391d806 | bellard | } |
1541 | 5391d806 | bellard | printf("\n");
|
1542 | 5391d806 | bellard | } |
1543 | 5391d806 | bellard | #endif
|
1544 | 9118e7f0 | aliguori | /* If there's a UNIT_ATTENTION condition pending, only
|
1545 | 9118e7f0 | aliguori | REQUEST_SENSE and INQUIRY commands are allowed to complete. */
|
1546 | 9118e7f0 | aliguori | if (s->sense_key == SENSE_UNIT_ATTENTION &&
|
1547 | 9118e7f0 | aliguori | s->io_buffer[0] != GPCMD_REQUEST_SENSE &&
|
1548 | 9118e7f0 | aliguori | s->io_buffer[0] != GPCMD_INQUIRY) {
|
1549 | 9118e7f0 | aliguori | ide_atapi_cmd_check_status(s); |
1550 | 9118e7f0 | aliguori | return;
|
1551 | 9118e7f0 | aliguori | } |
1552 | 5391d806 | bellard | switch(s->io_buffer[0]) { |
1553 | 5391d806 | bellard | case GPCMD_TEST_UNIT_READY:
|
1554 | caed8802 | bellard | if (bdrv_is_inserted(s->bs)) {
|
1555 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1556 | 5391d806 | bellard | } else {
|
1557 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1558 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1559 | 5391d806 | bellard | } |
1560 | 5391d806 | bellard | break;
|
1561 | d14049ea | ths | case GPCMD_MODE_SENSE_6:
|
1562 | 5391d806 | bellard | case GPCMD_MODE_SENSE_10:
|
1563 | 5391d806 | bellard | { |
1564 | 5391d806 | bellard | int action, code;
|
1565 | d14049ea | ths | if (packet[0] == GPCMD_MODE_SENSE_10) |
1566 | d14049ea | ths | max_len = ube16_to_cpu(packet + 7);
|
1567 | d14049ea | ths | else
|
1568 | d14049ea | ths | max_len = packet[4];
|
1569 | 5391d806 | bellard | action = packet[2] >> 6; |
1570 | 5391d806 | bellard | code = packet[2] & 0x3f; |
1571 | 5391d806 | bellard | switch(action) {
|
1572 | 5391d806 | bellard | case 0: /* current values */ |
1573 | 5391d806 | bellard | switch(code) {
|
1574 | 5391d806 | bellard | case 0x01: /* error recovery */ |
1575 | 5391d806 | bellard | cpu_to_ube16(&buf[0], 16 + 6); |
1576 | 5391d806 | bellard | buf[2] = 0x70; |
1577 | 5391d806 | bellard | buf[3] = 0; |
1578 | 5391d806 | bellard | buf[4] = 0; |
1579 | 5391d806 | bellard | buf[5] = 0; |
1580 | 5391d806 | bellard | buf[6] = 0; |
1581 | 5391d806 | bellard | buf[7] = 0; |
1582 | 5391d806 | bellard | |
1583 | 5391d806 | bellard | buf[8] = 0x01; |
1584 | 5391d806 | bellard | buf[9] = 0x06; |
1585 | 5391d806 | bellard | buf[10] = 0x00; |
1586 | 5391d806 | bellard | buf[11] = 0x05; |
1587 | 5391d806 | bellard | buf[12] = 0x00; |
1588 | 5391d806 | bellard | buf[13] = 0x00; |
1589 | 5391d806 | bellard | buf[14] = 0x00; |
1590 | 5391d806 | bellard | buf[15] = 0x00; |
1591 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 16, max_len);
|
1592 | 5391d806 | bellard | break;
|
1593 | 5391d806 | bellard | case 0x2a: |
1594 | 5391d806 | bellard | cpu_to_ube16(&buf[0], 28 + 6); |
1595 | 5391d806 | bellard | buf[2] = 0x70; |
1596 | 5391d806 | bellard | buf[3] = 0; |
1597 | 5391d806 | bellard | buf[4] = 0; |
1598 | 5391d806 | bellard | buf[5] = 0; |
1599 | 5391d806 | bellard | buf[6] = 0; |
1600 | 5391d806 | bellard | buf[7] = 0; |
1601 | 5391d806 | bellard | |
1602 | 5391d806 | bellard | buf[8] = 0x2a; |
1603 | 5391d806 | bellard | buf[9] = 0x12; |
1604 | 0d4a05a1 | ths | buf[10] = 0x00; |
1605 | 5391d806 | bellard | buf[11] = 0x00; |
1606 | 3b46e624 | ths | |
1607 | d5b4eb40 | aliguori | /* Claim PLAY_AUDIO capability (0x01) since some Linux
|
1608 | d5b4eb40 | aliguori | code checks for this to automount media. */
|
1609 | d5b4eb40 | aliguori | buf[12] = 0x71; |
1610 | 5391d806 | bellard | buf[13] = 3 << 5; |
1611 | 5391d806 | bellard | buf[14] = (1 << 0) | (1 << 3) | (1 << 5); |
1612 | caed8802 | bellard | if (bdrv_is_locked(s->bs))
|
1613 | 5391d806 | bellard | buf[6] |= 1 << 1; |
1614 | 5391d806 | bellard | buf[15] = 0x00; |
1615 | 5391d806 | bellard | cpu_to_ube16(&buf[16], 706); |
1616 | 5391d806 | bellard | buf[18] = 0; |
1617 | 5391d806 | bellard | buf[19] = 2; |
1618 | 5391d806 | bellard | cpu_to_ube16(&buf[20], 512); |
1619 | 5391d806 | bellard | cpu_to_ube16(&buf[22], 706); |
1620 | 5391d806 | bellard | buf[24] = 0; |
1621 | 5391d806 | bellard | buf[25] = 0; |
1622 | 5391d806 | bellard | buf[26] = 0; |
1623 | 5391d806 | bellard | buf[27] = 0; |
1624 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 28, max_len);
|
1625 | 5391d806 | bellard | break;
|
1626 | 5391d806 | bellard | default:
|
1627 | 5391d806 | bellard | goto error_cmd;
|
1628 | 5391d806 | bellard | } |
1629 | 5391d806 | bellard | break;
|
1630 | 5391d806 | bellard | case 1: /* changeable values */ |
1631 | 5391d806 | bellard | goto error_cmd;
|
1632 | 5391d806 | bellard | case 2: /* default values */ |
1633 | 5391d806 | bellard | goto error_cmd;
|
1634 | 5391d806 | bellard | default:
|
1635 | 5391d806 | bellard | case 3: /* saved values */ |
1636 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1637 | 5391d806 | bellard | ASC_SAVING_PARAMETERS_NOT_SUPPORTED); |
1638 | 5391d806 | bellard | break;
|
1639 | 5391d806 | bellard | } |
1640 | 5391d806 | bellard | } |
1641 | 5391d806 | bellard | break;
|
1642 | 5391d806 | bellard | case GPCMD_REQUEST_SENSE:
|
1643 | 5391d806 | bellard | max_len = packet[4];
|
1644 | 5391d806 | bellard | memset(buf, 0, 18); |
1645 | 5391d806 | bellard | buf[0] = 0x70 | (1 << 7); |
1646 | 5391d806 | bellard | buf[2] = s->sense_key;
|
1647 | 5391d806 | bellard | buf[7] = 10; |
1648 | 5391d806 | bellard | buf[12] = s->asc;
|
1649 | 9118e7f0 | aliguori | if (s->sense_key == SENSE_UNIT_ATTENTION)
|
1650 | 9118e7f0 | aliguori | s->sense_key = SENSE_NONE; |
1651 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 18, max_len);
|
1652 | 5391d806 | bellard | break;
|
1653 | 5391d806 | bellard | case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
|
1654 | caed8802 | bellard | if (bdrv_is_inserted(s->bs)) {
|
1655 | caed8802 | bellard | bdrv_set_locked(s->bs, packet[4] & 1); |
1656 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1657 | 5391d806 | bellard | } else {
|
1658 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1659 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1660 | 5391d806 | bellard | } |
1661 | 5391d806 | bellard | break;
|
1662 | 5391d806 | bellard | case GPCMD_READ_10:
|
1663 | 5391d806 | bellard | case GPCMD_READ_12:
|
1664 | 5391d806 | bellard | { |
1665 | 5391d806 | bellard | int nb_sectors, lba;
|
1666 | 5391d806 | bellard | |
1667 | 5391d806 | bellard | if (packet[0] == GPCMD_READ_10) |
1668 | 5391d806 | bellard | nb_sectors = ube16_to_cpu(packet + 7);
|
1669 | 5391d806 | bellard | else
|
1670 | 5391d806 | bellard | nb_sectors = ube32_to_cpu(packet + 6);
|
1671 | 5391d806 | bellard | lba = ube32_to_cpu(packet + 2);
|
1672 | 5391d806 | bellard | if (nb_sectors == 0) { |
1673 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1674 | 5391d806 | bellard | break;
|
1675 | 5391d806 | bellard | } |
1676 | 98087450 | bellard | ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
|
1677 | 98087450 | bellard | } |
1678 | 98087450 | bellard | break;
|
1679 | 98087450 | bellard | case GPCMD_READ_CD:
|
1680 | 98087450 | bellard | { |
1681 | 98087450 | bellard | int nb_sectors, lba, transfer_request;
|
1682 | 98087450 | bellard | |
1683 | 98087450 | bellard | nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8]; |
1684 | 98087450 | bellard | lba = ube32_to_cpu(packet + 2);
|
1685 | 98087450 | bellard | if (nb_sectors == 0) { |
1686 | 98087450 | bellard | ide_atapi_cmd_ok(s); |
1687 | 98087450 | bellard | break;
|
1688 | 98087450 | bellard | } |
1689 | 98087450 | bellard | transfer_request = packet[9];
|
1690 | 98087450 | bellard | switch(transfer_request & 0xf8) { |
1691 | 98087450 | bellard | case 0x00: |
1692 | 98087450 | bellard | /* nothing */
|
1693 | 98087450 | bellard | ide_atapi_cmd_ok(s); |
1694 | 98087450 | bellard | break;
|
1695 | 98087450 | bellard | case 0x10: |
1696 | 98087450 | bellard | /* normal read */
|
1697 | 98087450 | bellard | ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
|
1698 | 98087450 | bellard | break;
|
1699 | 98087450 | bellard | case 0xf8: |
1700 | 98087450 | bellard | /* read all data */
|
1701 | 98087450 | bellard | ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
|
1702 | 98087450 | bellard | break;
|
1703 | 98087450 | bellard | default:
|
1704 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1705 | 98087450 | bellard | ASC_INV_FIELD_IN_CMD_PACKET); |
1706 | 98087450 | bellard | break;
|
1707 | 98087450 | bellard | } |
1708 | 5391d806 | bellard | } |
1709 | 5391d806 | bellard | break;
|
1710 | 5391d806 | bellard | case GPCMD_SEEK:
|
1711 | 5391d806 | bellard | { |
1712 | 96b8f136 | ths | unsigned int lba; |
1713 | 96b8f136 | ths | uint64_t total_sectors; |
1714 | 66c6ef76 | bellard | |
1715 | 66c6ef76 | bellard | bdrv_get_geometry(s->bs, &total_sectors); |
1716 | 66c6ef76 | bellard | total_sectors >>= 2;
|
1717 | 96b8f136 | ths | if (total_sectors == 0) { |
1718 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1719 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1720 | 5391d806 | bellard | break;
|
1721 | 5391d806 | bellard | } |
1722 | 5391d806 | bellard | lba = ube32_to_cpu(packet + 2);
|
1723 | 66c6ef76 | bellard | if (lba >= total_sectors) {
|
1724 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1725 | 5391d806 | bellard | ASC_LOGICAL_BLOCK_OOR); |
1726 | 5391d806 | bellard | break;
|
1727 | 5391d806 | bellard | } |
1728 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1729 | 5391d806 | bellard | } |
1730 | 5391d806 | bellard | break;
|
1731 | 5391d806 | bellard | case GPCMD_START_STOP_UNIT:
|
1732 | 5391d806 | bellard | { |
1733 | 5391d806 | bellard | int start, eject;
|
1734 | 5391d806 | bellard | start = packet[4] & 1; |
1735 | 5391d806 | bellard | eject = (packet[4] >> 1) & 1; |
1736 | 3b46e624 | ths | |
1737 | caed8802 | bellard | if (eject && !start) {
|
1738 | caed8802 | bellard | /* eject the disk */
|
1739 | 66c6ef76 | bellard | bdrv_eject(s->bs, 1);
|
1740 | 66c6ef76 | bellard | } else if (eject && start) { |
1741 | 66c6ef76 | bellard | /* close the tray */
|
1742 | 66c6ef76 | bellard | bdrv_eject(s->bs, 0);
|
1743 | caed8802 | bellard | } |
1744 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1745 | 5391d806 | bellard | } |
1746 | 5391d806 | bellard | break;
|
1747 | 5391d806 | bellard | case GPCMD_MECHANISM_STATUS:
|
1748 | 5391d806 | bellard | { |
1749 | 5391d806 | bellard | max_len = ube16_to_cpu(packet + 8);
|
1750 | 5391d806 | bellard | cpu_to_ube16(buf, 0);
|
1751 | 5391d806 | bellard | /* no current LBA */
|
1752 | 5391d806 | bellard | buf[2] = 0; |
1753 | 5391d806 | bellard | buf[3] = 0; |
1754 | 5391d806 | bellard | buf[4] = 0; |
1755 | 5391d806 | bellard | buf[5] = 1; |
1756 | 5391d806 | bellard | cpu_to_ube16(buf + 6, 0); |
1757 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 8, max_len);
|
1758 | 5391d806 | bellard | } |
1759 | 5391d806 | bellard | break;
|
1760 | 5391d806 | bellard | case GPCMD_READ_TOC_PMA_ATIP:
|
1761 | 5391d806 | bellard | { |
1762 | 5391d806 | bellard | int format, msf, start_track, len;
|
1763 | 96b8f136 | ths | uint64_t total_sectors; |
1764 | 5391d806 | bellard | |
1765 | 66c6ef76 | bellard | bdrv_get_geometry(s->bs, &total_sectors); |
1766 | 66c6ef76 | bellard | total_sectors >>= 2;
|
1767 | 96b8f136 | ths | if (total_sectors == 0) { |
1768 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1769 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1770 | 5391d806 | bellard | break;
|
1771 | 5391d806 | bellard | } |
1772 | 5391d806 | bellard | max_len = ube16_to_cpu(packet + 7);
|
1773 | 5391d806 | bellard | format = packet[9] >> 6; |
1774 | 5391d806 | bellard | msf = (packet[1] >> 1) & 1; |
1775 | 5391d806 | bellard | start_track = packet[6];
|
1776 | 5391d806 | bellard | switch(format) {
|
1777 | 5391d806 | bellard | case 0: |
1778 | 66c6ef76 | bellard | len = cdrom_read_toc(total_sectors, buf, msf, start_track); |
1779 | 5391d806 | bellard | if (len < 0) |
1780 | 5391d806 | bellard | goto error_cmd;
|
1781 | 5391d806 | bellard | ide_atapi_cmd_reply(s, len, max_len); |
1782 | 5391d806 | bellard | break;
|
1783 | 5391d806 | bellard | case 1: |
1784 | 5391d806 | bellard | /* multi session : only a single session defined */
|
1785 | 5391d806 | bellard | memset(buf, 0, 12); |
1786 | 5391d806 | bellard | buf[1] = 0x0a; |
1787 | 5391d806 | bellard | buf[2] = 0x01; |
1788 | 5391d806 | bellard | buf[3] = 0x01; |
1789 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 12, max_len);
|
1790 | 5391d806 | bellard | break;
|
1791 | 98087450 | bellard | case 2: |
1792 | 66c6ef76 | bellard | len = cdrom_read_toc_raw(total_sectors, buf, msf, start_track); |
1793 | 98087450 | bellard | if (len < 0) |
1794 | 98087450 | bellard | goto error_cmd;
|
1795 | 98087450 | bellard | ide_atapi_cmd_reply(s, len, max_len); |
1796 | 98087450 | bellard | break;
|
1797 | 5391d806 | bellard | default:
|
1798 | 7f777bf3 | bellard | error_cmd:
|
1799 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1800 | 7f777bf3 | bellard | ASC_INV_FIELD_IN_CMD_PACKET); |
1801 | 7f777bf3 | bellard | break;
|
1802 | 5391d806 | bellard | } |
1803 | 5391d806 | bellard | } |
1804 | 5391d806 | bellard | break;
|
1805 | 5391d806 | bellard | case GPCMD_READ_CDVD_CAPACITY:
|
1806 | 66c6ef76 | bellard | { |
1807 | 96b8f136 | ths | uint64_t total_sectors; |
1808 | 66c6ef76 | bellard | |
1809 | 66c6ef76 | bellard | bdrv_get_geometry(s->bs, &total_sectors); |
1810 | 66c6ef76 | bellard | total_sectors >>= 2;
|
1811 | 96b8f136 | ths | if (total_sectors == 0) { |
1812 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1813 | 66c6ef76 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1814 | 66c6ef76 | bellard | break;
|
1815 | 66c6ef76 | bellard | } |
1816 | 66c6ef76 | bellard | /* NOTE: it is really the number of sectors minus 1 */
|
1817 | 66c6ef76 | bellard | cpu_to_ube32(buf, total_sectors - 1);
|
1818 | 66c6ef76 | bellard | cpu_to_ube32(buf + 4, 2048); |
1819 | 66c6ef76 | bellard | ide_atapi_cmd_reply(s, 8, 8); |
1820 | 5391d806 | bellard | } |
1821 | 5391d806 | bellard | break;
|
1822 | d14049ea | ths | case GPCMD_READ_DVD_STRUCTURE:
|
1823 | d14049ea | ths | { |
1824 | d14049ea | ths | int media = packet[1]; |
1825 | 8114e9e8 | ths | int format = packet[7]; |
1826 | 8114e9e8 | ths | int ret;
|
1827 | d14049ea | ths | |
1828 | 8114e9e8 | ths | max_len = ube16_to_cpu(packet + 8);
|
1829 | d14049ea | ths | |
1830 | 8114e9e8 | ths | if (format < 0xff) { |
1831 | 8114e9e8 | ths | if (media_is_cd(s)) {
|
1832 | 8114e9e8 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1833 | 8114e9e8 | ths | ASC_INCOMPATIBLE_FORMAT); |
1834 | 8114e9e8 | ths | break;
|
1835 | 8114e9e8 | ths | } else if (!media_present(s)) { |
1836 | 8114e9e8 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1837 | 8114e9e8 | ths | ASC_INV_FIELD_IN_CMD_PACKET); |
1838 | 8114e9e8 | ths | break;
|
1839 | 8114e9e8 | ths | } |
1840 | 8114e9e8 | ths | } |
1841 | d14049ea | ths | |
1842 | 8114e9e8 | ths | memset(buf, 0, max_len > IDE_DMA_BUF_SECTORS * 512 + 4 ? |
1843 | 8114e9e8 | ths | IDE_DMA_BUF_SECTORS * 512 + 4 : max_len); |
1844 | d14049ea | ths | |
1845 | 8114e9e8 | ths | switch (format) {
|
1846 | 8114e9e8 | ths | case 0x00 ... 0x7f: |
1847 | 8114e9e8 | ths | case 0xff: |
1848 | 8114e9e8 | ths | if (media == 0) { |
1849 | 8114e9e8 | ths | ret = ide_dvd_read_structure(s, format, packet, buf); |
1850 | d14049ea | ths | |
1851 | 8114e9e8 | ths | if (ret < 0) |
1852 | 8114e9e8 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, -ret); |
1853 | 8114e9e8 | ths | else
|
1854 | 8114e9e8 | ths | ide_atapi_cmd_reply(s, ret, max_len); |
1855 | d14049ea | ths | |
1856 | 8114e9e8 | ths | break;
|
1857 | 8114e9e8 | ths | } |
1858 | 8114e9e8 | ths | /* TODO: BD support, fall through for now */
|
1859 | 8114e9e8 | ths | |
1860 | 8114e9e8 | ths | /* Generic disk structures */
|
1861 | 8114e9e8 | ths | case 0x80: /* TODO: AACS volume identifier */ |
1862 | 8114e9e8 | ths | case 0x81: /* TODO: AACS media serial number */ |
1863 | 8114e9e8 | ths | case 0x82: /* TODO: AACS media identifier */ |
1864 | 8114e9e8 | ths | case 0x83: /* TODO: AACS media key block */ |
1865 | 8114e9e8 | ths | case 0x90: /* TODO: List of recognized format layers */ |
1866 | 8114e9e8 | ths | case 0xc0: /* TODO: Write protection status */ |
1867 | d14049ea | ths | default:
|
1868 | d14049ea | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1869 | d14049ea | ths | ASC_INV_FIELD_IN_CMD_PACKET); |
1870 | d14049ea | ths | break;
|
1871 | d14049ea | ths | } |
1872 | d14049ea | ths | } |
1873 | d14049ea | ths | break;
|
1874 | d14049ea | ths | case GPCMD_SET_SPEED:
|
1875 | d14049ea | ths | ide_atapi_cmd_ok(s); |
1876 | d14049ea | ths | break;
|
1877 | bd0d90b2 | bellard | case GPCMD_INQUIRY:
|
1878 | bd0d90b2 | bellard | max_len = packet[4];
|
1879 | bd0d90b2 | bellard | buf[0] = 0x05; /* CD-ROM */ |
1880 | bd0d90b2 | bellard | buf[1] = 0x80; /* removable */ |
1881 | bd0d90b2 | bellard | buf[2] = 0x00; /* ISO */ |
1882 | bd0d90b2 | bellard | buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */ |
1883 | aa1f17c1 | ths | buf[4] = 31; /* additional length */ |
1884 | bd0d90b2 | bellard | buf[5] = 0; /* reserved */ |
1885 | bd0d90b2 | bellard | buf[6] = 0; /* reserved */ |
1886 | bd0d90b2 | bellard | buf[7] = 0; /* reserved */ |
1887 | bd0d90b2 | bellard | padstr8(buf + 8, 8, "QEMU"); |
1888 | 38cdea7c | balrog | padstr8(buf + 16, 16, "QEMU DVD-ROM"); |
1889 | bd0d90b2 | bellard | padstr8(buf + 32, 4, QEMU_VERSION); |
1890 | bd0d90b2 | bellard | ide_atapi_cmd_reply(s, 36, max_len);
|
1891 | bd0d90b2 | bellard | break;
|
1892 | d14049ea | ths | case GPCMD_GET_CONFIGURATION:
|
1893 | d14049ea | ths | { |
1894 | 38cdea7c | balrog | uint32_t len; |
1895 | 091d055b | balrog | uint8_t index = 0;
|
1896 | d14049ea | ths | |
1897 | d14049ea | ths | /* only feature 0 is supported */
|
1898 | d14049ea | ths | if (packet[2] != 0 || packet[3] != 0) { |
1899 | d14049ea | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1900 | d14049ea | ths | ASC_INV_FIELD_IN_CMD_PACKET); |
1901 | d14049ea | ths | break;
|
1902 | d14049ea | ths | } |
1903 | 38cdea7c | balrog | |
1904 | 38cdea7c | balrog | /* XXX: could result in alignment problems in some architectures */
|
1905 | 38cdea7c | balrog | max_len = ube16_to_cpu(packet + 7);
|
1906 | 091d055b | balrog | |
1907 | 38cdea7c | balrog | /*
|
1908 | 091d055b | balrog | * XXX: avoid overflow for io_buffer if max_len is bigger than
|
1909 | 091d055b | balrog | * the size of that buffer (dimensioned to max number of
|
1910 | 091d055b | balrog | * sectors to transfer at once)
|
1911 | 38cdea7c | balrog | *
|
1912 | 091d055b | balrog | * Only a problem if the feature/profiles grow.
|
1913 | 38cdea7c | balrog | */
|
1914 | 38cdea7c | balrog | if (max_len > 512) /* XXX: assume 1 sector */ |
1915 | 38cdea7c | balrog | max_len = 512;
|
1916 | 38cdea7c | balrog | |
1917 | 38cdea7c | balrog | memset(buf, 0, max_len);
|
1918 | 38cdea7c | balrog | /*
|
1919 | 38cdea7c | balrog | * the number of sectors from the media tells us which profile
|
1920 | 38cdea7c | balrog | * to use as current. 0 means there is no media
|
1921 | 38cdea7c | balrog | */
|
1922 | 8114e9e8 | ths | if (media_is_dvd(s))
|
1923 | 8114e9e8 | ths | cpu_to_ube16(buf + 6, MMC_PROFILE_DVD_ROM);
|
1924 | 8114e9e8 | ths | else if (media_is_cd(s)) |
1925 | 8114e9e8 | ths | cpu_to_ube16(buf + 6, MMC_PROFILE_CD_ROM);
|
1926 | 38cdea7c | balrog | |
1927 | 091d055b | balrog | buf[10] = 0x02 | 0x01; /* persistent and current */ |
1928 | 091d055b | balrog | len = 12; /* headers: 8 + 4 */ |
1929 | 091d055b | balrog | len += ide_atapi_set_profile(buf, &index, MMC_PROFILE_DVD_ROM); |
1930 | 091d055b | balrog | len += ide_atapi_set_profile(buf, &index, MMC_PROFILE_CD_ROM); |
1931 | 38cdea7c | balrog | cpu_to_ube32(buf, len - 4); /* data length */ |
1932 | 38cdea7c | balrog | |
1933 | 38cdea7c | balrog | ide_atapi_cmd_reply(s, len, max_len); |
1934 | d14049ea | ths | break;
|
1935 | d14049ea | ths | } |
1936 | 5391d806 | bellard | default:
|
1937 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1938 | 7f777bf3 | bellard | ASC_ILLEGAL_OPCODE); |
1939 | 5391d806 | bellard | break;
|
1940 | 5391d806 | bellard | } |
1941 | 5391d806 | bellard | } |
1942 | 5391d806 | bellard | |
1943 | 201a51fc | balrog | static void ide_cfata_metadata_inquiry(IDEState *s) |
1944 | 201a51fc | balrog | { |
1945 | 201a51fc | balrog | uint16_t *p; |
1946 | 201a51fc | balrog | uint32_t spd; |
1947 | 201a51fc | balrog | |
1948 | 201a51fc | balrog | p = (uint16_t *) s->io_buffer; |
1949 | 201a51fc | balrog | memset(p, 0, 0x200); |
1950 | 201a51fc | balrog | spd = ((s->mdata_size - 1) >> 9) + 1; |
1951 | 201a51fc | balrog | |
1952 | 201a51fc | balrog | put_le16(p + 0, 0x0001); /* Data format revision */ |
1953 | 201a51fc | balrog | put_le16(p + 1, 0x0000); /* Media property: silicon */ |
1954 | 201a51fc | balrog | put_le16(p + 2, s->media_changed); /* Media status */ |
1955 | 201a51fc | balrog | put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ |
1956 | 201a51fc | balrog | put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ |
1957 | 201a51fc | balrog | put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ |
1958 | 201a51fc | balrog | put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ |
1959 | 201a51fc | balrog | } |
1960 | 201a51fc | balrog | |
1961 | 201a51fc | balrog | static void ide_cfata_metadata_read(IDEState *s) |
1962 | 201a51fc | balrog | { |
1963 | 201a51fc | balrog | uint16_t *p; |
1964 | 201a51fc | balrog | |
1965 | 201a51fc | balrog | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { |
1966 | 201a51fc | balrog | s->status = ERR_STAT; |
1967 | 201a51fc | balrog | s->error = ABRT_ERR; |
1968 | 201a51fc | balrog | return;
|
1969 | 201a51fc | balrog | } |
1970 | 201a51fc | balrog | |
1971 | 201a51fc | balrog | p = (uint16_t *) s->io_buffer; |
1972 | 201a51fc | balrog | memset(p, 0, 0x200); |
1973 | 201a51fc | balrog | |
1974 | 201a51fc | balrog | put_le16(p + 0, s->media_changed); /* Media status */ |
1975 | 201a51fc | balrog | memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), |
1976 | 201a51fc | balrog | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), |
1977 | 201a51fc | balrog | s->nsector << 9), 0x200 - 2)); |
1978 | 201a51fc | balrog | } |
1979 | 201a51fc | balrog | |
1980 | 201a51fc | balrog | static void ide_cfata_metadata_write(IDEState *s) |
1981 | 201a51fc | balrog | { |
1982 | 201a51fc | balrog | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { |
1983 | 201a51fc | balrog | s->status = ERR_STAT; |
1984 | 201a51fc | balrog | s->error = ABRT_ERR; |
1985 | 201a51fc | balrog | return;
|
1986 | 201a51fc | balrog | } |
1987 | 201a51fc | balrog | |
1988 | 201a51fc | balrog | s->media_changed = 0;
|
1989 | 201a51fc | balrog | |
1990 | 201a51fc | balrog | memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), |
1991 | 201a51fc | balrog | s->io_buffer + 2,
|
1992 | 201a51fc | balrog | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), |
1993 | 201a51fc | balrog | s->nsector << 9), 0x200 - 2)); |
1994 | 201a51fc | balrog | } |
1995 | 201a51fc | balrog | |
1996 | bd491d6a | ths | /* called when the inserted state of the media has changed */
|
1997 | bd491d6a | ths | static void cdrom_change_cb(void *opaque) |
1998 | bd491d6a | ths | { |
1999 | bd491d6a | ths | IDEState *s = opaque; |
2000 | 96b8f136 | ths | uint64_t nb_sectors; |
2001 | bd491d6a | ths | |
2002 | bd491d6a | ths | bdrv_get_geometry(s->bs, &nb_sectors); |
2003 | bd491d6a | ths | s->nb_sectors = nb_sectors; |
2004 | 9118e7f0 | aliguori | |
2005 | 9118e7f0 | aliguori | s->sense_key = SENSE_UNIT_ATTENTION; |
2006 | 9118e7f0 | aliguori | s->asc = ASC_MEDIUM_MAY_HAVE_CHANGED; |
2007 | 9118e7f0 | aliguori | |
2008 | 9118e7f0 | aliguori | ide_set_irq(s); |
2009 | bd491d6a | ths | } |
2010 | bd491d6a | ths | |
2011 | c2ff060f | bellard | static void ide_cmd_lba48_transform(IDEState *s, int lba48) |
2012 | c2ff060f | bellard | { |
2013 | c2ff060f | bellard | s->lba48 = lba48; |
2014 | c2ff060f | bellard | |
2015 | c2ff060f | bellard | /* handle the 'magic' 0 nsector count conversion here. to avoid
|
2016 | c2ff060f | bellard | * fiddling with the rest of the read logic, we just store the
|
2017 | c2ff060f | bellard | * full sector count in ->nsector and ignore ->hob_nsector from now
|
2018 | c2ff060f | bellard | */
|
2019 | c2ff060f | bellard | if (!s->lba48) {
|
2020 | c2ff060f | bellard | if (!s->nsector)
|
2021 | c2ff060f | bellard | s->nsector = 256;
|
2022 | c2ff060f | bellard | } else {
|
2023 | c2ff060f | bellard | if (!s->nsector && !s->hob_nsector)
|
2024 | c2ff060f | bellard | s->nsector = 65536;
|
2025 | c2ff060f | bellard | else {
|
2026 | c2ff060f | bellard | int lo = s->nsector;
|
2027 | c2ff060f | bellard | int hi = s->hob_nsector;
|
2028 | c2ff060f | bellard | |
2029 | c2ff060f | bellard | s->nsector = (hi << 8) | lo;
|
2030 | c2ff060f | bellard | } |
2031 | c2ff060f | bellard | } |
2032 | c2ff060f | bellard | } |
2033 | c2ff060f | bellard | |
2034 | c2ff060f | bellard | static void ide_clear_hob(IDEState *ide_if) |
2035 | c2ff060f | bellard | { |
2036 | c2ff060f | bellard | /* any write clears HOB high bit of device control register */
|
2037 | c2ff060f | bellard | ide_if[0].select &= ~(1 << 7); |
2038 | c2ff060f | bellard | ide_if[1].select &= ~(1 << 7); |
2039 | c2ff060f | bellard | } |
2040 | c2ff060f | bellard | |
2041 | caed8802 | bellard | static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
2042 | caed8802 | bellard | { |
2043 | caed8802 | bellard | IDEState *ide_if = opaque; |
2044 | c45c3d00 | bellard | IDEState *s; |
2045 | 5391d806 | bellard | int unit, n;
|
2046 | c2ff060f | bellard | int lba48 = 0; |
2047 | 5391d806 | bellard | |
2048 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2049 | 5391d806 | bellard | printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
2050 | 5391d806 | bellard | #endif
|
2051 | c2ff060f | bellard | |
2052 | 5391d806 | bellard | addr &= 7;
|
2053 | fcdd25ab | aliguori | |
2054 | fcdd25ab | aliguori | /* ignore writes to command block while busy with previous command */
|
2055 | fcdd25ab | aliguori | if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT))) |
2056 | fcdd25ab | aliguori | return;
|
2057 | fcdd25ab | aliguori | |
2058 | 5391d806 | bellard | switch(addr) {
|
2059 | 5391d806 | bellard | case 0: |
2060 | 5391d806 | bellard | break;
|
2061 | 5391d806 | bellard | case 1: |
2062 | c2ff060f | bellard | ide_clear_hob(ide_if); |
2063 | c45c3d00 | bellard | /* NOTE: data is written to the two drives */
|
2064 | c2ff060f | bellard | ide_if[0].hob_feature = ide_if[0].feature; |
2065 | c2ff060f | bellard | ide_if[1].hob_feature = ide_if[1].feature; |
2066 | c45c3d00 | bellard | ide_if[0].feature = val;
|
2067 | c45c3d00 | bellard | ide_if[1].feature = val;
|
2068 | 5391d806 | bellard | break;
|
2069 | 5391d806 | bellard | case 2: |
2070 | c2ff060f | bellard | ide_clear_hob(ide_if); |
2071 | c2ff060f | bellard | ide_if[0].hob_nsector = ide_if[0].nsector; |
2072 | c2ff060f | bellard | ide_if[1].hob_nsector = ide_if[1].nsector; |
2073 | c45c3d00 | bellard | ide_if[0].nsector = val;
|
2074 | c45c3d00 | bellard | ide_if[1].nsector = val;
|
2075 | 5391d806 | bellard | break;
|
2076 | 5391d806 | bellard | case 3: |
2077 | c2ff060f | bellard | ide_clear_hob(ide_if); |
2078 | c2ff060f | bellard | ide_if[0].hob_sector = ide_if[0].sector; |
2079 | c2ff060f | bellard | ide_if[1].hob_sector = ide_if[1].sector; |
2080 | c45c3d00 | bellard | ide_if[0].sector = val;
|
2081 | c45c3d00 | bellard | ide_if[1].sector = val;
|
2082 | 5391d806 | bellard | break;
|
2083 | 5391d806 | bellard | case 4: |
2084 | c2ff060f | bellard | ide_clear_hob(ide_if); |
2085 | c2ff060f | bellard | ide_if[0].hob_lcyl = ide_if[0].lcyl; |
2086 | c2ff060f | bellard | ide_if[1].hob_lcyl = ide_if[1].lcyl; |
2087 | c45c3d00 | bellard | ide_if[0].lcyl = val;
|
2088 | c45c3d00 | bellard | ide_if[1].lcyl = val;
|
2089 | 5391d806 | bellard | break;
|
2090 | 5391d806 | bellard | case 5: |
2091 | c2ff060f | bellard | ide_clear_hob(ide_if); |
2092 | c2ff060f | bellard | ide_if[0].hob_hcyl = ide_if[0].hcyl; |
2093 | c2ff060f | bellard | ide_if[1].hob_hcyl = ide_if[1].hcyl; |
2094 | c45c3d00 | bellard | ide_if[0].hcyl = val;
|
2095 | c45c3d00 | bellard | ide_if[1].hcyl = val;
|
2096 | 5391d806 | bellard | break;
|
2097 | 5391d806 | bellard | case 6: |
2098 | c2ff060f | bellard | /* FIXME: HOB readback uses bit 7 */
|
2099 | 7ae98627 | bellard | ide_if[0].select = (val & ~0x10) | 0xa0; |
2100 | 7ae98627 | bellard | ide_if[1].select = (val | 0x10) | 0xa0; |
2101 | 5391d806 | bellard | /* select drive */
|
2102 | 5391d806 | bellard | unit = (val >> 4) & 1; |
2103 | 5391d806 | bellard | s = ide_if + unit; |
2104 | 5391d806 | bellard | ide_if->cur_drive = s; |
2105 | 5391d806 | bellard | break;
|
2106 | 5391d806 | bellard | default:
|
2107 | 5391d806 | bellard | case 7: |
2108 | 5391d806 | bellard | /* command */
|
2109 | 5391d806 | bellard | #if defined(DEBUG_IDE)
|
2110 | 5391d806 | bellard | printf("ide: CMD=%02x\n", val);
|
2111 | 5391d806 | bellard | #endif
|
2112 | c45c3d00 | bellard | s = ide_if->cur_drive; |
2113 | 66201e2d | bellard | /* ignore commands to non existant slave */
|
2114 | 5fafdf24 | ths | if (s != ide_if && !s->bs)
|
2115 | 66201e2d | bellard | break;
|
2116 | c2ff060f | bellard | |
2117 | fcdd25ab | aliguori | /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
|
2118 | fcdd25ab | aliguori | if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
|
2119 | fcdd25ab | aliguori | break;
|
2120 | fcdd25ab | aliguori | |
2121 | 5391d806 | bellard | switch(val) {
|
2122 | 5391d806 | bellard | case WIN_IDENTIFY:
|
2123 | 5391d806 | bellard | if (s->bs && !s->is_cdrom) {
|
2124 | 201a51fc | balrog | if (!s->is_cf)
|
2125 | 201a51fc | balrog | ide_identify(s); |
2126 | 201a51fc | balrog | else
|
2127 | 201a51fc | balrog | ide_cfata_identify(s); |
2128 | 2a282056 | bellard | s->status = READY_STAT | SEEK_STAT; |
2129 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
2130 | 5391d806 | bellard | } else {
|
2131 | 5391d806 | bellard | if (s->is_cdrom) {
|
2132 | 5391d806 | bellard | ide_set_signature(s); |
2133 | 5391d806 | bellard | } |
2134 | 5391d806 | bellard | ide_abort_command(s); |
2135 | 5391d806 | bellard | } |
2136 | 5391d806 | bellard | ide_set_irq(s); |
2137 | 5391d806 | bellard | break;
|
2138 | 5391d806 | bellard | case WIN_SPECIFY:
|
2139 | 5391d806 | bellard | case WIN_RECAL:
|
2140 | a136e5a8 | bellard | s->error = 0;
|
2141 | 769bec72 | bellard | s->status = READY_STAT | SEEK_STAT; |
2142 | 5391d806 | bellard | ide_set_irq(s); |
2143 | 5391d806 | bellard | break;
|
2144 | 5391d806 | bellard | case WIN_SETMULT:
|
2145 | 201a51fc | balrog | if (s->is_cf && s->nsector == 0) { |
2146 | 201a51fc | balrog | /* Disable Read and Write Multiple */
|
2147 | 201a51fc | balrog | s->mult_sectors = 0;
|
2148 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2149 | 201a51fc | balrog | } else if ((s->nsector & 0xff) != 0 && |
2150 | 39dfc926 | ths | ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
|
2151 | 39dfc926 | ths | (s->nsector & (s->nsector - 1)) != 0)) { |
2152 | 5391d806 | bellard | ide_abort_command(s); |
2153 | 5391d806 | bellard | } else {
|
2154 | 292eef5a | ths | s->mult_sectors = s->nsector & 0xff;
|
2155 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2156 | 5391d806 | bellard | } |
2157 | 5391d806 | bellard | ide_set_irq(s); |
2158 | 5391d806 | bellard | break;
|
2159 | c2ff060f | bellard | case WIN_VERIFY_EXT:
|
2160 | c2ff060f | bellard | lba48 = 1;
|
2161 | 4ce900b4 | bellard | case WIN_VERIFY:
|
2162 | 4ce900b4 | bellard | case WIN_VERIFY_ONCE:
|
2163 | 4ce900b4 | bellard | /* do sector number check ? */
|
2164 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2165 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2166 | 4ce900b4 | bellard | ide_set_irq(s); |
2167 | 4ce900b4 | bellard | break;
|
2168 | c2ff060f | bellard | case WIN_READ_EXT:
|
2169 | c2ff060f | bellard | lba48 = 1;
|
2170 | 5391d806 | bellard | case WIN_READ:
|
2171 | 5391d806 | bellard | case WIN_READ_ONCE:
|
2172 | 5fafdf24 | ths | if (!s->bs)
|
2173 | 6b136f9e | bellard | goto abort_cmd;
|
2174 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2175 | 5391d806 | bellard | s->req_nb_sectors = 1;
|
2176 | 5391d806 | bellard | ide_sector_read(s); |
2177 | 5391d806 | bellard | break;
|
2178 | c2ff060f | bellard | case WIN_WRITE_EXT:
|
2179 | c2ff060f | bellard | lba48 = 1;
|
2180 | 5391d806 | bellard | case WIN_WRITE:
|
2181 | 5391d806 | bellard | case WIN_WRITE_ONCE:
|
2182 | 201a51fc | balrog | case CFA_WRITE_SECT_WO_ERASE:
|
2183 | 201a51fc | balrog | case WIN_WRITE_VERIFY:
|
2184 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2185 | a136e5a8 | bellard | s->error = 0;
|
2186 | f66723fa | bellard | s->status = SEEK_STAT | READY_STAT; |
2187 | 5391d806 | bellard | s->req_nb_sectors = 1;
|
2188 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
|
2189 | 201a51fc | balrog | s->media_changed = 1;
|
2190 | 5391d806 | bellard | break;
|
2191 | c2ff060f | bellard | case WIN_MULTREAD_EXT:
|
2192 | c2ff060f | bellard | lba48 = 1;
|
2193 | 5391d806 | bellard | case WIN_MULTREAD:
|
2194 | 5391d806 | bellard | if (!s->mult_sectors)
|
2195 | 5391d806 | bellard | goto abort_cmd;
|
2196 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2197 | 5391d806 | bellard | s->req_nb_sectors = s->mult_sectors; |
2198 | 5391d806 | bellard | ide_sector_read(s); |
2199 | 5391d806 | bellard | break;
|
2200 | c2ff060f | bellard | case WIN_MULTWRITE_EXT:
|
2201 | c2ff060f | bellard | lba48 = 1;
|
2202 | 5391d806 | bellard | case WIN_MULTWRITE:
|
2203 | 201a51fc | balrog | case CFA_WRITE_MULTI_WO_ERASE:
|
2204 | 5391d806 | bellard | if (!s->mult_sectors)
|
2205 | 5391d806 | bellard | goto abort_cmd;
|
2206 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2207 | a136e5a8 | bellard | s->error = 0;
|
2208 | f66723fa | bellard | s->status = SEEK_STAT | READY_STAT; |
2209 | 5391d806 | bellard | s->req_nb_sectors = s->mult_sectors; |
2210 | 5391d806 | bellard | n = s->nsector; |
2211 | 5391d806 | bellard | if (n > s->req_nb_sectors)
|
2212 | 5391d806 | bellard | n = s->req_nb_sectors; |
2213 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
|
2214 | 201a51fc | balrog | s->media_changed = 1;
|
2215 | 5391d806 | bellard | break;
|
2216 | c2ff060f | bellard | case WIN_READDMA_EXT:
|
2217 | c2ff060f | bellard | lba48 = 1;
|
2218 | 98087450 | bellard | case WIN_READDMA:
|
2219 | 98087450 | bellard | case WIN_READDMA_ONCE:
|
2220 | 5fafdf24 | ths | if (!s->bs)
|
2221 | 98087450 | bellard | goto abort_cmd;
|
2222 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2223 | 98087450 | bellard | ide_sector_read_dma(s); |
2224 | 98087450 | bellard | break;
|
2225 | c2ff060f | bellard | case WIN_WRITEDMA_EXT:
|
2226 | c2ff060f | bellard | lba48 = 1;
|
2227 | 98087450 | bellard | case WIN_WRITEDMA:
|
2228 | 98087450 | bellard | case WIN_WRITEDMA_ONCE:
|
2229 | 5fafdf24 | ths | if (!s->bs)
|
2230 | 98087450 | bellard | goto abort_cmd;
|
2231 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2232 | 98087450 | bellard | ide_sector_write_dma(s); |
2233 | 201a51fc | balrog | s->media_changed = 1;
|
2234 | 98087450 | bellard | break;
|
2235 | c2ff060f | bellard | case WIN_READ_NATIVE_MAX_EXT:
|
2236 | c2ff060f | bellard | lba48 = 1;
|
2237 | 5391d806 | bellard | case WIN_READ_NATIVE_MAX:
|
2238 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2239 | 5391d806 | bellard | ide_set_sector(s, s->nb_sectors - 1);
|
2240 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2241 | 5391d806 | bellard | ide_set_irq(s); |
2242 | 5391d806 | bellard | break;
|
2243 | a136e5a8 | bellard | case WIN_CHECKPOWERMODE1:
|
2244 | 201a51fc | balrog | case WIN_CHECKPOWERMODE2:
|
2245 | a136e5a8 | bellard | s->nsector = 0xff; /* device active or idle */ |
2246 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2247 | a136e5a8 | bellard | ide_set_irq(s); |
2248 | a136e5a8 | bellard | break;
|
2249 | 34e538ae | bellard | case WIN_SETFEATURES:
|
2250 | 34e538ae | bellard | if (!s->bs)
|
2251 | 34e538ae | bellard | goto abort_cmd;
|
2252 | 34e538ae | bellard | /* XXX: valid for CDROM ? */
|
2253 | 34e538ae | bellard | switch(s->feature) {
|
2254 | e1f63470 | ths | case 0xcc: /* reverting to power-on defaults enable */ |
2255 | e1f63470 | ths | case 0x66: /* reverting to power-on defaults disable */ |
2256 | 34e538ae | bellard | case 0x02: /* write cache enable */ |
2257 | 34e538ae | bellard | case 0x82: /* write cache disable */ |
2258 | 34e538ae | bellard | case 0xaa: /* read look-ahead enable */ |
2259 | 34e538ae | bellard | case 0x55: /* read look-ahead disable */ |
2260 | 201a51fc | balrog | case 0x05: /* set advanced power management mode */ |
2261 | 201a51fc | balrog | case 0x85: /* disable advanced power management mode */ |
2262 | 201a51fc | balrog | case 0x69: /* NOP */ |
2263 | 201a51fc | balrog | case 0x67: /* NOP */ |
2264 | 201a51fc | balrog | case 0x96: /* NOP */ |
2265 | 201a51fc | balrog | case 0x9a: /* NOP */ |
2266 | c3e88d8c | ths | case 0x42: /* enable Automatic Acoustic Mode */ |
2267 | c3e88d8c | ths | case 0xc2: /* disable Automatic Acoustic Mode */ |
2268 | e0fe67aa | bellard | s->status = READY_STAT | SEEK_STAT; |
2269 | 34e538ae | bellard | ide_set_irq(s); |
2270 | 34e538ae | bellard | break;
|
2271 | 94458802 | bellard | case 0x03: { /* set transfer mode */ |
2272 | 94458802 | bellard | uint8_t val = s->nsector & 0x07;
|
2273 | 94458802 | bellard | |
2274 | 94458802 | bellard | switch (s->nsector >> 3) { |
2275 | 94458802 | bellard | case 0x00: /* pio default */ |
2276 | 94458802 | bellard | case 0x01: /* pio mode */ |
2277 | d1b5c20d | ths | put_le16(s->identify_data + 62,0x07); |
2278 | d1b5c20d | ths | put_le16(s->identify_data + 63,0x07); |
2279 | d1b5c20d | ths | put_le16(s->identify_data + 88,0x3f); |
2280 | d1b5c20d | ths | break;
|
2281 | d1b5c20d | ths | case 0x02: /* sigle word dma mode*/ |
2282 | d1b5c20d | ths | put_le16(s->identify_data + 62,0x07 | (1 << (val + 8))); |
2283 | 94458802 | bellard | put_le16(s->identify_data + 63,0x07); |
2284 | 94458802 | bellard | put_le16(s->identify_data + 88,0x3f); |
2285 | 94458802 | bellard | break;
|
2286 | 94458802 | bellard | case 0x04: /* mdma mode */ |
2287 | d1b5c20d | ths | put_le16(s->identify_data + 62,0x07); |
2288 | 94458802 | bellard | put_le16(s->identify_data + 63,0x07 | (1 << (val + 8))); |
2289 | 94458802 | bellard | put_le16(s->identify_data + 88,0x3f); |
2290 | 94458802 | bellard | break;
|
2291 | 94458802 | bellard | case 0x08: /* udma mode */ |
2292 | d1b5c20d | ths | put_le16(s->identify_data + 62,0x07); |
2293 | 94458802 | bellard | put_le16(s->identify_data + 63,0x07); |
2294 | 94458802 | bellard | put_le16(s->identify_data + 88,0x3f | (1 << (val + 8))); |
2295 | 94458802 | bellard | break;
|
2296 | 94458802 | bellard | default:
|
2297 | 94458802 | bellard | goto abort_cmd;
|
2298 | 94458802 | bellard | } |
2299 | 94458802 | bellard | s->status = READY_STAT | SEEK_STAT; |
2300 | 94458802 | bellard | ide_set_irq(s); |
2301 | 94458802 | bellard | break;
|
2302 | 94458802 | bellard | } |
2303 | 34e538ae | bellard | default:
|
2304 | 34e538ae | bellard | goto abort_cmd;
|
2305 | 34e538ae | bellard | } |
2306 | 34e538ae | bellard | break;
|
2307 | c2ff060f | bellard | case WIN_FLUSH_CACHE:
|
2308 | c2ff060f | bellard | case WIN_FLUSH_CACHE_EXT:
|
2309 | 7a6cba61 | pbrook | if (s->bs)
|
2310 | 7a6cba61 | pbrook | bdrv_flush(s->bs); |
2311 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2312 | 7a6cba61 | pbrook | ide_set_irq(s); |
2313 | 7a6cba61 | pbrook | break;
|
2314 | c3e88d8c | ths | case WIN_STANDBY:
|
2315 | c3e88d8c | ths | case WIN_STANDBY2:
|
2316 | c3e88d8c | ths | case WIN_STANDBYNOW1:
|
2317 | 201a51fc | balrog | case WIN_STANDBYNOW2:
|
2318 | c451ee71 | bellard | case WIN_IDLEIMMEDIATE:
|
2319 | 201a51fc | balrog | case CFA_IDLEIMMEDIATE:
|
2320 | 201a51fc | balrog | case WIN_SETIDLE1:
|
2321 | 201a51fc | balrog | case WIN_SETIDLE2:
|
2322 | c3e88d8c | ths | case WIN_SLEEPNOW1:
|
2323 | c3e88d8c | ths | case WIN_SLEEPNOW2:
|
2324 | c3e88d8c | ths | s->status = READY_STAT; |
2325 | a7dfe172 | bellard | ide_set_irq(s); |
2326 | a7dfe172 | bellard | break;
|
2327 | 4fbfcd6d | aurel32 | case WIN_SEEK:
|
2328 | 4fbfcd6d | aurel32 | if(s->is_cdrom)
|
2329 | 4fbfcd6d | aurel32 | goto abort_cmd;
|
2330 | 4fbfcd6d | aurel32 | /* XXX: Check that seek is within bounds */
|
2331 | 4fbfcd6d | aurel32 | s->status = READY_STAT | SEEK_STAT; |
2332 | 4fbfcd6d | aurel32 | ide_set_irq(s); |
2333 | 4fbfcd6d | aurel32 | break;
|
2334 | 5391d806 | bellard | /* ATAPI commands */
|
2335 | 5391d806 | bellard | case WIN_PIDENTIFY:
|
2336 | 5391d806 | bellard | if (s->is_cdrom) {
|
2337 | 5391d806 | bellard | ide_atapi_identify(s); |
2338 | 1298fe63 | bellard | s->status = READY_STAT | SEEK_STAT; |
2339 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
2340 | 5391d806 | bellard | } else {
|
2341 | 5391d806 | bellard | ide_abort_command(s); |
2342 | 5391d806 | bellard | } |
2343 | 5391d806 | bellard | ide_set_irq(s); |
2344 | 5391d806 | bellard | break;
|
2345 | c451ee71 | bellard | case WIN_DIAGNOSE:
|
2346 | c451ee71 | bellard | ide_set_signature(s); |
2347 | 33256a25 | aliguori | if (s->is_cdrom)
|
2348 | 33256a25 | aliguori | s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet |
2349 | 33256a25 | aliguori | * devices to return a clear status register
|
2350 | 33256a25 | aliguori | * with READY_STAT *not* set. */
|
2351 | 33256a25 | aliguori | else
|
2352 | 33256a25 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2353 | 33256a25 | aliguori | s->error = 0x01; /* Device 0 passed, Device 1 passed or not |
2354 | 33256a25 | aliguori | * present.
|
2355 | 33256a25 | aliguori | */
|
2356 | f5fdd0a8 | balrog | ide_set_irq(s); |
2357 | c451ee71 | bellard | break;
|
2358 | 5391d806 | bellard | case WIN_SRST:
|
2359 | 5391d806 | bellard | if (!s->is_cdrom)
|
2360 | 5391d806 | bellard | goto abort_cmd;
|
2361 | 5391d806 | bellard | ide_set_signature(s); |
2362 | 6b136f9e | bellard | s->status = 0x00; /* NOTE: READY is _not_ set */ |
2363 | 5391d806 | bellard | s->error = 0x01;
|
2364 | 5391d806 | bellard | break;
|
2365 | 5391d806 | bellard | case WIN_PACKETCMD:
|
2366 | 5391d806 | bellard | if (!s->is_cdrom)
|
2367 | 5391d806 | bellard | goto abort_cmd;
|
2368 | 98087450 | bellard | /* overlapping commands not supported */
|
2369 | 98087450 | bellard | if (s->feature & 0x02) |
2370 | 5391d806 | bellard | goto abort_cmd;
|
2371 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2372 | 98087450 | bellard | s->atapi_dma = s->feature & 1;
|
2373 | 5391d806 | bellard | s->nsector = 1;
|
2374 | 5fafdf24 | ths | ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, |
2375 | 5391d806 | bellard | ide_atapi_cmd); |
2376 | 5391d806 | bellard | break;
|
2377 | 201a51fc | balrog | /* CF-ATA commands */
|
2378 | 201a51fc | balrog | case CFA_REQ_EXT_ERROR_CODE:
|
2379 | 201a51fc | balrog | if (!s->is_cf)
|
2380 | 201a51fc | balrog | goto abort_cmd;
|
2381 | 201a51fc | balrog | s->error = 0x09; /* miscellaneous error */ |
2382 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2383 | 201a51fc | balrog | ide_set_irq(s); |
2384 | 201a51fc | balrog | break;
|
2385 | 201a51fc | balrog | case CFA_ERASE_SECTORS:
|
2386 | 201a51fc | balrog | case CFA_WEAR_LEVEL:
|
2387 | 201a51fc | balrog | if (!s->is_cf)
|
2388 | 201a51fc | balrog | goto abort_cmd;
|
2389 | 201a51fc | balrog | if (val == CFA_WEAR_LEVEL)
|
2390 | 201a51fc | balrog | s->nsector = 0;
|
2391 | 201a51fc | balrog | if (val == CFA_ERASE_SECTORS)
|
2392 | 201a51fc | balrog | s->media_changed = 1;
|
2393 | 201a51fc | balrog | s->error = 0x00;
|
2394 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2395 | 201a51fc | balrog | ide_set_irq(s); |
2396 | 201a51fc | balrog | break;
|
2397 | 201a51fc | balrog | case CFA_TRANSLATE_SECTOR:
|
2398 | 201a51fc | balrog | if (!s->is_cf)
|
2399 | 201a51fc | balrog | goto abort_cmd;
|
2400 | 201a51fc | balrog | s->error = 0x00;
|
2401 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2402 | 201a51fc | balrog | memset(s->io_buffer, 0, 0x200); |
2403 | 201a51fc | balrog | s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ |
2404 | 201a51fc | balrog | s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ |
2405 | 201a51fc | balrog | s->io_buffer[0x02] = s->select; /* Head */ |
2406 | 201a51fc | balrog | s->io_buffer[0x03] = s->sector; /* Sector */ |
2407 | 201a51fc | balrog | s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ |
2408 | 201a51fc | balrog | s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ |
2409 | 201a51fc | balrog | s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ |
2410 | 201a51fc | balrog | s->io_buffer[0x13] = 0x00; /* Erase flag */ |
2411 | 201a51fc | balrog | s->io_buffer[0x18] = 0x00; /* Hot count */ |
2412 | 201a51fc | balrog | s->io_buffer[0x19] = 0x00; /* Hot count */ |
2413 | 201a51fc | balrog | s->io_buffer[0x1a] = 0x01; /* Hot count */ |
2414 | 201a51fc | balrog | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
2415 | 201a51fc | balrog | ide_set_irq(s); |
2416 | 201a51fc | balrog | break;
|
2417 | 201a51fc | balrog | case CFA_ACCESS_METADATA_STORAGE:
|
2418 | 201a51fc | balrog | if (!s->is_cf)
|
2419 | 201a51fc | balrog | goto abort_cmd;
|
2420 | 201a51fc | balrog | switch (s->feature) {
|
2421 | 201a51fc | balrog | case 0x02: /* Inquiry Metadata Storage */ |
2422 | 201a51fc | balrog | ide_cfata_metadata_inquiry(s); |
2423 | 201a51fc | balrog | break;
|
2424 | 201a51fc | balrog | case 0x03: /* Read Metadata Storage */ |
2425 | 201a51fc | balrog | ide_cfata_metadata_read(s); |
2426 | 201a51fc | balrog | break;
|
2427 | 201a51fc | balrog | case 0x04: /* Write Metadata Storage */ |
2428 | 201a51fc | balrog | ide_cfata_metadata_write(s); |
2429 | 201a51fc | balrog | break;
|
2430 | 201a51fc | balrog | default:
|
2431 | 201a51fc | balrog | goto abort_cmd;
|
2432 | 201a51fc | balrog | } |
2433 | 201a51fc | balrog | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
2434 | 201a51fc | balrog | s->status = 0x00; /* NOTE: READY is _not_ set */ |
2435 | 201a51fc | balrog | ide_set_irq(s); |
2436 | 201a51fc | balrog | break;
|
2437 | 201a51fc | balrog | case IBM_SENSE_CONDITION:
|
2438 | 201a51fc | balrog | if (!s->is_cf)
|
2439 | 201a51fc | balrog | goto abort_cmd;
|
2440 | 201a51fc | balrog | switch (s->feature) {
|
2441 | 201a51fc | balrog | case 0x01: /* sense temperature in device */ |
2442 | 201a51fc | balrog | s->nsector = 0x50; /* +20 C */ |
2443 | 201a51fc | balrog | break;
|
2444 | 201a51fc | balrog | default:
|
2445 | 201a51fc | balrog | goto abort_cmd;
|
2446 | 201a51fc | balrog | } |
2447 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2448 | 201a51fc | balrog | ide_set_irq(s); |
2449 | 201a51fc | balrog | break;
|
2450 | 5391d806 | bellard | default:
|
2451 | 5391d806 | bellard | abort_cmd:
|
2452 | 5391d806 | bellard | ide_abort_command(s); |
2453 | 5391d806 | bellard | ide_set_irq(s); |
2454 | 5391d806 | bellard | break;
|
2455 | 5391d806 | bellard | } |
2456 | 5391d806 | bellard | } |
2457 | 5391d806 | bellard | } |
2458 | 5391d806 | bellard | |
2459 | caed8802 | bellard | static uint32_t ide_ioport_read(void *opaque, uint32_t addr1) |
2460 | 5391d806 | bellard | { |
2461 | 7ae98627 | bellard | IDEState *ide_if = opaque; |
2462 | 7ae98627 | bellard | IDEState *s = ide_if->cur_drive; |
2463 | 5391d806 | bellard | uint32_t addr; |
2464 | c2ff060f | bellard | int ret, hob;
|
2465 | 5391d806 | bellard | |
2466 | 5391d806 | bellard | addr = addr1 & 7;
|
2467 | c2ff060f | bellard | /* FIXME: HOB readback uses bit 7, but it's always set right now */
|
2468 | c2ff060f | bellard | //hob = s->select & (1 << 7);
|
2469 | c2ff060f | bellard | hob = 0;
|
2470 | 5391d806 | bellard | switch(addr) {
|
2471 | 5391d806 | bellard | case 0: |
2472 | 5391d806 | bellard | ret = 0xff;
|
2473 | 5391d806 | bellard | break;
|
2474 | 5391d806 | bellard | case 1: |
2475 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2476 | c45c3d00 | bellard | ret = 0;
|
2477 | c2ff060f | bellard | else if (!hob) |
2478 | c45c3d00 | bellard | ret = s->error; |
2479 | c2ff060f | bellard | else
|
2480 | c2ff060f | bellard | ret = s->hob_feature; |
2481 | 5391d806 | bellard | break;
|
2482 | 5391d806 | bellard | case 2: |
2483 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2484 | c45c3d00 | bellard | ret = 0;
|
2485 | c2ff060f | bellard | else if (!hob) |
2486 | c45c3d00 | bellard | ret = s->nsector & 0xff;
|
2487 | c2ff060f | bellard | else
|
2488 | c2ff060f | bellard | ret = s->hob_nsector; |
2489 | 5391d806 | bellard | break;
|
2490 | 5391d806 | bellard | case 3: |
2491 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2492 | c45c3d00 | bellard | ret = 0;
|
2493 | c2ff060f | bellard | else if (!hob) |
2494 | c45c3d00 | bellard | ret = s->sector; |
2495 | c2ff060f | bellard | else
|
2496 | c2ff060f | bellard | ret = s->hob_sector; |
2497 | 5391d806 | bellard | break;
|
2498 | 5391d806 | bellard | case 4: |
2499 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2500 | c45c3d00 | bellard | ret = 0;
|
2501 | c2ff060f | bellard | else if (!hob) |
2502 | c45c3d00 | bellard | ret = s->lcyl; |
2503 | c2ff060f | bellard | else
|
2504 | c2ff060f | bellard | ret = s->hob_lcyl; |
2505 | 5391d806 | bellard | break;
|
2506 | 5391d806 | bellard | case 5: |
2507 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2508 | c45c3d00 | bellard | ret = 0;
|
2509 | c2ff060f | bellard | else if (!hob) |
2510 | c45c3d00 | bellard | ret = s->hcyl; |
2511 | c2ff060f | bellard | else
|
2512 | c2ff060f | bellard | ret = s->hob_hcyl; |
2513 | 5391d806 | bellard | break;
|
2514 | 5391d806 | bellard | case 6: |
2515 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2516 | c45c3d00 | bellard | ret = 0;
|
2517 | c45c3d00 | bellard | else
|
2518 | 7ae98627 | bellard | ret = s->select; |
2519 | 5391d806 | bellard | break;
|
2520 | 5391d806 | bellard | default:
|
2521 | 5391d806 | bellard | case 7: |
2522 | 66201e2d | bellard | if ((!ide_if[0].bs && !ide_if[1].bs) || |
2523 | 66201e2d | bellard | (s != ide_if && !s->bs)) |
2524 | c45c3d00 | bellard | ret = 0;
|
2525 | c45c3d00 | bellard | else
|
2526 | c45c3d00 | bellard | ret = s->status; |
2527 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
2528 | 5391d806 | bellard | break;
|
2529 | 5391d806 | bellard | } |
2530 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2531 | 5391d806 | bellard | printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
|
2532 | 5391d806 | bellard | #endif
|
2533 | 5391d806 | bellard | return ret;
|
2534 | 5391d806 | bellard | } |
2535 | 5391d806 | bellard | |
2536 | caed8802 | bellard | static uint32_t ide_status_read(void *opaque, uint32_t addr) |
2537 | 5391d806 | bellard | { |
2538 | 7ae98627 | bellard | IDEState *ide_if = opaque; |
2539 | 7ae98627 | bellard | IDEState *s = ide_if->cur_drive; |
2540 | 5391d806 | bellard | int ret;
|
2541 | 7ae98627 | bellard | |
2542 | 66201e2d | bellard | if ((!ide_if[0].bs && !ide_if[1].bs) || |
2543 | 66201e2d | bellard | (s != ide_if && !s->bs)) |
2544 | 7ae98627 | bellard | ret = 0;
|
2545 | 7ae98627 | bellard | else
|
2546 | 7ae98627 | bellard | ret = s->status; |
2547 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2548 | 5391d806 | bellard | printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
|
2549 | 5391d806 | bellard | #endif
|
2550 | 5391d806 | bellard | return ret;
|
2551 | 5391d806 | bellard | } |
2552 | 5391d806 | bellard | |
2553 | caed8802 | bellard | static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) |
2554 | 5391d806 | bellard | { |
2555 | caed8802 | bellard | IDEState *ide_if = opaque; |
2556 | 5391d806 | bellard | IDEState *s; |
2557 | 5391d806 | bellard | int i;
|
2558 | 5391d806 | bellard | |
2559 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2560 | 5391d806 | bellard | printf("ide: write control addr=0x%x val=%02x\n", addr, val);
|
2561 | 5391d806 | bellard | #endif
|
2562 | 5391d806 | bellard | /* common for both drives */
|
2563 | 5391d806 | bellard | if (!(ide_if[0].cmd & IDE_CMD_RESET) && |
2564 | 5391d806 | bellard | (val & IDE_CMD_RESET)) { |
2565 | 5391d806 | bellard | /* reset low to high */
|
2566 | 5391d806 | bellard | for(i = 0;i < 2; i++) { |
2567 | 5391d806 | bellard | s = &ide_if[i]; |
2568 | 5391d806 | bellard | s->status = BUSY_STAT | SEEK_STAT; |
2569 | 5391d806 | bellard | s->error = 0x01;
|
2570 | 5391d806 | bellard | } |
2571 | 5391d806 | bellard | } else if ((ide_if[0].cmd & IDE_CMD_RESET) && |
2572 | 5391d806 | bellard | !(val & IDE_CMD_RESET)) { |
2573 | 5391d806 | bellard | /* high to low */
|
2574 | 5391d806 | bellard | for(i = 0;i < 2; i++) { |
2575 | 5391d806 | bellard | s = &ide_if[i]; |
2576 | 6b136f9e | bellard | if (s->is_cdrom)
|
2577 | 6b136f9e | bellard | s->status = 0x00; /* NOTE: READY is _not_ set */ |
2578 | 6b136f9e | bellard | else
|
2579 | 56bf1d37 | bellard | s->status = READY_STAT | SEEK_STAT; |
2580 | 5391d806 | bellard | ide_set_signature(s); |
2581 | 5391d806 | bellard | } |
2582 | 5391d806 | bellard | } |
2583 | 5391d806 | bellard | |
2584 | 5391d806 | bellard | ide_if[0].cmd = val;
|
2585 | 5391d806 | bellard | ide_if[1].cmd = val;
|
2586 | 5391d806 | bellard | } |
2587 | 5391d806 | bellard | |
2588 | caed8802 | bellard | static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) |
2589 | 5391d806 | bellard | { |
2590 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2591 | 5391d806 | bellard | uint8_t *p; |
2592 | 5391d806 | bellard | |
2593 | fcdd25ab | aliguori | /* PIO data access allowed only when DRQ bit is set */
|
2594 | fcdd25ab | aliguori | if (!(s->status & DRQ_STAT))
|
2595 | fcdd25ab | aliguori | return;
|
2596 | fcdd25ab | aliguori | |
2597 | 5391d806 | bellard | p = s->data_ptr; |
2598 | 0c4ad8dc | bellard | *(uint16_t *)p = le16_to_cpu(val); |
2599 | 5391d806 | bellard | p += 2;
|
2600 | 5391d806 | bellard | s->data_ptr = p; |
2601 | 5391d806 | bellard | if (p >= s->data_end)
|
2602 | 5391d806 | bellard | s->end_transfer_func(s); |
2603 | 5391d806 | bellard | } |
2604 | 5391d806 | bellard | |
2605 | caed8802 | bellard | static uint32_t ide_data_readw(void *opaque, uint32_t addr) |
2606 | 5391d806 | bellard | { |
2607 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2608 | 5391d806 | bellard | uint8_t *p; |
2609 | 5391d806 | bellard | int ret;
|
2610 | fcdd25ab | aliguori | |
2611 | fcdd25ab | aliguori | /* PIO data access allowed only when DRQ bit is set */
|
2612 | fcdd25ab | aliguori | if (!(s->status & DRQ_STAT))
|
2613 | fcdd25ab | aliguori | return 0; |
2614 | fcdd25ab | aliguori | |
2615 | 5391d806 | bellard | p = s->data_ptr; |
2616 | 0c4ad8dc | bellard | ret = cpu_to_le16(*(uint16_t *)p); |
2617 | 5391d806 | bellard | p += 2;
|
2618 | 5391d806 | bellard | s->data_ptr = p; |
2619 | 5391d806 | bellard | if (p >= s->data_end)
|
2620 | 5391d806 | bellard | s->end_transfer_func(s); |
2621 | 5391d806 | bellard | return ret;
|
2622 | 5391d806 | bellard | } |
2623 | 5391d806 | bellard | |
2624 | caed8802 | bellard | static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) |
2625 | 5391d806 | bellard | { |
2626 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2627 | 5391d806 | bellard | uint8_t *p; |
2628 | 5391d806 | bellard | |
2629 | fcdd25ab | aliguori | /* PIO data access allowed only when DRQ bit is set */
|
2630 | fcdd25ab | aliguori | if (!(s->status & DRQ_STAT))
|
2631 | fcdd25ab | aliguori | return;
|
2632 | fcdd25ab | aliguori | |
2633 | 5391d806 | bellard | p = s->data_ptr; |
2634 | 0c4ad8dc | bellard | *(uint32_t *)p = le32_to_cpu(val); |
2635 | 5391d806 | bellard | p += 4;
|
2636 | 5391d806 | bellard | s->data_ptr = p; |
2637 | 5391d806 | bellard | if (p >= s->data_end)
|
2638 | 5391d806 | bellard | s->end_transfer_func(s); |
2639 | 5391d806 | bellard | } |
2640 | 5391d806 | bellard | |
2641 | caed8802 | bellard | static uint32_t ide_data_readl(void *opaque, uint32_t addr) |
2642 | 5391d806 | bellard | { |
2643 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2644 | 5391d806 | bellard | uint8_t *p; |
2645 | 5391d806 | bellard | int ret;
|
2646 | 3b46e624 | ths | |
2647 | fcdd25ab | aliguori | /* PIO data access allowed only when DRQ bit is set */
|
2648 | fcdd25ab | aliguori | if (!(s->status & DRQ_STAT))
|
2649 | fcdd25ab | aliguori | return 0; |
2650 | fcdd25ab | aliguori | |
2651 | 5391d806 | bellard | p = s->data_ptr; |
2652 | 0c4ad8dc | bellard | ret = cpu_to_le32(*(uint32_t *)p); |
2653 | 5391d806 | bellard | p += 4;
|
2654 | 5391d806 | bellard | s->data_ptr = p; |
2655 | 5391d806 | bellard | if (p >= s->data_end)
|
2656 | 5391d806 | bellard | s->end_transfer_func(s); |
2657 | 5391d806 | bellard | return ret;
|
2658 | 5391d806 | bellard | } |
2659 | 5391d806 | bellard | |
2660 | a7dfe172 | bellard | static void ide_dummy_transfer_stop(IDEState *s) |
2661 | a7dfe172 | bellard | { |
2662 | a7dfe172 | bellard | s->data_ptr = s->io_buffer; |
2663 | a7dfe172 | bellard | s->data_end = s->io_buffer; |
2664 | a7dfe172 | bellard | s->io_buffer[0] = 0xff; |
2665 | a7dfe172 | bellard | s->io_buffer[1] = 0xff; |
2666 | a7dfe172 | bellard | s->io_buffer[2] = 0xff; |
2667 | a7dfe172 | bellard | s->io_buffer[3] = 0xff; |
2668 | a7dfe172 | bellard | } |
2669 | a7dfe172 | bellard | |
2670 | 5391d806 | bellard | static void ide_reset(IDEState *s) |
2671 | 5391d806 | bellard | { |
2672 | 201a51fc | balrog | if (s->is_cf)
|
2673 | 201a51fc | balrog | s->mult_sectors = 0;
|
2674 | 201a51fc | balrog | else
|
2675 | 201a51fc | balrog | s->mult_sectors = MAX_MULT_SECTORS; |
2676 | 5391d806 | bellard | s->cur_drive = s; |
2677 | 5391d806 | bellard | s->select = 0xa0;
|
2678 | 41a2b959 | aliguori | s->status = READY_STAT | SEEK_STAT; |
2679 | 5391d806 | bellard | ide_set_signature(s); |
2680 | a7dfe172 | bellard | /* init the transfer handler so that 0xffff is returned on data
|
2681 | a7dfe172 | bellard | accesses */
|
2682 | a7dfe172 | bellard | s->end_transfer_func = ide_dummy_transfer_stop; |
2683 | a7dfe172 | bellard | ide_dummy_transfer_stop(s); |
2684 | 201a51fc | balrog | s->media_changed = 0;
|
2685 | 5391d806 | bellard | } |
2686 | 5391d806 | bellard | |
2687 | 5457c8ce | bellard | static void ide_init2(IDEState *ide_state, |
2688 | 5457c8ce | bellard | BlockDriverState *hd0, BlockDriverState *hd1, |
2689 | d537cf6c | pbrook | qemu_irq irq) |
2690 | 5391d806 | bellard | { |
2691 | 69b91039 | bellard | IDEState *s; |
2692 | aedf5382 | bellard | static int drive_serial = 1; |
2693 | f3d54fc4 | aliguori | int i, cylinders, heads, secs;
|
2694 | 96b8f136 | ths | uint64_t nb_sectors; |
2695 | 5391d806 | bellard | |
2696 | caed8802 | bellard | for(i = 0; i < 2; i++) { |
2697 | caed8802 | bellard | s = ide_state + i; |
2698 | 1d8cde5b | aurel32 | s->io_buffer = qemu_memalign(512, IDE_DMA_BUF_SECTORS*512 + 4); |
2699 | caed8802 | bellard | if (i == 0) |
2700 | caed8802 | bellard | s->bs = hd0; |
2701 | caed8802 | bellard | else
|
2702 | caed8802 | bellard | s->bs = hd1; |
2703 | 5391d806 | bellard | if (s->bs) {
|
2704 | 5391d806 | bellard | bdrv_get_geometry(s->bs, &nb_sectors); |
2705 | f3d54fc4 | aliguori | bdrv_guess_geometry(s->bs, &cylinders, &heads, &secs); |
2706 | f3d54fc4 | aliguori | s->cylinders = cylinders; |
2707 | f3d54fc4 | aliguori | s->heads = heads; |
2708 | f3d54fc4 | aliguori | s->sectors = secs; |
2709 | 5391d806 | bellard | s->nb_sectors = nb_sectors; |
2710 | f3d54fc4 | aliguori | |
2711 | caed8802 | bellard | if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
|
2712 | caed8802 | bellard | s->is_cdrom = 1;
|
2713 | bd491d6a | ths | bdrv_set_change_cb(s->bs, cdrom_change_cb, s); |
2714 | 5391d806 | bellard | } |
2715 | 5391d806 | bellard | } |
2716 | aedf5382 | bellard | s->drive_serial = drive_serial++; |
2717 | caed8802 | bellard | s->irq = irq; |
2718 | 5fafdf24 | ths | s->sector_write_timer = qemu_new_timer(vm_clock, |
2719 | a09db21f | bellard | ide_sector_write_timer_cb, s); |
2720 | 5391d806 | bellard | ide_reset(s); |
2721 | 5391d806 | bellard | } |
2722 | 69b91039 | bellard | } |
2723 | 69b91039 | bellard | |
2724 | 34e538ae | bellard | static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2) |
2725 | 69b91039 | bellard | { |
2726 | caed8802 | bellard | register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state); |
2727 | caed8802 | bellard | register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state); |
2728 | caed8802 | bellard | if (iobase2) {
|
2729 | caed8802 | bellard | register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state); |
2730 | caed8802 | bellard | register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state); |
2731 | 5391d806 | bellard | } |
2732 | 3b46e624 | ths | |
2733 | caed8802 | bellard | /* data ports */
|
2734 | caed8802 | bellard | register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state); |
2735 | caed8802 | bellard | register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state); |
2736 | caed8802 | bellard | register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state); |
2737 | caed8802 | bellard | register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state); |
2738 | 5391d806 | bellard | } |
2739 | 69b91039 | bellard | |
2740 | aa941b94 | balrog | /* save per IDE drive data */
|
2741 | aa941b94 | balrog | static void ide_save(QEMUFile* f, IDEState *s) |
2742 | aa941b94 | balrog | { |
2743 | bee8d684 | ths | qemu_put_be32(f, s->mult_sectors); |
2744 | bee8d684 | ths | qemu_put_be32(f, s->identify_set); |
2745 | aa941b94 | balrog | if (s->identify_set) {
|
2746 | aa941b94 | balrog | qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512); |
2747 | aa941b94 | balrog | } |
2748 | aa941b94 | balrog | qemu_put_8s(f, &s->feature); |
2749 | aa941b94 | balrog | qemu_put_8s(f, &s->error); |
2750 | aa941b94 | balrog | qemu_put_be32s(f, &s->nsector); |
2751 | aa941b94 | balrog | qemu_put_8s(f, &s->sector); |
2752 | aa941b94 | balrog | qemu_put_8s(f, &s->lcyl); |
2753 | aa941b94 | balrog | qemu_put_8s(f, &s->hcyl); |
2754 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_feature); |
2755 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_nsector); |
2756 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_sector); |
2757 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_lcyl); |
2758 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_hcyl); |
2759 | aa941b94 | balrog | qemu_put_8s(f, &s->select); |
2760 | aa941b94 | balrog | qemu_put_8s(f, &s->status); |
2761 | aa941b94 | balrog | qemu_put_8s(f, &s->lba48); |
2762 | aa941b94 | balrog | |
2763 | aa941b94 | balrog | qemu_put_8s(f, &s->sense_key); |
2764 | aa941b94 | balrog | qemu_put_8s(f, &s->asc); |
2765 | aa941b94 | balrog | /* XXX: if a transfer is pending, we do not save it yet */
|
2766 | aa941b94 | balrog | } |
2767 | aa941b94 | balrog | |
2768 | aa941b94 | balrog | /* load per IDE drive data */
|
2769 | aa941b94 | balrog | static void ide_load(QEMUFile* f, IDEState *s) |
2770 | aa941b94 | balrog | { |
2771 | bee8d684 | ths | s->mult_sectors=qemu_get_be32(f); |
2772 | bee8d684 | ths | s->identify_set=qemu_get_be32(f); |
2773 | aa941b94 | balrog | if (s->identify_set) {
|
2774 | aa941b94 | balrog | qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
|
2775 | aa941b94 | balrog | } |
2776 | aa941b94 | balrog | qemu_get_8s(f, &s->feature); |
2777 | aa941b94 | balrog | qemu_get_8s(f, &s->error); |
2778 | aa941b94 | balrog | qemu_get_be32s(f, &s->nsector); |
2779 | aa941b94 | balrog | qemu_get_8s(f, &s->sector); |
2780 | aa941b94 | balrog | qemu_get_8s(f, &s->lcyl); |
2781 | aa941b94 | balrog | qemu_get_8s(f, &s->hcyl); |
2782 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_feature); |
2783 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_nsector); |
2784 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_sector); |
2785 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_lcyl); |
2786 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_hcyl); |
2787 | aa941b94 | balrog | qemu_get_8s(f, &s->select); |
2788 | aa941b94 | balrog | qemu_get_8s(f, &s->status); |
2789 | aa941b94 | balrog | qemu_get_8s(f, &s->lba48); |
2790 | aa941b94 | balrog | |
2791 | aa941b94 | balrog | qemu_get_8s(f, &s->sense_key); |
2792 | aa941b94 | balrog | qemu_get_8s(f, &s->asc); |
2793 | aa941b94 | balrog | /* XXX: if a transfer is pending, we do not save it yet */
|
2794 | aa941b94 | balrog | } |
2795 | aa941b94 | balrog | |
2796 | 69b91039 | bellard | /***********************************************************/
|
2797 | 34e538ae | bellard | /* ISA IDE definitions */
|
2798 | 34e538ae | bellard | |
2799 | d537cf6c | pbrook | void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
2800 | 34e538ae | bellard | BlockDriverState *hd0, BlockDriverState *hd1) |
2801 | 34e538ae | bellard | { |
2802 | 34e538ae | bellard | IDEState *ide_state; |
2803 | 34e538ae | bellard | |
2804 | 34e538ae | bellard | ide_state = qemu_mallocz(sizeof(IDEState) * 2); |
2805 | 34e538ae | bellard | if (!ide_state)
|
2806 | 34e538ae | bellard | return;
|
2807 | 3b46e624 | ths | |
2808 | d537cf6c | pbrook | ide_init2(ide_state, hd0, hd1, irq); |
2809 | 34e538ae | bellard | ide_init_ioport(ide_state, iobase, iobase2); |
2810 | 34e538ae | bellard | } |
2811 | 34e538ae | bellard | |
2812 | 34e538ae | bellard | /***********************************************************/
|
2813 | 69b91039 | bellard | /* PCI IDE definitions */
|
2814 | 69b91039 | bellard | |
2815 | 5457c8ce | bellard | static void cmd646_update_irq(PCIIDEState *d); |
2816 | 5457c8ce | bellard | |
2817 | 5fafdf24 | ths | static void ide_map(PCIDevice *pci_dev, int region_num, |
2818 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type)
|
2819 | 69b91039 | bellard | { |
2820 | 69b91039 | bellard | PCIIDEState *d = (PCIIDEState *)pci_dev; |
2821 | 69b91039 | bellard | IDEState *ide_state; |
2822 | 69b91039 | bellard | |
2823 | 69b91039 | bellard | if (region_num <= 3) { |
2824 | 69b91039 | bellard | ide_state = &d->ide_if[(region_num >> 1) * 2]; |
2825 | 69b91039 | bellard | if (region_num & 1) { |
2826 | 69b91039 | bellard | register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state); |
2827 | 69b91039 | bellard | register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state); |
2828 | 69b91039 | bellard | } else {
|
2829 | 69b91039 | bellard | register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state); |
2830 | 69b91039 | bellard | register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state); |
2831 | 69b91039 | bellard | |
2832 | 69b91039 | bellard | /* data ports */
|
2833 | 69b91039 | bellard | register_ioport_write(addr, 2, 2, ide_data_writew, ide_state); |
2834 | 69b91039 | bellard | register_ioport_read(addr, 2, 2, ide_data_readw, ide_state); |
2835 | 69b91039 | bellard | register_ioport_write(addr, 4, 4, ide_data_writel, ide_state); |
2836 | 69b91039 | bellard | register_ioport_read(addr, 4, 4, ide_data_readl, ide_state); |
2837 | 69b91039 | bellard | } |
2838 | 69b91039 | bellard | } |
2839 | 69b91039 | bellard | } |
2840 | 69b91039 | bellard | |
2841 | 8ccad811 | bellard | static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb) |
2842 | 98087450 | bellard | { |
2843 | 98087450 | bellard | BMDMAState *bm = s->bmdma; |
2844 | 98087450 | bellard | if(!bm)
|
2845 | 98087450 | bellard | return;
|
2846 | 98087450 | bellard | bm->ide_if = s; |
2847 | 98087450 | bellard | bm->dma_cb = dma_cb; |
2848 | 8ccad811 | bellard | bm->cur_prd_last = 0;
|
2849 | 8ccad811 | bellard | bm->cur_prd_addr = 0;
|
2850 | 8ccad811 | bellard | bm->cur_prd_len = 0;
|
2851 | 98087450 | bellard | if (bm->status & BM_STATUS_DMAING) {
|
2852 | 8ccad811 | bellard | bm->dma_cb(bm, 0);
|
2853 | 98087450 | bellard | } |
2854 | 98087450 | bellard | } |
2855 | 98087450 | bellard | |
2856 | 72c7b06c | aliguori | static void ide_dma_cancel(BMDMAState *bm) |
2857 | 72c7b06c | aliguori | { |
2858 | 72c7b06c | aliguori | if (bm->status & BM_STATUS_DMAING) {
|
2859 | 72c7b06c | aliguori | bm->status &= ~BM_STATUS_DMAING; |
2860 | 72c7b06c | aliguori | /* cancel DMA request */
|
2861 | 72c7b06c | aliguori | bm->ide_if = NULL;
|
2862 | 72c7b06c | aliguori | bm->dma_cb = NULL;
|
2863 | 72c7b06c | aliguori | if (bm->aiocb) {
|
2864 | 72c7b06c | aliguori | #ifdef DEBUG_AIO
|
2865 | 72c7b06c | aliguori | printf("aio_cancel\n");
|
2866 | 72c7b06c | aliguori | #endif
|
2867 | 72c7b06c | aliguori | bdrv_aio_cancel(bm->aiocb); |
2868 | 72c7b06c | aliguori | bm->aiocb = NULL;
|
2869 | 72c7b06c | aliguori | } |
2870 | 72c7b06c | aliguori | } |
2871 | 72c7b06c | aliguori | } |
2872 | 72c7b06c | aliguori | |
2873 | 98087450 | bellard | static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) |
2874 | 98087450 | bellard | { |
2875 | 98087450 | bellard | BMDMAState *bm = opaque; |
2876 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2877 | 98087450 | bellard | printf("%s: 0x%08x\n", __func__, val);
|
2878 | 98087450 | bellard | #endif
|
2879 | 98087450 | bellard | if (!(val & BM_CMD_START)) {
|
2880 | 98087450 | bellard | /* XXX: do it better */
|
2881 | 72c7b06c | aliguori | ide_dma_cancel(bm); |
2882 | 98087450 | bellard | bm->cmd = val & 0x09;
|
2883 | 98087450 | bellard | } else {
|
2884 | 8ccad811 | bellard | if (!(bm->status & BM_STATUS_DMAING)) {
|
2885 | 8ccad811 | bellard | bm->status |= BM_STATUS_DMAING; |
2886 | 8ccad811 | bellard | /* start dma transfer if possible */
|
2887 | 8ccad811 | bellard | if (bm->dma_cb)
|
2888 | 8ccad811 | bellard | bm->dma_cb(bm, 0);
|
2889 | 8ccad811 | bellard | } |
2890 | 98087450 | bellard | bm->cmd = val & 0x09;
|
2891 | 98087450 | bellard | } |
2892 | 98087450 | bellard | } |
2893 | 98087450 | bellard | |
2894 | 5457c8ce | bellard | static uint32_t bmdma_readb(void *opaque, uint32_t addr) |
2895 | 98087450 | bellard | { |
2896 | 98087450 | bellard | BMDMAState *bm = opaque; |
2897 | 5457c8ce | bellard | PCIIDEState *pci_dev; |
2898 | 98087450 | bellard | uint32_t val; |
2899 | 3b46e624 | ths | |
2900 | 5457c8ce | bellard | switch(addr & 3) { |
2901 | 5fafdf24 | ths | case 0: |
2902 | 5457c8ce | bellard | val = bm->cmd; |
2903 | 5457c8ce | bellard | break;
|
2904 | 5457c8ce | bellard | case 1: |
2905 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2906 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2907 | 5457c8ce | bellard | val = pci_dev->dev.config[MRDMODE]; |
2908 | 5457c8ce | bellard | } else {
|
2909 | 5457c8ce | bellard | val = 0xff;
|
2910 | 5457c8ce | bellard | } |
2911 | 5457c8ce | bellard | break;
|
2912 | 5457c8ce | bellard | case 2: |
2913 | 5457c8ce | bellard | val = bm->status; |
2914 | 5457c8ce | bellard | break;
|
2915 | 5457c8ce | bellard | case 3: |
2916 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2917 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2918 | 5457c8ce | bellard | if (bm == &pci_dev->bmdma[0]) |
2919 | 5457c8ce | bellard | val = pci_dev->dev.config[UDIDETCR0]; |
2920 | 5457c8ce | bellard | else
|
2921 | 5457c8ce | bellard | val = pci_dev->dev.config[UDIDETCR1]; |
2922 | 5457c8ce | bellard | } else {
|
2923 | 5457c8ce | bellard | val = 0xff;
|
2924 | 5457c8ce | bellard | } |
2925 | 5457c8ce | bellard | break;
|
2926 | 5457c8ce | bellard | default:
|
2927 | 5457c8ce | bellard | val = 0xff;
|
2928 | 5457c8ce | bellard | break;
|
2929 | 5457c8ce | bellard | } |
2930 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2931 | 5457c8ce | bellard | printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
|
2932 | 98087450 | bellard | #endif
|
2933 | 98087450 | bellard | return val;
|
2934 | 98087450 | bellard | } |
2935 | 98087450 | bellard | |
2936 | 5457c8ce | bellard | static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) |
2937 | 98087450 | bellard | { |
2938 | 98087450 | bellard | BMDMAState *bm = opaque; |
2939 | 5457c8ce | bellard | PCIIDEState *pci_dev; |
2940 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2941 | 5457c8ce | bellard | printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
|
2942 | 98087450 | bellard | #endif
|
2943 | 5457c8ce | bellard | switch(addr & 3) { |
2944 | 5457c8ce | bellard | case 1: |
2945 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2946 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2947 | 5fafdf24 | ths | pci_dev->dev.config[MRDMODE] = |
2948 | 5457c8ce | bellard | (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); |
2949 | 5457c8ce | bellard | cmd646_update_irq(pci_dev); |
2950 | 5457c8ce | bellard | } |
2951 | 5457c8ce | bellard | break;
|
2952 | 5457c8ce | bellard | case 2: |
2953 | 5457c8ce | bellard | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); |
2954 | 5457c8ce | bellard | break;
|
2955 | 5457c8ce | bellard | case 3: |
2956 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2957 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2958 | 5457c8ce | bellard | if (bm == &pci_dev->bmdma[0]) |
2959 | 5457c8ce | bellard | pci_dev->dev.config[UDIDETCR0] = val; |
2960 | 5457c8ce | bellard | else
|
2961 | 5457c8ce | bellard | pci_dev->dev.config[UDIDETCR1] = val; |
2962 | 5457c8ce | bellard | } |
2963 | 5457c8ce | bellard | break;
|
2964 | 5457c8ce | bellard | } |
2965 | 98087450 | bellard | } |
2966 | 98087450 | bellard | |
2967 | 5b9a1293 | aurel32 | static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) |
2968 | 5b9a1293 | aurel32 | { |
2969 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2970 | 5b9a1293 | aurel32 | uint32_t val; |
2971 | 5b9a1293 | aurel32 | val = (bm->addr >> ((addr & 3) * 8)) & 0xff; |
2972 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2973 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2974 | 5b9a1293 | aurel32 | #endif
|
2975 | 5b9a1293 | aurel32 | return val;
|
2976 | 5b9a1293 | aurel32 | } |
2977 | 5b9a1293 | aurel32 | |
2978 | 5b9a1293 | aurel32 | static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) |
2979 | 5b9a1293 | aurel32 | { |
2980 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2981 | 5b9a1293 | aurel32 | int shift = (addr & 3) * 8; |
2982 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2983 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2984 | 5b9a1293 | aurel32 | #endif
|
2985 | 5b9a1293 | aurel32 | bm->addr &= ~(0xFF << shift);
|
2986 | 5b9a1293 | aurel32 | bm->addr |= ((val & 0xFF) << shift) & ~3; |
2987 | 5b9a1293 | aurel32 | bm->cur_addr = bm->addr; |
2988 | 5b9a1293 | aurel32 | } |
2989 | 5b9a1293 | aurel32 | |
2990 | 5b9a1293 | aurel32 | static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr) |
2991 | 5b9a1293 | aurel32 | { |
2992 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2993 | 5b9a1293 | aurel32 | uint32_t val; |
2994 | 5b9a1293 | aurel32 | val = (bm->addr >> ((addr & 3) * 8)) & 0xffff; |
2995 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2996 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2997 | 5b9a1293 | aurel32 | #endif
|
2998 | 5b9a1293 | aurel32 | return val;
|
2999 | 5b9a1293 | aurel32 | } |
3000 | 5b9a1293 | aurel32 | |
3001 | 5b9a1293 | aurel32 | static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val) |
3002 | 5b9a1293 | aurel32 | { |
3003 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
3004 | 5b9a1293 | aurel32 | int shift = (addr & 3) * 8; |
3005 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
3006 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
3007 | 5b9a1293 | aurel32 | #endif
|
3008 | 5b9a1293 | aurel32 | bm->addr &= ~(0xFFFF << shift);
|
3009 | 5b9a1293 | aurel32 | bm->addr |= ((val & 0xFFFF) << shift) & ~3; |
3010 | 5b9a1293 | aurel32 | bm->cur_addr = bm->addr; |
3011 | 5b9a1293 | aurel32 | } |
3012 | 5b9a1293 | aurel32 | |
3013 | 98087450 | bellard | static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) |
3014 | 98087450 | bellard | { |
3015 | 98087450 | bellard | BMDMAState *bm = opaque; |
3016 | 98087450 | bellard | uint32_t val; |
3017 | 98087450 | bellard | val = bm->addr; |
3018 | 98087450 | bellard | #ifdef DEBUG_IDE
|
3019 | 98087450 | bellard | printf("%s: 0x%08x\n", __func__, val);
|
3020 | 98087450 | bellard | #endif
|
3021 | 98087450 | bellard | return val;
|
3022 | 98087450 | bellard | } |
3023 | 98087450 | bellard | |
3024 | 98087450 | bellard | static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) |
3025 | 98087450 | bellard | { |
3026 | 98087450 | bellard | BMDMAState *bm = opaque; |
3027 | 98087450 | bellard | #ifdef DEBUG_IDE
|
3028 | 98087450 | bellard | printf("%s: 0x%08x\n", __func__, val);
|
3029 | 98087450 | bellard | #endif
|
3030 | 98087450 | bellard | bm->addr = val & ~3;
|
3031 | 30c4bbac | ths | bm->cur_addr = bm->addr; |
3032 | 98087450 | bellard | } |
3033 | 98087450 | bellard | |
3034 | 5fafdf24 | ths | static void bmdma_map(PCIDevice *pci_dev, int region_num, |
3035 | 98087450 | bellard | uint32_t addr, uint32_t size, int type)
|
3036 | 98087450 | bellard | { |
3037 | 98087450 | bellard | PCIIDEState *d = (PCIIDEState *)pci_dev; |
3038 | 98087450 | bellard | int i;
|
3039 | 98087450 | bellard | |
3040 | 98087450 | bellard | for(i = 0;i < 2; i++) { |
3041 | 98087450 | bellard | BMDMAState *bm = &d->bmdma[i]; |
3042 | 98087450 | bellard | d->ide_if[2 * i].bmdma = bm;
|
3043 | 98087450 | bellard | d->ide_if[2 * i + 1].bmdma = bm; |
3044 | 5457c8ce | bellard | bm->pci_dev = (PCIIDEState *)pci_dev; |
3045 | 5457c8ce | bellard | |
3046 | 98087450 | bellard | register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); |
3047 | 98087450 | bellard | |
3048 | 5457c8ce | bellard | register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); |
3049 | 5457c8ce | bellard | register_ioport_read(addr, 4, 1, bmdma_readb, bm); |
3050 | 98087450 | bellard | |
3051 | 5b9a1293 | aurel32 | register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); |
3052 | 5b9a1293 | aurel32 | register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); |
3053 | 5b9a1293 | aurel32 | register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); |
3054 | 5b9a1293 | aurel32 | register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); |
3055 | 98087450 | bellard | register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); |
3056 | 98087450 | bellard | register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); |
3057 | 98087450 | bellard | addr += 8;
|
3058 | 98087450 | bellard | } |
3059 | 98087450 | bellard | } |
3060 | 98087450 | bellard | |
3061 | 9b64997f | blueswir1 | static void pci_ide_save(QEMUFile* f, void *opaque) |
3062 | 9b64997f | blueswir1 | { |
3063 | 9b64997f | blueswir1 | PCIIDEState *d = opaque; |
3064 | 9b64997f | blueswir1 | int i;
|
3065 | 9b64997f | blueswir1 | |
3066 | 9b64997f | blueswir1 | pci_device_save(&d->dev, f); |
3067 | 9b64997f | blueswir1 | |
3068 | 9b64997f | blueswir1 | for(i = 0; i < 2; i++) { |
3069 | 9b64997f | blueswir1 | BMDMAState *bm = &d->bmdma[i]; |
3070 | 9b64997f | blueswir1 | qemu_put_8s(f, &bm->cmd); |
3071 | 9b64997f | blueswir1 | qemu_put_8s(f, &bm->status); |
3072 | 9b64997f | blueswir1 | qemu_put_be32s(f, &bm->addr); |
3073 | 9b64997f | blueswir1 | /* XXX: if a transfer is pending, we do not save it yet */
|
3074 | 9b64997f | blueswir1 | } |
3075 | 9b64997f | blueswir1 | |
3076 | 9b64997f | blueswir1 | /* per IDE interface data */
|
3077 | 9b64997f | blueswir1 | for(i = 0; i < 2; i++) { |
3078 | 9b64997f | blueswir1 | IDEState *s = &d->ide_if[i * 2];
|
3079 | 9b64997f | blueswir1 | uint8_t drive1_selected; |
3080 | 9b64997f | blueswir1 | qemu_put_8s(f, &s->cmd); |
3081 | 9b64997f | blueswir1 | drive1_selected = (s->cur_drive != s); |
3082 | 9b64997f | blueswir1 | qemu_put_8s(f, &drive1_selected); |
3083 | 9b64997f | blueswir1 | } |
3084 | 9b64997f | blueswir1 | |
3085 | 9b64997f | blueswir1 | /* per IDE drive data */
|
3086 | 9b64997f | blueswir1 | for(i = 0; i < 4; i++) { |
3087 | 9b64997f | blueswir1 | ide_save(f, &d->ide_if[i]); |
3088 | 9b64997f | blueswir1 | } |
3089 | 9b64997f | blueswir1 | } |
3090 | 9b64997f | blueswir1 | |
3091 | 9b64997f | blueswir1 | static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) |
3092 | 9b64997f | blueswir1 | { |
3093 | 9b64997f | blueswir1 | PCIIDEState *d = opaque; |
3094 | 9b64997f | blueswir1 | int ret, i;
|
3095 | 9b64997f | blueswir1 | |
3096 | 9b64997f | blueswir1 | if (version_id != 1) |
3097 | 9b64997f | blueswir1 | return -EINVAL;
|
3098 | 9b64997f | blueswir1 | ret = pci_device_load(&d->dev, f); |
3099 | 9b64997f | blueswir1 | if (ret < 0) |
3100 | 9b64997f | blueswir1 | return ret;
|
3101 | 9b64997f | blueswir1 | |
3102 | 9b64997f | blueswir1 | for(i = 0; i < 2; i++) { |
3103 | 9b64997f | blueswir1 | BMDMAState *bm = &d->bmdma[i]; |
3104 | 9b64997f | blueswir1 | qemu_get_8s(f, &bm->cmd); |
3105 | 9b64997f | blueswir1 | qemu_get_8s(f, &bm->status); |
3106 | 9b64997f | blueswir1 | qemu_get_be32s(f, &bm->addr); |
3107 | 9b64997f | blueswir1 | /* XXX: if a transfer is pending, we do not save it yet */
|
3108 | 9b64997f | blueswir1 | } |
3109 | 9b64997f | blueswir1 | |
3110 | 9b64997f | blueswir1 | /* per IDE interface data */
|
3111 | 9b64997f | blueswir1 | for(i = 0; i < 2; i++) { |
3112 | 9b64997f | blueswir1 | IDEState *s = &d->ide_if[i * 2];
|
3113 | 9b64997f | blueswir1 | uint8_t drive1_selected; |
3114 | 9b64997f | blueswir1 | qemu_get_8s(f, &s->cmd); |
3115 | 9b64997f | blueswir1 | qemu_get_8s(f, &drive1_selected); |
3116 | 9b64997f | blueswir1 | s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)]; |
3117 | 9b64997f | blueswir1 | } |
3118 | 9b64997f | blueswir1 | |
3119 | 9b64997f | blueswir1 | /* per IDE drive data */
|
3120 | 9b64997f | blueswir1 | for(i = 0; i < 4; i++) { |
3121 | 9b64997f | blueswir1 | ide_load(f, &d->ide_if[i]); |
3122 | 9b64997f | blueswir1 | } |
3123 | 9b64997f | blueswir1 | return 0; |
3124 | 9b64997f | blueswir1 | } |
3125 | 9b64997f | blueswir1 | |
3126 | 5457c8ce | bellard | /* XXX: call it also when the MRDMODE is changed from the PCI config
|
3127 | 5457c8ce | bellard | registers */
|
3128 | 5457c8ce | bellard | static void cmd646_update_irq(PCIIDEState *d) |
3129 | 5457c8ce | bellard | { |
3130 | 5457c8ce | bellard | int pci_level;
|
3131 | 5457c8ce | bellard | pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && |
3132 | 5457c8ce | bellard | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || |
3133 | 5457c8ce | bellard | ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && |
3134 | 5457c8ce | bellard | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); |
3135 | d537cf6c | pbrook | qemu_set_irq(d->dev.irq[0], pci_level);
|
3136 | 5457c8ce | bellard | } |
3137 | 5457c8ce | bellard | |
3138 | 5457c8ce | bellard | /* the PCI irq level is the logical OR of the two channels */
|
3139 | 5457c8ce | bellard | static void cmd646_set_irq(void *opaque, int channel, int level) |
3140 | 5457c8ce | bellard | { |
3141 | 5457c8ce | bellard | PCIIDEState *d = opaque; |
3142 | 5457c8ce | bellard | int irq_mask;
|
3143 | 5457c8ce | bellard | |
3144 | 5457c8ce | bellard | irq_mask = MRDMODE_INTR_CH0 << channel; |
3145 | 5457c8ce | bellard | if (level)
|
3146 | 5457c8ce | bellard | d->dev.config[MRDMODE] |= irq_mask; |
3147 | 5457c8ce | bellard | else
|
3148 | 5457c8ce | bellard | d->dev.config[MRDMODE] &= ~irq_mask; |
3149 | 5457c8ce | bellard | cmd646_update_irq(d); |
3150 | 5457c8ce | bellard | } |
3151 | 5457c8ce | bellard | |
3152 | 6e6b7363 | blueswir1 | static void cmd646_reset(void *opaque) |
3153 | 6e6b7363 | blueswir1 | { |
3154 | 6e6b7363 | blueswir1 | PCIIDEState *d = opaque; |
3155 | 6e6b7363 | blueswir1 | unsigned int i; |
3156 | 6e6b7363 | blueswir1 | |
3157 | 6e6b7363 | blueswir1 | for (i = 0; i < 2; i++) |
3158 | 6e6b7363 | blueswir1 | ide_dma_cancel(&d->bmdma[i]); |
3159 | 6e6b7363 | blueswir1 | } |
3160 | 6e6b7363 | blueswir1 | |
3161 | 5457c8ce | bellard | /* CMD646 PCI IDE controller */
|
3162 | 5457c8ce | bellard | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
3163 | 5457c8ce | bellard | int secondary_ide_enabled)
|
3164 | 69b91039 | bellard | { |
3165 | 69b91039 | bellard | PCIIDEState *d; |
3166 | 69b91039 | bellard | uint8_t *pci_conf; |
3167 | 34e538ae | bellard | int i;
|
3168 | d537cf6c | pbrook | qemu_irq *irq; |
3169 | 34e538ae | bellard | |
3170 | 5fafdf24 | ths | d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
|
3171 | 5457c8ce | bellard | sizeof(PCIIDEState),
|
3172 | 5fafdf24 | ths | -1,
|
3173 | 73c11f63 | bellard | NULL, NULL); |
3174 | 5457c8ce | bellard | d->type = IDE_TYPE_CMD646; |
3175 | 69b91039 | bellard | pci_conf = d->dev.config; |
3176 | 5457c8ce | bellard | pci_conf[0x00] = 0x95; // CMD646 |
3177 | 5457c8ce | bellard | pci_conf[0x01] = 0x10; |
3178 | 5457c8ce | bellard | pci_conf[0x02] = 0x46; |
3179 | 5457c8ce | bellard | pci_conf[0x03] = 0x06; |
3180 | 5457c8ce | bellard | |
3181 | 5457c8ce | bellard | pci_conf[0x08] = 0x07; // IDE controller revision |
3182 | 5fafdf24 | ths | pci_conf[0x09] = 0x8f; |
3183 | 5457c8ce | bellard | |
3184 | 69b91039 | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
3185 | 69b91039 | bellard | pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
3186 | 5457c8ce | bellard | pci_conf[0x0e] = 0x00; // header_type |
3187 | 3b46e624 | ths | |
3188 | 5457c8ce | bellard | if (secondary_ide_enabled) {
|
3189 | 5457c8ce | bellard | /* XXX: if not enabled, really disable the seconday IDE controller */
|
3190 | 5457c8ce | bellard | pci_conf[0x51] = 0x80; /* enable IDE1 */ |
3191 | 5457c8ce | bellard | } |
3192 | 69b91039 | bellard | |
3193 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 0, 0x8, |
3194 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
3195 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 1, 0x4, |
3196 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
3197 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 2, 0x8, |
3198 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
3199 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 3, 0x4, |
3200 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
3201 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 4, 0x10, |
3202 | 98087450 | bellard | PCI_ADDRESS_SPACE_IO, bmdma_map); |
3203 | 69b91039 | bellard | |
3204 | 34e538ae | bellard | pci_conf[0x3d] = 0x01; // interrupt on pin 1 |
3205 | 3b46e624 | ths | |
3206 | 34e538ae | bellard | for(i = 0; i < 4; i++) |
3207 | 34e538ae | bellard | d->ide_if[i].pci_dev = (PCIDevice *)d; |
3208 | d537cf6c | pbrook | |
3209 | d537cf6c | pbrook | irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
|
3210 | d537cf6c | pbrook | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]); |
3211 | d537cf6c | pbrook | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]); |
3212 | 6e6b7363 | blueswir1 | |
3213 | 9b64997f | blueswir1 | register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); |
3214 | 6e6b7363 | blueswir1 | qemu_register_reset(cmd646_reset, d); |
3215 | 6e6b7363 | blueswir1 | cmd646_reset(d); |
3216 | 34e538ae | bellard | } |
3217 | 34e538ae | bellard | |
3218 | 72c7b06c | aliguori | static void piix3_reset(void *opaque) |
3219 | e6a71ae3 | ths | { |
3220 | 72c7b06c | aliguori | PCIIDEState *d = opaque; |
3221 | e6a71ae3 | ths | uint8_t *pci_conf = d->dev.config; |
3222 | 72c7b06c | aliguori | int i;
|
3223 | 72c7b06c | aliguori | |
3224 | 72c7b06c | aliguori | for (i = 0; i < 2; i++) |
3225 | 72c7b06c | aliguori | ide_dma_cancel(&d->bmdma[i]); |
3226 | e6a71ae3 | ths | |
3227 | e6a71ae3 | ths | pci_conf[0x04] = 0x00; |
3228 | e6a71ae3 | ths | pci_conf[0x05] = 0x00; |
3229 | e6a71ae3 | ths | pci_conf[0x06] = 0x80; /* FBC */ |
3230 | e6a71ae3 | ths | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
3231 | e6a71ae3 | ths | pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ |
3232 | e6a71ae3 | ths | } |
3233 | e6a71ae3 | ths | |
3234 | 34e538ae | bellard | /* hd_table must contain 4 block drivers */
|
3235 | 34e538ae | bellard | /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
3236 | d537cf6c | pbrook | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
3237 | d537cf6c | pbrook | qemu_irq *pic) |
3238 | 34e538ae | bellard | { |
3239 | 34e538ae | bellard | PCIIDEState *d; |
3240 | 34e538ae | bellard | uint8_t *pci_conf; |
3241 | 3b46e624 | ths | |
3242 | 34e538ae | bellard | /* register a function 1 of PIIX3 */
|
3243 | 5fafdf24 | ths | d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
|
3244 | 46e50e9d | bellard | sizeof(PCIIDEState),
|
3245 | 502a5395 | pbrook | devfn, |
3246 | 34e538ae | bellard | NULL, NULL); |
3247 | 5457c8ce | bellard | d->type = IDE_TYPE_PIIX3; |
3248 | 5457c8ce | bellard | |
3249 | 34e538ae | bellard | pci_conf = d->dev.config; |
3250 | 34e538ae | bellard | pci_conf[0x00] = 0x86; // Intel |
3251 | 34e538ae | bellard | pci_conf[0x01] = 0x80; |
3252 | 34e538ae | bellard | pci_conf[0x02] = 0x10; |
3253 | 34e538ae | bellard | pci_conf[0x03] = 0x70; |
3254 | 92510b8c | bellard | pci_conf[0x09] = 0x80; // legacy ATA mode |
3255 | 34e538ae | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
3256 | 34e538ae | bellard | pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
3257 | 34e538ae | bellard | pci_conf[0x0e] = 0x00; // header_type |
3258 | 34e538ae | bellard | |
3259 | 72c7b06c | aliguori | qemu_register_reset(piix3_reset, d); |
3260 | e6a71ae3 | ths | piix3_reset(d); |
3261 | e6a71ae3 | ths | |
3262 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 4, 0x10, |
3263 | 98087450 | bellard | PCI_ADDRESS_SPACE_IO, bmdma_map); |
3264 | 34e538ae | bellard | |
3265 | d537cf6c | pbrook | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]); |
3266 | d537cf6c | pbrook | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]); |
3267 | 34e538ae | bellard | ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); |
3268 | 34e538ae | bellard | ide_init_ioport(&d->ide_if[2], 0x170, 0x376); |
3269 | c3d78997 | bellard | |
3270 | c3d78997 | bellard | register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); |
3271 | 69b91039 | bellard | } |
3272 | 1ade1de2 | bellard | |
3273 | afcc3cdf | ths | /* hd_table must contain 4 block drivers */
|
3274 | afcc3cdf | ths | /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
|
3275 | afcc3cdf | ths | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
3276 | afcc3cdf | ths | qemu_irq *pic) |
3277 | afcc3cdf | ths | { |
3278 | afcc3cdf | ths | PCIIDEState *d; |
3279 | afcc3cdf | ths | uint8_t *pci_conf; |
3280 | afcc3cdf | ths | |
3281 | afcc3cdf | ths | /* register a function 1 of PIIX4 */
|
3282 | afcc3cdf | ths | d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
|
3283 | afcc3cdf | ths | sizeof(PCIIDEState),
|
3284 | afcc3cdf | ths | devfn, |
3285 | afcc3cdf | ths | NULL, NULL); |
3286 | afcc3cdf | ths | d->type = IDE_TYPE_PIIX4; |
3287 | afcc3cdf | ths | |
3288 | afcc3cdf | ths | pci_conf = d->dev.config; |
3289 | afcc3cdf | ths | pci_conf[0x00] = 0x86; // Intel |
3290 | afcc3cdf | ths | pci_conf[0x01] = 0x80; |
3291 | afcc3cdf | ths | pci_conf[0x02] = 0x11; |
3292 | afcc3cdf | ths | pci_conf[0x03] = 0x71; |
3293 | afcc3cdf | ths | pci_conf[0x09] = 0x80; // legacy ATA mode |
3294 | afcc3cdf | ths | pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
3295 | afcc3cdf | ths | pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
3296 | afcc3cdf | ths | pci_conf[0x0e] = 0x00; // header_type |
3297 | afcc3cdf | ths | |
3298 | 72c7b06c | aliguori | qemu_register_reset(piix3_reset, d); |
3299 | afcc3cdf | ths | piix3_reset(d); |
3300 | afcc3cdf | ths | |
3301 | afcc3cdf | ths | pci_register_io_region((PCIDevice *)d, 4, 0x10, |
3302 | afcc3cdf | ths | PCI_ADDRESS_SPACE_IO, bmdma_map); |
3303 | afcc3cdf | ths | |
3304 | afcc3cdf | ths | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]); |
3305 | afcc3cdf | ths | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]); |
3306 | afcc3cdf | ths | ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); |
3307 | afcc3cdf | ths | ide_init_ioport(&d->ide_if[2], 0x170, 0x376); |
3308 | afcc3cdf | ths | |
3309 | afcc3cdf | ths | register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); |
3310 | afcc3cdf | ths | } |
3311 | afcc3cdf | ths | |
3312 | 1ade1de2 | bellard | /***********************************************************/
|
3313 | 1ade1de2 | bellard | /* MacIO based PowerPC IDE */
|
3314 | 1ade1de2 | bellard | |
3315 | 1ade1de2 | bellard | /* PowerMac IDE memory IO */
|
3316 | 1ade1de2 | bellard | static void pmac_ide_writeb (void *opaque, |
3317 | 1ade1de2 | bellard | target_phys_addr_t addr, uint32_t val) |
3318 | 1ade1de2 | bellard | { |
3319 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3320 | 1ade1de2 | bellard | switch (addr) {
|
3321 | 1ade1de2 | bellard | case 1 ... 7: |
3322 | 1ade1de2 | bellard | ide_ioport_write(opaque, addr, val); |
3323 | 1ade1de2 | bellard | break;
|
3324 | 1ade1de2 | bellard | case 8: |
3325 | 1ade1de2 | bellard | case 22: |
3326 | 1ade1de2 | bellard | ide_cmd_write(opaque, 0, val);
|
3327 | 1ade1de2 | bellard | break;
|
3328 | 1ade1de2 | bellard | default:
|
3329 | 1ade1de2 | bellard | break;
|
3330 | 1ade1de2 | bellard | } |
3331 | 1ade1de2 | bellard | } |
3332 | 1ade1de2 | bellard | |
3333 | 1ade1de2 | bellard | static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr) |
3334 | 1ade1de2 | bellard | { |
3335 | 1ade1de2 | bellard | uint8_t retval; |
3336 | 1ade1de2 | bellard | |
3337 | 1ade1de2 | bellard | addr = (addr & 0xFFF) >> 4; |
3338 | 1ade1de2 | bellard | switch (addr) {
|
3339 | 1ade1de2 | bellard | case 1 ... 7: |
3340 | 1ade1de2 | bellard | retval = ide_ioport_read(opaque, addr); |
3341 | 1ade1de2 | bellard | break;
|
3342 | 1ade1de2 | bellard | case 8: |
3343 | 1ade1de2 | bellard | case 22: |
3344 | 1ade1de2 | bellard | retval = ide_status_read(opaque, 0);
|
3345 | 1ade1de2 | bellard | break;
|
3346 | 1ade1de2 | bellard | default:
|
3347 | 1ade1de2 | bellard | retval = 0xFF;
|
3348 | 1ade1de2 | bellard | break;
|
3349 | 1ade1de2 | bellard | } |
3350 | 1ade1de2 | bellard | return retval;
|
3351 | 1ade1de2 | bellard | } |
3352 | 1ade1de2 | bellard | |
3353 | 1ade1de2 | bellard | static void pmac_ide_writew (void *opaque, |
3354 | 1ade1de2 | bellard | target_phys_addr_t addr, uint32_t val) |
3355 | 1ade1de2 | bellard | { |
3356 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3357 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3358 | 1ade1de2 | bellard | val = bswap16(val); |
3359 | 1ade1de2 | bellard | #endif
|
3360 | 1ade1de2 | bellard | if (addr == 0) { |
3361 | 1ade1de2 | bellard | ide_data_writew(opaque, 0, val);
|
3362 | 1ade1de2 | bellard | } |
3363 | 1ade1de2 | bellard | } |
3364 | 1ade1de2 | bellard | |
3365 | 1ade1de2 | bellard | static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr) |
3366 | 1ade1de2 | bellard | { |
3367 | 1ade1de2 | bellard | uint16_t retval; |
3368 | 1ade1de2 | bellard | |
3369 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3370 | 1ade1de2 | bellard | if (addr == 0) { |
3371 | 1ade1de2 | bellard | retval = ide_data_readw(opaque, 0);
|
3372 | 1ade1de2 | bellard | } else {
|
3373 | 1ade1de2 | bellard | retval = 0xFFFF;
|
3374 | 1ade1de2 | bellard | } |
3375 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3376 | 1ade1de2 | bellard | retval = bswap16(retval); |
3377 | 1ade1de2 | bellard | #endif
|
3378 | 1ade1de2 | bellard | return retval;
|
3379 | 1ade1de2 | bellard | } |
3380 | 1ade1de2 | bellard | |
3381 | 1ade1de2 | bellard | static void pmac_ide_writel (void *opaque, |
3382 | 1ade1de2 | bellard | target_phys_addr_t addr, uint32_t val) |
3383 | 1ade1de2 | bellard | { |
3384 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3385 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3386 | 1ade1de2 | bellard | val = bswap32(val); |
3387 | 1ade1de2 | bellard | #endif
|
3388 | 1ade1de2 | bellard | if (addr == 0) { |
3389 | 1ade1de2 | bellard | ide_data_writel(opaque, 0, val);
|
3390 | 1ade1de2 | bellard | } |
3391 | 1ade1de2 | bellard | } |
3392 | 1ade1de2 | bellard | |
3393 | 1ade1de2 | bellard | static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr) |
3394 | 1ade1de2 | bellard | { |
3395 | 1ade1de2 | bellard | uint32_t retval; |
3396 | 1ade1de2 | bellard | |
3397 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3398 | 1ade1de2 | bellard | if (addr == 0) { |
3399 | 1ade1de2 | bellard | retval = ide_data_readl(opaque, 0);
|
3400 | 1ade1de2 | bellard | } else {
|
3401 | 1ade1de2 | bellard | retval = 0xFFFFFFFF;
|
3402 | 1ade1de2 | bellard | } |
3403 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3404 | 1ade1de2 | bellard | retval = bswap32(retval); |
3405 | 1ade1de2 | bellard | #endif
|
3406 | 1ade1de2 | bellard | return retval;
|
3407 | 1ade1de2 | bellard | } |
3408 | 1ade1de2 | bellard | |
3409 | 1ade1de2 | bellard | static CPUWriteMemoryFunc *pmac_ide_write[] = {
|
3410 | 1ade1de2 | bellard | pmac_ide_writeb, |
3411 | 1ade1de2 | bellard | pmac_ide_writew, |
3412 | 1ade1de2 | bellard | pmac_ide_writel, |
3413 | 1ade1de2 | bellard | }; |
3414 | 1ade1de2 | bellard | |
3415 | 1ade1de2 | bellard | static CPUReadMemoryFunc *pmac_ide_read[] = {
|
3416 | 1ade1de2 | bellard | pmac_ide_readb, |
3417 | 1ade1de2 | bellard | pmac_ide_readw, |
3418 | 1ade1de2 | bellard | pmac_ide_readl, |
3419 | 1ade1de2 | bellard | }; |
3420 | 1ade1de2 | bellard | |
3421 | 9b64997f | blueswir1 | static void pmac_ide_save(QEMUFile *f, void *opaque) |
3422 | 9b64997f | blueswir1 | { |
3423 | 9b64997f | blueswir1 | IDEState *s = (IDEState *)opaque; |
3424 | 9b64997f | blueswir1 | uint8_t drive1_selected; |
3425 | 9b64997f | blueswir1 | unsigned int i; |
3426 | 9b64997f | blueswir1 | |
3427 | 9b64997f | blueswir1 | /* per IDE interface data */
|
3428 | 9b64997f | blueswir1 | qemu_put_8s(f, &s->cmd); |
3429 | 9b64997f | blueswir1 | drive1_selected = (s->cur_drive != s); |
3430 | 9b64997f | blueswir1 | qemu_put_8s(f, &drive1_selected); |
3431 | 9b64997f | blueswir1 | |
3432 | 9b64997f | blueswir1 | /* per IDE drive data */
|
3433 | 9b64997f | blueswir1 | for(i = 0; i < 2; i++) { |
3434 | 9b64997f | blueswir1 | ide_save(f, &s[i]); |
3435 | 9b64997f | blueswir1 | } |
3436 | 9b64997f | blueswir1 | } |
3437 | 9b64997f | blueswir1 | |
3438 | 9b64997f | blueswir1 | static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id) |
3439 | 9b64997f | blueswir1 | { |
3440 | 9b64997f | blueswir1 | IDEState *s = (IDEState *)opaque; |
3441 | 9b64997f | blueswir1 | uint8_t drive1_selected; |
3442 | 9b64997f | blueswir1 | unsigned int i; |
3443 | 9b64997f | blueswir1 | |
3444 | 9b64997f | blueswir1 | if (version_id != 1) |
3445 | 9b64997f | blueswir1 | return -EINVAL;
|
3446 | 9b64997f | blueswir1 | |
3447 | 9b64997f | blueswir1 | /* per IDE interface data */
|
3448 | 9b64997f | blueswir1 | qemu_get_8s(f, &s->cmd); |
3449 | 9b64997f | blueswir1 | qemu_get_8s(f, &drive1_selected); |
3450 | 9b64997f | blueswir1 | s->cur_drive = &s[(drive1_selected != 0)];
|
3451 | 9b64997f | blueswir1 | |
3452 | 9b64997f | blueswir1 | /* per IDE drive data */
|
3453 | 9b64997f | blueswir1 | for(i = 0; i < 2; i++) { |
3454 | 9b64997f | blueswir1 | ide_load(f, &s[i]); |
3455 | 9b64997f | blueswir1 | } |
3456 | 9b64997f | blueswir1 | return 0; |
3457 | 9b64997f | blueswir1 | } |
3458 | 9b64997f | blueswir1 | |
3459 | 6e6b7363 | blueswir1 | static void pmac_ide_reset(void *opaque) |
3460 | 6e6b7363 | blueswir1 | { |
3461 | 6e6b7363 | blueswir1 | IDEState *s = (IDEState *)opaque; |
3462 | 6e6b7363 | blueswir1 | |
3463 | 6e6b7363 | blueswir1 | ide_reset(&s[0]);
|
3464 | 6e6b7363 | blueswir1 | ide_reset(&s[1]);
|
3465 | 6e6b7363 | blueswir1 | } |
3466 | 6e6b7363 | blueswir1 | |
3467 | 1ade1de2 | bellard | /* hd_table must contain 4 block drivers */
|
3468 | 1ade1de2 | bellard | /* PowerMac uses memory mapped registers, not I/O. Return the memory
|
3469 | 1ade1de2 | bellard | I/O index to access the ide. */
|
3470 | d537cf6c | pbrook | int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
|
3471 | 1ade1de2 | bellard | { |
3472 | 1ade1de2 | bellard | IDEState *ide_if; |
3473 | 1ade1de2 | bellard | int pmac_ide_memory;
|
3474 | 1ade1de2 | bellard | |
3475 | 1ade1de2 | bellard | ide_if = qemu_mallocz(sizeof(IDEState) * 2); |
3476 | d537cf6c | pbrook | ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq); |
3477 | 3b46e624 | ths | |
3478 | 1ade1de2 | bellard | pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
|
3479 | 1ade1de2 | bellard | pmac_ide_write, &ide_if[0]);
|
3480 | 9b64997f | blueswir1 | register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, &ide_if[0]); |
3481 | 6e6b7363 | blueswir1 | qemu_register_reset(pmac_ide_reset, &ide_if[0]);
|
3482 | 6e6b7363 | blueswir1 | pmac_ide_reset(&ide_if[0]);
|
3483 | 1ade1de2 | bellard | return pmac_ide_memory;
|
3484 | 1ade1de2 | bellard | } |
3485 | 201a51fc | balrog | |
3486 | 201a51fc | balrog | /***********************************************************/
|
3487 | a4a771c0 | balrog | /* MMIO based ide port
|
3488 | a4a771c0 | balrog | * This emulates IDE device connected directly to the CPU bus without
|
3489 | a4a771c0 | balrog | * dedicated ide controller, which is often seen on embedded boards.
|
3490 | a4a771c0 | balrog | */
|
3491 | a4a771c0 | balrog | |
3492 | a4a771c0 | balrog | typedef struct { |
3493 | a4a771c0 | balrog | void *dev;
|
3494 | a4a771c0 | balrog | int shift;
|
3495 | a4a771c0 | balrog | } MMIOState; |
3496 | a4a771c0 | balrog | |
3497 | a4a771c0 | balrog | static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) |
3498 | a4a771c0 | balrog | { |
3499 | a4a771c0 | balrog | MMIOState *s = (MMIOState*)opaque; |
3500 | a4a771c0 | balrog | IDEState *ide = (IDEState*)s->dev; |
3501 | a4a771c0 | balrog | addr >>= s->shift; |
3502 | a4a771c0 | balrog | if (addr & 7) |
3503 | a4a771c0 | balrog | return ide_ioport_read(ide, addr);
|
3504 | a4a771c0 | balrog | else
|
3505 | a4a771c0 | balrog | return ide_data_readw(ide, 0); |
3506 | a4a771c0 | balrog | } |
3507 | a4a771c0 | balrog | |
3508 | a4a771c0 | balrog | static void mmio_ide_write (void *opaque, target_phys_addr_t addr, |
3509 | a4a771c0 | balrog | uint32_t val) |
3510 | a4a771c0 | balrog | { |
3511 | a4a771c0 | balrog | MMIOState *s = (MMIOState*)opaque; |
3512 | a4a771c0 | balrog | IDEState *ide = (IDEState*)s->dev; |
3513 | a4a771c0 | balrog | addr >>= s->shift; |
3514 | a4a771c0 | balrog | if (addr & 7) |
3515 | a4a771c0 | balrog | ide_ioport_write(ide, addr, val); |
3516 | a4a771c0 | balrog | else
|
3517 | a4a771c0 | balrog | ide_data_writew(ide, 0, val);
|
3518 | a4a771c0 | balrog | } |
3519 | a4a771c0 | balrog | |
3520 | a4a771c0 | balrog | static CPUReadMemoryFunc *mmio_ide_reads[] = {
|
3521 | a4a771c0 | balrog | mmio_ide_read, |
3522 | a4a771c0 | balrog | mmio_ide_read, |
3523 | a4a771c0 | balrog | mmio_ide_read, |
3524 | a4a771c0 | balrog | }; |
3525 | a4a771c0 | balrog | |
3526 | a4a771c0 | balrog | static CPUWriteMemoryFunc *mmio_ide_writes[] = {
|
3527 | a4a771c0 | balrog | mmio_ide_write, |
3528 | a4a771c0 | balrog | mmio_ide_write, |
3529 | a4a771c0 | balrog | mmio_ide_write, |
3530 | a4a771c0 | balrog | }; |
3531 | a4a771c0 | balrog | |
3532 | a4a771c0 | balrog | static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) |
3533 | a4a771c0 | balrog | { |
3534 | a4a771c0 | balrog | MMIOState *s= (MMIOState*)opaque; |
3535 | a4a771c0 | balrog | IDEState *ide = (IDEState*)s->dev; |
3536 | a4a771c0 | balrog | return ide_status_read(ide, 0); |
3537 | a4a771c0 | balrog | } |
3538 | a4a771c0 | balrog | |
3539 | a4a771c0 | balrog | static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, |
3540 | a4a771c0 | balrog | uint32_t val) |
3541 | a4a771c0 | balrog | { |
3542 | a4a771c0 | balrog | MMIOState *s = (MMIOState*)opaque; |
3543 | a4a771c0 | balrog | IDEState *ide = (IDEState*)s->dev; |
3544 | a4a771c0 | balrog | ide_cmd_write(ide, 0, val);
|
3545 | a4a771c0 | balrog | } |
3546 | a4a771c0 | balrog | |
3547 | a4a771c0 | balrog | static CPUReadMemoryFunc *mmio_ide_status[] = {
|
3548 | a4a771c0 | balrog | mmio_ide_status_read, |
3549 | a4a771c0 | balrog | mmio_ide_status_read, |
3550 | a4a771c0 | balrog | mmio_ide_status_read, |
3551 | a4a771c0 | balrog | }; |
3552 | a4a771c0 | balrog | |
3553 | a4a771c0 | balrog | static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
|
3554 | a4a771c0 | balrog | mmio_ide_cmd_write, |
3555 | a4a771c0 | balrog | mmio_ide_cmd_write, |
3556 | a4a771c0 | balrog | mmio_ide_cmd_write, |
3557 | a4a771c0 | balrog | }; |
3558 | a4a771c0 | balrog | |
3559 | a4a771c0 | balrog | void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
|
3560 | a4a771c0 | balrog | qemu_irq irq, int shift,
|
3561 | a4a771c0 | balrog | BlockDriverState *hd0, BlockDriverState *hd1) |
3562 | a4a771c0 | balrog | { |
3563 | a4a771c0 | balrog | MMIOState *s = qemu_mallocz(sizeof(MMIOState));
|
3564 | a4a771c0 | balrog | IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2); |
3565 | a4a771c0 | balrog | int mem1, mem2;
|
3566 | a4a771c0 | balrog | |
3567 | a4a771c0 | balrog | ide_init2(ide, hd0, hd1, irq); |
3568 | a4a771c0 | balrog | |
3569 | a4a771c0 | balrog | s->dev = ide; |
3570 | a4a771c0 | balrog | s->shift = shift; |
3571 | a4a771c0 | balrog | |
3572 | a4a771c0 | balrog | mem1 = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s);
|
3573 | a4a771c0 | balrog | mem2 = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s);
|
3574 | a4a771c0 | balrog | cpu_register_physical_memory(membase, 16 << shift, mem1);
|
3575 | a4a771c0 | balrog | cpu_register_physical_memory(membase2, 2 << shift, mem2);
|
3576 | a4a771c0 | balrog | } |
3577 | a4a771c0 | balrog | |
3578 | a4a771c0 | balrog | /***********************************************************/
|
3579 | 201a51fc | balrog | /* CF-ATA Microdrive */
|
3580 | 201a51fc | balrog | |
3581 | 201a51fc | balrog | #define METADATA_SIZE 0x20 |
3582 | 201a51fc | balrog | |
3583 | 201a51fc | balrog | /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
|
3584 | 201a51fc | balrog | struct md_s {
|
3585 | 201a51fc | balrog | IDEState ide[2];
|
3586 | 201a51fc | balrog | struct pcmcia_card_s card;
|
3587 | 201a51fc | balrog | uint32_t attr_base; |
3588 | 201a51fc | balrog | uint32_t io_base; |
3589 | 201a51fc | balrog | |
3590 | 201a51fc | balrog | /* Card state */
|
3591 | 201a51fc | balrog | uint8_t opt; |
3592 | 201a51fc | balrog | uint8_t stat; |
3593 | 201a51fc | balrog | uint8_t pins; |
3594 | 201a51fc | balrog | |
3595 | 201a51fc | balrog | uint8_t ctrl; |
3596 | 201a51fc | balrog | uint16_t io; |
3597 | 201a51fc | balrog | int cycle;
|
3598 | 201a51fc | balrog | }; |
3599 | 201a51fc | balrog | |
3600 | 201a51fc | balrog | /* Register bitfields */
|
3601 | 201a51fc | balrog | enum md_opt {
|
3602 | 201a51fc | balrog | OPT_MODE_MMAP = 0,
|
3603 | 201a51fc | balrog | OPT_MODE_IOMAP16 = 1,
|
3604 | 201a51fc | balrog | OPT_MODE_IOMAP1 = 2,
|
3605 | 201a51fc | balrog | OPT_MODE_IOMAP2 = 3,
|
3606 | 201a51fc | balrog | OPT_MODE = 0x3f,
|
3607 | 201a51fc | balrog | OPT_LEVIREQ = 0x40,
|
3608 | 201a51fc | balrog | OPT_SRESET = 0x80,
|
3609 | 201a51fc | balrog | }; |
3610 | 201a51fc | balrog | enum md_cstat {
|
3611 | 201a51fc | balrog | STAT_INT = 0x02,
|
3612 | 201a51fc | balrog | STAT_PWRDWN = 0x04,
|
3613 | 201a51fc | balrog | STAT_XE = 0x10,
|
3614 | 201a51fc | balrog | STAT_IOIS8 = 0x20,
|
3615 | 201a51fc | balrog | STAT_SIGCHG = 0x40,
|
3616 | 201a51fc | balrog | STAT_CHANGED = 0x80,
|
3617 | 201a51fc | balrog | }; |
3618 | 201a51fc | balrog | enum md_pins {
|
3619 | 201a51fc | balrog | PINS_MRDY = 0x02,
|
3620 | 201a51fc | balrog | PINS_CRDY = 0x20,
|
3621 | 201a51fc | balrog | }; |
3622 | 201a51fc | balrog | enum md_ctrl {
|
3623 | 201a51fc | balrog | CTRL_IEN = 0x02,
|
3624 | 201a51fc | balrog | CTRL_SRST = 0x04,
|
3625 | 201a51fc | balrog | }; |
3626 | 201a51fc | balrog | |
3627 | 201a51fc | balrog | static inline void md_interrupt_update(struct md_s *s) |
3628 | 201a51fc | balrog | { |
3629 | 201a51fc | balrog | if (!s->card.slot)
|
3630 | 201a51fc | balrog | return;
|
3631 | 201a51fc | balrog | |
3632 | 201a51fc | balrog | qemu_set_irq(s->card.slot->irq, |
3633 | 201a51fc | balrog | !(s->stat & STAT_INT) && /* Inverted */
|
3634 | 201a51fc | balrog | !(s->ctrl & (CTRL_IEN | CTRL_SRST)) && |
3635 | 201a51fc | balrog | !(s->opt & OPT_SRESET)); |
3636 | 201a51fc | balrog | } |
3637 | 201a51fc | balrog | |
3638 | 201a51fc | balrog | static void md_set_irq(void *opaque, int irq, int level) |
3639 | 201a51fc | balrog | { |
3640 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3641 | 201a51fc | balrog | if (level)
|
3642 | 201a51fc | balrog | s->stat |= STAT_INT; |
3643 | 201a51fc | balrog | else
|
3644 | 201a51fc | balrog | s->stat &= ~STAT_INT; |
3645 | 201a51fc | balrog | |
3646 | 201a51fc | balrog | md_interrupt_update(s); |
3647 | 201a51fc | balrog | } |
3648 | 201a51fc | balrog | |
3649 | 201a51fc | balrog | static void md_reset(struct md_s *s) |
3650 | 201a51fc | balrog | { |
3651 | 201a51fc | balrog | s->opt = OPT_MODE_MMAP; |
3652 | 201a51fc | balrog | s->stat = 0;
|
3653 | 201a51fc | balrog | s->pins = 0;
|
3654 | 201a51fc | balrog | s->cycle = 0;
|
3655 | 201a51fc | balrog | s->ctrl = 0;
|
3656 | 201a51fc | balrog | ide_reset(s->ide); |
3657 | 201a51fc | balrog | } |
3658 | 201a51fc | balrog | |
3659 | 9e315fa9 | balrog | static uint8_t md_attr_read(void *opaque, uint32_t at) |
3660 | 201a51fc | balrog | { |
3661 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3662 | 201a51fc | balrog | if (at < s->attr_base) {
|
3663 | 201a51fc | balrog | if (at < s->card.cis_len)
|
3664 | 201a51fc | balrog | return s->card.cis[at];
|
3665 | 201a51fc | balrog | else
|
3666 | 201a51fc | balrog | return 0x00; |
3667 | 201a51fc | balrog | } |
3668 | 201a51fc | balrog | |
3669 | 201a51fc | balrog | at -= s->attr_base; |
3670 | 201a51fc | balrog | |
3671 | 201a51fc | balrog | switch (at) {
|
3672 | 201a51fc | balrog | case 0x00: /* Configuration Option Register */ |
3673 | 201a51fc | balrog | return s->opt;
|
3674 | 201a51fc | balrog | case 0x02: /* Card Configuration Status Register */ |
3675 | 201a51fc | balrog | if (s->ctrl & CTRL_IEN)
|
3676 | 201a51fc | balrog | return s->stat & ~STAT_INT;
|
3677 | 201a51fc | balrog | else
|
3678 | 201a51fc | balrog | return s->stat;
|
3679 | 201a51fc | balrog | case 0x04: /* Pin Replacement Register */ |
3680 | 201a51fc | balrog | return (s->pins & PINS_CRDY) | 0x0c; |
3681 | 201a51fc | balrog | case 0x06: /* Socket and Copy Register */ |
3682 | 201a51fc | balrog | return 0x00; |
3683 | 201a51fc | balrog | #ifdef VERBOSE
|
3684 | 201a51fc | balrog | default:
|
3685 | 201a51fc | balrog | printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
|
3686 | 201a51fc | balrog | #endif
|
3687 | 201a51fc | balrog | } |
3688 | 201a51fc | balrog | |
3689 | 201a51fc | balrog | return 0; |
3690 | 201a51fc | balrog | } |
3691 | 201a51fc | balrog | |
3692 | 9e315fa9 | balrog | static void md_attr_write(void *opaque, uint32_t at, uint8_t value) |
3693 | 201a51fc | balrog | { |
3694 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3695 | 201a51fc | balrog | at -= s->attr_base; |
3696 | 201a51fc | balrog | |
3697 | 201a51fc | balrog | switch (at) {
|
3698 | 201a51fc | balrog | case 0x00: /* Configuration Option Register */ |
3699 | 201a51fc | balrog | s->opt = value & 0xcf;
|
3700 | 201a51fc | balrog | if (value & OPT_SRESET)
|
3701 | 201a51fc | balrog | md_reset(s); |
3702 | 201a51fc | balrog | md_interrupt_update(s); |
3703 | 201a51fc | balrog | break;
|
3704 | 201a51fc | balrog | case 0x02: /* Card Configuration Status Register */ |
3705 | 201a51fc | balrog | if ((s->stat ^ value) & STAT_PWRDWN)
|
3706 | 201a51fc | balrog | s->pins |= PINS_CRDY; |
3707 | 201a51fc | balrog | s->stat &= 0x82;
|
3708 | 201a51fc | balrog | s->stat |= value & 0x74;
|
3709 | 201a51fc | balrog | md_interrupt_update(s); |
3710 | 201a51fc | balrog | /* Word 170 in Identify Device must be equal to STAT_XE */
|
3711 | 201a51fc | balrog | break;
|
3712 | 201a51fc | balrog | case 0x04: /* Pin Replacement Register */ |
3713 | 201a51fc | balrog | s->pins &= PINS_CRDY; |
3714 | 201a51fc | balrog | s->pins |= value & PINS_MRDY; |
3715 | 201a51fc | balrog | break;
|
3716 | 201a51fc | balrog | case 0x06: /* Socket and Copy Register */ |
3717 | 201a51fc | balrog | break;
|
3718 | 201a51fc | balrog | default:
|
3719 | 201a51fc | balrog | printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
|
3720 | 201a51fc | balrog | } |
3721 | 201a51fc | balrog | } |
3722 | 201a51fc | balrog | |
3723 | 9e315fa9 | balrog | static uint16_t md_common_read(void *opaque, uint32_t at) |
3724 | 201a51fc | balrog | { |
3725 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3726 | 201a51fc | balrog | uint16_t ret; |
3727 | 201a51fc | balrog | at -= s->io_base; |
3728 | 201a51fc | balrog | |
3729 | 201a51fc | balrog | switch (s->opt & OPT_MODE) {
|
3730 | 201a51fc | balrog | case OPT_MODE_MMAP:
|
3731 | 201a51fc | balrog | if ((at & ~0x3ff) == 0x400) |
3732 | 201a51fc | balrog | at = 0;
|
3733 | 201a51fc | balrog | break;
|
3734 | 201a51fc | balrog | case OPT_MODE_IOMAP16:
|
3735 | 201a51fc | balrog | at &= 0xf;
|
3736 | 201a51fc | balrog | break;
|
3737 | 201a51fc | balrog | case OPT_MODE_IOMAP1:
|
3738 | 201a51fc | balrog | if ((at & ~0xf) == 0x3f0) |
3739 | 201a51fc | balrog | at -= 0x3e8;
|
3740 | 201a51fc | balrog | else if ((at & ~0xf) == 0x1f0) |
3741 | 201a51fc | balrog | at -= 0x1f0;
|
3742 | 201a51fc | balrog | break;
|
3743 | 201a51fc | balrog | case OPT_MODE_IOMAP2:
|
3744 | 201a51fc | balrog | if ((at & ~0xf) == 0x370) |
3745 | 201a51fc | balrog | at -= 0x368;
|
3746 | 201a51fc | balrog | else if ((at & ~0xf) == 0x170) |
3747 | 201a51fc | balrog | at -= 0x170;
|
3748 | 201a51fc | balrog | } |
3749 | 201a51fc | balrog | |
3750 | 201a51fc | balrog | switch (at) {
|
3751 | 201a51fc | balrog | case 0x0: /* Even RD Data */ |
3752 | 201a51fc | balrog | case 0x8: |
3753 | 201a51fc | balrog | return ide_data_readw(s->ide, 0); |
3754 | 201a51fc | balrog | |
3755 | 201a51fc | balrog | /* TODO: 8-bit accesses */
|
3756 | 201a51fc | balrog | if (s->cycle)
|
3757 | 201a51fc | balrog | ret = s->io >> 8;
|
3758 | 201a51fc | balrog | else {
|
3759 | 201a51fc | balrog | s->io = ide_data_readw(s->ide, 0);
|
3760 | 201a51fc | balrog | ret = s->io & 0xff;
|
3761 | 201a51fc | balrog | } |
3762 | 201a51fc | balrog | s->cycle = !s->cycle; |
3763 | 201a51fc | balrog | return ret;
|
3764 | 201a51fc | balrog | case 0x9: /* Odd RD Data */ |
3765 | 201a51fc | balrog | return s->io >> 8; |
3766 | 201a51fc | balrog | case 0xd: /* Error */ |
3767 | 201a51fc | balrog | return ide_ioport_read(s->ide, 0x1); |
3768 | 201a51fc | balrog | case 0xe: /* Alternate Status */ |
3769 | 201a51fc | balrog | if (s->ide->cur_drive->bs)
|
3770 | 201a51fc | balrog | return s->ide->cur_drive->status;
|
3771 | 201a51fc | balrog | else
|
3772 | 201a51fc | balrog | return 0; |
3773 | 201a51fc | balrog | case 0xf: /* Device Address */ |
3774 | 201a51fc | balrog | return 0xc2 | ((~s->ide->select << 2) & 0x3c); |
3775 | 201a51fc | balrog | default:
|
3776 | 201a51fc | balrog | return ide_ioport_read(s->ide, at);
|
3777 | 201a51fc | balrog | } |
3778 | 201a51fc | balrog | |
3779 | 201a51fc | balrog | return 0; |
3780 | 201a51fc | balrog | } |
3781 | 201a51fc | balrog | |
3782 | 9e315fa9 | balrog | static void md_common_write(void *opaque, uint32_t at, uint16_t value) |
3783 | 201a51fc | balrog | { |
3784 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3785 | 201a51fc | balrog | at -= s->io_base; |
3786 | 201a51fc | balrog | |
3787 | 201a51fc | balrog | switch (s->opt & OPT_MODE) {
|
3788 | 201a51fc | balrog | case OPT_MODE_MMAP:
|
3789 | 201a51fc | balrog | if ((at & ~0x3ff) == 0x400) |
3790 | 201a51fc | balrog | at = 0;
|
3791 | 201a51fc | balrog | break;
|
3792 | 201a51fc | balrog | case OPT_MODE_IOMAP16:
|
3793 | 201a51fc | balrog | at &= 0xf;
|
3794 | 201a51fc | balrog | break;
|
3795 | 201a51fc | balrog | case OPT_MODE_IOMAP1:
|
3796 | 201a51fc | balrog | if ((at & ~0xf) == 0x3f0) |
3797 | 201a51fc | balrog | at -= 0x3e8;
|
3798 | 201a51fc | balrog | else if ((at & ~0xf) == 0x1f0) |
3799 | 201a51fc | balrog | at -= 0x1f0;
|
3800 | 201a51fc | balrog | break;
|
3801 | 201a51fc | balrog | case OPT_MODE_IOMAP2:
|
3802 | 201a51fc | balrog | if ((at & ~0xf) == 0x370) |
3803 | 201a51fc | balrog | at -= 0x368;
|
3804 | 201a51fc | balrog | else if ((at & ~0xf) == 0x170) |
3805 | 201a51fc | balrog | at -= 0x170;
|
3806 | 201a51fc | balrog | } |
3807 | 201a51fc | balrog | |
3808 | 201a51fc | balrog | switch (at) {
|
3809 | 201a51fc | balrog | case 0x0: /* Even WR Data */ |
3810 | 201a51fc | balrog | case 0x8: |
3811 | 201a51fc | balrog | ide_data_writew(s->ide, 0, value);
|
3812 | 201a51fc | balrog | break;
|
3813 | 201a51fc | balrog | |
3814 | 201a51fc | balrog | /* TODO: 8-bit accesses */
|
3815 | 201a51fc | balrog | if (s->cycle)
|
3816 | 201a51fc | balrog | ide_data_writew(s->ide, 0, s->io | (value << 8)); |
3817 | 201a51fc | balrog | else
|
3818 | 201a51fc | balrog | s->io = value & 0xff;
|
3819 | 201a51fc | balrog | s->cycle = !s->cycle; |
3820 | 201a51fc | balrog | break;
|
3821 | 201a51fc | balrog | case 0x9: |
3822 | 201a51fc | balrog | s->io = value & 0xff;
|
3823 | 201a51fc | balrog | s->cycle = !s->cycle; |
3824 | 201a51fc | balrog | break;
|
3825 | 201a51fc | balrog | case 0xd: /* Features */ |
3826 | 201a51fc | balrog | ide_ioport_write(s->ide, 0x1, value);
|
3827 | 201a51fc | balrog | break;
|
3828 | 201a51fc | balrog | case 0xe: /* Device Control */ |
3829 | 201a51fc | balrog | s->ctrl = value; |
3830 | 201a51fc | balrog | if (value & CTRL_SRST)
|
3831 | 201a51fc | balrog | md_reset(s); |
3832 | 201a51fc | balrog | md_interrupt_update(s); |
3833 | 201a51fc | balrog | break;
|
3834 | 201a51fc | balrog | default:
|
3835 | 201a51fc | balrog | if (s->stat & STAT_PWRDWN) {
|
3836 | 201a51fc | balrog | s->pins |= PINS_CRDY; |
3837 | 201a51fc | balrog | s->stat &= ~STAT_PWRDWN; |
3838 | 201a51fc | balrog | } |
3839 | 201a51fc | balrog | ide_ioport_write(s->ide, at, value); |
3840 | 201a51fc | balrog | } |
3841 | 201a51fc | balrog | } |
3842 | 201a51fc | balrog | |
3843 | aa941b94 | balrog | static void md_save(QEMUFile *f, void *opaque) |
3844 | aa941b94 | balrog | { |
3845 | aa941b94 | balrog | struct md_s *s = (struct md_s *) opaque; |
3846 | aa941b94 | balrog | int i;
|
3847 | aa941b94 | balrog | uint8_t drive1_selected; |
3848 | aa941b94 | balrog | |
3849 | aa941b94 | balrog | qemu_put_8s(f, &s->opt); |
3850 | aa941b94 | balrog | qemu_put_8s(f, &s->stat); |
3851 | aa941b94 | balrog | qemu_put_8s(f, &s->pins); |
3852 | aa941b94 | balrog | |
3853 | aa941b94 | balrog | qemu_put_8s(f, &s->ctrl); |
3854 | aa941b94 | balrog | qemu_put_be16s(f, &s->io); |
3855 | aa941b94 | balrog | qemu_put_byte(f, s->cycle); |
3856 | aa941b94 | balrog | |
3857 | aa941b94 | balrog | drive1_selected = (s->ide->cur_drive != s->ide); |
3858 | aa941b94 | balrog | qemu_put_8s(f, &s->ide->cmd); |
3859 | aa941b94 | balrog | qemu_put_8s(f, &drive1_selected); |
3860 | aa941b94 | balrog | |
3861 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
3862 | aa941b94 | balrog | ide_save(f, &s->ide[i]); |
3863 | aa941b94 | balrog | } |
3864 | aa941b94 | balrog | |
3865 | aa941b94 | balrog | static int md_load(QEMUFile *f, void *opaque, int version_id) |
3866 | aa941b94 | balrog | { |
3867 | aa941b94 | balrog | struct md_s *s = (struct md_s *) opaque; |
3868 | aa941b94 | balrog | int i;
|
3869 | aa941b94 | balrog | uint8_t drive1_selected; |
3870 | aa941b94 | balrog | |
3871 | aa941b94 | balrog | qemu_get_8s(f, &s->opt); |
3872 | aa941b94 | balrog | qemu_get_8s(f, &s->stat); |
3873 | aa941b94 | balrog | qemu_get_8s(f, &s->pins); |
3874 | aa941b94 | balrog | |
3875 | aa941b94 | balrog | qemu_get_8s(f, &s->ctrl); |
3876 | aa941b94 | balrog | qemu_get_be16s(f, &s->io); |
3877 | aa941b94 | balrog | s->cycle = qemu_get_byte(f); |
3878 | aa941b94 | balrog | |
3879 | aa941b94 | balrog | qemu_get_8s(f, &s->ide->cmd); |
3880 | aa941b94 | balrog | qemu_get_8s(f, &drive1_selected); |
3881 | aa941b94 | balrog | s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
|
3882 | aa941b94 | balrog | |
3883 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
3884 | aa941b94 | balrog | ide_load(f, &s->ide[i]); |
3885 | aa941b94 | balrog | |
3886 | aa941b94 | balrog | return 0; |
3887 | aa941b94 | balrog | } |
3888 | aa941b94 | balrog | |
3889 | 201a51fc | balrog | static const uint8_t dscm1xxxx_cis[0x14a] = { |
3890 | 201a51fc | balrog | [0x000] = CISTPL_DEVICE, /* 5V Device Information */ |
3891 | 201a51fc | balrog | [0x002] = 0x03, /* Tuple length = 4 bytes */ |
3892 | 201a51fc | balrog | [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ |
3893 | 201a51fc | balrog | [0x006] = 0x01, /* Size = 2K bytes */ |
3894 | 201a51fc | balrog | [0x008] = CISTPL_ENDMARK,
|
3895 | 201a51fc | balrog | |
3896 | 201a51fc | balrog | [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */ |
3897 | 201a51fc | balrog | [0x00c] = 0x04, /* Tuple length = 4 byest */ |
3898 | 201a51fc | balrog | [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */ |
3899 | 201a51fc | balrog | [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ |
3900 | 201a51fc | balrog | [0x012] = 0x01, /* Size = 2K bytes */ |
3901 | 201a51fc | balrog | [0x014] = CISTPL_ENDMARK,
|
3902 | 201a51fc | balrog | |
3903 | 201a51fc | balrog | [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */ |
3904 | 201a51fc | balrog | [0x018] = 0x02, /* Tuple length = 2 bytes */ |
3905 | 201a51fc | balrog | [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */ |
3906 | 201a51fc | balrog | [0x01c] = 0x01, |
3907 | 201a51fc | balrog | |
3908 | 201a51fc | balrog | [0x01e] = CISTPL_MANFID, /* Manufacture ID */ |
3909 | 201a51fc | balrog | [0x020] = 0x04, /* Tuple length = 4 bytes */ |
3910 | 201a51fc | balrog | [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */ |
3911 | 201a51fc | balrog | [0x024] = 0x00, |
3912 | 201a51fc | balrog | [0x026] = 0x00, /* PLMID_CARD = 0000 */ |
3913 | 201a51fc | balrog | [0x028] = 0x00, |
3914 | 201a51fc | balrog | |
3915 | 201a51fc | balrog | [0x02a] = CISTPL_VERS_1, /* Level 1 Version */ |
3916 | 201a51fc | balrog | [0x02c] = 0x12, /* Tuple length = 23 bytes */ |
3917 | 201a51fc | balrog | [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */ |
3918 | 201a51fc | balrog | [0x030] = 0x01, /* Minor Version = 1 */ |
3919 | 201a51fc | balrog | [0x032] = 'I', |
3920 | 201a51fc | balrog | [0x034] = 'B', |
3921 | 201a51fc | balrog | [0x036] = 'M', |
3922 | 201a51fc | balrog | [0x038] = 0x00, |
3923 | 201a51fc | balrog | [0x03a] = 'm', |
3924 | 201a51fc | balrog | [0x03c] = 'i', |
3925 | 201a51fc | balrog | [0x03e] = 'c', |
3926 | 201a51fc | balrog | [0x040] = 'r', |
3927 | 201a51fc | balrog | [0x042] = 'o', |
3928 | 201a51fc | balrog | [0x044] = 'd', |
3929 | 201a51fc | balrog | [0x046] = 'r', |
3930 | 201a51fc | balrog | [0x048] = 'i', |
3931 | 201a51fc | balrog | [0x04a] = 'v', |
3932 | 201a51fc | balrog | [0x04c] = 'e', |
3933 | 201a51fc | balrog | [0x04e] = 0x00, |
3934 | 201a51fc | balrog | [0x050] = CISTPL_ENDMARK,
|
3935 | 201a51fc | balrog | |
3936 | 201a51fc | balrog | [0x052] = CISTPL_FUNCID, /* Function ID */ |
3937 | 201a51fc | balrog | [0x054] = 0x02, /* Tuple length = 2 bytes */ |
3938 | 201a51fc | balrog | [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */ |
3939 | 201a51fc | balrog | [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */ |
3940 | 201a51fc | balrog | |
3941 | 201a51fc | balrog | [0x05a] = CISTPL_FUNCE, /* Function Extension */ |
3942 | 201a51fc | balrog | [0x05c] = 0x02, /* Tuple length = 2 bytes */ |
3943 | 201a51fc | balrog | [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */ |
3944 | 201a51fc | balrog | [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */ |
3945 | 201a51fc | balrog | |
3946 | 201a51fc | balrog | [0x062] = CISTPL_FUNCE, /* Function Extension */ |
3947 | 201a51fc | balrog | [0x064] = 0x03, /* Tuple length = 3 bytes */ |
3948 | 201a51fc | balrog | [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */ |
3949 | 201a51fc | balrog | [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */ |
3950 | 201a51fc | balrog | [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */ |
3951 | 201a51fc | balrog | |
3952 | 201a51fc | balrog | [0x06c] = CISTPL_CONFIG, /* Configuration */ |
3953 | 201a51fc | balrog | [0x06e] = 0x05, /* Tuple length = 5 bytes */ |
3954 | 201a51fc | balrog | [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */ |
3955 | 201a51fc | balrog | [0x072] = 0x07, /* TPCC_LAST = 7 */ |
3956 | 201a51fc | balrog | [0x074] = 0x00, /* TPCC_RADR = 0200 */ |
3957 | 201a51fc | balrog | [0x076] = 0x02, |
3958 | 201a51fc | balrog | [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */ |
3959 | 201a51fc | balrog | |
3960 | 201a51fc | balrog | [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3961 | 201a51fc | balrog | [0x07c] = 0x0b, /* Tuple length = 11 bytes */ |
3962 | 201a51fc | balrog | [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */ |
3963 | 201a51fc | balrog | [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */ |
3964 | 201a51fc | balrog | [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */ |
3965 | 201a51fc | balrog | [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
3966 | 201a51fc | balrog | [0x086] = 0x55, /* NomV: 5.0 V */ |
3967 | 201a51fc | balrog | [0x088] = 0x4d, /* MinV: 4.5 V */ |
3968 | 201a51fc | balrog | [0x08a] = 0x5d, /* MaxV: 5.5 V */ |
3969 | 201a51fc | balrog | [0x08c] = 0x4e, /* Peakl: 450 mA */ |
3970 | 201a51fc | balrog | [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */ |
3971 | 201a51fc | balrog | [0x090] = 0x00, /* Window descriptor: Window length = 0 */ |
3972 | 201a51fc | balrog | [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */ |
3973 | 201a51fc | balrog | |
3974 | 201a51fc | balrog | [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3975 | 201a51fc | balrog | [0x096] = 0x06, /* Tuple length = 6 bytes */ |
3976 | 201a51fc | balrog | [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */ |
3977 | 201a51fc | balrog | [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
3978 | 201a51fc | balrog | [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
3979 | 201a51fc | balrog | [0x09e] = 0xb5, /* NomV: 3.3 V */ |
3980 | 201a51fc | balrog | [0x0a0] = 0x1e, |
3981 | 201a51fc | balrog | [0x0a2] = 0x3e, /* Peakl: 350 mA */ |
3982 | 201a51fc | balrog | |
3983 | 201a51fc | balrog | [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3984 | 201a51fc | balrog | [0x0a6] = 0x0d, /* Tuple length = 13 bytes */ |
3985 | 201a51fc | balrog | [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */ |
3986 | 201a51fc | balrog | [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
3987 | 201a51fc | balrog | [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
3988 | 201a51fc | balrog | [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
3989 | 201a51fc | balrog | [0x0b0] = 0x55, /* NomV: 5.0 V */ |
3990 | 201a51fc | balrog | [0x0b2] = 0x4d, /* MinV: 4.5 V */ |
3991 | 201a51fc | balrog | [0x0b4] = 0x5d, /* MaxV: 5.5 V */ |
3992 | 201a51fc | balrog | [0x0b6] = 0x4e, /* Peakl: 450 mA */ |
3993 | 201a51fc | balrog | [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */ |
3994 | 201a51fc | balrog | [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */ |
3995 | 201a51fc | balrog | [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */ |
3996 | 201a51fc | balrog | [0x0be] = 0xff, /* IRQ8..IRQ15 supported */ |
3997 | 201a51fc | balrog | [0x0c0] = 0x20, /* TPCE_MI = support power down mode */ |
3998 | 201a51fc | balrog | |
3999 | 201a51fc | balrog | [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
4000 | 201a51fc | balrog | [0x0c4] = 0x06, /* Tuple length = 6 bytes */ |
4001 | 201a51fc | balrog | [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */ |
4002 | 201a51fc | balrog | [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
4003 | 201a51fc | balrog | [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
4004 | 201a51fc | balrog | [0x0cc] = 0xb5, /* NomV: 3.3 V */ |
4005 | 201a51fc | balrog | [0x0ce] = 0x1e, |
4006 | 201a51fc | balrog | [0x0d0] = 0x3e, /* Peakl: 350 mA */ |
4007 | 201a51fc | balrog | |
4008 | 201a51fc | balrog | [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
4009 | 201a51fc | balrog | [0x0d4] = 0x12, /* Tuple length = 18 bytes */ |
4010 | 201a51fc | balrog | [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */ |
4011 | 201a51fc | balrog | [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
4012 | 201a51fc | balrog | [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
4013 | 201a51fc | balrog | [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
4014 | 201a51fc | balrog | [0x0de] = 0x55, /* NomV: 5.0 V */ |
4015 | 201a51fc | balrog | [0x0e0] = 0x4d, /* MinV: 4.5 V */ |
4016 | 201a51fc | balrog | [0x0e2] = 0x5d, /* MaxV: 5.5 V */ |
4017 | 201a51fc | balrog | [0x0e4] = 0x4e, /* Peakl: 450 mA */ |
4018 | 201a51fc | balrog | [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ |
4019 | 201a51fc | balrog | [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */ |
4020 | 201a51fc | balrog | [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */ |
4021 | 201a51fc | balrog | [0x0ec] = 0x01, |
4022 | 201a51fc | balrog | [0x0ee] = 0x07, /* Address block length = 8 */ |
4023 | 201a51fc | balrog | [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */ |
4024 | 201a51fc | balrog | [0x0f2] = 0x03, |
4025 | 201a51fc | balrog | [0x0f4] = 0x01, /* Address block length = 2 */ |
4026 | 201a51fc | balrog | [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ |
4027 | 201a51fc | balrog | [0x0f8] = 0x20, /* TPCE_MI = support power down mode */ |
4028 | 201a51fc | balrog | |
4029 | 201a51fc | balrog | [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
4030 | 201a51fc | balrog | [0x0fc] = 0x06, /* Tuple length = 6 bytes */ |
4031 | 201a51fc | balrog | [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */ |
4032 | 201a51fc | balrog | [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
4033 | 201a51fc | balrog | [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
4034 | 201a51fc | balrog | [0x104] = 0xb5, /* NomV: 3.3 V */ |
4035 | 201a51fc | balrog | [0x106] = 0x1e, |
4036 | 201a51fc | balrog | [0x108] = 0x3e, /* Peakl: 350 mA */ |
4037 | 201a51fc | balrog | |
4038 | 201a51fc | balrog | [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
4039 | 201a51fc | balrog | [0x10c] = 0x12, /* Tuple length = 18 bytes */ |
4040 | 201a51fc | balrog | [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */ |
4041 | 201a51fc | balrog | [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
4042 | 201a51fc | balrog | [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
4043 | 201a51fc | balrog | [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
4044 | 201a51fc | balrog | [0x116] = 0x55, /* NomV: 5.0 V */ |
4045 | 201a51fc | balrog | [0x118] = 0x4d, /* MinV: 4.5 V */ |
4046 | 201a51fc | balrog | [0x11a] = 0x5d, /* MaxV: 5.5 V */ |
4047 | 201a51fc | balrog | [0x11c] = 0x4e, /* Peakl: 450 mA */ |
4048 | 201a51fc | balrog | [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ |
4049 | 201a51fc | balrog | [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */ |
4050 | 201a51fc | balrog | [0x122] = 0x70, /* Field 1 address = 0x0170 */ |
4051 | 201a51fc | balrog | [0x124] = 0x01, |
4052 | 201a51fc | balrog | [0x126] = 0x07, /* Address block length = 8 */ |
4053 | 201a51fc | balrog | [0x128] = 0x76, /* Field 2 address = 0x0376 */ |
4054 | 201a51fc | balrog | [0x12a] = 0x03, |
4055 | 201a51fc | balrog | [0x12c] = 0x01, /* Address block length = 2 */ |
4056 | 201a51fc | balrog | [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ |
4057 | 201a51fc | balrog | [0x130] = 0x20, /* TPCE_MI = support power down mode */ |
4058 | 201a51fc | balrog | |
4059 | 201a51fc | balrog | [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
4060 | 201a51fc | balrog | [0x134] = 0x06, /* Tuple length = 6 bytes */ |
4061 | 201a51fc | balrog | [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */ |
4062 | 201a51fc | balrog | [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
4063 | 201a51fc | balrog | [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
4064 | 201a51fc | balrog | [0x13c] = 0xb5, /* NomV: 3.3 V */ |
4065 | 201a51fc | balrog | [0x13e] = 0x1e, |
4066 | 201a51fc | balrog | [0x140] = 0x3e, /* Peakl: 350 mA */ |
4067 | 201a51fc | balrog | |
4068 | 201a51fc | balrog | [0x142] = CISTPL_NO_LINK, /* No Link */ |
4069 | 201a51fc | balrog | [0x144] = 0x00, /* Tuple length = 0 bytes */ |
4070 | 201a51fc | balrog | |
4071 | 201a51fc | balrog | [0x146] = CISTPL_END, /* Tuple End */ |
4072 | 201a51fc | balrog | }; |
4073 | 201a51fc | balrog | |
4074 | 201a51fc | balrog | static int dscm1xxxx_attach(void *opaque) |
4075 | 201a51fc | balrog | { |
4076 | 201a51fc | balrog | struct md_s *md = (struct md_s *) opaque; |
4077 | 201a51fc | balrog | md->card.attr_read = md_attr_read; |
4078 | 201a51fc | balrog | md->card.attr_write = md_attr_write; |
4079 | 201a51fc | balrog | md->card.common_read = md_common_read; |
4080 | 201a51fc | balrog | md->card.common_write = md_common_write; |
4081 | 201a51fc | balrog | md->card.io_read = md_common_read; |
4082 | 201a51fc | balrog | md->card.io_write = md_common_write; |
4083 | 201a51fc | balrog | |
4084 | 201a51fc | balrog | md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8); |
4085 | 201a51fc | balrog | md->io_base = 0x0;
|
4086 | 201a51fc | balrog | |
4087 | 201a51fc | balrog | md_reset(md); |
4088 | 201a51fc | balrog | md_interrupt_update(md); |
4089 | 201a51fc | balrog | |
4090 | 201a51fc | balrog | md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
|
4091 | 201a51fc | balrog | return 0; |
4092 | 201a51fc | balrog | } |
4093 | 201a51fc | balrog | |
4094 | 201a51fc | balrog | static int dscm1xxxx_detach(void *opaque) |
4095 | 201a51fc | balrog | { |
4096 | 201a51fc | balrog | struct md_s *md = (struct md_s *) opaque; |
4097 | 201a51fc | balrog | md_reset(md); |
4098 | 201a51fc | balrog | return 0; |
4099 | 201a51fc | balrog | } |
4100 | 201a51fc | balrog | |
4101 | 201a51fc | balrog | struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
|
4102 | 201a51fc | balrog | { |
4103 | 201a51fc | balrog | struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s)); |
4104 | 201a51fc | balrog | md->card.state = md; |
4105 | 201a51fc | balrog | md->card.attach = dscm1xxxx_attach; |
4106 | 201a51fc | balrog | md->card.detach = dscm1xxxx_detach; |
4107 | 201a51fc | balrog | md->card.cis = dscm1xxxx_cis; |
4108 | 201a51fc | balrog | md->card.cis_len = sizeof(dscm1xxxx_cis);
|
4109 | 201a51fc | balrog | |
4110 | 201a51fc | balrog | ide_init2(md->ide, bdrv, 0, qemu_allocate_irqs(md_set_irq, md, 1)[0]); |
4111 | 201a51fc | balrog | md->ide->is_cf = 1;
|
4112 | 201a51fc | balrog | md->ide->mdata_size = METADATA_SIZE; |
4113 | 201a51fc | balrog | md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE); |
4114 | aa941b94 | balrog | |
4115 | 18be5187 | pbrook | register_savevm("microdrive", -1, 0, md_save, md_load, md); |
4116 | aa941b94 | balrog | |
4117 | 201a51fc | balrog | return &md->card;
|
4118 | 201a51fc | balrog | } |