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1 | 5fafdf24 | ths | /*
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2 | 16406950 | pbrook | * ARM Versatile Platform/Application Baseboard System emulation.
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3 | cdbdb648 | pbrook | *
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4 | a1bb27b1 | pbrook | * Copyright (c) 2005-2007 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "arm-misc.h" |
12 | 87ecb68b | pbrook | #include "primecell.h" |
13 | 87ecb68b | pbrook | #include "devices.h" |
14 | 87ecb68b | pbrook | #include "net.h" |
15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | 87ecb68b | pbrook | #include "pci.h" |
17 | 87ecb68b | pbrook | #include "boards.h" |
18 | cdbdb648 | pbrook | |
19 | cdbdb648 | pbrook | /* Primary interrupt controller. */
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20 | cdbdb648 | pbrook | |
21 | cdbdb648 | pbrook | typedef struct vpb_sic_state |
22 | cdbdb648 | pbrook | { |
23 | cdbdb648 | pbrook | uint32_t level; |
24 | cdbdb648 | pbrook | uint32_t mask; |
25 | cdbdb648 | pbrook | uint32_t pic_enable; |
26 | d537cf6c | pbrook | qemu_irq *parent; |
27 | cdbdb648 | pbrook | int irq;
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28 | cdbdb648 | pbrook | } vpb_sic_state; |
29 | cdbdb648 | pbrook | |
30 | cdbdb648 | pbrook | static void vpb_sic_update(vpb_sic_state *s) |
31 | cdbdb648 | pbrook | { |
32 | cdbdb648 | pbrook | uint32_t flags; |
33 | cdbdb648 | pbrook | |
34 | cdbdb648 | pbrook | flags = s->level & s->mask; |
35 | d537cf6c | pbrook | qemu_set_irq(s->parent[s->irq], flags != 0);
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36 | cdbdb648 | pbrook | } |
37 | cdbdb648 | pbrook | |
38 | cdbdb648 | pbrook | static void vpb_sic_update_pic(vpb_sic_state *s) |
39 | cdbdb648 | pbrook | { |
40 | cdbdb648 | pbrook | int i;
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41 | cdbdb648 | pbrook | uint32_t mask; |
42 | cdbdb648 | pbrook | |
43 | cdbdb648 | pbrook | for (i = 21; i <= 30; i++) { |
44 | cdbdb648 | pbrook | mask = 1u << i;
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45 | cdbdb648 | pbrook | if (!(s->pic_enable & mask))
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46 | cdbdb648 | pbrook | continue;
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47 | d537cf6c | pbrook | qemu_set_irq(s->parent[i], (s->level & mask) != 0);
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48 | cdbdb648 | pbrook | } |
49 | cdbdb648 | pbrook | } |
50 | cdbdb648 | pbrook | |
51 | cdbdb648 | pbrook | static void vpb_sic_set_irq(void *opaque, int irq, int level) |
52 | cdbdb648 | pbrook | { |
53 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
54 | cdbdb648 | pbrook | if (level)
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55 | cdbdb648 | pbrook | s->level |= 1u << irq;
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56 | cdbdb648 | pbrook | else
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57 | cdbdb648 | pbrook | s->level &= ~(1u << irq);
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58 | cdbdb648 | pbrook | if (s->pic_enable & (1u << irq)) |
59 | d537cf6c | pbrook | qemu_set_irq(s->parent[irq], level); |
60 | cdbdb648 | pbrook | vpb_sic_update(s); |
61 | cdbdb648 | pbrook | } |
62 | cdbdb648 | pbrook | |
63 | cdbdb648 | pbrook | static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) |
64 | cdbdb648 | pbrook | { |
65 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
66 | cdbdb648 | pbrook | |
67 | cdbdb648 | pbrook | switch (offset >> 2) { |
68 | cdbdb648 | pbrook | case 0: /* STATUS */ |
69 | cdbdb648 | pbrook | return s->level & s->mask;
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70 | cdbdb648 | pbrook | case 1: /* RAWSTAT */ |
71 | cdbdb648 | pbrook | return s->level;
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72 | cdbdb648 | pbrook | case 2: /* ENABLE */ |
73 | cdbdb648 | pbrook | return s->mask;
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74 | cdbdb648 | pbrook | case 4: /* SOFTINT */ |
75 | cdbdb648 | pbrook | return s->level & 1; |
76 | cdbdb648 | pbrook | case 8: /* PICENABLE */ |
77 | cdbdb648 | pbrook | return s->pic_enable;
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78 | cdbdb648 | pbrook | default:
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79 | e69954b9 | pbrook | printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
80 | cdbdb648 | pbrook | return 0; |
81 | cdbdb648 | pbrook | } |
82 | cdbdb648 | pbrook | } |
83 | cdbdb648 | pbrook | |
84 | cdbdb648 | pbrook | static void vpb_sic_write(void *opaque, target_phys_addr_t offset, |
85 | cdbdb648 | pbrook | uint32_t value) |
86 | cdbdb648 | pbrook | { |
87 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
88 | cdbdb648 | pbrook | |
89 | cdbdb648 | pbrook | switch (offset >> 2) { |
90 | cdbdb648 | pbrook | case 2: /* ENSET */ |
91 | cdbdb648 | pbrook | s->mask |= value; |
92 | cdbdb648 | pbrook | break;
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93 | cdbdb648 | pbrook | case 3: /* ENCLR */ |
94 | cdbdb648 | pbrook | s->mask &= ~value; |
95 | cdbdb648 | pbrook | break;
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96 | cdbdb648 | pbrook | case 4: /* SOFTINTSET */ |
97 | cdbdb648 | pbrook | if (value)
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98 | cdbdb648 | pbrook | s->mask |= 1;
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99 | cdbdb648 | pbrook | break;
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100 | cdbdb648 | pbrook | case 5: /* SOFTINTCLR */ |
101 | cdbdb648 | pbrook | if (value)
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102 | cdbdb648 | pbrook | s->mask &= ~1u;
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103 | cdbdb648 | pbrook | break;
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104 | cdbdb648 | pbrook | case 8: /* PICENSET */ |
105 | cdbdb648 | pbrook | s->pic_enable |= (value & 0x7fe00000);
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106 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
107 | cdbdb648 | pbrook | break;
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108 | cdbdb648 | pbrook | case 9: /* PICENCLR */ |
109 | cdbdb648 | pbrook | s->pic_enable &= ~value; |
110 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
111 | cdbdb648 | pbrook | break;
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112 | cdbdb648 | pbrook | default:
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113 | e69954b9 | pbrook | printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
114 | cdbdb648 | pbrook | return;
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115 | cdbdb648 | pbrook | } |
116 | cdbdb648 | pbrook | vpb_sic_update(s); |
117 | cdbdb648 | pbrook | } |
118 | cdbdb648 | pbrook | |
119 | cdbdb648 | pbrook | static CPUReadMemoryFunc *vpb_sic_readfn[] = {
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120 | cdbdb648 | pbrook | vpb_sic_read, |
121 | cdbdb648 | pbrook | vpb_sic_read, |
122 | cdbdb648 | pbrook | vpb_sic_read |
123 | cdbdb648 | pbrook | }; |
124 | cdbdb648 | pbrook | |
125 | cdbdb648 | pbrook | static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
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126 | cdbdb648 | pbrook | vpb_sic_write, |
127 | cdbdb648 | pbrook | vpb_sic_write, |
128 | cdbdb648 | pbrook | vpb_sic_write |
129 | cdbdb648 | pbrook | }; |
130 | cdbdb648 | pbrook | |
131 | d537cf6c | pbrook | static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq) |
132 | cdbdb648 | pbrook | { |
133 | cdbdb648 | pbrook | vpb_sic_state *s; |
134 | d537cf6c | pbrook | qemu_irq *qi; |
135 | cdbdb648 | pbrook | int iomemtype;
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136 | cdbdb648 | pbrook | |
137 | cdbdb648 | pbrook | s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
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138 | cdbdb648 | pbrook | if (!s)
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139 | cdbdb648 | pbrook | return NULL; |
140 | d537cf6c | pbrook | qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
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141 | cdbdb648 | pbrook | s->parent = parent; |
142 | cdbdb648 | pbrook | s->irq = irq; |
143 | cdbdb648 | pbrook | iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
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144 | cdbdb648 | pbrook | vpb_sic_writefn, s); |
145 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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146 | cdbdb648 | pbrook | /* ??? Save/restore. */
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147 | d537cf6c | pbrook | return qi;
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148 | cdbdb648 | pbrook | } |
149 | cdbdb648 | pbrook | |
150 | cdbdb648 | pbrook | /* Board init. */
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151 | cdbdb648 | pbrook | |
152 | 16406950 | pbrook | /* The AB and PB boards both use the same core, just with different
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153 | 16406950 | pbrook | peripherans and expansion busses. For now we emulate a subset of the
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154 | 16406950 | pbrook | PB peripherals and just change the board ID. */
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155 | cdbdb648 | pbrook | |
156 | f93eb9ff | balrog | static struct arm_boot_info versatile_binfo; |
157 | f93eb9ff | balrog | |
158 | 00f82b8a | aurel32 | static void versatile_init(ram_addr_t ram_size, int vga_ram_size, |
159 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
160 | cdbdb648 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
161 | 3371d272 | pbrook | const char *initrd_filename, const char *cpu_model, |
162 | 3371d272 | pbrook | int board_id)
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163 | cdbdb648 | pbrook | { |
164 | cdbdb648 | pbrook | CPUState *env; |
165 | d537cf6c | pbrook | qemu_irq *pic; |
166 | d537cf6c | pbrook | qemu_irq *sic; |
167 | 7d8406be | pbrook | void *scsi_hba;
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168 | 502a5395 | pbrook | PCIBus *pci_bus; |
169 | 502a5395 | pbrook | NICInfo *nd; |
170 | 502a5395 | pbrook | int n;
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171 | 502a5395 | pbrook | int done_smc = 0; |
172 | e4bcb14c | ths | int index;
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173 | cdbdb648 | pbrook | |
174 | 3371d272 | pbrook | if (!cpu_model)
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175 | 3371d272 | pbrook | cpu_model = "arm926";
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176 | aaed909a | bellard | env = cpu_init(cpu_model); |
177 | aaed909a | bellard | if (!env) {
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178 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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179 | aaed909a | bellard | exit(1);
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180 | aaed909a | bellard | } |
181 | 1235fc06 | ths | /* ??? RAM should repeat to fill physical memory space. */
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182 | cdbdb648 | pbrook | /* SDRAM at address zero. */
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183 | cdbdb648 | pbrook | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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184 | cdbdb648 | pbrook | |
185 | e69954b9 | pbrook | arm_sysctl_init(0x10000000, 0x41007004); |
186 | cdbdb648 | pbrook | pic = arm_pic_init_cpu(env); |
187 | d537cf6c | pbrook | pic = pl190_init(0x10140000, pic[0], pic[1]); |
188 | cdbdb648 | pbrook | sic = vpb_sic_init(0x10003000, pic, 31); |
189 | d537cf6c | pbrook | pl050_init(0x10006000, sic[3], 0); |
190 | d537cf6c | pbrook | pl050_init(0x10007000, sic[4], 1); |
191 | cdbdb648 | pbrook | |
192 | e69954b9 | pbrook | pci_bus = pci_vpb_init(sic, 27, 0); |
193 | 502a5395 | pbrook | /* The Versatile PCI bridge does not provide access to PCI IO space,
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194 | 502a5395 | pbrook | so many of the qemu PCI devices are not useable. */
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195 | 502a5395 | pbrook | for(n = 0; n < nb_nics; n++) { |
196 | 502a5395 | pbrook | nd = &nd_table[n]; |
197 | 502a5395 | pbrook | if (!nd->model)
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198 | 502a5395 | pbrook | nd->model = done_smc ? "rtl8139" : "smc91c111"; |
199 | 502a5395 | pbrook | if (strcmp(nd->model, "smc91c111") == 0) { |
200 | d537cf6c | pbrook | smc91c111_init(nd, 0x10010000, sic[25]); |
201 | cdbdb648 | pbrook | } else {
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202 | abcebc7e | ths | pci_nic_init(pci_bus, nd, -1);
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203 | cdbdb648 | pbrook | } |
204 | cdbdb648 | pbrook | } |
205 | 0d92ed30 | pbrook | if (usb_enabled) {
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206 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
207 | 0d92ed30 | pbrook | } |
208 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
209 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
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210 | e4bcb14c | ths | exit(1);
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211 | e4bcb14c | ths | } |
212 | 7d8406be | pbrook | scsi_hba = lsi_scsi_init(pci_bus, -1);
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213 | e4bcb14c | ths | for (n = 0; n < LSI_MAX_DEVS; n++) { |
214 | e4bcb14c | ths | index = drive_get_index(IF_SCSI, 0, n);
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215 | e4bcb14c | ths | if (index == -1) |
216 | e4bcb14c | ths | continue;
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217 | e4bcb14c | ths | lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n); |
218 | 7d8406be | pbrook | } |
219 | cdbdb648 | pbrook | |
220 | 9ee6e8bb | pbrook | pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM); |
221 | 9ee6e8bb | pbrook | pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM); |
222 | 9ee6e8bb | pbrook | pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM); |
223 | 9ee6e8bb | pbrook | pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM); |
224 | cdbdb648 | pbrook | |
225 | d537cf6c | pbrook | pl080_init(0x10130000, pic[17], 8); |
226 | d537cf6c | pbrook | sp804_init(0x101e2000, pic[4]); |
227 | d537cf6c | pbrook | sp804_init(0x101e3000, pic[5]); |
228 | cdbdb648 | pbrook | |
229 | cdbdb648 | pbrook | /* The versatile/PB actually has a modified Color LCD controller
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230 | cdbdb648 | pbrook | that includes hardware cursor support from the PL111. */
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231 | d537cf6c | pbrook | pl110_init(ds, 0x10120000, pic[16], 1); |
232 | cdbdb648 | pbrook | |
233 | e4bcb14c | ths | index = drive_get_index(IF_SD, 0, 0); |
234 | e4bcb14c | ths | if (index == -1) { |
235 | e4bcb14c | ths | fprintf(stderr, "qemu: missing SecureDigital card\n");
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236 | e4bcb14c | ths | exit(1);
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237 | e4bcb14c | ths | } |
238 | e4bcb14c | ths | |
239 | e4bcb14c | ths | pl181_init(0x10005000, drives_table[index].bdrv, sic[22], sic[1]); |
240 | a1bb27b1 | pbrook | #if 0
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241 | a1bb27b1 | pbrook | /* Disabled because there's no way of specifying a block device. */
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242 | a1bb27b1 | pbrook | pl181_init(0x1000b000, NULL, sic, 23, 2);
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243 | a1bb27b1 | pbrook | #endif
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244 | a1bb27b1 | pbrook | |
245 | 7e1543c2 | pbrook | /* Add PL031 Real Time Clock. */
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246 | 7e1543c2 | pbrook | pl031_init(0x101e8000,pic[10]); |
247 | 7e1543c2 | pbrook | |
248 | 16406950 | pbrook | /* Memory map for Versatile/PB: */
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249 | cdbdb648 | pbrook | /* 0x10000000 System registers. */
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250 | cdbdb648 | pbrook | /* 0x10001000 PCI controller config registers. */
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251 | cdbdb648 | pbrook | /* 0x10002000 Serial bus interface. */
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252 | cdbdb648 | pbrook | /* 0x10003000 Secondary interrupt controller. */
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253 | cdbdb648 | pbrook | /* 0x10004000 AACI (audio). */
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254 | a1bb27b1 | pbrook | /* 0x10005000 MMCI0. */
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255 | cdbdb648 | pbrook | /* 0x10006000 KMI0 (keyboard). */
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256 | cdbdb648 | pbrook | /* 0x10007000 KMI1 (mouse). */
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257 | cdbdb648 | pbrook | /* 0x10008000 Character LCD Interface. */
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258 | cdbdb648 | pbrook | /* 0x10009000 UART3. */
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259 | cdbdb648 | pbrook | /* 0x1000a000 Smart card 1. */
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260 | a1bb27b1 | pbrook | /* 0x1000b000 MMCI1. */
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261 | cdbdb648 | pbrook | /* 0x10010000 Ethernet. */
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262 | cdbdb648 | pbrook | /* 0x10020000 USB. */
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263 | cdbdb648 | pbrook | /* 0x10100000 SSMC. */
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264 | cdbdb648 | pbrook | /* 0x10110000 MPMC. */
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265 | cdbdb648 | pbrook | /* 0x10120000 CLCD Controller. */
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266 | cdbdb648 | pbrook | /* 0x10130000 DMA Controller. */
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267 | cdbdb648 | pbrook | /* 0x10140000 Vectored interrupt controller. */
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268 | cdbdb648 | pbrook | /* 0x101d0000 AHB Monitor Interface. */
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269 | cdbdb648 | pbrook | /* 0x101e0000 System Controller. */
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270 | cdbdb648 | pbrook | /* 0x101e1000 Watchdog Interface. */
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271 | cdbdb648 | pbrook | /* 0x101e2000 Timer 0/1. */
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272 | cdbdb648 | pbrook | /* 0x101e3000 Timer 2/3. */
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273 | cdbdb648 | pbrook | /* 0x101e4000 GPIO port 0. */
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274 | cdbdb648 | pbrook | /* 0x101e5000 GPIO port 1. */
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275 | cdbdb648 | pbrook | /* 0x101e6000 GPIO port 2. */
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276 | cdbdb648 | pbrook | /* 0x101e7000 GPIO port 3. */
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277 | cdbdb648 | pbrook | /* 0x101e8000 RTC. */
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278 | cdbdb648 | pbrook | /* 0x101f0000 Smart card 0. */
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279 | cdbdb648 | pbrook | /* 0x101f1000 UART0. */
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280 | cdbdb648 | pbrook | /* 0x101f2000 UART1. */
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281 | cdbdb648 | pbrook | /* 0x101f3000 UART2. */
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282 | cdbdb648 | pbrook | /* 0x101f4000 SSPI. */
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283 | cdbdb648 | pbrook | |
284 | f93eb9ff | balrog | versatile_binfo.ram_size = ram_size; |
285 | f93eb9ff | balrog | versatile_binfo.kernel_filename = kernel_filename; |
286 | f93eb9ff | balrog | versatile_binfo.kernel_cmdline = kernel_cmdline; |
287 | f93eb9ff | balrog | versatile_binfo.initrd_filename = initrd_filename; |
288 | f93eb9ff | balrog | versatile_binfo.board_id = board_id; |
289 | f93eb9ff | balrog | arm_load_kernel(env, &versatile_binfo); |
290 | 16406950 | pbrook | } |
291 | 16406950 | pbrook | |
292 | 00f82b8a | aurel32 | static void vpb_init(ram_addr_t ram_size, int vga_ram_size, |
293 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
294 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
295 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
296 | 16406950 | pbrook | { |
297 | b881c2c6 | blueswir1 | versatile_init(ram_size, vga_ram_size, |
298 | b881c2c6 | blueswir1 | boot_device, ds, |
299 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
300 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x183);
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301 | 16406950 | pbrook | } |
302 | 16406950 | pbrook | |
303 | 00f82b8a | aurel32 | static void vab_init(ram_addr_t ram_size, int vga_ram_size, |
304 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
305 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
306 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
307 | 16406950 | pbrook | { |
308 | b881c2c6 | blueswir1 | versatile_init(ram_size, vga_ram_size, |
309 | b881c2c6 | blueswir1 | boot_device, ds, |
310 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
311 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x25e);
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312 | cdbdb648 | pbrook | } |
313 | cdbdb648 | pbrook | |
314 | cdbdb648 | pbrook | QEMUMachine versatilepb_machine = { |
315 | c9b1ae2c | blueswir1 | .name = "versatilepb",
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316 | c9b1ae2c | blueswir1 | .desc = "ARM Versatile/PB (ARM926EJ-S)",
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317 | c9b1ae2c | blueswir1 | .init = vpb_init, |
318 | c9b1ae2c | blueswir1 | .use_scsi = 1,
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319 | cdbdb648 | pbrook | }; |
320 | 16406950 | pbrook | |
321 | 16406950 | pbrook | QEMUMachine versatileab_machine = { |
322 | c9b1ae2c | blueswir1 | .name = "versatileab",
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323 | c9b1ae2c | blueswir1 | .desc = "ARM Versatile/AB (ARM926EJ-S)",
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324 | c9b1ae2c | blueswir1 | .init = vab_init, |
325 | c9b1ae2c | blueswir1 | .use_scsi = 1,
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326 | 16406950 | pbrook | }; |