Revision 36081602 target-ppc/op_mem.h
| b/target-ppc/op_mem.h | ||
|---|---|---|
| 517 | 517 |
do_raise_exception(EXCP_ALIGN); |
| 518 | 518 |
} else {
|
| 519 | 519 |
T1 = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
| 520 |
regs->reserve = (uint32_t)T0;
|
|
| 520 |
env->reserve = (uint32_t)T0;
|
|
| 521 | 521 |
} |
| 522 | 522 |
RETURN(); |
| 523 | 523 |
} |
| ... | ... | |
| 529 | 529 |
do_raise_exception(EXCP_ALIGN); |
| 530 | 530 |
} else {
|
| 531 | 531 |
T1 = glue(ldl, MEMSUFFIX)((uint64_t)T0); |
| 532 |
regs->reserve = (uint64_t)T0;
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|
| 532 |
env->reserve = (uint64_t)T0;
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|
| 533 | 533 |
} |
| 534 | 534 |
RETURN(); |
| 535 | 535 |
} |
| ... | ... | |
| 540 | 540 |
do_raise_exception(EXCP_ALIGN); |
| 541 | 541 |
} else {
|
| 542 | 542 |
T1 = glue(ldq, MEMSUFFIX)((uint32_t)T0); |
| 543 |
regs->reserve = (uint32_t)T0;
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|
| 543 |
env->reserve = (uint32_t)T0;
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|
| 544 | 544 |
} |
| 545 | 545 |
RETURN(); |
| 546 | 546 |
} |
| ... | ... | |
| 551 | 551 |
do_raise_exception(EXCP_ALIGN); |
| 552 | 552 |
} else {
|
| 553 | 553 |
T1 = glue(ldq, MEMSUFFIX)((uint64_t)T0); |
| 554 |
regs->reserve = (uint64_t)T0;
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|
| 554 |
env->reserve = (uint64_t)T0;
|
|
| 555 | 555 |
} |
| 556 | 556 |
RETURN(); |
| 557 | 557 |
} |
| ... | ... | |
| 563 | 563 |
do_raise_exception(EXCP_ALIGN); |
| 564 | 564 |
} else {
|
| 565 | 565 |
T1 = glue(ld32r, MEMSUFFIX)((uint32_t)T0); |
| 566 |
regs->reserve = (uint32_t)T0;
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|
| 566 |
env->reserve = (uint32_t)T0;
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|
| 567 | 567 |
} |
| 568 | 568 |
RETURN(); |
| 569 | 569 |
} |
| ... | ... | |
| 575 | 575 |
do_raise_exception(EXCP_ALIGN); |
| 576 | 576 |
} else {
|
| 577 | 577 |
T1 = glue(ld32r, MEMSUFFIX)((uint64_t)T0); |
| 578 |
regs->reserve = (uint64_t)T0;
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|
| 578 |
env->reserve = (uint64_t)T0;
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|
| 579 | 579 |
} |
| 580 | 580 |
RETURN(); |
| 581 | 581 |
} |
| ... | ... | |
| 586 | 586 |
do_raise_exception(EXCP_ALIGN); |
| 587 | 587 |
} else {
|
| 588 | 588 |
T1 = glue(ld64r, MEMSUFFIX)((uint32_t)T0); |
| 589 |
regs->reserve = (uint32_t)T0;
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|
| 589 |
env->reserve = (uint32_t)T0;
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|
| 590 | 590 |
} |
| 591 | 591 |
RETURN(); |
| 592 | 592 |
} |
| ... | ... | |
| 597 | 597 |
do_raise_exception(EXCP_ALIGN); |
| 598 | 598 |
} else {
|
| 599 | 599 |
T1 = glue(ld64r, MEMSUFFIX)((uint64_t)T0); |
| 600 |
regs->reserve = (uint64_t)T0;
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|
| 600 |
env->reserve = (uint64_t)T0;
|
|
| 601 | 601 |
} |
| 602 | 602 |
RETURN(); |
| 603 | 603 |
} |
| ... | ... | |
| 609 | 609 |
if (unlikely(T0 & 0x03)) {
|
| 610 | 610 |
do_raise_exception(EXCP_ALIGN); |
| 611 | 611 |
} else {
|
| 612 |
if (unlikely(regs->reserve != (uint32_t)T0)) {
|
|
| 612 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
|
| 613 | 613 |
env->crf[0] = xer_ov; |
| 614 | 614 |
} else {
|
| 615 | 615 |
glue(stl, MEMSUFFIX)((uint32_t)T0, T1); |
| 616 | 616 |
env->crf[0] = xer_ov | 0x02; |
| 617 | 617 |
} |
| 618 | 618 |
} |
| 619 |
regs->reserve = -1;
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|
| 619 |
env->reserve = -1;
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|
| 620 | 620 |
RETURN(); |
| 621 | 621 |
} |
| 622 | 622 |
|
| ... | ... | |
| 626 | 626 |
if (unlikely(T0 & 0x03)) {
|
| 627 | 627 |
do_raise_exception(EXCP_ALIGN); |
| 628 | 628 |
} else {
|
| 629 |
if (unlikely(regs->reserve != (uint64_t)T0)) {
|
|
| 629 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
|
| 630 | 630 |
env->crf[0] = xer_ov; |
| 631 | 631 |
} else {
|
| 632 | 632 |
glue(stl, MEMSUFFIX)((uint64_t)T0, T1); |
| 633 | 633 |
env->crf[0] = xer_ov | 0x02; |
| 634 | 634 |
} |
| 635 | 635 |
} |
| 636 |
regs->reserve = -1;
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|
| 636 |
env->reserve = -1;
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|
| 637 | 637 |
RETURN(); |
| 638 | 638 |
} |
| 639 | 639 |
|
| ... | ... | |
| 642 | 642 |
if (unlikely(T0 & 0x03)) {
|
| 643 | 643 |
do_raise_exception(EXCP_ALIGN); |
| 644 | 644 |
} else {
|
| 645 |
if (unlikely(regs->reserve != (uint32_t)T0)) {
|
|
| 645 |
if (unlikely(env->reserve != (uint32_t)T0)) {
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|
| 646 | 646 |
env->crf[0] = xer_ov; |
| 647 | 647 |
} else {
|
| 648 | 648 |
glue(stq, MEMSUFFIX)((uint32_t)T0, T1); |
| 649 | 649 |
env->crf[0] = xer_ov | 0x02; |
| 650 | 650 |
} |
| 651 | 651 |
} |
| 652 |
regs->reserve = -1;
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|
| 652 |
env->reserve = -1;
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|
| 653 | 653 |
RETURN(); |
| 654 | 654 |
} |
| 655 | 655 |
|
| ... | ... | |
| 658 | 658 |
if (unlikely(T0 & 0x03)) {
|
| 659 | 659 |
do_raise_exception(EXCP_ALIGN); |
| 660 | 660 |
} else {
|
| 661 |
if (unlikely(regs->reserve != (uint64_t)T0)) {
|
|
| 661 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
|
| 662 | 662 |
env->crf[0] = xer_ov; |
| 663 | 663 |
} else {
|
| 664 | 664 |
glue(stq, MEMSUFFIX)((uint64_t)T0, T1); |
| 665 | 665 |
env->crf[0] = xer_ov | 0x02; |
| 666 | 666 |
} |
| 667 | 667 |
} |
| 668 |
regs->reserve = -1;
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|
| 668 |
env->reserve = -1;
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|
| 669 | 669 |
RETURN(); |
| 670 | 670 |
} |
| 671 | 671 |
#endif |
| ... | ... | |
| 675 | 675 |
if (unlikely(T0 & 0x03)) {
|
| 676 | 676 |
do_raise_exception(EXCP_ALIGN); |
| 677 | 677 |
} else {
|
| 678 |
if (unlikely(regs->reserve != (uint32_t)T0)) {
|
|
| 678 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
|
| 679 | 679 |
env->crf[0] = xer_ov; |
| 680 | 680 |
} else {
|
| 681 | 681 |
glue(st32r, MEMSUFFIX)((uint32_t)T0, T1); |
| 682 | 682 |
env->crf[0] = xer_ov | 0x02; |
| 683 | 683 |
} |
| 684 | 684 |
} |
| 685 |
regs->reserve = -1;
|
|
| 685 |
env->reserve = -1;
|
|
| 686 | 686 |
RETURN(); |
| 687 | 687 |
} |
| 688 | 688 |
|
| ... | ... | |
| 692 | 692 |
if (unlikely(T0 & 0x03)) {
|
| 693 | 693 |
do_raise_exception(EXCP_ALIGN); |
| 694 | 694 |
} else {
|
| 695 |
if (unlikely(regs->reserve != (uint64_t)T0)) {
|
|
| 695 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
|
| 696 | 696 |
env->crf[0] = xer_ov; |
| 697 | 697 |
} else {
|
| 698 | 698 |
glue(st32r, MEMSUFFIX)((uint64_t)T0, T1); |
| 699 | 699 |
env->crf[0] = xer_ov | 0x02; |
| 700 | 700 |
} |
| 701 | 701 |
} |
| 702 |
regs->reserve = -1;
|
|
| 702 |
env->reserve = -1;
|
|
| 703 | 703 |
RETURN(); |
| 704 | 704 |
} |
| 705 | 705 |
|
| ... | ... | |
| 708 | 708 |
if (unlikely(T0 & 0x03)) {
|
| 709 | 709 |
do_raise_exception(EXCP_ALIGN); |
| 710 | 710 |
} else {
|
| 711 |
if (unlikely(regs->reserve != (uint32_t)T0)) {
|
|
| 711 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
|
| 712 | 712 |
env->crf[0] = xer_ov; |
| 713 | 713 |
} else {
|
| 714 | 714 |
glue(st64r, MEMSUFFIX)((uint32_t)T0, T1); |
| 715 | 715 |
env->crf[0] = xer_ov | 0x02; |
| 716 | 716 |
} |
| 717 | 717 |
} |
| 718 |
regs->reserve = -1;
|
|
| 718 |
env->reserve = -1;
|
|
| 719 | 719 |
RETURN(); |
| 720 | 720 |
} |
| 721 | 721 |
|
| ... | ... | |
| 724 | 724 |
if (unlikely(T0 & 0x03)) {
|
| 725 | 725 |
do_raise_exception(EXCP_ALIGN); |
| 726 | 726 |
} else {
|
| 727 |
if (unlikely(regs->reserve != (uint64_t)T0)) {
|
|
| 727 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
|
| 728 | 728 |
env->crf[0] = xer_ov; |
| 729 | 729 |
} else {
|
| 730 | 730 |
glue(st64r, MEMSUFFIX)((uint64_t)T0, T1); |
| 731 | 731 |
env->crf[0] = xer_ov | 0x02; |
| 732 | 732 |
} |
| 733 | 733 |
} |
| 734 |
regs->reserve = -1;
|
|
| 734 |
env->reserve = -1;
|
|
| 735 | 735 |
RETURN(); |
| 736 | 736 |
} |
| 737 | 737 |
#endif |
| ... | ... | |
| 1095 | 1095 |
} |
| 1096 | 1096 |
PPC_SPE_ST_OP(wwo, spe_stwwo); |
| 1097 | 1097 |
static inline void glue(spe_stwwo_le, MEMSUFFIX) (target_ulong EA, |
| 1098 |
uint64_t data) |
|
| 1098 |
uint64_t data)
|
|
| 1099 | 1099 |
{
|
| 1100 | 1100 |
glue(st32r, MEMSUFFIX)(EA, data); |
| 1101 | 1101 |
} |
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