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1 | 05c2a3e7 | bellard | /*
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2 | 05c2a3e7 | bellard | * KQEMU header
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3 | 05c2a3e7 | bellard | *
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4 | 05c2a3e7 | bellard | * Copyright (c) 2004-2006 Fabrice Bellard
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5 | 05c2a3e7 | bellard | *
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6 | 05c2a3e7 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 05c2a3e7 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 05c2a3e7 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 05c2a3e7 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 05c2a3e7 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 05c2a3e7 | bellard | * furnished to do so, subject to the following conditions:
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12 | 05c2a3e7 | bellard | *
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13 | 05c2a3e7 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 05c2a3e7 | bellard | * all copies or substantial portions of the Software.
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15 | 05c2a3e7 | bellard | *
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16 | 05c2a3e7 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 05c2a3e7 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 05c2a3e7 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 05c2a3e7 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 05c2a3e7 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 05c2a3e7 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 05c2a3e7 | bellard | * THE SOFTWARE.
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23 | 05c2a3e7 | bellard | */
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24 | 05c2a3e7 | bellard | #ifndef KQEMU_H
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25 | 05c2a3e7 | bellard | #define KQEMU_H
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26 | 05c2a3e7 | bellard | |
27 | 05c2a3e7 | bellard | #define KQEMU_VERSION 0x010300 |
28 | 05c2a3e7 | bellard | |
29 | 05c2a3e7 | bellard | struct kqemu_segment_cache {
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30 | 05c2a3e7 | bellard | uint32_t selector; |
31 | 05c2a3e7 | bellard | unsigned long base; |
32 | 05c2a3e7 | bellard | uint32_t limit; |
33 | 05c2a3e7 | bellard | uint32_t flags; |
34 | 05c2a3e7 | bellard | }; |
35 | 05c2a3e7 | bellard | |
36 | 05c2a3e7 | bellard | struct kqemu_cpu_state {
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37 | 05c2a3e7 | bellard | #ifdef __x86_64__
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38 | 05c2a3e7 | bellard | unsigned long regs[16]; |
39 | 05c2a3e7 | bellard | #else
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40 | 05c2a3e7 | bellard | unsigned long regs[8]; |
41 | 05c2a3e7 | bellard | #endif
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42 | 05c2a3e7 | bellard | unsigned long eip; |
43 | 05c2a3e7 | bellard | unsigned long eflags; |
44 | 05c2a3e7 | bellard | |
45 | 05c2a3e7 | bellard | uint32_t dummy0, dummy1, dumm2, dummy3, dummy4; |
46 | 05c2a3e7 | bellard | |
47 | 05c2a3e7 | bellard | struct kqemu_segment_cache segs[6]; /* selector values */ |
48 | 05c2a3e7 | bellard | struct kqemu_segment_cache ldt;
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49 | 05c2a3e7 | bellard | struct kqemu_segment_cache tr;
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50 | 05c2a3e7 | bellard | struct kqemu_segment_cache gdt; /* only base and limit are used */ |
51 | 05c2a3e7 | bellard | struct kqemu_segment_cache idt; /* only base and limit are used */ |
52 | 05c2a3e7 | bellard | |
53 | 05c2a3e7 | bellard | unsigned long cr0; |
54 | 05c2a3e7 | bellard | unsigned long dummy5; |
55 | 05c2a3e7 | bellard | unsigned long cr2; |
56 | 05c2a3e7 | bellard | unsigned long cr3; |
57 | 05c2a3e7 | bellard | unsigned long cr4; |
58 | 05c2a3e7 | bellard | uint32_t a20_mask; |
59 | 05c2a3e7 | bellard | |
60 | 05c2a3e7 | bellard | /* sysenter registers */
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61 | 05c2a3e7 | bellard | uint32_t sysenter_cs; |
62 | 05c2a3e7 | bellard | uint32_t sysenter_esp; |
63 | 05c2a3e7 | bellard | uint32_t sysenter_eip; |
64 | 05c2a3e7 | bellard | uint64_t efer __attribute__((aligned(8)));
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65 | 05c2a3e7 | bellard | uint64_t star; |
66 | 05c2a3e7 | bellard | #ifdef __x86_64__
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67 | 05c2a3e7 | bellard | unsigned long lstar; |
68 | 05c2a3e7 | bellard | unsigned long cstar; |
69 | 05c2a3e7 | bellard | unsigned long fmask; |
70 | 05c2a3e7 | bellard | unsigned long kernelgsbase; |
71 | 05c2a3e7 | bellard | #endif
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72 | 05c2a3e7 | bellard | uint64_t tsc_offset; |
73 | 05c2a3e7 | bellard | |
74 | 05c2a3e7 | bellard | unsigned long dr0; |
75 | 05c2a3e7 | bellard | unsigned long dr1; |
76 | 05c2a3e7 | bellard | unsigned long dr2; |
77 | 05c2a3e7 | bellard | unsigned long dr3; |
78 | 05c2a3e7 | bellard | unsigned long dr6; |
79 | 05c2a3e7 | bellard | unsigned long dr7; |
80 | 05c2a3e7 | bellard | |
81 | 05c2a3e7 | bellard | uint8_t cpl; |
82 | 05c2a3e7 | bellard | uint8_t user_only; |
83 | 05c2a3e7 | bellard | |
84 | 05c2a3e7 | bellard | uint32_t error_code; /* error_code when exiting with an exception */
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85 | 05c2a3e7 | bellard | unsigned long next_eip; /* next eip value when exiting with an interrupt */ |
86 | 05c2a3e7 | bellard | unsigned int nb_pages_to_flush; /* number of pages to flush, |
87 | 05c2a3e7 | bellard | KQEMU_FLUSH_ALL means full flush */
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88 | 05c2a3e7 | bellard | #define KQEMU_MAX_PAGES_TO_FLUSH 512 |
89 | 05c2a3e7 | bellard | #define KQEMU_FLUSH_ALL (KQEMU_MAX_PAGES_TO_FLUSH + 1) |
90 | 05c2a3e7 | bellard | |
91 | 05c2a3e7 | bellard | long retval;
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92 | 05c2a3e7 | bellard | |
93 | 05c2a3e7 | bellard | /* number of ram_dirty entries to update */
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94 | 05c2a3e7 | bellard | unsigned int nb_ram_pages_to_update; |
95 | 05c2a3e7 | bellard | #define KQEMU_MAX_RAM_PAGES_TO_UPDATE 512 |
96 | 05c2a3e7 | bellard | #define KQEMU_RAM_PAGES_UPDATE_ALL (KQEMU_MAX_RAM_PAGES_TO_UPDATE + 1) |
97 | 05c2a3e7 | bellard | |
98 | 05c2a3e7 | bellard | #define KQEMU_MAX_MODIFIED_RAM_PAGES 512 |
99 | 05c2a3e7 | bellard | unsigned int nb_modified_ram_pages; |
100 | 05c2a3e7 | bellard | }; |
101 | 05c2a3e7 | bellard | |
102 | 05c2a3e7 | bellard | struct kqemu_init {
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103 | 05c2a3e7 | bellard | uint8_t *ram_base; /* must be page aligned */
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104 | 05c2a3e7 | bellard | unsigned long ram_size; /* must be multiple of 4 KB */ |
105 | 05c2a3e7 | bellard | uint8_t *ram_dirty; /* must be page aligned */
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106 | 05c2a3e7 | bellard | uint32_t **phys_to_ram_map; /* must be page aligned */
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107 | 05c2a3e7 | bellard | unsigned long *pages_to_flush; /* must be page aligned */ |
108 | 05c2a3e7 | bellard | unsigned long *ram_pages_to_update; /* must be page aligned */ |
109 | 05c2a3e7 | bellard | unsigned long *modified_ram_pages; /* must be page aligned */ |
110 | 05c2a3e7 | bellard | }; |
111 | 05c2a3e7 | bellard | |
112 | 05c2a3e7 | bellard | #define KQEMU_RET_ABORT (-1) |
113 | 05c2a3e7 | bellard | #define KQEMU_RET_EXCEPTION 0x0000 /* 8 low order bit are the exception */ |
114 | 05c2a3e7 | bellard | #define KQEMU_RET_INT 0x0100 /* 8 low order bit are the interrupt */ |
115 | 05c2a3e7 | bellard | #define KQEMU_RET_SOFTMMU 0x0200 /* emulation needed (I/O or |
116 | 05c2a3e7 | bellard | unsupported INSN) */
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117 | 05c2a3e7 | bellard | #define KQEMU_RET_INTR 0x0201 /* interrupted by a signal */ |
118 | 05c2a3e7 | bellard | #define KQEMU_RET_SYSCALL 0x0300 /* syscall insn */ |
119 | 05c2a3e7 | bellard | |
120 | 05c2a3e7 | bellard | #ifdef _WIN32
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121 | 05c2a3e7 | bellard | #define KQEMU_EXEC CTL_CODE(FILE_DEVICE_UNKNOWN, 1, METHOD_BUFFERED, FILE_READ_ACCESS | FILE_WRITE_ACCESS) |
122 | 05c2a3e7 | bellard | #define KQEMU_INIT CTL_CODE(FILE_DEVICE_UNKNOWN, 2, METHOD_BUFFERED, FILE_WRITE_ACCESS) |
123 | 05c2a3e7 | bellard | #define KQEMU_GET_VERSION CTL_CODE(FILE_DEVICE_UNKNOWN, 3, METHOD_BUFFERED, FILE_READ_ACCESS) |
124 | 05c2a3e7 | bellard | #define KQEMU_MODIFY_RAM_PAGES CTL_CODE(FILE_DEVICE_UNKNOWN, 4, METHOD_BUFFERED, FILE_WRITE_ACCESS) |
125 | 05c2a3e7 | bellard | #else
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126 | 05c2a3e7 | bellard | #define KQEMU_EXEC _IOWR('q', 1, struct kqemu_cpu_state) |
127 | 05c2a3e7 | bellard | #define KQEMU_INIT _IOW('q', 2, struct kqemu_init) |
128 | 05c2a3e7 | bellard | #define KQEMU_GET_VERSION _IOR('q', 3, int) |
129 | 05c2a3e7 | bellard | #define KQEMU_MODIFY_RAM_PAGES _IOW('q', 4, int) |
130 | 05c2a3e7 | bellard | #endif
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131 | 05c2a3e7 | bellard | |
132 | 05c2a3e7 | bellard | #endif /* KQEMU_H */ |