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1 | 00406dff | bellard | /*
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2 | 00406dff | bellard | NetWinder Floating Point Emulator
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3 | 00406dff | bellard | (c) Rebel.COM, 1998,1999
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4 | 00406dff | bellard | |
5 | 00406dff | bellard | Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
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6 | 00406dff | bellard | |
7 | 00406dff | bellard | This program is free software; you can redistribute it and/or modify
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8 | 00406dff | bellard | it under the terms of the GNU General Public License as published by
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9 | 00406dff | bellard | the Free Software Foundation; either version 2 of the License, or
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10 | 00406dff | bellard | (at your option) any later version.
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11 | 00406dff | bellard | |
12 | 00406dff | bellard | This program is distributed in the hope that it will be useful,
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13 | 00406dff | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 00406dff | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 00406dff | bellard | GNU General Public License for more details.
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16 | 00406dff | bellard | |
17 | 00406dff | bellard | You should have received a copy of the GNU General Public License
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18 | 00406dff | bellard | along with this program; if not, write to the Free Software
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19 | 00406dff | bellard | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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20 | 00406dff | bellard | */
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21 | 00406dff | bellard | |
22 | 00406dff | bellard | #ifndef __FPOPCODE_H__
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23 | 00406dff | bellard | #define __FPOPCODE_H__
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24 | 00406dff | bellard | |
25 | 00406dff | bellard | /*
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26 | 00406dff | bellard | ARM Floating Point Instruction Classes
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27 | 00406dff | bellard | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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28 | 00406dff | bellard | |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
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29 | 00406dff | bellard | |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
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30 | 00406dff | bellard | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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31 | 00406dff | bellard | |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
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32 | 00406dff | bellard | |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
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33 | 00406dff | bellard | |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
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34 | 00406dff | bellard | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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35 | 00406dff | bellard | |
36 | 00406dff | bellard | CPDT data transfer instructions
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37 | 00406dff | bellard | LDF, STF, LFM, SFM
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38 | 00406dff | bellard |
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39 | 00406dff | bellard | CPDO dyadic arithmetic instructions
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40 | 00406dff | bellard | ADF, MUF, SUF, RSF, DVF, RDF,
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41 | 00406dff | bellard | POW, RPW, RMF, FML, FDV, FRD, POL
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42 | 00406dff | bellard | |
43 | 00406dff | bellard | CPDO monadic arithmetic instructions
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44 | 00406dff | bellard | MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
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45 | 00406dff | bellard | SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
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46 | 00406dff | bellard |
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47 | 00406dff | bellard | CPRT joint arithmetic/data transfer instructions
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48 | 00406dff | bellard | FIX (arithmetic followed by load/store)
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49 | 00406dff | bellard | FLT (load/store followed by arithmetic)
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50 | 00406dff | bellard | CMF, CNF CMFE, CNFE (comparisons)
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51 | 00406dff | bellard | WFS, RFS (write/read floating point status register)
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52 | 00406dff | bellard | WFC, RFC (write/read floating point control register)
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53 | 00406dff | bellard | |
54 | 00406dff | bellard | cond condition codes
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55 | 00406dff | bellard | P pre/post index bit: 0 = postindex, 1 = preindex
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56 | 00406dff | bellard | U up/down bit: 0 = stack grows down, 1 = stack grows up
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57 | 00406dff | bellard | W write back bit: 1 = update base register (Rn)
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58 | 00406dff | bellard | L load/store bit: 0 = store, 1 = load
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59 | 00406dff | bellard | Rn base register
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60 | 00406dff | bellard | Rd destination/source register
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61 | 00406dff | bellard | Fd floating point destination register
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62 | 00406dff | bellard | Fn floating point source register
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63 | 00406dff | bellard | Fm floating point source register or floating point constant
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64 | 00406dff | bellard | |
65 | 00406dff | bellard | uv transfer length (TABLE 1)
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66 | 00406dff | bellard | wx register count (TABLE 2)
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67 | 00406dff | bellard | abcd arithmetic opcode (TABLES 3 & 4)
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68 | 00406dff | bellard | ef destination size (rounding precision) (TABLE 5)
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69 | 00406dff | bellard | gh rounding mode (TABLE 6)
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70 | 00406dff | bellard | j dyadic/monadic bit: 0 = dyadic, 1 = monadic
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71 | 00406dff | bellard | i constant bit: 1 = constant (TABLE 6)
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72 | 00406dff | bellard | */
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73 | 00406dff | bellard | |
74 | 00406dff | bellard | /*
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75 | 00406dff | bellard | TABLE 1
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76 | 00406dff | bellard | +-------------------------+---+---+---------+---------+
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77 | 00406dff | bellard | | Precision | u | v | FPSR.EP | length |
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78 | 00406dff | bellard | +-------------------------+---+---+---------+---------+
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79 | 00406dff | bellard | | Single | 0 ? 0 | x | 1 words |
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80 | 00406dff | bellard | | Double | 1 ? 1 | x | 2 words |
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81 | 00406dff | bellard | | Extended | 1 ? 1 | x | 3 words |
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82 | 00406dff | bellard | | Packed decimal | 1 ? 1 | 0 | 3 words |
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83 | 00406dff | bellard | | Expanded packed decimal | 1 ? 1 | 1 | 4 words |
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84 | 00406dff | bellard | +-------------------------+---+---+---------+---------+
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85 | 00406dff | bellard | Note: x = don't care
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86 | 00406dff | bellard | */
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87 | 00406dff | bellard | |
88 | 00406dff | bellard | /*
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89 | 00406dff | bellard | TABLE 2
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90 | 00406dff | bellard | +---+---+---------------------------------+
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91 | 00406dff | bellard | | w | x | Number of registers to transfer |
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92 | 00406dff | bellard | +---+---+---------------------------------+
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93 | 00406dff | bellard | | 0 ? 1 | 1 |
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94 | 00406dff | bellard | | 1 ? 0 | 2 |
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95 | 00406dff | bellard | | 1 ? 1 | 3 |
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96 | 00406dff | bellard | | 0 ? 0 | 4 |
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97 | 00406dff | bellard | +---+---+---------------------------------+
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98 | 00406dff | bellard | */
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99 | 00406dff | bellard | |
100 | 00406dff | bellard | /*
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101 | 00406dff | bellard | TABLE 3: Dyadic Floating Point Opcodes
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102 | 00406dff | bellard | +---+---+---+---+----------+-----------------------+-----------------------+
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103 | 00406dff | bellard | | a | b | c | d | Mnemonic | Description | Operation |
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104 | 00406dff | bellard | +---+---+---+---+----------+-----------------------+-----------------------+
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105 | 00406dff | bellard | | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
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106 | 00406dff | bellard | | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
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107 | 00406dff | bellard | | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
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108 | 00406dff | bellard | | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
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109 | 00406dff | bellard | | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
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110 | 00406dff | bellard | | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
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111 | 00406dff | bellard | | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
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112 | 00406dff | bellard | | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
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113 | 00406dff | bellard | | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
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114 | 00406dff | bellard | | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
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115 | 00406dff | bellard | | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
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116 | 00406dff | bellard | | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
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117 | 00406dff | bellard | | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
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118 | 00406dff | bellard | | 1 | 1 | 0 | 1 | | undefined instruction | trap |
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119 | 00406dff | bellard | | 1 | 1 | 1 | 0 | | undefined instruction | trap |
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120 | 00406dff | bellard | | 1 | 1 | 1 | 1 | | undefined instruction | trap |
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121 | 00406dff | bellard | +---+---+---+---+----------+-----------------------+-----------------------+
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122 | 00406dff | bellard | Note: POW, RPW, POL are deprecated, and are available for backwards
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123 | 00406dff | bellard | compatibility only.
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124 | 00406dff | bellard | */
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125 | 00406dff | bellard | |
126 | 00406dff | bellard | /*
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127 | 00406dff | bellard | TABLE 4: Monadic Floating Point Opcodes
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128 | 00406dff | bellard | +---+---+---+---+----------+-----------------------+-----------------------+
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129 | 00406dff | bellard | | a | b | c | d | Mnemonic | Description | Operation |
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130 | 00406dff | bellard | +---+---+---+---+----------+-----------------------+-----------------------+
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131 | 00406dff | bellard | | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
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132 | 00406dff | bellard | | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
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133 | 00406dff | bellard | | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
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134 | 00406dff | bellard | | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
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135 | 00406dff | bellard | | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
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136 | 00406dff | bellard | | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
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137 | 00406dff | bellard | | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
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138 | 00406dff | bellard | | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
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139 | 00406dff | bellard | | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
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140 | 00406dff | bellard | | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
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141 | 00406dff | bellard | | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
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142 | 00406dff | bellard | | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
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143 | 00406dff | bellard | | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
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144 | 00406dff | bellard | | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
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145 | 00406dff | bellard | | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
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146 | 00406dff | bellard | | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
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147 | 00406dff | bellard | +---+---+---+---+----------+-----------------------+-----------------------+
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148 | 00406dff | bellard | Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
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149 | 00406dff | bellard | available for backwards compatibility only.
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150 | 00406dff | bellard | */
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151 | 00406dff | bellard | |
152 | 00406dff | bellard | /*
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153 | 00406dff | bellard | TABLE 5
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154 | 00406dff | bellard | +-------------------------+---+---+
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155 | 00406dff | bellard | | Rounding Precision | e | f |
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156 | 00406dff | bellard | +-------------------------+---+---+
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157 | 00406dff | bellard | | IEEE Single precision | 0 ? 0 |
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158 | 00406dff | bellard | | IEEE Double precision | 0 ? 1 |
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159 | 00406dff | bellard | | IEEE Extended precision | 1 ? 0 |
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160 | 00406dff | bellard | | undefined (trap) | 1 ? 1 |
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161 | 00406dff | bellard | +-------------------------+---+---+
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162 | 00406dff | bellard | */
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163 | 00406dff | bellard | |
164 | 00406dff | bellard | /*
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165 | 00406dff | bellard | TABLE 5
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166 | 00406dff | bellard | +---------------------------------+---+---+
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167 | 00406dff | bellard | | Rounding Mode | g | h |
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168 | 00406dff | bellard | +---------------------------------+---+---+
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169 | 00406dff | bellard | | Round to nearest (default) | 0 ? 0 |
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170 | 00406dff | bellard | | Round toward plus infinity | 0 ? 1 |
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171 | 00406dff | bellard | | Round toward negative infinity | 1 ? 0 |
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172 | 00406dff | bellard | | Round toward zero | 1 ? 1 |
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173 | 00406dff | bellard | +---------------------------------+---+---+
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174 | 00406dff | bellard | */
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175 | 00406dff | bellard | |
176 | 00406dff | bellard | /*
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177 | 00406dff | bellard | ===
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178 | 00406dff | bellard | === Definitions for load and store instructions
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179 | 00406dff | bellard | ===
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180 | 00406dff | bellard | */
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181 | 00406dff | bellard | |
182 | 00406dff | bellard | /* bit masks */
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183 | 00406dff | bellard | #define BIT_PREINDEX 0x01000000 |
184 | 00406dff | bellard | #define BIT_UP 0x00800000 |
185 | 00406dff | bellard | #define BIT_WRITE_BACK 0x00200000 |
186 | 00406dff | bellard | #define BIT_LOAD 0x00100000 |
187 | 00406dff | bellard | |
188 | 00406dff | bellard | /* masks for load/store */
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189 | 00406dff | bellard | #define MASK_CPDT 0x0c000000 /* data processing opcode */ |
190 | 00406dff | bellard | #define MASK_OFFSET 0x000000ff |
191 | 00406dff | bellard | #define MASK_TRANSFER_LENGTH 0x00408000 |
192 | 00406dff | bellard | #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
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193 | 00406dff | bellard | #define MASK_COPROCESSOR 0x00000f00 |
194 | 00406dff | bellard | |
195 | 00406dff | bellard | /* Tests for transfer length */
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196 | 00406dff | bellard | #define TRANSFER_SINGLE 0x00000000 |
197 | 00406dff | bellard | #define TRANSFER_DOUBLE 0x00008000 |
198 | 00406dff | bellard | #define TRANSFER_EXTENDED 0x00400000 |
199 | 00406dff | bellard | #define TRANSFER_PACKED MASK_TRANSFER_LENGTH
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200 | 00406dff | bellard | |
201 | 00406dff | bellard | /* Get the coprocessor number from the opcode. */
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202 | 00406dff | bellard | #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8) |
203 | 00406dff | bellard | |
204 | 00406dff | bellard | /* Get the offset from the opcode. */
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205 | 00406dff | bellard | #define getOffset(opcode) (opcode & MASK_OFFSET)
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206 | 00406dff | bellard | |
207 | 00406dff | bellard | /* Tests for specific data transfer load/store opcodes. */
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208 | 00406dff | bellard | #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
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209 | 00406dff | bellard | |
210 | 00406dff | bellard | #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
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211 | 00406dff | bellard | #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
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212 | 00406dff | bellard | |
213 | 00406dff | bellard | #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) |
214 | 00406dff | bellard | #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) |
215 | 00406dff | bellard | #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) |
216 | 00406dff | bellard | #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) |
217 | 00406dff | bellard | |
218 | 00406dff | bellard | #define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0) |
219 | 00406dff | bellard | #define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0) |
220 | 00406dff | bellard | #define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0) |
221 | 00406dff | bellard | #define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0) |
222 | 00406dff | bellard | #define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0) |
223 | 00406dff | bellard | #define LOAD(opcode) ((opcode & BIT_LOAD) != 0) |
224 | 00406dff | bellard | #define STORE(opcode) ((opcode & BIT_LOAD) == 0) |
225 | 00406dff | bellard | |
226 | 00406dff | bellard | /*
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227 | 00406dff | bellard | ===
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228 | 00406dff | bellard | === Definitions for arithmetic instructions
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229 | 00406dff | bellard | ===
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230 | 00406dff | bellard | */
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231 | 00406dff | bellard | /* bit masks */
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232 | 00406dff | bellard | #define BIT_MONADIC 0x00008000 |
233 | 00406dff | bellard | #define BIT_CONSTANT 0x00000008 |
234 | 00406dff | bellard | |
235 | 00406dff | bellard | #define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0) |
236 | 00406dff | bellard | #define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0) |
237 | 00406dff | bellard | |
238 | 00406dff | bellard | /* instruction identification masks */
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239 | 00406dff | bellard | #define MASK_CPDO 0x0e000000 /* arithmetic opcode */ |
240 | 00406dff | bellard | #define MASK_ARITHMETIC_OPCODE 0x00f08000 |
241 | 00406dff | bellard | #define MASK_DESTINATION_SIZE 0x00080080 |
242 | 00406dff | bellard | |
243 | 00406dff | bellard | /* dyadic arithmetic opcodes. */
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244 | 00406dff | bellard | #define ADF_CODE 0x00000000 |
245 | 00406dff | bellard | #define MUF_CODE 0x00100000 |
246 | 00406dff | bellard | #define SUF_CODE 0x00200000 |
247 | 00406dff | bellard | #define RSF_CODE 0x00300000 |
248 | 00406dff | bellard | #define DVF_CODE 0x00400000 |
249 | 00406dff | bellard | #define RDF_CODE 0x00500000 |
250 | 00406dff | bellard | #define POW_CODE 0x00600000 |
251 | 00406dff | bellard | #define RPW_CODE 0x00700000 |
252 | 00406dff | bellard | #define RMF_CODE 0x00800000 |
253 | 00406dff | bellard | #define FML_CODE 0x00900000 |
254 | 00406dff | bellard | #define FDV_CODE 0x00a00000 |
255 | 00406dff | bellard | #define FRD_CODE 0x00b00000 |
256 | 00406dff | bellard | #define POL_CODE 0x00c00000 |
257 | 00406dff | bellard | /* 0x00d00000 is an invalid dyadic arithmetic opcode */
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258 | 00406dff | bellard | /* 0x00e00000 is an invalid dyadic arithmetic opcode */
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259 | 00406dff | bellard | /* 0x00f00000 is an invalid dyadic arithmetic opcode */
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260 | 00406dff | bellard | |
261 | 00406dff | bellard | /* monadic arithmetic opcodes. */
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262 | 00406dff | bellard | #define MVF_CODE 0x00008000 |
263 | 00406dff | bellard | #define MNF_CODE 0x00108000 |
264 | 00406dff | bellard | #define ABS_CODE 0x00208000 |
265 | 00406dff | bellard | #define RND_CODE 0x00308000 |
266 | 00406dff | bellard | #define SQT_CODE 0x00408000 |
267 | 00406dff | bellard | #define LOG_CODE 0x00508000 |
268 | 00406dff | bellard | #define LGN_CODE 0x00608000 |
269 | 00406dff | bellard | #define EXP_CODE 0x00708000 |
270 | 00406dff | bellard | #define SIN_CODE 0x00808000 |
271 | 00406dff | bellard | #define COS_CODE 0x00908000 |
272 | 00406dff | bellard | #define TAN_CODE 0x00a08000 |
273 | 00406dff | bellard | #define ASN_CODE 0x00b08000 |
274 | 00406dff | bellard | #define ACS_CODE 0x00c08000 |
275 | 00406dff | bellard | #define ATN_CODE 0x00d08000 |
276 | 00406dff | bellard | #define URD_CODE 0x00e08000 |
277 | 00406dff | bellard | #define NRM_CODE 0x00f08000 |
278 | 00406dff | bellard | |
279 | 00406dff | bellard | /*
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280 | 00406dff | bellard | ===
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281 | 00406dff | bellard | === Definitions for register transfer and comparison instructions
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282 | 00406dff | bellard | ===
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283 | 00406dff | bellard | */
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284 | 00406dff | bellard | |
285 | 00406dff | bellard | #define MASK_CPRT 0x0e000010 /* register transfer opcode */ |
286 | 00406dff | bellard | #define MASK_CPRT_CODE 0x00f00000 |
287 | 00406dff | bellard | #define FLT_CODE 0x00000000 |
288 | 00406dff | bellard | #define FIX_CODE 0x00100000 |
289 | 00406dff | bellard | #define WFS_CODE 0x00200000 |
290 | 00406dff | bellard | #define RFS_CODE 0x00300000 |
291 | 00406dff | bellard | #define WFC_CODE 0x00400000 |
292 | 00406dff | bellard | #define RFC_CODE 0x00500000 |
293 | 00406dff | bellard | #define CMF_CODE 0x00900000 |
294 | 00406dff | bellard | #define CNF_CODE 0x00b00000 |
295 | 00406dff | bellard | #define CMFE_CODE 0x00d00000 |
296 | 00406dff | bellard | #define CNFE_CODE 0x00f00000 |
297 | 00406dff | bellard | |
298 | 00406dff | bellard | /*
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299 | 00406dff | bellard | ===
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300 | 00406dff | bellard | === Common definitions
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301 | 00406dff | bellard | ===
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302 | 00406dff | bellard | */
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303 | 00406dff | bellard | |
304 | 00406dff | bellard | /* register masks */
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305 | 00406dff | bellard | #define MASK_Rd 0x0000f000 |
306 | 00406dff | bellard | #define MASK_Rn 0x000f0000 |
307 | 00406dff | bellard | #define MASK_Fd 0x00007000 |
308 | 00406dff | bellard | #define MASK_Fm 0x00000007 |
309 | 00406dff | bellard | #define MASK_Fn 0x00070000 |
310 | 00406dff | bellard | |
311 | 00406dff | bellard | /* condition code masks */
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312 | 00406dff | bellard | #define CC_MASK 0xf0000000 |
313 | 00406dff | bellard | #define CC_NEGATIVE 0x80000000 |
314 | 00406dff | bellard | #define CC_ZERO 0x40000000 |
315 | 00406dff | bellard | #define CC_CARRY 0x20000000 |
316 | 00406dff | bellard | #define CC_OVERFLOW 0x10000000 |
317 | 00406dff | bellard | #define CC_EQ 0x00000000 |
318 | 00406dff | bellard | #define CC_NE 0x10000000 |
319 | 00406dff | bellard | #define CC_CS 0x20000000 |
320 | 00406dff | bellard | #define CC_HS CC_CS
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321 | 00406dff | bellard | #define CC_CC 0x30000000 |
322 | 00406dff | bellard | #define CC_LO CC_CC
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323 | 00406dff | bellard | #define CC_MI 0x40000000 |
324 | 00406dff | bellard | #define CC_PL 0x50000000 |
325 | 00406dff | bellard | #define CC_VS 0x60000000 |
326 | 00406dff | bellard | #define CC_VC 0x70000000 |
327 | 00406dff | bellard | #define CC_HI 0x80000000 |
328 | 00406dff | bellard | #define CC_LS 0x90000000 |
329 | 00406dff | bellard | #define CC_GE 0xa0000000 |
330 | 00406dff | bellard | #define CC_LT 0xb0000000 |
331 | 00406dff | bellard | #define CC_GT 0xc0000000 |
332 | 00406dff | bellard | #define CC_LE 0xd0000000 |
333 | 00406dff | bellard | #define CC_AL 0xe0000000 |
334 | 00406dff | bellard | #define CC_NV 0xf0000000 |
335 | 00406dff | bellard | |
336 | 00406dff | bellard | /* rounding masks/values */
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337 | 00406dff | bellard | #define MASK_ROUNDING_MODE 0x00000060 |
338 | 00406dff | bellard | #define ROUND_TO_NEAREST 0x00000000 |
339 | 00406dff | bellard | #define ROUND_TO_PLUS_INFINITY 0x00000020 |
340 | 00406dff | bellard | #define ROUND_TO_MINUS_INFINITY 0x00000040 |
341 | 00406dff | bellard | #define ROUND_TO_ZERO 0x00000060 |
342 | 00406dff | bellard | |
343 | 00406dff | bellard | #define MASK_ROUNDING_PRECISION 0x00080080 |
344 | 00406dff | bellard | #define ROUND_SINGLE 0x00000000 |
345 | 00406dff | bellard | #define ROUND_DOUBLE 0x00000080 |
346 | 00406dff | bellard | #define ROUND_EXTENDED 0x00080000 |
347 | 00406dff | bellard | |
348 | 00406dff | bellard | /* Get the condition code from the opcode. */
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349 | 00406dff | bellard | #define getCondition(opcode) (opcode >> 28) |
350 | 00406dff | bellard | |
351 | 00406dff | bellard | /* Get the source register from the opcode. */
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352 | 00406dff | bellard | #define getRn(opcode) ((opcode & MASK_Rn) >> 16) |
353 | 00406dff | bellard | |
354 | 00406dff | bellard | /* Get the destination floating point register from the opcode. */
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355 | 00406dff | bellard | #define getFd(opcode) ((opcode & MASK_Fd) >> 12) |
356 | 00406dff | bellard | |
357 | 00406dff | bellard | /* Get the first source floating point register from the opcode. */
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358 | 00406dff | bellard | #define getFn(opcode) ((opcode & MASK_Fn) >> 16) |
359 | 00406dff | bellard | |
360 | 00406dff | bellard | /* Get the second source floating point register from the opcode. */
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361 | 00406dff | bellard | #define getFm(opcode) (opcode & MASK_Fm)
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362 | 00406dff | bellard | |
363 | 00406dff | bellard | /* Get the destination register from the opcode. */
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364 | 00406dff | bellard | #define getRd(opcode) ((opcode & MASK_Rd) >> 12) |
365 | 00406dff | bellard | |
366 | 00406dff | bellard | /* Get the rounding mode from the opcode. */
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367 | 00406dff | bellard | #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5) |
368 | 00406dff | bellard | |
369 | 00406dff | bellard | static inline const floatx80 getExtendedConstant(const unsigned int nIndex) |
370 | 00406dff | bellard | { |
371 | 00406dff | bellard | extern const floatx80 floatx80Constant[]; |
372 | 00406dff | bellard | return floatx80Constant[nIndex];
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373 | 00406dff | bellard | } |
374 | 00406dff | bellard | |
375 | 00406dff | bellard | static inline const float64 getDoubleConstant(const unsigned int nIndex) |
376 | 00406dff | bellard | { |
377 | 00406dff | bellard | extern const float64 float64Constant[]; |
378 | 00406dff | bellard | return float64Constant[nIndex];
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379 | 00406dff | bellard | } |
380 | 00406dff | bellard | |
381 | 00406dff | bellard | static inline const float32 getSingleConstant(const unsigned int nIndex) |
382 | 00406dff | bellard | { |
383 | 00406dff | bellard | extern const float32 float32Constant[]; |
384 | 00406dff | bellard | return float32Constant[nIndex];
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385 | 00406dff | bellard | } |
386 | 00406dff | bellard | |
387 | 00406dff | bellard | extern unsigned int getRegisterCount(const unsigned int opcode); |
388 | 00406dff | bellard | extern unsigned int getDestinationSize(const unsigned int opcode); |
389 | 00406dff | bellard | |
390 | 00406dff | bellard | #endif |