root / target-sh4 / helper.c @ 36bb244b
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | fdf9b3e8 | bellard | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <signal.h> |
26 | fdf9b3e8 | bellard | #include <assert.h> |
27 | fdf9b3e8 | bellard | |
28 | fdf9b3e8 | bellard | #include "cpu.h" |
29 | fdf9b3e8 | bellard | #include "exec-all.h" |
30 | fdf9b3e8 | bellard | |
31 | 355fb23d | pbrook | #if defined(CONFIG_USER_ONLY)
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32 | 355fb23d | pbrook | |
33 | 355fb23d | pbrook | void do_interrupt (CPUState *env)
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34 | 355fb23d | pbrook | { |
35 | 355fb23d | pbrook | env->exception_index = -1;
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36 | 355fb23d | pbrook | } |
37 | 355fb23d | pbrook | |
38 | 355fb23d | pbrook | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
39 | 355fb23d | pbrook | int is_user, int is_softmmu) |
40 | 355fb23d | pbrook | { |
41 | 355fb23d | pbrook | env->tea = address; |
42 | 355fb23d | pbrook | switch (rw) {
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43 | 355fb23d | pbrook | case 0: |
44 | 355fb23d | pbrook | env->exception_index = 0x0a0;
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45 | 355fb23d | pbrook | break;
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46 | 355fb23d | pbrook | case 1: |
47 | 355fb23d | pbrook | env->exception_index = 0x0c0;
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48 | 355fb23d | pbrook | break;
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49 | 355fb23d | pbrook | case 2: |
50 | 355fb23d | pbrook | env->exception_index = 0x0a0;
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51 | 355fb23d | pbrook | break;
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52 | 355fb23d | pbrook | } |
53 | 355fb23d | pbrook | return 1; |
54 | 355fb23d | pbrook | } |
55 | 355fb23d | pbrook | |
56 | 355fb23d | pbrook | target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
57 | 355fb23d | pbrook | { |
58 | 355fb23d | pbrook | return addr;
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59 | 355fb23d | pbrook | } |
60 | 355fb23d | pbrook | |
61 | 355fb23d | pbrook | #else /* !CONFIG_USER_ONLY */ |
62 | 355fb23d | pbrook | |
63 | fdf9b3e8 | bellard | #define MMU_OK 0 |
64 | fdf9b3e8 | bellard | #define MMU_ITLB_MISS (-1) |
65 | fdf9b3e8 | bellard | #define MMU_ITLB_MULTIPLE (-2) |
66 | fdf9b3e8 | bellard | #define MMU_ITLB_VIOLATION (-3) |
67 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_READ (-4) |
68 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_WRITE (-5) |
69 | fdf9b3e8 | bellard | #define MMU_DTLB_INITIAL_WRITE (-6) |
70 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_READ (-7) |
71 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_WRITE (-8) |
72 | fdf9b3e8 | bellard | #define MMU_DTLB_MULTIPLE (-9) |
73 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS (-10) |
74 | fdf9b3e8 | bellard | |
75 | fdf9b3e8 | bellard | void do_interrupt(CPUState * env)
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76 | fdf9b3e8 | bellard | { |
77 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_INT) {
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78 | fdf9b3e8 | bellard | const char *expname; |
79 | fdf9b3e8 | bellard | switch (env->exception_index) {
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80 | fdf9b3e8 | bellard | case 0x0e0: |
81 | fdf9b3e8 | bellard | expname = "addr_error";
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82 | fdf9b3e8 | bellard | break;
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83 | fdf9b3e8 | bellard | case 0x040: |
84 | fdf9b3e8 | bellard | expname = "tlb_miss";
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85 | fdf9b3e8 | bellard | break;
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86 | fdf9b3e8 | bellard | case 0x0a0: |
87 | fdf9b3e8 | bellard | expname = "tlb_violation";
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88 | fdf9b3e8 | bellard | break;
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89 | fdf9b3e8 | bellard | case 0x180: |
90 | fdf9b3e8 | bellard | expname = "illegal_instruction";
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91 | fdf9b3e8 | bellard | break;
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92 | fdf9b3e8 | bellard | case 0x1a0: |
93 | fdf9b3e8 | bellard | expname = "slot_illegal_instruction";
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94 | fdf9b3e8 | bellard | break;
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95 | fdf9b3e8 | bellard | case 0x800: |
96 | fdf9b3e8 | bellard | expname = "fpu_disable";
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97 | fdf9b3e8 | bellard | break;
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98 | fdf9b3e8 | bellard | case 0x820: |
99 | fdf9b3e8 | bellard | expname = "slot_fpu";
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100 | fdf9b3e8 | bellard | break;
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101 | fdf9b3e8 | bellard | case 0x100: |
102 | fdf9b3e8 | bellard | expname = "data_write";
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103 | fdf9b3e8 | bellard | break;
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104 | fdf9b3e8 | bellard | case 0x060: |
105 | fdf9b3e8 | bellard | expname = "dtlb_miss_write";
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106 | fdf9b3e8 | bellard | break;
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107 | fdf9b3e8 | bellard | case 0x0c0: |
108 | fdf9b3e8 | bellard | expname = "dtlb_violation_write";
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109 | fdf9b3e8 | bellard | break;
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110 | fdf9b3e8 | bellard | case 0x120: |
111 | fdf9b3e8 | bellard | expname = "fpu_exception";
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112 | fdf9b3e8 | bellard | break;
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113 | fdf9b3e8 | bellard | case 0x080: |
114 | fdf9b3e8 | bellard | expname = "initial_page_write";
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115 | fdf9b3e8 | bellard | break;
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116 | fdf9b3e8 | bellard | case 0x160: |
117 | fdf9b3e8 | bellard | expname = "trapa";
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118 | fdf9b3e8 | bellard | break;
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119 | fdf9b3e8 | bellard | default:
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120 | fdf9b3e8 | bellard | expname = "???";
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121 | fdf9b3e8 | bellard | break;
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122 | fdf9b3e8 | bellard | } |
123 | fdf9b3e8 | bellard | fprintf(logfile, "exception 0x%03x [%s] raised\n",
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124 | fdf9b3e8 | bellard | env->exception_index, expname); |
125 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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126 | fdf9b3e8 | bellard | } |
127 | fdf9b3e8 | bellard | |
128 | fdf9b3e8 | bellard | env->ssr = env->sr; |
129 | fdf9b3e8 | bellard | env->spc = env->spc; |
130 | fdf9b3e8 | bellard | env->sgr = env->gregs[15];
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131 | fdf9b3e8 | bellard | env->sr |= SR_BL | SR_MD | SR_RB; |
132 | fdf9b3e8 | bellard | |
133 | fdf9b3e8 | bellard | env->expevt = env->exception_index & 0x7ff;
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134 | fdf9b3e8 | bellard | switch (env->exception_index) {
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135 | fdf9b3e8 | bellard | case 0x040: |
136 | fdf9b3e8 | bellard | case 0x060: |
137 | fdf9b3e8 | bellard | case 0x080: |
138 | fdf9b3e8 | bellard | env->pc = env->vbr + 0x400;
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139 | fdf9b3e8 | bellard | break;
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140 | fdf9b3e8 | bellard | case 0x140: |
141 | fdf9b3e8 | bellard | env->pc = 0xa0000000;
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142 | fdf9b3e8 | bellard | break;
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143 | fdf9b3e8 | bellard | default:
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144 | fdf9b3e8 | bellard | env->pc = env->vbr + 0x100;
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145 | fdf9b3e8 | bellard | break;
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146 | fdf9b3e8 | bellard | } |
147 | fdf9b3e8 | bellard | } |
148 | fdf9b3e8 | bellard | |
149 | fdf9b3e8 | bellard | static void update_itlb_use(CPUState * env, int itlbnb) |
150 | fdf9b3e8 | bellard | { |
151 | fdf9b3e8 | bellard | uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
152 | fdf9b3e8 | bellard | |
153 | fdf9b3e8 | bellard | switch (itlbnb) {
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154 | fdf9b3e8 | bellard | case 0: |
155 | fdf9b3e8 | bellard | and_mask = 0x7f;
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156 | fdf9b3e8 | bellard | break;
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157 | fdf9b3e8 | bellard | case 1: |
158 | fdf9b3e8 | bellard | and_mask = 0xe7;
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159 | fdf9b3e8 | bellard | or_mask = 0x80;
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160 | fdf9b3e8 | bellard | break;
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161 | fdf9b3e8 | bellard | case 2: |
162 | fdf9b3e8 | bellard | and_mask = 0xfb;
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163 | fdf9b3e8 | bellard | or_mask = 0x50;
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164 | fdf9b3e8 | bellard | break;
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165 | fdf9b3e8 | bellard | case 3: |
166 | fdf9b3e8 | bellard | or_mask = 0x2c;
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167 | fdf9b3e8 | bellard | break;
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168 | fdf9b3e8 | bellard | } |
169 | fdf9b3e8 | bellard | |
170 | fdf9b3e8 | bellard | env->mmucr &= (and_mask << 24);
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171 | fdf9b3e8 | bellard | env->mmucr |= (or_mask << 24);
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172 | fdf9b3e8 | bellard | } |
173 | fdf9b3e8 | bellard | |
174 | fdf9b3e8 | bellard | static int itlb_replacement(CPUState * env) |
175 | fdf9b3e8 | bellard | { |
176 | fdf9b3e8 | bellard | if ((env->mmucr & 0xe0000000) == 0xe0000000) |
177 | fdf9b3e8 | bellard | return 0; |
178 | fdf9b3e8 | bellard | if ((env->mmucr & 0x98000000) == 0x08000000) |
179 | fdf9b3e8 | bellard | return 1; |
180 | fdf9b3e8 | bellard | if ((env->mmucr & 0x54000000) == 0x04000000) |
181 | fdf9b3e8 | bellard | return 2; |
182 | fdf9b3e8 | bellard | if ((env->mmucr & 0x2c000000) == 0x00000000) |
183 | fdf9b3e8 | bellard | return 3; |
184 | fdf9b3e8 | bellard | assert(0);
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185 | fdf9b3e8 | bellard | } |
186 | fdf9b3e8 | bellard | |
187 | fdf9b3e8 | bellard | /* Find the corresponding entry in the right TLB
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188 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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189 | fdf9b3e8 | bellard | */
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190 | fdf9b3e8 | bellard | static int find_tlb_entry(CPUState * env, target_ulong address, |
191 | fdf9b3e8 | bellard | tlb_t * entries, uint8_t nbtlb, int use_asid)
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192 | fdf9b3e8 | bellard | { |
193 | fdf9b3e8 | bellard | int match = MMU_DTLB_MISS;
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194 | fdf9b3e8 | bellard | uint32_t start, end; |
195 | fdf9b3e8 | bellard | uint8_t asid; |
196 | fdf9b3e8 | bellard | int i;
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197 | fdf9b3e8 | bellard | |
198 | fdf9b3e8 | bellard | asid = env->pteh & 0xff;
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199 | fdf9b3e8 | bellard | |
200 | fdf9b3e8 | bellard | for (i = 0; i < nbtlb; i++) { |
201 | fdf9b3e8 | bellard | if (!entries[i].v)
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202 | fdf9b3e8 | bellard | continue; /* Invalid entry */ |
203 | fdf9b3e8 | bellard | if (use_asid && entries[i].asid != asid && !entries[i].sh)
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204 | fdf9b3e8 | bellard | continue; /* Bad ASID */ |
205 | fdf9b3e8 | bellard | #if 0
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206 | fdf9b3e8 | bellard | switch (entries[i].sz) {
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207 | fdf9b3e8 | bellard | case 0:
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208 | fdf9b3e8 | bellard | size = 1024; /* 1kB */
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209 | fdf9b3e8 | bellard | break;
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210 | fdf9b3e8 | bellard | case 1:
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211 | fdf9b3e8 | bellard | size = 4 * 1024; /* 4kB */
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212 | fdf9b3e8 | bellard | break;
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213 | fdf9b3e8 | bellard | case 2:
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214 | fdf9b3e8 | bellard | size = 64 * 1024; /* 64kB */
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215 | fdf9b3e8 | bellard | break;
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216 | fdf9b3e8 | bellard | case 3:
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217 | fdf9b3e8 | bellard | size = 1024 * 1024; /* 1MB */
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218 | fdf9b3e8 | bellard | break;
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219 | fdf9b3e8 | bellard | default:
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220 | fdf9b3e8 | bellard | assert(0);
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221 | fdf9b3e8 | bellard | }
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222 | fdf9b3e8 | bellard | #endif
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223 | fdf9b3e8 | bellard | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
224 | fdf9b3e8 | bellard | end = start + entries[i].size - 1;
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225 | fdf9b3e8 | bellard | if (address >= start && address <= end) { /* Match */ |
226 | fdf9b3e8 | bellard | if (match != -1) |
227 | fdf9b3e8 | bellard | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
228 | fdf9b3e8 | bellard | match = i; |
229 | fdf9b3e8 | bellard | } |
230 | fdf9b3e8 | bellard | } |
231 | fdf9b3e8 | bellard | return match;
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232 | fdf9b3e8 | bellard | } |
233 | fdf9b3e8 | bellard | |
234 | fdf9b3e8 | bellard | /* Find itlb entry - update itlb from utlb if necessary and asked for
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235 | fdf9b3e8 | bellard | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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236 | fdf9b3e8 | bellard | Update the itlb from utlb if update is not 0
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237 | fdf9b3e8 | bellard | */
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238 | fdf9b3e8 | bellard | int find_itlb_entry(CPUState * env, target_ulong address,
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239 | fdf9b3e8 | bellard | int use_asid, int update) |
240 | fdf9b3e8 | bellard | { |
241 | fdf9b3e8 | bellard | int e, n;
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242 | fdf9b3e8 | bellard | |
243 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
244 | fdf9b3e8 | bellard | if (e == MMU_DTLB_MULTIPLE)
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245 | fdf9b3e8 | bellard | e = MMU_ITLB_MULTIPLE; |
246 | fdf9b3e8 | bellard | else if (e == MMU_DTLB_MISS && update) { |
247 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
248 | fdf9b3e8 | bellard | if (e >= 0) { |
249 | fdf9b3e8 | bellard | n = itlb_replacement(env); |
250 | fdf9b3e8 | bellard | env->itlb[n] = env->utlb[e]; |
251 | fdf9b3e8 | bellard | e = n; |
252 | fdf9b3e8 | bellard | } |
253 | fdf9b3e8 | bellard | } |
254 | fdf9b3e8 | bellard | if (e >= 0) |
255 | fdf9b3e8 | bellard | update_itlb_use(env, e); |
256 | fdf9b3e8 | bellard | return e;
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257 | fdf9b3e8 | bellard | } |
258 | fdf9b3e8 | bellard | |
259 | fdf9b3e8 | bellard | /* Find utlb entry
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260 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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261 | fdf9b3e8 | bellard | int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
262 | fdf9b3e8 | bellard | { |
263 | fdf9b3e8 | bellard | uint8_t urb, urc; |
264 | fdf9b3e8 | bellard | |
265 | fdf9b3e8 | bellard | /* Increment URC */
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266 | fdf9b3e8 | bellard | urb = ((env->mmucr) >> 18) & 0x3f; |
267 | fdf9b3e8 | bellard | urc = ((env->mmucr) >> 10) & 0x3f; |
268 | fdf9b3e8 | bellard | urc++; |
269 | fdf9b3e8 | bellard | if (urc == urb || urc == UTLB_SIZE - 1) |
270 | fdf9b3e8 | bellard | urc = 0;
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271 | fdf9b3e8 | bellard | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
272 | fdf9b3e8 | bellard | |
273 | fdf9b3e8 | bellard | /* Return entry */
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274 | fdf9b3e8 | bellard | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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275 | fdf9b3e8 | bellard | } |
276 | fdf9b3e8 | bellard | |
277 | fdf9b3e8 | bellard | /* Match address against MMU
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278 | fdf9b3e8 | bellard | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
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279 | fdf9b3e8 | bellard | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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280 | fdf9b3e8 | bellard | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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281 | fdf9b3e8 | bellard | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
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282 | fdf9b3e8 | bellard | */
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283 | fdf9b3e8 | bellard | static int get_mmu_address(CPUState * env, target_ulong * physical, |
284 | fdf9b3e8 | bellard | int *prot, target_ulong address,
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285 | fdf9b3e8 | bellard | int rw, int access_type) |
286 | fdf9b3e8 | bellard | { |
287 | fdf9b3e8 | bellard | int use_asid, is_code, n;
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288 | fdf9b3e8 | bellard | tlb_t *matching = NULL;
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289 | fdf9b3e8 | bellard | |
290 | fdf9b3e8 | bellard | use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0; |
291 | fdf9b3e8 | bellard | is_code = env->pc == address; /* Hack */
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292 | fdf9b3e8 | bellard | |
293 | fdf9b3e8 | bellard | /* Use a hack to find if this is an instruction or data access */
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294 | fdf9b3e8 | bellard | if (env->pc == address && !(rw & PAGE_WRITE)) {
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295 | fdf9b3e8 | bellard | n = find_itlb_entry(env, address, use_asid, 1);
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296 | fdf9b3e8 | bellard | if (n >= 0) { |
297 | fdf9b3e8 | bellard | matching = &env->itlb[n]; |
298 | fdf9b3e8 | bellard | if ((env->sr & SR_MD) & !(matching->pr & 2)) |
299 | fdf9b3e8 | bellard | n = MMU_ITLB_VIOLATION; |
300 | fdf9b3e8 | bellard | else
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301 | fdf9b3e8 | bellard | *prot = PAGE_READ; |
302 | fdf9b3e8 | bellard | } |
303 | fdf9b3e8 | bellard | } else {
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304 | fdf9b3e8 | bellard | n = find_utlb_entry(env, address, use_asid); |
305 | fdf9b3e8 | bellard | if (n >= 0) { |
306 | fdf9b3e8 | bellard | matching = &env->utlb[n]; |
307 | fdf9b3e8 | bellard | switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) { |
308 | fdf9b3e8 | bellard | case 0: /* 000 */ |
309 | fdf9b3e8 | bellard | case 2: /* 010 */ |
310 | fdf9b3e8 | bellard | n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE : |
311 | fdf9b3e8 | bellard | MMU_DTLB_VIOLATION_READ; |
312 | fdf9b3e8 | bellard | break;
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313 | fdf9b3e8 | bellard | case 1: /* 001 */ |
314 | fdf9b3e8 | bellard | case 4: /* 100 */ |
315 | fdf9b3e8 | bellard | case 5: /* 101 */ |
316 | fdf9b3e8 | bellard | if (rw & PAGE_WRITE)
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317 | fdf9b3e8 | bellard | n = MMU_DTLB_VIOLATION_WRITE; |
318 | fdf9b3e8 | bellard | else
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319 | fdf9b3e8 | bellard | *prot = PAGE_READ; |
320 | fdf9b3e8 | bellard | break;
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321 | fdf9b3e8 | bellard | case 3: /* 011 */ |
322 | fdf9b3e8 | bellard | case 6: /* 110 */ |
323 | fdf9b3e8 | bellard | case 7: /* 111 */ |
324 | fdf9b3e8 | bellard | *prot = rw & (PAGE_READ | PAGE_WRITE); |
325 | fdf9b3e8 | bellard | break;
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326 | fdf9b3e8 | bellard | } |
327 | fdf9b3e8 | bellard | } else if (n == MMU_DTLB_MISS) { |
328 | fdf9b3e8 | bellard | n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : |
329 | fdf9b3e8 | bellard | MMU_DTLB_MISS_READ; |
330 | fdf9b3e8 | bellard | } |
331 | fdf9b3e8 | bellard | } |
332 | fdf9b3e8 | bellard | if (n >= 0) { |
333 | fdf9b3e8 | bellard | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
334 | fdf9b3e8 | bellard | (address & (matching->size - 1));
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335 | fdf9b3e8 | bellard | if ((rw & PAGE_WRITE) & !matching->d)
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336 | fdf9b3e8 | bellard | n = MMU_DTLB_INITIAL_WRITE; |
337 | fdf9b3e8 | bellard | else
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338 | fdf9b3e8 | bellard | n = MMU_OK; |
339 | fdf9b3e8 | bellard | } |
340 | fdf9b3e8 | bellard | return n;
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341 | fdf9b3e8 | bellard | } |
342 | fdf9b3e8 | bellard | |
343 | fdf9b3e8 | bellard | int get_physical_address(CPUState * env, target_ulong * physical,
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344 | fdf9b3e8 | bellard | int *prot, target_ulong address,
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345 | fdf9b3e8 | bellard | int rw, int access_type) |
346 | fdf9b3e8 | bellard | { |
347 | fdf9b3e8 | bellard | /* P1, P2 and P4 areas do not use translation */
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348 | fdf9b3e8 | bellard | if ((address >= 0x80000000 && address < 0xc0000000) || |
349 | fdf9b3e8 | bellard | address >= 0xe0000000) {
|
350 | fdf9b3e8 | bellard | if (!(env->sr & SR_MD)
|
351 | fdf9b3e8 | bellard | && (address < 0xe0000000 || address > 0xe4000000)) { |
352 | fdf9b3e8 | bellard | /* Unauthorized access in user mode (only store queues are available) */
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353 | fdf9b3e8 | bellard | fprintf(stderr, "Unauthorized access\n");
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354 | fdf9b3e8 | bellard | return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
|
355 | fdf9b3e8 | bellard | MMU_DTLB_MISS_READ; |
356 | fdf9b3e8 | bellard | } |
357 | fdf9b3e8 | bellard | /* Mask upper 3 bits */
|
358 | fdf9b3e8 | bellard | *physical = address & 0x1FFFFFFF;
|
359 | fdf9b3e8 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
360 | fdf9b3e8 | bellard | return MMU_OK;
|
361 | fdf9b3e8 | bellard | } |
362 | fdf9b3e8 | bellard | |
363 | fdf9b3e8 | bellard | /* If MMU is disabled, return the corresponding physical page */
|
364 | fdf9b3e8 | bellard | if (!env->mmucr & MMUCR_AT) {
|
365 | fdf9b3e8 | bellard | *physical = address & 0x1FFFFFFF;
|
366 | fdf9b3e8 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
367 | fdf9b3e8 | bellard | return MMU_OK;
|
368 | fdf9b3e8 | bellard | } |
369 | fdf9b3e8 | bellard | |
370 | fdf9b3e8 | bellard | /* We need to resort to the MMU */
|
371 | fdf9b3e8 | bellard | return get_mmu_address(env, physical, prot, address, rw, access_type);
|
372 | fdf9b3e8 | bellard | } |
373 | fdf9b3e8 | bellard | |
374 | fdf9b3e8 | bellard | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
375 | fdf9b3e8 | bellard | int is_user, int is_softmmu) |
376 | fdf9b3e8 | bellard | { |
377 | fdf9b3e8 | bellard | target_ulong physical, page_offset, page_size; |
378 | fdf9b3e8 | bellard | int prot, ret, access_type;
|
379 | fdf9b3e8 | bellard | |
380 | fdf9b3e8 | bellard | /* XXXXX */
|
381 | fdf9b3e8 | bellard | #if 0
|
382 | fdf9b3e8 | bellard | fprintf(stderr, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
|
383 | fdf9b3e8 | bellard | __func__, env->pc, address, rw, is_user, is_softmmu);
|
384 | fdf9b3e8 | bellard | #endif
|
385 | fdf9b3e8 | bellard | |
386 | fdf9b3e8 | bellard | access_type = ACCESS_INT; |
387 | fdf9b3e8 | bellard | ret = |
388 | fdf9b3e8 | bellard | get_physical_address(env, &physical, &prot, address, rw, |
389 | fdf9b3e8 | bellard | access_type); |
390 | fdf9b3e8 | bellard | |
391 | fdf9b3e8 | bellard | if (ret != MMU_OK) {
|
392 | fdf9b3e8 | bellard | env->tea = address; |
393 | fdf9b3e8 | bellard | switch (ret) {
|
394 | fdf9b3e8 | bellard | case MMU_ITLB_MISS:
|
395 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_READ:
|
396 | fdf9b3e8 | bellard | env->exception_index = 0x040;
|
397 | fdf9b3e8 | bellard | break;
|
398 | fdf9b3e8 | bellard | case MMU_DTLB_MULTIPLE:
|
399 | fdf9b3e8 | bellard | case MMU_ITLB_MULTIPLE:
|
400 | fdf9b3e8 | bellard | env->exception_index = 0x140;
|
401 | fdf9b3e8 | bellard | break;
|
402 | fdf9b3e8 | bellard | case MMU_ITLB_VIOLATION:
|
403 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
404 | fdf9b3e8 | bellard | break;
|
405 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_WRITE:
|
406 | fdf9b3e8 | bellard | env->exception_index = 0x060;
|
407 | fdf9b3e8 | bellard | break;
|
408 | fdf9b3e8 | bellard | case MMU_DTLB_INITIAL_WRITE:
|
409 | fdf9b3e8 | bellard | env->exception_index = 0x080;
|
410 | fdf9b3e8 | bellard | break;
|
411 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_READ:
|
412 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
413 | fdf9b3e8 | bellard | break;
|
414 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_WRITE:
|
415 | fdf9b3e8 | bellard | env->exception_index = 0x0c0;
|
416 | fdf9b3e8 | bellard | break;
|
417 | fdf9b3e8 | bellard | default:
|
418 | fdf9b3e8 | bellard | assert(0);
|
419 | fdf9b3e8 | bellard | } |
420 | fdf9b3e8 | bellard | return 1; |
421 | fdf9b3e8 | bellard | } |
422 | fdf9b3e8 | bellard | |
423 | fdf9b3e8 | bellard | page_size = TARGET_PAGE_SIZE; |
424 | fdf9b3e8 | bellard | page_offset = |
425 | fdf9b3e8 | bellard | (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
|
426 | fdf9b3e8 | bellard | address = (address & TARGET_PAGE_MASK) + page_offset; |
427 | fdf9b3e8 | bellard | physical = (physical & TARGET_PAGE_MASK) + page_offset; |
428 | fdf9b3e8 | bellard | |
429 | fdf9b3e8 | bellard | return tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
|
430 | fdf9b3e8 | bellard | } |
431 | 355fb23d | pbrook | |
432 | 355fb23d | pbrook | target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
433 | 355fb23d | pbrook | { |
434 | 355fb23d | pbrook | target_ulong physical; |
435 | 355fb23d | pbrook | int prot;
|
436 | 355fb23d | pbrook | |
437 | 355fb23d | pbrook | get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
|
438 | 355fb23d | pbrook | return physical;
|
439 | 355fb23d | pbrook | } |
440 | 355fb23d | pbrook | |
441 | 355fb23d | pbrook | #endif |