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/*
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 * QEMU System Emulator header
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd, 
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                         IOCanRWHandler *fd_read_poll, 
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                         IOHandler *fd_read, 
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                         IOHandler *fd_write, 
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read, 
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s, 
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                           IOCanRWHandler *fd_can_read, 
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
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    void *buffer;
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    int count;
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};
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
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    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
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       rate-limit the slirp code.  */
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    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
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    struct VLANState *vlan;
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    char info_str[256];
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};
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typedef struct VLANState {
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    int id;
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    VLANClientState *first_client;
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    struct VLANState *next;
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} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
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                                      IOReadHandler *fd_read,
388 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
389 d861b05e pbrook
                                      void *opaque);
390 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
391 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
392 d861b05e pbrook
void qemu_handler_true(void *opaque);
393 7c9d8e07 bellard
394 7c9d8e07 bellard
void do_info_network(void);
395 7c9d8e07 bellard
396 7fb843f8 bellard
/* TAP win32 */
397 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
398 7fb843f8 bellard
399 7c9d8e07 bellard
/* NIC info */
400 c4b1fcc0 bellard
401 c4b1fcc0 bellard
#define MAX_NICS 8
402 c4b1fcc0 bellard
403 7c9d8e07 bellard
typedef struct NICInfo {
404 c4b1fcc0 bellard
    uint8_t macaddr[6];
405 a41b2ff2 pbrook
    const char *model;
406 7c9d8e07 bellard
    VLANState *vlan;
407 7c9d8e07 bellard
} NICInfo;
408 c4b1fcc0 bellard
409 c4b1fcc0 bellard
extern int nb_nics;
410 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
411 8a7ddc38 bellard
412 8a7ddc38 bellard
/* timers */
413 8a7ddc38 bellard
414 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
415 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
416 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
417 8a7ddc38 bellard
418 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
419 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
420 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
421 8a7ddc38 bellard
   Hz. */
422 8a7ddc38 bellard
extern QEMUClock *rt_clock;
423 8a7ddc38 bellard
424 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
425 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
426 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
427 8a7ddc38 bellard
extern QEMUClock *vm_clock;
428 8a7ddc38 bellard
429 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
430 8a7ddc38 bellard
431 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
432 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
433 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
434 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
435 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
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extern int64_t ticks_per_sec;
438 8a7ddc38 bellard
extern int pit_min_timer_count;
439 8a7ddc38 bellard
440 1dce7c3c bellard
int64_t cpu_get_ticks(void);
441 8a7ddc38 bellard
void cpu_enable_ticks(void);
442 8a7ddc38 bellard
void cpu_disable_ticks(void);
443 8a7ddc38 bellard
444 8a7ddc38 bellard
/* VM Load/Save */
445 8a7ddc38 bellard
446 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
447 8a7ddc38 bellard
448 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
449 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
450 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
451 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
452 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
453 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
454 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
455 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
456 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
457 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
458 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
459 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
460 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
461 8a7ddc38 bellard
462 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
463 8a7ddc38 bellard
{
464 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
465 8a7ddc38 bellard
}
466 8a7ddc38 bellard
467 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
468 8a7ddc38 bellard
{
469 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
470 8a7ddc38 bellard
}
471 8a7ddc38 bellard
472 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
473 8a7ddc38 bellard
{
474 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
475 8a7ddc38 bellard
}
476 8a7ddc38 bellard
477 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
478 8a7ddc38 bellard
{
479 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
480 8a7ddc38 bellard
}
481 8a7ddc38 bellard
482 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
483 8a7ddc38 bellard
{
484 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
485 8a7ddc38 bellard
}
486 8a7ddc38 bellard
487 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
488 8a7ddc38 bellard
{
489 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
490 8a7ddc38 bellard
}
491 8a7ddc38 bellard
492 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
493 8a7ddc38 bellard
{
494 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
495 8a7ddc38 bellard
}
496 8a7ddc38 bellard
497 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
498 8a7ddc38 bellard
{
499 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
500 8a7ddc38 bellard
}
501 8a7ddc38 bellard
502 c27004ec bellard
#if TARGET_LONG_BITS == 64
503 c27004ec bellard
#define qemu_put_betl qemu_put_be64
504 c27004ec bellard
#define qemu_get_betl qemu_get_be64
505 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
506 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
507 c27004ec bellard
#else
508 c27004ec bellard
#define qemu_put_betl qemu_put_be32
509 c27004ec bellard
#define qemu_get_betl qemu_get_be32
510 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
511 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
512 c27004ec bellard
#endif
513 c27004ec bellard
514 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
515 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
516 8a7ddc38 bellard
517 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
518 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
519 8a7ddc38 bellard
520 8a7ddc38 bellard
int register_savevm(const char *idstr, 
521 8a7ddc38 bellard
                    int instance_id, 
522 8a7ddc38 bellard
                    int version_id,
523 8a7ddc38 bellard
                    SaveStateHandler *save_state,
524 8a7ddc38 bellard
                    LoadStateHandler *load_state,
525 8a7ddc38 bellard
                    void *opaque);
526 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
527 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
528 c4b1fcc0 bellard
529 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
530 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
531 6a00d601 bellard
532 faea38e7 bellard
void do_savevm(const char *name);
533 faea38e7 bellard
void do_loadvm(const char *name);
534 faea38e7 bellard
void do_delvm(const char *name);
535 faea38e7 bellard
void do_info_snapshots(void);
536 faea38e7 bellard
537 83f64091 bellard
/* bottom halves */
538 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
539 83f64091 bellard
540 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
541 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
542 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
543 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
544 6eb5733a bellard
int qemu_bh_poll(void);
545 83f64091 bellard
546 fc01f7e7 bellard
/* block.c */
547 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
548 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
549 ea2384d3 bellard
550 ea2384d3 bellard
extern BlockDriver bdrv_raw;
551 19cb3738 bellard
extern BlockDriver bdrv_host_device;
552 ea2384d3 bellard
extern BlockDriver bdrv_cow;
553 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
554 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
555 3c56521b bellard
extern BlockDriver bdrv_cloop;
556 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
557 a8753c34 bellard
extern BlockDriver bdrv_bochs;
558 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
559 de167e41 bellard
extern BlockDriver bdrv_vvfat;
560 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
561 faea38e7 bellard
562 faea38e7 bellard
typedef struct BlockDriverInfo {
563 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
564 faea38e7 bellard
    int cluster_size; 
565 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
566 faea38e7 bellard
    int64_t vm_state_offset; 
567 faea38e7 bellard
} BlockDriverInfo;
568 faea38e7 bellard
569 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
570 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
571 faea38e7 bellard
    /* the following fields are informative. They are not needed for
572 faea38e7 bellard
       the consistency of the snapshot */
573 faea38e7 bellard
    char name[256]; /* user choosen name */
574 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
575 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
576 faea38e7 bellard
    uint32_t date_nsec;
577 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
578 faea38e7 bellard
} QEMUSnapshotInfo;
579 ea2384d3 bellard
580 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
581 83f64091 bellard
#define BDRV_O_RDWR        0x0002
582 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
583 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
584 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
585 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
586 83f64091 bellard
                                     use a disk image format on top of
587 83f64091 bellard
                                     it (default for
588 83f64091 bellard
                                     bdrv_file_open()) */
589 83f64091 bellard
590 ea2384d3 bellard
void bdrv_init(void);
591 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
592 ea2384d3 bellard
int bdrv_create(BlockDriver *drv, 
593 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
594 ea2384d3 bellard
                const char *backing_file, int flags);
595 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
596 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
597 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
598 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
599 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
600 ea2384d3 bellard
               BlockDriver *drv);
601 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
602 fc01f7e7 bellard
int bdrv_read(BlockDriverState *bs, int64_t sector_num, 
603 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
604 fc01f7e7 bellard
int bdrv_write(BlockDriverState *bs, int64_t sector_num, 
605 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
606 83f64091 bellard
int bdrv_pread(BlockDriverState *bs, int64_t offset, 
607 83f64091 bellard
               void *buf, int count);
608 83f64091 bellard
int bdrv_pwrite(BlockDriverState *bs, int64_t offset, 
609 83f64091 bellard
                const void *buf, int count);
610 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
611 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
612 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
613 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
614 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
615 83f64091 bellard
/* async block I/O */
616 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
617 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
618 83f64091 bellard
619 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
620 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
621 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
622 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
623 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
624 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
625 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
626 83f64091 bellard
627 83f64091 bellard
void qemu_aio_init(void);
628 83f64091 bellard
void qemu_aio_poll(void);
629 6192bc37 pbrook
void qemu_aio_flush(void);
630 83f64091 bellard
void qemu_aio_wait_start(void);
631 83f64091 bellard
void qemu_aio_wait(void);
632 83f64091 bellard
void qemu_aio_wait_end(void);
633 83f64091 bellard
634 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
635 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
636 33e3963e bellard
637 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
638 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
639 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
640 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
641 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
642 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
643 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
644 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
645 c4b1fcc0 bellard
646 c4b1fcc0 bellard
void bdrv_set_geometry_hint(BlockDriverState *bs, 
647 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
648 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
649 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
650 c4b1fcc0 bellard
void bdrv_get_geometry_hint(BlockDriverState *bs, 
651 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
652 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
653 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
654 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
655 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
656 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
657 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
658 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
659 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
660 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
661 c4b1fcc0 bellard
void bdrv_set_change_cb(BlockDriverState *bs, 
662 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
663 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
664 c4b1fcc0 bellard
void bdrv_info(void);
665 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
666 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
667 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
668 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
669 ea2384d3 bellard
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), 
670 ea2384d3 bellard
                         void *opaque);
671 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
672 faea38e7 bellard
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num, 
673 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
674 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
675 c4b1fcc0 bellard
676 83f64091 bellard
void bdrv_get_backing_filename(BlockDriverState *bs, 
677 83f64091 bellard
                               char *filename, int filename_size);
678 faea38e7 bellard
int bdrv_snapshot_create(BlockDriverState *bs, 
679 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
680 faea38e7 bellard
int bdrv_snapshot_goto(BlockDriverState *bs, 
681 faea38e7 bellard
                       const char *snapshot_id);
682 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
683 faea38e7 bellard
int bdrv_snapshot_list(BlockDriverState *bs, 
684 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
685 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
686 faea38e7 bellard
687 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
688 83f64091 bellard
int path_is_absolute(const char *path);
689 83f64091 bellard
void path_combine(char *dest, int dest_size,
690 83f64091 bellard
                  const char *base_path,
691 83f64091 bellard
                  const char *filename);
692 ea2384d3 bellard
693 ea2384d3 bellard
#ifndef QEMU_TOOL
694 54fa5af5 bellard
695 54fa5af5 bellard
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, 
696 54fa5af5 bellard
                                 int boot_device,
697 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
698 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
699 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
700 54fa5af5 bellard
701 54fa5af5 bellard
typedef struct QEMUMachine {
702 54fa5af5 bellard
    const char *name;
703 54fa5af5 bellard
    const char *desc;
704 54fa5af5 bellard
    QEMUMachineInitFunc *init;
705 54fa5af5 bellard
    struct QEMUMachine *next;
706 54fa5af5 bellard
} QEMUMachine;
707 54fa5af5 bellard
708 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
709 54fa5af5 bellard
710 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
711 3de388f6 bellard
typedef void IRQRequestFunc(void *opaque, int level);
712 54fa5af5 bellard
713 94fc95cd j_mayer
#if defined(TARGET_PPC)
714 94fc95cd j_mayer
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
715 94fc95cd j_mayer
#endif
716 94fc95cd j_mayer
717 33d68b5f ths
#if defined(TARGET_MIPS)
718 33d68b5f ths
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
719 33d68b5f ths
#endif
720 33d68b5f ths
721 26aa7d72 bellard
/* ISA bus */
722 26aa7d72 bellard
723 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
724 26aa7d72 bellard
725 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
726 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
727 26aa7d72 bellard
728 26aa7d72 bellard
int register_ioport_read(int start, int length, int size, 
729 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
730 26aa7d72 bellard
int register_ioport_write(int start, int length, int size, 
731 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
732 69b91039 bellard
void isa_unassign_ioport(int start, int length);
733 69b91039 bellard
734 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
735 aef445bd pbrook
736 69b91039 bellard
/* PCI bus */
737 69b91039 bellard
738 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
739 69b91039 bellard
740 46e50e9d bellard
typedef struct PCIBus PCIBus;
741 69b91039 bellard
typedef struct PCIDevice PCIDevice;
742 69b91039 bellard
743 69b91039 bellard
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 
744 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
745 69b91039 bellard
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 
746 69b91039 bellard
                                   uint32_t address, int len);
747 69b91039 bellard
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 
748 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
749 69b91039 bellard
750 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
751 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
752 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
753 69b91039 bellard
754 69b91039 bellard
typedef struct PCIIORegion {
755 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
756 69b91039 bellard
    uint32_t size;
757 69b91039 bellard
    uint8_t type;
758 69b91039 bellard
    PCIMapIORegionFunc *map_func;
759 69b91039 bellard
} PCIIORegion;
760 69b91039 bellard
761 8a8696a3 bellard
#define PCI_ROM_SLOT 6
762 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
763 502a5395 pbrook
764 502a5395 pbrook
#define PCI_DEVICES_MAX 64
765 502a5395 pbrook
766 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
767 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
768 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
769 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
770 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
771 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
772 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
773 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
774 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
775 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
776 502a5395 pbrook
777 69b91039 bellard
struct PCIDevice {
778 69b91039 bellard
    /* PCI config space */
779 69b91039 bellard
    uint8_t config[256];
780 69b91039 bellard
781 69b91039 bellard
    /* the following fields are read only */
782 46e50e9d bellard
    PCIBus *bus;
783 69b91039 bellard
    int devfn;
784 69b91039 bellard
    char name[64];
785 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
786 69b91039 bellard
    
787 69b91039 bellard
    /* do not access the following fields */
788 69b91039 bellard
    PCIConfigReadFunc *config_read;
789 69b91039 bellard
    PCIConfigWriteFunc *config_write;
790 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
791 5768f5ac bellard
    int irq_index;
792 d2b59317 pbrook
793 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
794 d2b59317 pbrook
    int irq_state[4];
795 69b91039 bellard
};
796 69b91039 bellard
797 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
798 46e50e9d bellard
                               int instance_size, int devfn,
799 69b91039 bellard
                               PCIConfigReadFunc *config_read, 
800 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
801 69b91039 bellard
802 69b91039 bellard
void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
803 69b91039 bellard
                            uint32_t size, int type, 
804 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
805 69b91039 bellard
806 5768f5ac bellard
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
807 5768f5ac bellard
808 5768f5ac bellard
uint32_t pci_default_read_config(PCIDevice *d, 
809 5768f5ac bellard
                                 uint32_t address, int len);
810 5768f5ac bellard
void pci_default_write_config(PCIDevice *d, 
811 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
812 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
813 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
814 5768f5ac bellard
815 d2b59317 pbrook
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
816 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
817 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
818 80b3ada7 pbrook
                         void *pic, int devfn_min, int nirq);
819 502a5395 pbrook
820 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
821 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
822 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
823 502a5395 pbrook
int pci_bus_num(PCIBus *s);
824 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
825 9995c51f bellard
826 5768f5ac bellard
void pci_info(void);
827 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
828 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
829 26aa7d72 bellard
830 502a5395 pbrook
/* prep_pci.c */
831 46e50e9d bellard
PCIBus *pci_prep_init(void);
832 77d4bc34 bellard
833 502a5395 pbrook
/* grackle_pci.c */
834 502a5395 pbrook
PCIBus *pci_grackle_init(uint32_t base, void *pic);
835 502a5395 pbrook
836 502a5395 pbrook
/* unin_pci.c */
837 502a5395 pbrook
PCIBus *pci_pmac_init(void *pic);
838 502a5395 pbrook
839 502a5395 pbrook
/* apb_pci.c */
840 502a5395 pbrook
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
841 502a5395 pbrook
                     void *pic);
842 502a5395 pbrook
843 e69954b9 pbrook
PCIBus *pci_vpb_init(void *pic, int irq, int realview);
844 502a5395 pbrook
845 502a5395 pbrook
/* piix_pci.c */
846 f00fc47c bellard
PCIBus *i440fx_init(PCIDevice **pi440fx_state);
847 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
848 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
849 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
850 a41b2ff2 pbrook
851 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
852 5856de80 ths
853 28b9b5af bellard
/* openpic.c */
854 28b9b5af bellard
typedef struct openpic_t openpic_t;
855 47103572 j_mayer
enum {
856 47103572 j_mayer
    OPENPIC_EVT_INT = 0, /* IRQ                       */
857 47103572 j_mayer
    OPENPIC_EVT_CINT,    /* critical IRQ              */
858 47103572 j_mayer
    OPENPIC_EVT_MCK,     /* Machine check event       */
859 47103572 j_mayer
    OPENPIC_EVT_DEBUG,   /* Inconditional debug event */
860 47103572 j_mayer
    OPENPIC_EVT_RESET,   /* Core reset event          */
861 47103572 j_mayer
};
862 e69f67b6 ths
struct CPUPPCState;
863 54fa5af5 bellard
void openpic_set_irq(void *opaque, int n_IRQ, int level);
864 47103572 j_mayer
openpic_t *openpic_init (PCIBus *bus, SetIRQFunc *set_irq,
865 e69f67b6 ths
                         int *pmem_index, int nb_cpus,
866 e69f67b6 ths
                         struct CPUPPCState **envp);
867 28b9b5af bellard
868 54fa5af5 bellard
/* heathrow_pic.c */
869 54fa5af5 bellard
typedef struct HeathrowPICS HeathrowPICS;
870 54fa5af5 bellard
void heathrow_pic_set_irq(void *opaque, int num, int level);
871 54fa5af5 bellard
HeathrowPICS *heathrow_pic_init(int *pmem_index);
872 54fa5af5 bellard
873 fde7d5bd ths
/* gt64xxx.c */
874 fde7d5bd ths
PCIBus *pci_gt64120_init(void *pic);
875 fde7d5bd ths
876 6a36d84e bellard
#ifdef HAS_AUDIO
877 6a36d84e bellard
struct soundhw {
878 6a36d84e bellard
    const char *name;
879 6a36d84e bellard
    const char *descr;
880 6a36d84e bellard
    int enabled;
881 6a36d84e bellard
    int isa;
882 6a36d84e bellard
    union {
883 6a36d84e bellard
        int (*init_isa) (AudioState *s);
884 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
885 6a36d84e bellard
    } init;
886 6a36d84e bellard
};
887 6a36d84e bellard
888 6a36d84e bellard
extern struct soundhw soundhw[];
889 6a36d84e bellard
#endif
890 6a36d84e bellard
891 313aa567 bellard
/* vga.c */
892 313aa567 bellard
893 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
894 313aa567 bellard
895 82c643ff bellard
struct DisplayState {
896 313aa567 bellard
    uint8_t *data;
897 313aa567 bellard
    int linesize;
898 313aa567 bellard
    int depth;
899 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
900 82c643ff bellard
    int width;
901 82c643ff bellard
    int height;
902 24236869 bellard
    void *opaque;
903 24236869 bellard
904 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
905 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
906 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
907 24236869 bellard
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h);
908 82c643ff bellard
};
909 313aa567 bellard
910 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
911 313aa567 bellard
{
912 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
913 313aa567 bellard
}
914 313aa567 bellard
915 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
916 313aa567 bellard
{
917 313aa567 bellard
    s->dpy_resize(s, w, h);
918 313aa567 bellard
}
919 313aa567 bellard
920 89b6b508 bellard
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
921 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
922 89b6b508 bellard
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
923 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
924 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
925 313aa567 bellard
926 d6bfa22f bellard
/* cirrus_vga.c */
927 46e50e9d bellard
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
928 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
929 d6bfa22f bellard
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
930 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
931 d6bfa22f bellard
932 313aa567 bellard
/* sdl.c */
933 43523e93 ths
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
934 313aa567 bellard
935 da4dbf74 bellard
/* cocoa.m */
936 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
937 da4dbf74 bellard
938 24236869 bellard
/* vnc.c */
939 73fc9742 ths
void vnc_display_init(DisplayState *ds, const char *display);
940 a9ce8590 bellard
void do_info_vnc(void);
941 24236869 bellard
942 6070dd07 ths
/* x_keymap.c */
943 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
944 6070dd07 ths
945 5391d806 bellard
/* ide.c */
946 5391d806 bellard
#define MAX_DISKS 4
947 5391d806 bellard
948 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
949 5391d806 bellard
950 69b91039 bellard
void isa_ide_init(int iobase, int iobase2, int irq,
951 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
952 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
953 54fa5af5 bellard
                         int secondary_ide_enabled);
954 502a5395 pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn);
955 28b9b5af bellard
int pmac_ide_init (BlockDriverState **hd_table,
956 54fa5af5 bellard
                   SetIRQFunc *set_irq, void *irq_opaque, int irq);
957 5391d806 bellard
958 2e5d83bb pbrook
/* cdrom.c */
959 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
960 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
961 2e5d83bb pbrook
962 9542611a ths
/* ds1225y.c */
963 9542611a ths
typedef struct ds1225y_t ds1225y_t;
964 9542611a ths
ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
965 9542611a ths
966 1d14ffa9 bellard
/* es1370.c */
967 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
968 1d14ffa9 bellard
969 fb065187 bellard
/* sb16.c */
970 c0fe3827 bellard
int SB16_init (AudioState *s);
971 fb065187 bellard
972 fb065187 bellard
/* adlib.c */
973 c0fe3827 bellard
int Adlib_init (AudioState *s);
974 fb065187 bellard
975 fb065187 bellard
/* gus.c */
976 c0fe3827 bellard
int GUS_init (AudioState *s);
977 27503323 bellard
978 27503323 bellard
/* dma.c */
979 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
980 27503323 bellard
int DMA_get_channel_mode (int nchan);
981 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
982 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
983 27503323 bellard
void DMA_hold_DREQ (int nchan);
984 27503323 bellard
void DMA_release_DREQ (int nchan);
985 16f62432 bellard
void DMA_schedule(int nchan);
986 27503323 bellard
void DMA_run (void);
987 28b9b5af bellard
void DMA_init (int high_page_enable);
988 27503323 bellard
void DMA_register_channel (int nchan,
989 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
990 85571bc7 bellard
                           void *opaque);
991 7138fcfb bellard
/* fdc.c */
992 7138fcfb bellard
#define MAX_FD 2
993 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
994 7138fcfb bellard
995 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
996 baca51fa bellard
997 baca51fa bellard
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, 
998 baca51fa bellard
                       uint32_t io_base,
999 baca51fa bellard
                       BlockDriverState **fds);
1000 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1001 7138fcfb bellard
1002 80cabfad bellard
/* ne2000.c */
1003 80cabfad bellard
1004 7c9d8e07 bellard
void isa_ne2000_init(int base, int irq, NICInfo *nd);
1005 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1006 80cabfad bellard
1007 a41b2ff2 pbrook
/* rtl8139.c */
1008 a41b2ff2 pbrook
1009 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1010 a41b2ff2 pbrook
1011 e3c2613f bellard
/* pcnet.c */
1012 e3c2613f bellard
1013 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1014 67e999be bellard
void pcnet_h_reset(void *opaque);
1015 67e999be bellard
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
1016 67e999be bellard
1017 548df2ac ths
/* vmmouse.c */
1018 548df2ac ths
void *vmmouse_init(void *m);
1019 e3c2613f bellard
1020 80cabfad bellard
/* pckbd.c */
1021 80cabfad bellard
1022 80cabfad bellard
void kbd_init(void);
1023 80cabfad bellard
1024 80cabfad bellard
/* mc146818rtc.c */
1025 80cabfad bellard
1026 8a7ddc38 bellard
typedef struct RTCState RTCState;
1027 80cabfad bellard
1028 8a7ddc38 bellard
RTCState *rtc_init(int base, int irq);
1029 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1030 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1031 80cabfad bellard
1032 80cabfad bellard
/* serial.c */
1033 80cabfad bellard
1034 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1035 e5d13e2f bellard
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
1036 e5d13e2f bellard
                         int base, int irq, CharDriverState *chr);
1037 e5d13e2f bellard
SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
1038 e5d13e2f bellard
                             target_ulong base, int it_shift,
1039 e5d13e2f bellard
                             int irq, CharDriverState *chr);
1040 80cabfad bellard
1041 6508fe59 bellard
/* parallel.c */
1042 6508fe59 bellard
1043 6508fe59 bellard
typedef struct ParallelState ParallelState;
1044 6508fe59 bellard
ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
1045 6508fe59 bellard
1046 80cabfad bellard
/* i8259.c */
1047 80cabfad bellard
1048 3de388f6 bellard
typedef struct PicState2 PicState2;
1049 3de388f6 bellard
extern PicState2 *isa_pic;
1050 80cabfad bellard
void pic_set_irq(int irq, int level);
1051 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1052 3de388f6 bellard
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
1053 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1054 d592d303 bellard
                          void *alt_irq_opaque);
1055 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1056 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1057 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1058 c20709aa bellard
void pic_info(void);
1059 4a0fb71e bellard
void irq_info(void);
1060 80cabfad bellard
1061 c27004ec bellard
/* APIC */
1062 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1063 d592d303 bellard
1064 c27004ec bellard
int apic_init(CPUState *env);
1065 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1066 d592d303 bellard
IOAPICState *ioapic_init(void);
1067 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1068 c27004ec bellard
1069 80cabfad bellard
/* i8254.c */
1070 80cabfad bellard
1071 80cabfad bellard
#define PIT_FREQ 1193182
1072 80cabfad bellard
1073 ec844b96 bellard
typedef struct PITState PITState;
1074 ec844b96 bellard
1075 ec844b96 bellard
PITState *pit_init(int base, int irq);
1076 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1077 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1078 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1079 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1080 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1081 80cabfad bellard
1082 fd06c375 bellard
/* pcspk.c */
1083 fd06c375 bellard
void pcspk_init(PITState *);
1084 fd06c375 bellard
int pcspk_audio_init(AudioState *);
1085 fd06c375 bellard
1086 3fffc223 ths
#include "hw/smbus.h"
1087 3fffc223 ths
1088 6515b203 bellard
/* acpi.c */
1089 6515b203 bellard
extern int acpi_enabled;
1090 502a5395 pbrook
void piix4_pm_init(PCIBus *bus, int devfn);
1091 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1092 6515b203 bellard
void acpi_bios_init(void);
1093 6515b203 bellard
1094 3fffc223 ths
/* smbus_eeprom.c */
1095 3fffc223 ths
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1096 3fffc223 ths
1097 80cabfad bellard
/* pc.c */
1098 54fa5af5 bellard
extern QEMUMachine pc_machine;
1099 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1100 52ca8d6a bellard
extern int fd_bootchk;
1101 80cabfad bellard
1102 6a00d601 bellard
void ioport_set_a20(int enable);
1103 6a00d601 bellard
int ioport_get_a20(void);
1104 6a00d601 bellard
1105 26aa7d72 bellard
/* ppc.c */
1106 54fa5af5 bellard
extern QEMUMachine prep_machine;
1107 54fa5af5 bellard
extern QEMUMachine core99_machine;
1108 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1109 54fa5af5 bellard
1110 6af0bf9c bellard
/* mips_r4k.c */
1111 6af0bf9c bellard
extern QEMUMachine mips_machine;
1112 6af0bf9c bellard
1113 5856de80 ths
/* mips_malta.c */
1114 5856de80 ths
extern QEMUMachine mips_malta_machine;
1115 5856de80 ths
1116 4de9b249 ths
/* mips_int */
1117 4de9b249 ths
extern void cpu_mips_irq_request(void *opaque, int irq, int level);
1118 4de9b249 ths
1119 e16fe40c ths
/* mips_timer.c */
1120 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1121 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1122 e16fe40c ths
1123 27c7ca7e bellard
/* shix.c */
1124 27c7ca7e bellard
extern QEMUMachine shix_machine;
1125 27c7ca7e bellard
1126 8cc43fef bellard
#ifdef TARGET_PPC
1127 47103572 j_mayer
/* PowerPC hardware exceptions management helpers */
1128 47103572 j_mayer
void ppc_set_irq (void *opaque, int n_IRQ, int level);
1129 47103572 j_mayer
void ppc_openpic_irq (void *opaque, int n_IRQ, int level);
1130 47103572 j_mayer
int ppc_hw_interrupt (CPUState *env);
1131 8cc43fef bellard
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1132 8cc43fef bellard
#endif
1133 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1134 77d4bc34 bellard
1135 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1136 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1137 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1138 26aa7d72 bellard
1139 e95c8d51 bellard
/* sun4m.c */
1140 54fa5af5 bellard
extern QEMUMachine sun4m_machine;
1141 ba3c64fb bellard
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
1142 e95c8d51 bellard
1143 e95c8d51 bellard
/* iommu.c */
1144 e80cfcfc bellard
void *iommu_init(uint32_t addr);
1145 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1146 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1147 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1148 67e999be bellard
                                           target_phys_addr_t addr,
1149 67e999be bellard
                                           uint8_t *buf, int len)
1150 67e999be bellard
{
1151 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1152 67e999be bellard
}
1153 e95c8d51 bellard
1154 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1155 67e999be bellard
                                            target_phys_addr_t addr,
1156 67e999be bellard
                                            uint8_t *buf, int len)
1157 67e999be bellard
{
1158 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1159 67e999be bellard
}
1160 e95c8d51 bellard
1161 e95c8d51 bellard
/* tcx.c */
1162 95219897 pbrook
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1163 6f7e9aec bellard
               unsigned long vram_offset, int vram_size, int width, int height);
1164 e80cfcfc bellard
1165 e80cfcfc bellard
/* slavio_intctl.c */
1166 e80cfcfc bellard
void *slavio_intctl_init();
1167 ba3c64fb bellard
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1168 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1169 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1170 e80cfcfc bellard
void slavio_pic_set_irq(void *opaque, int irq, int level);
1171 ba3c64fb bellard
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1172 e95c8d51 bellard
1173 5fe141fd bellard
/* loader.c */
1174 5fe141fd bellard
int get_image_size(const char *filename);
1175 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1176 9ee3c029 bellard
int load_elf(const char *filename, int64_t virt_to_phys_addend, uint64_t *pentry);
1177 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1178 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1179 e80cfcfc bellard
1180 e80cfcfc bellard
/* slavio_timer.c */
1181 ba3c64fb bellard
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
1182 8d5f07fa bellard
1183 e80cfcfc bellard
/* slavio_serial.c */
1184 e80cfcfc bellard
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
1185 e80cfcfc bellard
void slavio_serial_ms_kbd_init(int base, int irq);
1186 e95c8d51 bellard
1187 3475187d bellard
/* slavio_misc.c */
1188 3475187d bellard
void *slavio_misc_init(uint32_t base, int irq);
1189 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1190 3475187d bellard
1191 6f7e9aec bellard
/* esp.c */
1192 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1193 67e999be bellard
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1194 67e999be bellard
void esp_reset(void *opaque);
1195 67e999be bellard
1196 67e999be bellard
/* sparc32_dma.c */
1197 67e999be bellard
void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
1198 67e999be bellard
                       void *intctl);
1199 67e999be bellard
void ledma_set_irq(void *opaque, int isr);
1200 9b94dc32 bellard
void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
1201 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1202 9b94dc32 bellard
void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
1203 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1204 67e999be bellard
void espdma_raise_irq(void *opaque);
1205 67e999be bellard
void espdma_clear_irq(void *opaque);
1206 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1207 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1208 67e999be bellard
void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1209 67e999be bellard
                                void *lance_opaque);
1210 6f7e9aec bellard
1211 b8174937 bellard
/* cs4231.c */
1212 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1213 b8174937 bellard
1214 3475187d bellard
/* sun4u.c */
1215 3475187d bellard
extern QEMUMachine sun4u_machine;
1216 3475187d bellard
1217 64201201 bellard
/* NVRAM helpers */
1218 64201201 bellard
#include "hw/m48t59.h"
1219 64201201 bellard
1220 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1221 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1222 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1223 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1224 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1225 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1226 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1227 64201201 bellard
                       const unsigned char *str, uint32_t max);
1228 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1229 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1230 64201201 bellard
                    uint32_t start, uint32_t count);
1231 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1232 64201201 bellard
                          const unsigned char *arch,
1233 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1234 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1235 28b9b5af bellard
                          const char *cmdline,
1236 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1237 28b9b5af bellard
                          uint32_t NVRAM_image,
1238 28b9b5af bellard
                          int width, int height, int depth);
1239 64201201 bellard
1240 63066f4f bellard
/* adb.c */
1241 63066f4f bellard
1242 63066f4f bellard
#define MAX_ADB_DEVICES 16
1243 63066f4f bellard
1244 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1245 63066f4f bellard
1246 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1247 63066f4f bellard
1248 e2733d20 bellard
/* buf = NULL means polling */
1249 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1250 e2733d20 bellard
                              const uint8_t *buf, int len);
1251 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1252 12c28fed bellard
1253 63066f4f bellard
struct ADBDevice {
1254 63066f4f bellard
    struct ADBBusState *bus;
1255 63066f4f bellard
    int devaddr;
1256 63066f4f bellard
    int handler;
1257 e2733d20 bellard
    ADBDeviceRequest *devreq;
1258 12c28fed bellard
    ADBDeviceReset *devreset;
1259 63066f4f bellard
    void *opaque;
1260 63066f4f bellard
};
1261 63066f4f bellard
1262 63066f4f bellard
typedef struct ADBBusState {
1263 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1264 63066f4f bellard
    int nb_devices;
1265 e2733d20 bellard
    int poll_index;
1266 63066f4f bellard
} ADBBusState;
1267 63066f4f bellard
1268 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1269 e2733d20 bellard
                const uint8_t *buf, int len);
1270 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1271 63066f4f bellard
1272 63066f4f bellard
ADBDevice *adb_register_device(ADBBusState *s, int devaddr, 
1273 e2733d20 bellard
                               ADBDeviceRequest *devreq, 
1274 12c28fed bellard
                               ADBDeviceReset *devreset, 
1275 63066f4f bellard
                               void *opaque);
1276 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1277 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1278 63066f4f bellard
1279 63066f4f bellard
/* cuda.c */
1280 63066f4f bellard
1281 63066f4f bellard
extern ADBBusState adb_bus;
1282 54fa5af5 bellard
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
1283 63066f4f bellard
1284 bb36d470 bellard
#include "hw/usb.h"
1285 bb36d470 bellard
1286 a594cfbf bellard
/* usb ports of the VM */
1287 a594cfbf bellard
1288 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1289 0d92ed30 pbrook
                            usb_attachfn attach);
1290 a594cfbf bellard
1291 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1292 a594cfbf bellard
1293 a594cfbf bellard
void do_usb_add(const char *devname);
1294 a594cfbf bellard
void do_usb_del(const char *devname);
1295 a594cfbf bellard
void usb_info(void);
1296 a594cfbf bellard
1297 2e5d83bb pbrook
/* scsi-disk.c */
1298 4d611c9a pbrook
enum scsi_reason {
1299 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1300 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1301 4d611c9a pbrook
};
1302 4d611c9a pbrook
1303 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1304 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1305 a917d384 pbrook
                                  uint32_t arg);
1306 2e5d83bb pbrook
1307 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1308 a917d384 pbrook
                           int tcq,
1309 2e5d83bb pbrook
                           scsi_completionfn completion,
1310 2e5d83bb pbrook
                           void *opaque);
1311 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1312 2e5d83bb pbrook
1313 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1314 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1315 4d611c9a pbrook
   layer the completion routine may be called directly by
1316 4d611c9a pbrook
   scsi_{read,write}_data.  */
1317 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1318 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1319 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1320 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1321 2e5d83bb pbrook
1322 7d8406be pbrook
/* lsi53c895a.c */
1323 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1324 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1325 7d8406be pbrook
1326 b5ff1b31 bellard
/* integratorcp.c */
1327 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1328 b5ff1b31 bellard
1329 cdbdb648 pbrook
/* versatilepb.c */
1330 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1331 16406950 pbrook
extern QEMUMachine versatileab_machine;
1332 cdbdb648 pbrook
1333 e69954b9 pbrook
/* realview.c */
1334 e69954b9 pbrook
extern QEMUMachine realview_machine;
1335 e69954b9 pbrook
1336 daa57963 bellard
/* ps2.c */
1337 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1338 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1339 daa57963 bellard
void ps2_write_mouse(void *, int val);
1340 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1341 daa57963 bellard
uint32_t ps2_read_data(void *);
1342 daa57963 bellard
void ps2_queue(void *, int b);
1343 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1344 548df2ac ths
void ps2_mouse_fake_event(void *opaque);
1345 daa57963 bellard
1346 80337b66 bellard
/* smc91c111.c */
1347 80337b66 bellard
void smc91c111_init(NICInfo *, uint32_t, void *, int);
1348 80337b66 bellard
1349 bdd5003a pbrook
/* pl110.c */
1350 95219897 pbrook
void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
1351 bdd5003a pbrook
1352 cdbdb648 pbrook
/* pl011.c */
1353 cdbdb648 pbrook
void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr);
1354 cdbdb648 pbrook
1355 cdbdb648 pbrook
/* pl050.c */
1356 cdbdb648 pbrook
void pl050_init(uint32_t base, void *pic, int irq, int is_mouse);
1357 cdbdb648 pbrook
1358 cdbdb648 pbrook
/* pl080.c */
1359 e69954b9 pbrook
void *pl080_init(uint32_t base, void *pic, int irq, int nchannels);
1360 cdbdb648 pbrook
1361 cdbdb648 pbrook
/* pl190.c */
1362 cdbdb648 pbrook
void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
1363 cdbdb648 pbrook
1364 cdbdb648 pbrook
/* arm-timer.c */
1365 cdbdb648 pbrook
void sp804_init(uint32_t base, void *pic, int irq);
1366 cdbdb648 pbrook
void icp_pit_init(uint32_t base, void *pic, int irq);
1367 cdbdb648 pbrook
1368 e69954b9 pbrook
/* arm_sysctl.c */
1369 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1370 e69954b9 pbrook
1371 e69954b9 pbrook
/* arm_gic.c */
1372 e69954b9 pbrook
void *arm_gic_init(uint32_t base, void *parent, int parent_irq);
1373 e69954b9 pbrook
1374 16406950 pbrook
/* arm_boot.c */
1375 16406950 pbrook
1376 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1377 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1378 16406950 pbrook
                     int board_id);
1379 16406950 pbrook
1380 27c7ca7e bellard
/* sh7750.c */
1381 27c7ca7e bellard
struct SH7750State;
1382 27c7ca7e bellard
1383 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1384 27c7ca7e bellard
1385 27c7ca7e bellard
typedef struct {
1386 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1387 27c7ca7e bellard
    uint16_t portamask_trigger;
1388 27c7ca7e bellard
    uint16_t portbmask_trigger;
1389 27c7ca7e bellard
    /* Return 0 if no action was taken */
1390 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1391 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1392 27c7ca7e bellard
                           uint16_t * periph_portdira,
1393 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1394 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1395 27c7ca7e bellard
} sh7750_io_device;
1396 27c7ca7e bellard
1397 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1398 27c7ca7e bellard
                              sh7750_io_device * device);
1399 27c7ca7e bellard
/* tc58128.c */
1400 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1401 27c7ca7e bellard
1402 29133e9a bellard
/* NOR flash devices */
1403 29133e9a bellard
typedef struct pflash_t pflash_t;
1404 29133e9a bellard
1405 29133e9a bellard
pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1406 29133e9a bellard
                           BlockDriverState *bs,
1407 29133e9a bellard
                           target_ulong sector_len, int nb_blocs, int width,
1408 29133e9a bellard
                           uint16_t id0, uint16_t id1, 
1409 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1410 29133e9a bellard
1411 4046d913 pbrook
#include "gdbstub.h"
1412 4046d913 pbrook
1413 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1414 ea2384d3 bellard
1415 c4b1fcc0 bellard
/* monitor.c */
1416 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1417 ea2384d3 bellard
void term_puts(const char *str);
1418 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1419 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1420 fef30743 ths
void term_print_filename(const char *filename);
1421 c4b1fcc0 bellard
void term_flush(void);
1422 c4b1fcc0 bellard
void term_print_help(void);
1423 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1424 ea2384d3 bellard
                      char *buf, int buf_size);
1425 ea2384d3 bellard
1426 ea2384d3 bellard
/* readline.c */
1427 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1428 ea2384d3 bellard
1429 ea2384d3 bellard
extern int completion_index;
1430 ea2384d3 bellard
void add_completion(const char *str);
1431 ea2384d3 bellard
void readline_handle_byte(int ch);
1432 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1433 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1434 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1435 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1436 c4b1fcc0 bellard
1437 5e6ad6f9 bellard
void kqemu_record_dump(void);
1438 5e6ad6f9 bellard
1439 fc01f7e7 bellard
#endif /* VL_H */