root / target-sparc / op_helper.c @ 375ee38b
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1 | e8af50a3 | bellard | #include "exec.h" |
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2 | eed152bb | blueswir1 | #include "host-utils.h" |
3 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
4 | e8af50a3 | bellard | |
5 | 83469015 | bellard | //#define DEBUG_PCALL
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6 | e80cfcfc | bellard | //#define DEBUG_MMU
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7 | 952a328f | blueswir1 | //#define DEBUG_MXCC
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8 | 94554550 | blueswir1 | //#define DEBUG_UNALIGNED
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9 | 6c36d3fa | blueswir1 | //#define DEBUG_UNASSIGNED
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10 | 8543e2cf | blueswir1 | //#define DEBUG_ASI
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11 | e80cfcfc | bellard | |
12 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
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13 | 952a328f | blueswir1 | #define DPRINTF_MMU(fmt, args...) \
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14 | 952a328f | blueswir1 | do { printf("MMU: " fmt , ##args); } while (0) |
15 | 952a328f | blueswir1 | #else
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16 | 952a328f | blueswir1 | #define DPRINTF_MMU(fmt, args...)
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17 | 952a328f | blueswir1 | #endif
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18 | 952a328f | blueswir1 | |
19 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
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20 | 952a328f | blueswir1 | #define DPRINTF_MXCC(fmt, args...) \
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21 | 952a328f | blueswir1 | do { printf("MXCC: " fmt , ##args); } while (0) |
22 | 952a328f | blueswir1 | #else
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23 | 952a328f | blueswir1 | #define DPRINTF_MXCC(fmt, args...)
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24 | 952a328f | blueswir1 | #endif
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25 | 952a328f | blueswir1 | |
26 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
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27 | 8543e2cf | blueswir1 | #define DPRINTF_ASI(fmt, args...) \
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28 | 8543e2cf | blueswir1 | do { printf("ASI: " fmt , ##args); } while (0) |
29 | 8543e2cf | blueswir1 | #else
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30 | 8543e2cf | blueswir1 | #define DPRINTF_ASI(fmt, args...)
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31 | 8543e2cf | blueswir1 | #endif
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32 | 8543e2cf | blueswir1 | |
33 | 9d893301 | bellard | void raise_exception(int tt) |
34 | 9d893301 | bellard | { |
35 | 9d893301 | bellard | env->exception_index = tt; |
36 | 9d893301 | bellard | cpu_loop_exit(); |
37 | 3b46e624 | ths | } |
38 | 9d893301 | bellard | |
39 | 1a2fb1c0 | blueswir1 | void helper_trap(target_ulong nb_trap)
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40 | 417454b0 | blueswir1 | { |
41 | 1a2fb1c0 | blueswir1 | env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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42 | 1a2fb1c0 | blueswir1 | cpu_loop_exit(); |
43 | 1a2fb1c0 | blueswir1 | } |
44 | 1a2fb1c0 | blueswir1 | |
45 | 1a2fb1c0 | blueswir1 | void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
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46 | 1a2fb1c0 | blueswir1 | { |
47 | 1a2fb1c0 | blueswir1 | if (do_trap) {
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48 | 1a2fb1c0 | blueswir1 | env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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49 | 1a2fb1c0 | blueswir1 | cpu_loop_exit(); |
50 | 1a2fb1c0 | blueswir1 | } |
51 | 1a2fb1c0 | blueswir1 | } |
52 | 1a2fb1c0 | blueswir1 | |
53 | 7e8c2b6c | blueswir1 | void helper_check_ieee_exceptions(void) |
54 | 1a2fb1c0 | blueswir1 | { |
55 | 1a2fb1c0 | blueswir1 | target_ulong status; |
56 | 1a2fb1c0 | blueswir1 | |
57 | 1a2fb1c0 | blueswir1 | status = get_float_exception_flags(&env->fp_status); |
58 | 1a2fb1c0 | blueswir1 | if (status) {
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59 | 0f8a249a | blueswir1 | /* Copy IEEE 754 flags into FSR */
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60 | 1a2fb1c0 | blueswir1 | if (status & float_flag_invalid)
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61 | 0f8a249a | blueswir1 | env->fsr |= FSR_NVC; |
62 | 1a2fb1c0 | blueswir1 | if (status & float_flag_overflow)
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63 | 0f8a249a | blueswir1 | env->fsr |= FSR_OFC; |
64 | 1a2fb1c0 | blueswir1 | if (status & float_flag_underflow)
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65 | 0f8a249a | blueswir1 | env->fsr |= FSR_UFC; |
66 | 1a2fb1c0 | blueswir1 | if (status & float_flag_divbyzero)
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67 | 0f8a249a | blueswir1 | env->fsr |= FSR_DZC; |
68 | 1a2fb1c0 | blueswir1 | if (status & float_flag_inexact)
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69 | 0f8a249a | blueswir1 | env->fsr |= FSR_NXC; |
70 | 0f8a249a | blueswir1 | |
71 | 1a2fb1c0 | blueswir1 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { |
72 | 0f8a249a | blueswir1 | /* Unmasked exception, generate a trap */
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73 | 0f8a249a | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; |
74 | 0f8a249a | blueswir1 | raise_exception(TT_FP_EXCP); |
75 | 1a2fb1c0 | blueswir1 | } else {
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76 | 0f8a249a | blueswir1 | /* Accumulate exceptions */
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77 | 0f8a249a | blueswir1 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
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78 | 0f8a249a | blueswir1 | } |
79 | 1a2fb1c0 | blueswir1 | } |
80 | 417454b0 | blueswir1 | } |
81 | 417454b0 | blueswir1 | |
82 | 7e8c2b6c | blueswir1 | void helper_clear_float_exceptions(void) |
83 | 7e8c2b6c | blueswir1 | { |
84 | 7e8c2b6c | blueswir1 | set_float_exception_flags(0, &env->fp_status);
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85 | 7e8c2b6c | blueswir1 | } |
86 | 7e8c2b6c | blueswir1 | |
87 | a0c4cb4a | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
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88 | a0c4cb4a | bellard | void do_fitos(void) |
89 | a0c4cb4a | bellard | { |
90 | ec230928 | ths | FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
91 | a0c4cb4a | bellard | } |
92 | a0c4cb4a | bellard | |
93 | a0c4cb4a | bellard | void do_fitod(void) |
94 | a0c4cb4a | bellard | { |
95 | ec230928 | ths | DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
96 | a0c4cb4a | bellard | } |
97 | 9c2b428e | blueswir1 | |
98 | 9c2b428e | blueswir1 | #if defined(CONFIG_USER_ONLY)
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99 | 9c2b428e | blueswir1 | void do_fitoq(void) |
100 | 9c2b428e | blueswir1 | { |
101 | 9c2b428e | blueswir1 | QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status); |
102 | 9c2b428e | blueswir1 | } |
103 | 9c2b428e | blueswir1 | #endif
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104 | 9c2b428e | blueswir1 | |
105 | 1e64e78d | blueswir1 | #ifdef TARGET_SPARC64
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106 | 1e64e78d | blueswir1 | void do_fxtos(void) |
107 | 1e64e78d | blueswir1 | { |
108 | 1e64e78d | blueswir1 | FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
109 | 1e64e78d | blueswir1 | } |
110 | 1e64e78d | blueswir1 | |
111 | 1e64e78d | blueswir1 | void do_fxtod(void) |
112 | 1e64e78d | blueswir1 | { |
113 | 1e64e78d | blueswir1 | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
114 | 1e64e78d | blueswir1 | } |
115 | 9c2b428e | blueswir1 | |
116 | 9c2b428e | blueswir1 | #if defined(CONFIG_USER_ONLY)
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117 | 9c2b428e | blueswir1 | void do_fxtoq(void) |
118 | 9c2b428e | blueswir1 | { |
119 | 9c2b428e | blueswir1 | QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status); |
120 | 9c2b428e | blueswir1 | } |
121 | 9c2b428e | blueswir1 | #endif
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122 | 1e64e78d | blueswir1 | #endif
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123 | a0c4cb4a | bellard | #endif
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124 | a0c4cb4a | bellard | |
125 | 7e8c2b6c | blueswir1 | void helper_fabss(void) |
126 | e8af50a3 | bellard | { |
127 | 7a0e1f41 | bellard | FT0 = float32_abs(FT1); |
128 | e8af50a3 | bellard | } |
129 | e8af50a3 | bellard | |
130 | 3475187d | bellard | #ifdef TARGET_SPARC64
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131 | 7e8c2b6c | blueswir1 | void helper_fabsd(void) |
132 | 3475187d | bellard | { |
133 | 3475187d | bellard | DT0 = float64_abs(DT1); |
134 | 3475187d | bellard | } |
135 | 1f587329 | blueswir1 | |
136 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
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137 | 7e8c2b6c | blueswir1 | void helper_fabsq(void) |
138 | 1f587329 | blueswir1 | { |
139 | 1f587329 | blueswir1 | QT0 = float128_abs(QT1); |
140 | 1f587329 | blueswir1 | } |
141 | 1f587329 | blueswir1 | #endif
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142 | 3475187d | bellard | #endif
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143 | 3475187d | bellard | |
144 | 7e8c2b6c | blueswir1 | void helper_fsqrts(void) |
145 | e8af50a3 | bellard | { |
146 | 7a0e1f41 | bellard | FT0 = float32_sqrt(FT1, &env->fp_status); |
147 | e8af50a3 | bellard | } |
148 | e8af50a3 | bellard | |
149 | 7e8c2b6c | blueswir1 | void helper_fsqrtd(void) |
150 | e8af50a3 | bellard | { |
151 | 7a0e1f41 | bellard | DT0 = float64_sqrt(DT1, &env->fp_status); |
152 | e8af50a3 | bellard | } |
153 | e8af50a3 | bellard | |
154 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
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155 | 7e8c2b6c | blueswir1 | void helper_fsqrtq(void) |
156 | 1f587329 | blueswir1 | { |
157 | 1f587329 | blueswir1 | QT0 = float128_sqrt(QT1, &env->fp_status); |
158 | 1f587329 | blueswir1 | } |
159 | 1f587329 | blueswir1 | #endif
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160 | 1f587329 | blueswir1 | |
161 | 417454b0 | blueswir1 | #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
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162 | 7e8c2b6c | blueswir1 | void glue(helper_, name) (void) \ |
163 | 65ce8c2f | bellard | { \ |
164 | 1a2fb1c0 | blueswir1 | target_ulong new_fsr; \ |
165 | 1a2fb1c0 | blueswir1 | \ |
166 | 65ce8c2f | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
167 | 65ce8c2f | bellard | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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168 | 65ce8c2f | bellard | case float_relation_unordered: \
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169 | 1a2fb1c0 | blueswir1 | new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ |
170 | 417454b0 | blueswir1 | if ((env->fsr & FSR_NVM) || TRAP) { \
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171 | 1a2fb1c0 | blueswir1 | env->fsr |= new_fsr; \ |
172 | 417454b0 | blueswir1 | env->fsr |= FSR_NVC; \ |
173 | 417454b0 | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
174 | 65ce8c2f | bellard | raise_exception(TT_FP_EXCP); \ |
175 | 65ce8c2f | bellard | } else { \
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176 | 65ce8c2f | bellard | env->fsr |= FSR_NVA; \ |
177 | 65ce8c2f | bellard | } \ |
178 | 65ce8c2f | bellard | break; \
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179 | 65ce8c2f | bellard | case float_relation_less: \
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180 | 1a2fb1c0 | blueswir1 | new_fsr = FSR_FCC0 << FS; \ |
181 | 65ce8c2f | bellard | break; \
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182 | 65ce8c2f | bellard | case float_relation_greater: \
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183 | 1a2fb1c0 | blueswir1 | new_fsr = FSR_FCC1 << FS; \ |
184 | 65ce8c2f | bellard | break; \
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185 | 65ce8c2f | bellard | default: \
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186 | 1a2fb1c0 | blueswir1 | new_fsr = 0; \
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187 | 65ce8c2f | bellard | break; \
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188 | 65ce8c2f | bellard | } \ |
189 | 1a2fb1c0 | blueswir1 | env->fsr |= new_fsr; \ |
190 | e8af50a3 | bellard | } |
191 | e8af50a3 | bellard | |
192 | 417454b0 | blueswir1 | GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
193 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
194 | 417454b0 | blueswir1 | |
195 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
196 | 417454b0 | blueswir1 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
197 | 3475187d | bellard | |
198 | 1f587329 | blueswir1 | #ifdef CONFIG_USER_ONLY
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199 | 1f587329 | blueswir1 | GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); |
200 | 1f587329 | blueswir1 | GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); |
201 | 1f587329 | blueswir1 | #endif
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202 | 1f587329 | blueswir1 | |
203 | 3475187d | bellard | #ifdef TARGET_SPARC64
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204 | 417454b0 | blueswir1 | GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
205 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
206 | 417454b0 | blueswir1 | |
207 | 417454b0 | blueswir1 | GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
208 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
209 | 417454b0 | blueswir1 | |
210 | 417454b0 | blueswir1 | GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
211 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
212 | 417454b0 | blueswir1 | |
213 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
214 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
215 | 3475187d | bellard | |
216 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
217 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
218 | 3475187d | bellard | |
219 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
220 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
221 | 1f587329 | blueswir1 | #ifdef CONFIG_USER_ONLY
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222 | 1f587329 | blueswir1 | GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); |
223 | 1f587329 | blueswir1 | GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); |
224 | 1f587329 | blueswir1 | GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); |
225 | 1f587329 | blueswir1 | GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); |
226 | 1f587329 | blueswir1 | GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); |
227 | 1f587329 | blueswir1 | GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
228 | 1f587329 | blueswir1 | #endif
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229 | 3475187d | bellard | #endif
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230 | 3475187d | bellard | |
231 | 1a2fb1c0 | blueswir1 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
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232 | 952a328f | blueswir1 | static void dump_mxcc(CPUState *env) |
233 | 952a328f | blueswir1 | { |
234 | 952a328f | blueswir1 | printf("mxccdata: %016llx %016llx %016llx %016llx\n",
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235 | 952a328f | blueswir1 | env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); |
236 | 952a328f | blueswir1 | printf("mxccregs: %016llx %016llx %016llx %016llx\n"
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237 | 952a328f | blueswir1 | " %016llx %016llx %016llx %016llx\n",
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238 | 952a328f | blueswir1 | env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], |
239 | 952a328f | blueswir1 | env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); |
240 | 952a328f | blueswir1 | } |
241 | 952a328f | blueswir1 | #endif
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242 | 952a328f | blueswir1 | |
243 | 1a2fb1c0 | blueswir1 | #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
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244 | 1a2fb1c0 | blueswir1 | && defined(DEBUG_ASI) |
245 | 1a2fb1c0 | blueswir1 | static void dump_asi(const char *txt, target_ulong addr, int asi, int size, |
246 | 1a2fb1c0 | blueswir1 | uint64_t r1) |
247 | 8543e2cf | blueswir1 | { |
248 | 8543e2cf | blueswir1 | switch (size)
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249 | 8543e2cf | blueswir1 | { |
250 | 8543e2cf | blueswir1 | case 1: |
251 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
252 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xff);
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253 | 8543e2cf | blueswir1 | break;
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254 | 8543e2cf | blueswir1 | case 2: |
255 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
256 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xffff);
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257 | 8543e2cf | blueswir1 | break;
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258 | 8543e2cf | blueswir1 | case 4: |
259 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
260 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xffffffff);
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261 | 8543e2cf | blueswir1 | break;
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262 | 8543e2cf | blueswir1 | case 8: |
263 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
264 | 1a2fb1c0 | blueswir1 | addr, asi, r1); |
265 | 8543e2cf | blueswir1 | break;
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266 | 8543e2cf | blueswir1 | } |
267 | 8543e2cf | blueswir1 | } |
268 | 8543e2cf | blueswir1 | #endif
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269 | 8543e2cf | blueswir1 | |
270 | 1a2fb1c0 | blueswir1 | #ifndef TARGET_SPARC64
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271 | 1a2fb1c0 | blueswir1 | #ifndef CONFIG_USER_ONLY
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272 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
273 | e8af50a3 | bellard | { |
274 | 1a2fb1c0 | blueswir1 | uint64_t ret = 0;
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275 | 8543e2cf | blueswir1 | #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
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276 | 1a2fb1c0 | blueswir1 | uint32_t last_addr = addr; |
277 | 952a328f | blueswir1 | #endif
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278 | e80cfcfc | bellard | |
279 | e80cfcfc | bellard | switch (asi) {
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280 | 6c36d3fa | blueswir1 | case 2: /* SuperSparc MXCC registers */ |
281 | 1a2fb1c0 | blueswir1 | switch (addr) {
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282 | 952a328f | blueswir1 | case 0x01c00a00: /* MXCC control register */ |
283 | 1a2fb1c0 | blueswir1 | if (size == 8) |
284 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[3];
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285 | 1a2fb1c0 | blueswir1 | else
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286 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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287 | 952a328f | blueswir1 | break;
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288 | 952a328f | blueswir1 | case 0x01c00a04: /* MXCC control register */ |
289 | 952a328f | blueswir1 | if (size == 4) |
290 | 952a328f | blueswir1 | ret = env->mxccregs[3];
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291 | 952a328f | blueswir1 | else
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292 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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293 | 952a328f | blueswir1 | break;
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294 | 295db113 | blueswir1 | case 0x01c00c00: /* Module reset register */ |
295 | 295db113 | blueswir1 | if (size == 8) { |
296 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[5];
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297 | 295db113 | blueswir1 | // should we do something here?
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298 | 295db113 | blueswir1 | } else
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299 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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300 | 295db113 | blueswir1 | break;
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301 | 952a328f | blueswir1 | case 0x01c00f00: /* MBus port address register */ |
302 | 1a2fb1c0 | blueswir1 | if (size == 8) |
303 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[7];
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304 | 1a2fb1c0 | blueswir1 | else
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305 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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306 | 952a328f | blueswir1 | break;
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307 | 952a328f | blueswir1 | default:
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308 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
309 | 952a328f | blueswir1 | break;
|
310 | 952a328f | blueswir1 | } |
311 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
|
312 | 1a2fb1c0 | blueswir1 | "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
313 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
314 | 952a328f | blueswir1 | dump_mxcc(env); |
315 | 952a328f | blueswir1 | #endif
|
316 | 6c36d3fa | blueswir1 | break;
|
317 | e8af50a3 | bellard | case 3: /* MMU probe */ |
318 | 0f8a249a | blueswir1 | { |
319 | 0f8a249a | blueswir1 | int mmulev;
|
320 | 0f8a249a | blueswir1 | |
321 | 1a2fb1c0 | blueswir1 | mmulev = (addr >> 8) & 15; |
322 | 0f8a249a | blueswir1 | if (mmulev > 4) |
323 | 0f8a249a | blueswir1 | ret = 0;
|
324 | 1a2fb1c0 | blueswir1 | else
|
325 | 1a2fb1c0 | blueswir1 | ret = mmu_probe(env, addr, mmulev); |
326 | 1a2fb1c0 | blueswir1 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", |
327 | 1a2fb1c0 | blueswir1 | addr, mmulev, ret); |
328 | 0f8a249a | blueswir1 | } |
329 | 0f8a249a | blueswir1 | break;
|
330 | e8af50a3 | bellard | case 4: /* read MMU regs */ |
331 | 0f8a249a | blueswir1 | { |
332 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 8) & 0x1f; |
333 | 3b46e624 | ths | |
334 | 0f8a249a | blueswir1 | ret = env->mmuregs[reg]; |
335 | 0f8a249a | blueswir1 | if (reg == 3) /* Fault status cleared on read */ |
336 | 3dd9a152 | blueswir1 | env->mmuregs[3] = 0; |
337 | 3dd9a152 | blueswir1 | else if (reg == 0x13) /* Fault status read */ |
338 | 3dd9a152 | blueswir1 | ret = env->mmuregs[3];
|
339 | 3dd9a152 | blueswir1 | else if (reg == 0x14) /* Fault address read */ |
340 | 3dd9a152 | blueswir1 | ret = env->mmuregs[4];
|
341 | 1a2fb1c0 | blueswir1 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
342 | 0f8a249a | blueswir1 | } |
343 | 0f8a249a | blueswir1 | break;
|
344 | 045380be | blueswir1 | case 5: // Turbosparc ITLB Diagnostic |
345 | 045380be | blueswir1 | case 6: // Turbosparc DTLB Diagnostic |
346 | 045380be | blueswir1 | case 7: // Turbosparc IOTLB Diagnostic |
347 | 045380be | blueswir1 | break;
|
348 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access */ |
349 | 6c36d3fa | blueswir1 | switch(size) {
|
350 | 6c36d3fa | blueswir1 | case 1: |
351 | 1a2fb1c0 | blueswir1 | ret = ldub_code(addr); |
352 | 6c36d3fa | blueswir1 | break;
|
353 | 6c36d3fa | blueswir1 | case 2: |
354 | 1a2fb1c0 | blueswir1 | ret = lduw_code(addr & ~1);
|
355 | 6c36d3fa | blueswir1 | break;
|
356 | 6c36d3fa | blueswir1 | default:
|
357 | 6c36d3fa | blueswir1 | case 4: |
358 | 1a2fb1c0 | blueswir1 | ret = ldl_code(addr & ~3);
|
359 | 6c36d3fa | blueswir1 | break;
|
360 | 6c36d3fa | blueswir1 | case 8: |
361 | 1a2fb1c0 | blueswir1 | ret = ldq_code(addr & ~7);
|
362 | 6c36d3fa | blueswir1 | break;
|
363 | 6c36d3fa | blueswir1 | } |
364 | 6c36d3fa | blueswir1 | break;
|
365 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
366 | 81ad8ba2 | blueswir1 | switch(size) {
|
367 | 81ad8ba2 | blueswir1 | case 1: |
368 | 1a2fb1c0 | blueswir1 | ret = ldub_user(addr); |
369 | 81ad8ba2 | blueswir1 | break;
|
370 | 81ad8ba2 | blueswir1 | case 2: |
371 | 1a2fb1c0 | blueswir1 | ret = lduw_user(addr & ~1);
|
372 | 81ad8ba2 | blueswir1 | break;
|
373 | 81ad8ba2 | blueswir1 | default:
|
374 | 81ad8ba2 | blueswir1 | case 4: |
375 | 1a2fb1c0 | blueswir1 | ret = ldl_user(addr & ~3);
|
376 | 81ad8ba2 | blueswir1 | break;
|
377 | 81ad8ba2 | blueswir1 | case 8: |
378 | 1a2fb1c0 | blueswir1 | ret = ldq_user(addr & ~7);
|
379 | 81ad8ba2 | blueswir1 | break;
|
380 | 81ad8ba2 | blueswir1 | } |
381 | 81ad8ba2 | blueswir1 | break;
|
382 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
383 | 81ad8ba2 | blueswir1 | switch(size) {
|
384 | 81ad8ba2 | blueswir1 | case 1: |
385 | 1a2fb1c0 | blueswir1 | ret = ldub_kernel(addr); |
386 | 81ad8ba2 | blueswir1 | break;
|
387 | 81ad8ba2 | blueswir1 | case 2: |
388 | 1a2fb1c0 | blueswir1 | ret = lduw_kernel(addr & ~1);
|
389 | 81ad8ba2 | blueswir1 | break;
|
390 | 81ad8ba2 | blueswir1 | default:
|
391 | 81ad8ba2 | blueswir1 | case 4: |
392 | 1a2fb1c0 | blueswir1 | ret = ldl_kernel(addr & ~3);
|
393 | 81ad8ba2 | blueswir1 | break;
|
394 | 81ad8ba2 | blueswir1 | case 8: |
395 | 1a2fb1c0 | blueswir1 | ret = ldq_kernel(addr & ~7);
|
396 | 81ad8ba2 | blueswir1 | break;
|
397 | 81ad8ba2 | blueswir1 | } |
398 | 81ad8ba2 | blueswir1 | break;
|
399 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
400 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
401 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
402 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
403 | 6c36d3fa | blueswir1 | break;
|
404 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
405 | 02aab46a | bellard | switch(size) {
|
406 | 02aab46a | bellard | case 1: |
407 | 1a2fb1c0 | blueswir1 | ret = ldub_phys(addr); |
408 | 02aab46a | bellard | break;
|
409 | 02aab46a | bellard | case 2: |
410 | 1a2fb1c0 | blueswir1 | ret = lduw_phys(addr & ~1);
|
411 | 02aab46a | bellard | break;
|
412 | 02aab46a | bellard | default:
|
413 | 02aab46a | bellard | case 4: |
414 | 1a2fb1c0 | blueswir1 | ret = ldl_phys(addr & ~3);
|
415 | 02aab46a | bellard | break;
|
416 | 9e61bde5 | bellard | case 8: |
417 | 1a2fb1c0 | blueswir1 | ret = ldq_phys(addr & ~7);
|
418 | 0f8a249a | blueswir1 | break;
|
419 | 02aab46a | bellard | } |
420 | 0f8a249a | blueswir1 | break;
|
421 | 7d85892b | blueswir1 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
422 | 5dcb6b91 | blueswir1 | switch(size) {
|
423 | 5dcb6b91 | blueswir1 | case 1: |
424 | 1a2fb1c0 | blueswir1 | ret = ldub_phys((target_phys_addr_t)addr |
425 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
426 | 5dcb6b91 | blueswir1 | break;
|
427 | 5dcb6b91 | blueswir1 | case 2: |
428 | 1a2fb1c0 | blueswir1 | ret = lduw_phys((target_phys_addr_t)(addr & ~1)
|
429 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
430 | 5dcb6b91 | blueswir1 | break;
|
431 | 5dcb6b91 | blueswir1 | default:
|
432 | 5dcb6b91 | blueswir1 | case 4: |
433 | 1a2fb1c0 | blueswir1 | ret = ldl_phys((target_phys_addr_t)(addr & ~3)
|
434 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
435 | 5dcb6b91 | blueswir1 | break;
|
436 | 5dcb6b91 | blueswir1 | case 8: |
437 | 1a2fb1c0 | blueswir1 | ret = ldq_phys((target_phys_addr_t)(addr & ~7)
|
438 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
439 | 0f8a249a | blueswir1 | break;
|
440 | 5dcb6b91 | blueswir1 | } |
441 | 0f8a249a | blueswir1 | break;
|
442 | 045380be | blueswir1 | case 0x30: // Turbosparc secondary cache diagnostic |
443 | 045380be | blueswir1 | case 0x31: // Turbosparc RAM snoop |
444 | 045380be | blueswir1 | case 0x32: // Turbosparc page table descriptor diagnostic |
445 | 666c87aa | blueswir1 | case 0x39: /* data cache diagnostic register */ |
446 | 666c87aa | blueswir1 | ret = 0;
|
447 | 666c87aa | blueswir1 | break;
|
448 | 045380be | blueswir1 | case 8: /* User code access, XXX */ |
449 | e8af50a3 | bellard | default:
|
450 | 1a2fb1c0 | blueswir1 | do_unassigned_access(addr, 0, 0, asi); |
451 | 0f8a249a | blueswir1 | ret = 0;
|
452 | 0f8a249a | blueswir1 | break;
|
453 | e8af50a3 | bellard | } |
454 | 81ad8ba2 | blueswir1 | if (sign) {
|
455 | 81ad8ba2 | blueswir1 | switch(size) {
|
456 | 81ad8ba2 | blueswir1 | case 1: |
457 | 1a2fb1c0 | blueswir1 | ret = (int8_t) ret; |
458 | e32664fb | blueswir1 | break;
|
459 | 81ad8ba2 | blueswir1 | case 2: |
460 | 1a2fb1c0 | blueswir1 | ret = (int16_t) ret; |
461 | 1a2fb1c0 | blueswir1 | break;
|
462 | 1a2fb1c0 | blueswir1 | case 4: |
463 | 1a2fb1c0 | blueswir1 | ret = (int32_t) ret; |
464 | e32664fb | blueswir1 | break;
|
465 | 81ad8ba2 | blueswir1 | default:
|
466 | 81ad8ba2 | blueswir1 | break;
|
467 | 81ad8ba2 | blueswir1 | } |
468 | 81ad8ba2 | blueswir1 | } |
469 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
470 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
471 | 8543e2cf | blueswir1 | #endif
|
472 | 1a2fb1c0 | blueswir1 | return ret;
|
473 | e8af50a3 | bellard | } |
474 | e8af50a3 | bellard | |
475 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
476 | e8af50a3 | bellard | { |
477 | e8af50a3 | bellard | switch(asi) {
|
478 | 6c36d3fa | blueswir1 | case 2: /* SuperSparc MXCC registers */ |
479 | 1a2fb1c0 | blueswir1 | switch (addr) {
|
480 | 952a328f | blueswir1 | case 0x01c00000: /* MXCC stream data register 0 */ |
481 | 952a328f | blueswir1 | if (size == 8) |
482 | 1a2fb1c0 | blueswir1 | env->mxccdata[0] = val;
|
483 | 952a328f | blueswir1 | else
|
484 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
485 | 952a328f | blueswir1 | break;
|
486 | 952a328f | blueswir1 | case 0x01c00008: /* MXCC stream data register 1 */ |
487 | 952a328f | blueswir1 | if (size == 8) |
488 | 1a2fb1c0 | blueswir1 | env->mxccdata[1] = val;
|
489 | 952a328f | blueswir1 | else
|
490 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
491 | 952a328f | blueswir1 | break;
|
492 | 952a328f | blueswir1 | case 0x01c00010: /* MXCC stream data register 2 */ |
493 | 952a328f | blueswir1 | if (size == 8) |
494 | 1a2fb1c0 | blueswir1 | env->mxccdata[2] = val;
|
495 | 952a328f | blueswir1 | else
|
496 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
497 | 952a328f | blueswir1 | break;
|
498 | 952a328f | blueswir1 | case 0x01c00018: /* MXCC stream data register 3 */ |
499 | 952a328f | blueswir1 | if (size == 8) |
500 | 1a2fb1c0 | blueswir1 | env->mxccdata[3] = val;
|
501 | 952a328f | blueswir1 | else
|
502 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
503 | 952a328f | blueswir1 | break;
|
504 | 952a328f | blueswir1 | case 0x01c00100: /* MXCC stream source */ |
505 | 952a328f | blueswir1 | if (size == 8) |
506 | 1a2fb1c0 | blueswir1 | env->mxccregs[0] = val;
|
507 | 952a328f | blueswir1 | else
|
508 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
509 | 952a328f | blueswir1 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
510 | 952a328f | blueswir1 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); |
511 | 952a328f | blueswir1 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); |
512 | 952a328f | blueswir1 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); |
513 | 952a328f | blueswir1 | break;
|
514 | 952a328f | blueswir1 | case 0x01c00200: /* MXCC stream destination */ |
515 | 952a328f | blueswir1 | if (size == 8) |
516 | 1a2fb1c0 | blueswir1 | env->mxccregs[1] = val;
|
517 | 952a328f | blueswir1 | else
|
518 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
519 | 952a328f | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
520 | 952a328f | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); |
521 | 952a328f | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); |
522 | 952a328f | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); |
523 | 952a328f | blueswir1 | break;
|
524 | 952a328f | blueswir1 | case 0x01c00a00: /* MXCC control register */ |
525 | 952a328f | blueswir1 | if (size == 8) |
526 | 1a2fb1c0 | blueswir1 | env->mxccregs[3] = val;
|
527 | 952a328f | blueswir1 | else
|
528 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
529 | 952a328f | blueswir1 | break;
|
530 | 952a328f | blueswir1 | case 0x01c00a04: /* MXCC control register */ |
531 | 952a328f | blueswir1 | if (size == 4) |
532 | 1a2fb1c0 | blueswir1 | env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val; |
533 | 952a328f | blueswir1 | else
|
534 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
535 | 952a328f | blueswir1 | break;
|
536 | 952a328f | blueswir1 | case 0x01c00e00: /* MXCC error register */ |
537 | bbf7d96b | blueswir1 | // writing a 1 bit clears the error
|
538 | 952a328f | blueswir1 | if (size == 8) |
539 | 1a2fb1c0 | blueswir1 | env->mxccregs[6] &= ~val;
|
540 | 952a328f | blueswir1 | else
|
541 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
542 | 952a328f | blueswir1 | break;
|
543 | 952a328f | blueswir1 | case 0x01c00f00: /* MBus port address register */ |
544 | 952a328f | blueswir1 | if (size == 8) |
545 | 1a2fb1c0 | blueswir1 | env->mxccregs[7] = val;
|
546 | 952a328f | blueswir1 | else
|
547 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
548 | 952a328f | blueswir1 | break;
|
549 | 952a328f | blueswir1 | default:
|
550 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
551 | 952a328f | blueswir1 | break;
|
552 | 952a328f | blueswir1 | } |
553 | 1a2fb1c0 | blueswir1 | DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
|
554 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
555 | 952a328f | blueswir1 | dump_mxcc(env); |
556 | 952a328f | blueswir1 | #endif
|
557 | 6c36d3fa | blueswir1 | break;
|
558 | e8af50a3 | bellard | case 3: /* MMU flush */ |
559 | 0f8a249a | blueswir1 | { |
560 | 0f8a249a | blueswir1 | int mmulev;
|
561 | e80cfcfc | bellard | |
562 | 1a2fb1c0 | blueswir1 | mmulev = (addr >> 8) & 15; |
563 | 952a328f | blueswir1 | DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
564 | 0f8a249a | blueswir1 | switch (mmulev) {
|
565 | 0f8a249a | blueswir1 | case 0: // flush page |
566 | 1a2fb1c0 | blueswir1 | tlb_flush_page(env, addr & 0xfffff000);
|
567 | 0f8a249a | blueswir1 | break;
|
568 | 0f8a249a | blueswir1 | case 1: // flush segment (256k) |
569 | 0f8a249a | blueswir1 | case 2: // flush region (16M) |
570 | 0f8a249a | blueswir1 | case 3: // flush context (4G) |
571 | 0f8a249a | blueswir1 | case 4: // flush entire |
572 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
573 | 0f8a249a | blueswir1 | break;
|
574 | 0f8a249a | blueswir1 | default:
|
575 | 0f8a249a | blueswir1 | break;
|
576 | 0f8a249a | blueswir1 | } |
577 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
578 | 0f8a249a | blueswir1 | dump_mmu(env); |
579 | 55754d9e | bellard | #endif
|
580 | 0f8a249a | blueswir1 | } |
581 | 8543e2cf | blueswir1 | break;
|
582 | e8af50a3 | bellard | case 4: /* write MMU regs */ |
583 | 0f8a249a | blueswir1 | { |
584 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 8) & 0x1f; |
585 | 0f8a249a | blueswir1 | uint32_t oldreg; |
586 | 3b46e624 | ths | |
587 | 0f8a249a | blueswir1 | oldreg = env->mmuregs[reg]; |
588 | 55754d9e | bellard | switch(reg) {
|
589 | 3deaeab7 | blueswir1 | case 0: // Control Register |
590 | 3dd9a152 | blueswir1 | env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
591 | 1a2fb1c0 | blueswir1 | (val & 0x00ffffff);
|
592 | 0f8a249a | blueswir1 | // Mappings generated during no-fault mode or MMU
|
593 | 0f8a249a | blueswir1 | // disabled mode are invalid in normal mode
|
594 | 3dd9a152 | blueswir1 | if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
|
595 | 3dd9a152 | blueswir1 | (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm))) |
596 | 55754d9e | bellard | tlb_flush(env, 1);
|
597 | 55754d9e | bellard | break;
|
598 | 3deaeab7 | blueswir1 | case 1: // Context Table Pointer Register |
599 | 1a2fb1c0 | blueswir1 | env->mmuregs[reg] = val & env->mmu_ctpr_mask; |
600 | 3deaeab7 | blueswir1 | break;
|
601 | 3deaeab7 | blueswir1 | case 2: // Context Register |
602 | 1a2fb1c0 | blueswir1 | env->mmuregs[reg] = val & env->mmu_cxr_mask; |
603 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
604 | 55754d9e | bellard | /* we flush when the MMU context changes because
|
605 | 55754d9e | bellard | QEMU has no MMU context support */
|
606 | 55754d9e | bellard | tlb_flush(env, 1);
|
607 | 55754d9e | bellard | } |
608 | 55754d9e | bellard | break;
|
609 | 3deaeab7 | blueswir1 | case 3: // Synchronous Fault Status Register with Clear |
610 | 3deaeab7 | blueswir1 | case 4: // Synchronous Fault Address Register |
611 | 3deaeab7 | blueswir1 | break;
|
612 | 3deaeab7 | blueswir1 | case 0x10: // TLB Replacement Control Register |
613 | 1a2fb1c0 | blueswir1 | env->mmuregs[reg] = val & env->mmu_trcr_mask; |
614 | 55754d9e | bellard | break;
|
615 | 3deaeab7 | blueswir1 | case 0x13: // Synchronous Fault Status Register with Read and Clear |
616 | 1a2fb1c0 | blueswir1 | env->mmuregs[3] = val & env->mmu_sfsr_mask;
|
617 | 3dd9a152 | blueswir1 | break;
|
618 | 3deaeab7 | blueswir1 | case 0x14: // Synchronous Fault Address Register |
619 | 1a2fb1c0 | blueswir1 | env->mmuregs[4] = val;
|
620 | 3dd9a152 | blueswir1 | break;
|
621 | 55754d9e | bellard | default:
|
622 | 1a2fb1c0 | blueswir1 | env->mmuregs[reg] = val; |
623 | 55754d9e | bellard | break;
|
624 | 55754d9e | bellard | } |
625 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
626 | 952a328f | blueswir1 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
627 | 55754d9e | bellard | } |
628 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
629 | 0f8a249a | blueswir1 | dump_mmu(env); |
630 | 55754d9e | bellard | #endif
|
631 | 0f8a249a | blueswir1 | } |
632 | 8543e2cf | blueswir1 | break;
|
633 | 045380be | blueswir1 | case 5: // Turbosparc ITLB Diagnostic |
634 | 045380be | blueswir1 | case 6: // Turbosparc DTLB Diagnostic |
635 | 045380be | blueswir1 | case 7: // Turbosparc IOTLB Diagnostic |
636 | 045380be | blueswir1 | break;
|
637 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
638 | 81ad8ba2 | blueswir1 | switch(size) {
|
639 | 81ad8ba2 | blueswir1 | case 1: |
640 | 1a2fb1c0 | blueswir1 | stb_user(addr, val); |
641 | 81ad8ba2 | blueswir1 | break;
|
642 | 81ad8ba2 | blueswir1 | case 2: |
643 | 1a2fb1c0 | blueswir1 | stw_user(addr & ~1, val);
|
644 | 81ad8ba2 | blueswir1 | break;
|
645 | 81ad8ba2 | blueswir1 | default:
|
646 | 81ad8ba2 | blueswir1 | case 4: |
647 | 1a2fb1c0 | blueswir1 | stl_user(addr & ~3, val);
|
648 | 81ad8ba2 | blueswir1 | break;
|
649 | 81ad8ba2 | blueswir1 | case 8: |
650 | 1a2fb1c0 | blueswir1 | stq_user(addr & ~7, val);
|
651 | 81ad8ba2 | blueswir1 | break;
|
652 | 81ad8ba2 | blueswir1 | } |
653 | 81ad8ba2 | blueswir1 | break;
|
654 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
655 | 81ad8ba2 | blueswir1 | switch(size) {
|
656 | 81ad8ba2 | blueswir1 | case 1: |
657 | 1a2fb1c0 | blueswir1 | stb_kernel(addr, val); |
658 | 81ad8ba2 | blueswir1 | break;
|
659 | 81ad8ba2 | blueswir1 | case 2: |
660 | 1a2fb1c0 | blueswir1 | stw_kernel(addr & ~1, val);
|
661 | 81ad8ba2 | blueswir1 | break;
|
662 | 81ad8ba2 | blueswir1 | default:
|
663 | 81ad8ba2 | blueswir1 | case 4: |
664 | 1a2fb1c0 | blueswir1 | stl_kernel(addr & ~3, val);
|
665 | 81ad8ba2 | blueswir1 | break;
|
666 | 81ad8ba2 | blueswir1 | case 8: |
667 | 1a2fb1c0 | blueswir1 | stq_kernel(addr & ~7, val);
|
668 | 81ad8ba2 | blueswir1 | break;
|
669 | 81ad8ba2 | blueswir1 | } |
670 | 81ad8ba2 | blueswir1 | break;
|
671 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
672 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
673 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
674 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
675 | 6c36d3fa | blueswir1 | case 0x10: /* I/D-cache flush page */ |
676 | 6c36d3fa | blueswir1 | case 0x11: /* I/D-cache flush segment */ |
677 | 6c36d3fa | blueswir1 | case 0x12: /* I/D-cache flush region */ |
678 | 6c36d3fa | blueswir1 | case 0x13: /* I/D-cache flush context */ |
679 | 6c36d3fa | blueswir1 | case 0x14: /* I/D-cache flush user */ |
680 | 6c36d3fa | blueswir1 | break;
|
681 | e80cfcfc | bellard | case 0x17: /* Block copy, sta access */ |
682 | 0f8a249a | blueswir1 | { |
683 | 1a2fb1c0 | blueswir1 | // val = src
|
684 | 1a2fb1c0 | blueswir1 | // addr = dst
|
685 | 0f8a249a | blueswir1 | // copy 32 bytes
|
686 | 6c36d3fa | blueswir1 | unsigned int i; |
687 | 1a2fb1c0 | blueswir1 | uint32_t src = val & ~3, dst = addr & ~3, temp; |
688 | 3b46e624 | ths | |
689 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
690 | 6c36d3fa | blueswir1 | temp = ldl_kernel(src); |
691 | 6c36d3fa | blueswir1 | stl_kernel(dst, temp); |
692 | 6c36d3fa | blueswir1 | } |
693 | 0f8a249a | blueswir1 | } |
694 | 8543e2cf | blueswir1 | break;
|
695 | e80cfcfc | bellard | case 0x1f: /* Block fill, stda access */ |
696 | 0f8a249a | blueswir1 | { |
697 | 1a2fb1c0 | blueswir1 | // addr = dst
|
698 | 1a2fb1c0 | blueswir1 | // fill 32 bytes with val
|
699 | 6c36d3fa | blueswir1 | unsigned int i; |
700 | 1a2fb1c0 | blueswir1 | uint32_t dst = addr & 7;
|
701 | 6c36d3fa | blueswir1 | |
702 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 8, dst += 8) |
703 | 6c36d3fa | blueswir1 | stq_kernel(dst, val); |
704 | 0f8a249a | blueswir1 | } |
705 | 8543e2cf | blueswir1 | break;
|
706 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
707 | 0f8a249a | blueswir1 | { |
708 | 02aab46a | bellard | switch(size) {
|
709 | 02aab46a | bellard | case 1: |
710 | 1a2fb1c0 | blueswir1 | stb_phys(addr, val); |
711 | 02aab46a | bellard | break;
|
712 | 02aab46a | bellard | case 2: |
713 | 1a2fb1c0 | blueswir1 | stw_phys(addr & ~1, val);
|
714 | 02aab46a | bellard | break;
|
715 | 02aab46a | bellard | case 4: |
716 | 02aab46a | bellard | default:
|
717 | 1a2fb1c0 | blueswir1 | stl_phys(addr & ~3, val);
|
718 | 02aab46a | bellard | break;
|
719 | 9e61bde5 | bellard | case 8: |
720 | 1a2fb1c0 | blueswir1 | stq_phys(addr & ~7, val);
|
721 | 9e61bde5 | bellard | break;
|
722 | 02aab46a | bellard | } |
723 | 0f8a249a | blueswir1 | } |
724 | 8543e2cf | blueswir1 | break;
|
725 | 045380be | blueswir1 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
726 | 0f8a249a | blueswir1 | { |
727 | 5dcb6b91 | blueswir1 | switch(size) {
|
728 | 5dcb6b91 | blueswir1 | case 1: |
729 | 1a2fb1c0 | blueswir1 | stb_phys((target_phys_addr_t)addr |
730 | 1a2fb1c0 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
731 | 5dcb6b91 | blueswir1 | break;
|
732 | 5dcb6b91 | blueswir1 | case 2: |
733 | 1a2fb1c0 | blueswir1 | stw_phys((target_phys_addr_t)(addr & ~1)
|
734 | 1a2fb1c0 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
735 | 5dcb6b91 | blueswir1 | break;
|
736 | 5dcb6b91 | blueswir1 | case 4: |
737 | 5dcb6b91 | blueswir1 | default:
|
738 | 1a2fb1c0 | blueswir1 | stl_phys((target_phys_addr_t)(addr & ~3)
|
739 | 1a2fb1c0 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
740 | 5dcb6b91 | blueswir1 | break;
|
741 | 5dcb6b91 | blueswir1 | case 8: |
742 | 1a2fb1c0 | blueswir1 | stq_phys((target_phys_addr_t)(addr & ~7)
|
743 | 1a2fb1c0 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
744 | 5dcb6b91 | blueswir1 | break;
|
745 | 5dcb6b91 | blueswir1 | } |
746 | 0f8a249a | blueswir1 | } |
747 | 8543e2cf | blueswir1 | break;
|
748 | 045380be | blueswir1 | case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
749 | 045380be | blueswir1 | case 0x31: // store buffer data, Ross RT620 I-cache flush or |
750 | 045380be | blueswir1 | // Turbosparc snoop RAM
|
751 | 045380be | blueswir1 | case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic |
752 | 6c36d3fa | blueswir1 | case 0x36: /* I-cache flash clear */ |
753 | 6c36d3fa | blueswir1 | case 0x37: /* D-cache flash clear */ |
754 | 666c87aa | blueswir1 | case 0x38: /* breakpoint diagnostics */ |
755 | 666c87aa | blueswir1 | case 0x4c: /* breakpoint action */ |
756 | 6c36d3fa | blueswir1 | break;
|
757 | 045380be | blueswir1 | case 8: /* User code access, XXX */ |
758 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access, XXX */ |
759 | e8af50a3 | bellard | default:
|
760 | 1a2fb1c0 | blueswir1 | do_unassigned_access(addr, 1, 0, asi); |
761 | 8543e2cf | blueswir1 | break;
|
762 | e8af50a3 | bellard | } |
763 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
764 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
765 | 8543e2cf | blueswir1 | #endif
|
766 | e8af50a3 | bellard | } |
767 | e8af50a3 | bellard | |
768 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
769 | 81ad8ba2 | blueswir1 | #else /* TARGET_SPARC64 */ |
770 | 81ad8ba2 | blueswir1 | |
771 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
772 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
773 | 81ad8ba2 | blueswir1 | { |
774 | 81ad8ba2 | blueswir1 | uint64_t ret = 0;
|
775 | 1a2fb1c0 | blueswir1 | #if defined(DEBUG_ASI)
|
776 | 1a2fb1c0 | blueswir1 | target_ulong last_addr = addr; |
777 | 1a2fb1c0 | blueswir1 | #endif
|
778 | 81ad8ba2 | blueswir1 | |
779 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
780 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
781 | 81ad8ba2 | blueswir1 | |
782 | 81ad8ba2 | blueswir1 | switch (asi) {
|
783 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
784 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault |
785 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
786 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
787 | 81ad8ba2 | blueswir1 | { |
788 | 81ad8ba2 | blueswir1 | switch(size) {
|
789 | 81ad8ba2 | blueswir1 | case 1: |
790 | 1a2fb1c0 | blueswir1 | ret = ldub_raw(addr); |
791 | 81ad8ba2 | blueswir1 | break;
|
792 | 81ad8ba2 | blueswir1 | case 2: |
793 | 1a2fb1c0 | blueswir1 | ret = lduw_raw(addr & ~1);
|
794 | 81ad8ba2 | blueswir1 | break;
|
795 | 81ad8ba2 | blueswir1 | case 4: |
796 | 1a2fb1c0 | blueswir1 | ret = ldl_raw(addr & ~3);
|
797 | 81ad8ba2 | blueswir1 | break;
|
798 | 81ad8ba2 | blueswir1 | default:
|
799 | 81ad8ba2 | blueswir1 | case 8: |
800 | 1a2fb1c0 | blueswir1 | ret = ldq_raw(addr & ~7);
|
801 | 81ad8ba2 | blueswir1 | break;
|
802 | 81ad8ba2 | blueswir1 | } |
803 | 81ad8ba2 | blueswir1 | } |
804 | 81ad8ba2 | blueswir1 | break;
|
805 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
806 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault |
807 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
808 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
809 | 81ad8ba2 | blueswir1 | // XXX
|
810 | 81ad8ba2 | blueswir1 | break;
|
811 | 81ad8ba2 | blueswir1 | default:
|
812 | 81ad8ba2 | blueswir1 | break;
|
813 | 81ad8ba2 | blueswir1 | } |
814 | 81ad8ba2 | blueswir1 | |
815 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
816 | 81ad8ba2 | blueswir1 | switch (asi) {
|
817 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
818 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
819 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
820 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
821 | 81ad8ba2 | blueswir1 | switch(size) {
|
822 | 81ad8ba2 | blueswir1 | case 2: |
823 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
824 | e32664fb | blueswir1 | break;
|
825 | 81ad8ba2 | blueswir1 | case 4: |
826 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
827 | e32664fb | blueswir1 | break;
|
828 | 81ad8ba2 | blueswir1 | case 8: |
829 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
830 | e32664fb | blueswir1 | break;
|
831 | 81ad8ba2 | blueswir1 | default:
|
832 | 81ad8ba2 | blueswir1 | break;
|
833 | 81ad8ba2 | blueswir1 | } |
834 | 81ad8ba2 | blueswir1 | default:
|
835 | 81ad8ba2 | blueswir1 | break;
|
836 | 81ad8ba2 | blueswir1 | } |
837 | 81ad8ba2 | blueswir1 | |
838 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
839 | 81ad8ba2 | blueswir1 | if (sign) {
|
840 | 81ad8ba2 | blueswir1 | switch(size) {
|
841 | 81ad8ba2 | blueswir1 | case 1: |
842 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
843 | e32664fb | blueswir1 | break;
|
844 | 81ad8ba2 | blueswir1 | case 2: |
845 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
846 | e32664fb | blueswir1 | break;
|
847 | 81ad8ba2 | blueswir1 | case 4: |
848 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
849 | e32664fb | blueswir1 | break;
|
850 | 81ad8ba2 | blueswir1 | default:
|
851 | 81ad8ba2 | blueswir1 | break;
|
852 | 81ad8ba2 | blueswir1 | } |
853 | 81ad8ba2 | blueswir1 | } |
854 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
855 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
856 | 1a2fb1c0 | blueswir1 | #endif
|
857 | 1a2fb1c0 | blueswir1 | return ret;
|
858 | 81ad8ba2 | blueswir1 | } |
859 | 81ad8ba2 | blueswir1 | |
860 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
861 | 81ad8ba2 | blueswir1 | { |
862 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
863 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
864 | 1a2fb1c0 | blueswir1 | #endif
|
865 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
866 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
867 | 81ad8ba2 | blueswir1 | |
868 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
869 | 81ad8ba2 | blueswir1 | switch (asi) {
|
870 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
871 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
872 | 81ad8ba2 | blueswir1 | switch(size) {
|
873 | 81ad8ba2 | blueswir1 | case 2: |
874 | 1a2fb1c0 | blueswir1 | addr = bswap16(addr); |
875 | e32664fb | blueswir1 | break;
|
876 | 81ad8ba2 | blueswir1 | case 4: |
877 | 1a2fb1c0 | blueswir1 | addr = bswap32(addr); |
878 | e32664fb | blueswir1 | break;
|
879 | 81ad8ba2 | blueswir1 | case 8: |
880 | 1a2fb1c0 | blueswir1 | addr = bswap64(addr); |
881 | e32664fb | blueswir1 | break;
|
882 | 81ad8ba2 | blueswir1 | default:
|
883 | 81ad8ba2 | blueswir1 | break;
|
884 | 81ad8ba2 | blueswir1 | } |
885 | 81ad8ba2 | blueswir1 | default:
|
886 | 81ad8ba2 | blueswir1 | break;
|
887 | 81ad8ba2 | blueswir1 | } |
888 | 81ad8ba2 | blueswir1 | |
889 | 81ad8ba2 | blueswir1 | switch(asi) {
|
890 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
891 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
892 | 81ad8ba2 | blueswir1 | { |
893 | 81ad8ba2 | blueswir1 | switch(size) {
|
894 | 81ad8ba2 | blueswir1 | case 1: |
895 | 1a2fb1c0 | blueswir1 | stb_raw(addr, val); |
896 | 81ad8ba2 | blueswir1 | break;
|
897 | 81ad8ba2 | blueswir1 | case 2: |
898 | 1a2fb1c0 | blueswir1 | stw_raw(addr & ~1, val);
|
899 | 81ad8ba2 | blueswir1 | break;
|
900 | 81ad8ba2 | blueswir1 | case 4: |
901 | 1a2fb1c0 | blueswir1 | stl_raw(addr & ~3, val);
|
902 | 81ad8ba2 | blueswir1 | break;
|
903 | 81ad8ba2 | blueswir1 | case 8: |
904 | 81ad8ba2 | blueswir1 | default:
|
905 | 1a2fb1c0 | blueswir1 | stq_raw(addr & ~7, val);
|
906 | 81ad8ba2 | blueswir1 | break;
|
907 | 81ad8ba2 | blueswir1 | } |
908 | 81ad8ba2 | blueswir1 | } |
909 | 81ad8ba2 | blueswir1 | break;
|
910 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
911 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
912 | 81ad8ba2 | blueswir1 | // XXX
|
913 | 81ad8ba2 | blueswir1 | return;
|
914 | 81ad8ba2 | blueswir1 | |
915 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault, RO |
916 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault, RO |
917 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE, RO |
918 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE, RO |
919 | 81ad8ba2 | blueswir1 | default:
|
920 | 1a2fb1c0 | blueswir1 | do_unassigned_access(addr, 1, 0, 1); |
921 | 81ad8ba2 | blueswir1 | return;
|
922 | 81ad8ba2 | blueswir1 | } |
923 | 81ad8ba2 | blueswir1 | } |
924 | 81ad8ba2 | blueswir1 | |
925 | 81ad8ba2 | blueswir1 | #else /* CONFIG_USER_ONLY */ |
926 | 3475187d | bellard | |
927 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
928 | 3475187d | bellard | { |
929 | 83469015 | bellard | uint64_t ret = 0;
|
930 | 1a2fb1c0 | blueswir1 | #if defined(DEBUG_ASI)
|
931 | 1a2fb1c0 | blueswir1 | target_ulong last_addr = addr; |
932 | 1a2fb1c0 | blueswir1 | #endif
|
933 | 3475187d | bellard | |
934 | 6f27aba6 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
935 | 20b749f6 | blueswir1 | || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
936 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
937 | 3475187d | bellard | |
938 | 3475187d | bellard | switch (asi) {
|
939 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
940 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
941 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
942 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault |
943 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
944 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
945 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
946 | 6f27aba6 | blueswir1 | if (env->hpstate & HS_PRIV) {
|
947 | 6f27aba6 | blueswir1 | switch(size) {
|
948 | 6f27aba6 | blueswir1 | case 1: |
949 | 1a2fb1c0 | blueswir1 | ret = ldub_hypv(addr); |
950 | 6f27aba6 | blueswir1 | break;
|
951 | 6f27aba6 | blueswir1 | case 2: |
952 | 1a2fb1c0 | blueswir1 | ret = lduw_hypv(addr & ~1);
|
953 | 6f27aba6 | blueswir1 | break;
|
954 | 6f27aba6 | blueswir1 | case 4: |
955 | 1a2fb1c0 | blueswir1 | ret = ldl_hypv(addr & ~3);
|
956 | 6f27aba6 | blueswir1 | break;
|
957 | 6f27aba6 | blueswir1 | default:
|
958 | 6f27aba6 | blueswir1 | case 8: |
959 | 1a2fb1c0 | blueswir1 | ret = ldq_hypv(addr & ~7);
|
960 | 6f27aba6 | blueswir1 | break;
|
961 | 6f27aba6 | blueswir1 | } |
962 | 6f27aba6 | blueswir1 | } else {
|
963 | 6f27aba6 | blueswir1 | switch(size) {
|
964 | 6f27aba6 | blueswir1 | case 1: |
965 | 1a2fb1c0 | blueswir1 | ret = ldub_kernel(addr); |
966 | 6f27aba6 | blueswir1 | break;
|
967 | 6f27aba6 | blueswir1 | case 2: |
968 | 1a2fb1c0 | blueswir1 | ret = lduw_kernel(addr & ~1);
|
969 | 6f27aba6 | blueswir1 | break;
|
970 | 6f27aba6 | blueswir1 | case 4: |
971 | 1a2fb1c0 | blueswir1 | ret = ldl_kernel(addr & ~3);
|
972 | 6f27aba6 | blueswir1 | break;
|
973 | 6f27aba6 | blueswir1 | default:
|
974 | 6f27aba6 | blueswir1 | case 8: |
975 | 1a2fb1c0 | blueswir1 | ret = ldq_kernel(addr & ~7);
|
976 | 6f27aba6 | blueswir1 | break;
|
977 | 6f27aba6 | blueswir1 | } |
978 | 81ad8ba2 | blueswir1 | } |
979 | 81ad8ba2 | blueswir1 | } else {
|
980 | 81ad8ba2 | blueswir1 | switch(size) {
|
981 | 81ad8ba2 | blueswir1 | case 1: |
982 | 1a2fb1c0 | blueswir1 | ret = ldub_user(addr); |
983 | 81ad8ba2 | blueswir1 | break;
|
984 | 81ad8ba2 | blueswir1 | case 2: |
985 | 1a2fb1c0 | blueswir1 | ret = lduw_user(addr & ~1);
|
986 | 81ad8ba2 | blueswir1 | break;
|
987 | 81ad8ba2 | blueswir1 | case 4: |
988 | 1a2fb1c0 | blueswir1 | ret = ldl_user(addr & ~3);
|
989 | 81ad8ba2 | blueswir1 | break;
|
990 | 81ad8ba2 | blueswir1 | default:
|
991 | 81ad8ba2 | blueswir1 | case 8: |
992 | 1a2fb1c0 | blueswir1 | ret = ldq_user(addr & ~7);
|
993 | 81ad8ba2 | blueswir1 | break;
|
994 | 81ad8ba2 | blueswir1 | } |
995 | 81ad8ba2 | blueswir1 | } |
996 | 81ad8ba2 | blueswir1 | break;
|
997 | 3475187d | bellard | case 0x14: // Bypass |
998 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
999 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
1000 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
1001 | 0f8a249a | blueswir1 | { |
1002 | 02aab46a | bellard | switch(size) {
|
1003 | 02aab46a | bellard | case 1: |
1004 | 1a2fb1c0 | blueswir1 | ret = ldub_phys(addr); |
1005 | 02aab46a | bellard | break;
|
1006 | 02aab46a | bellard | case 2: |
1007 | 1a2fb1c0 | blueswir1 | ret = lduw_phys(addr & ~1);
|
1008 | 02aab46a | bellard | break;
|
1009 | 02aab46a | bellard | case 4: |
1010 | 1a2fb1c0 | blueswir1 | ret = ldl_phys(addr & ~3);
|
1011 | 02aab46a | bellard | break;
|
1012 | 02aab46a | bellard | default:
|
1013 | 02aab46a | bellard | case 8: |
1014 | 1a2fb1c0 | blueswir1 | ret = ldq_phys(addr & ~7);
|
1015 | 02aab46a | bellard | break;
|
1016 | 02aab46a | bellard | } |
1017 | 0f8a249a | blueswir1 | break;
|
1018 | 0f8a249a | blueswir1 | } |
1019 | 83469015 | bellard | case 0x04: // Nucleus |
1020 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
1021 | 83469015 | bellard | case 0x11: // As if user secondary |
1022 | 83469015 | bellard | case 0x19: // As if user secondary LE |
1023 | 83469015 | bellard | case 0x24: // Nucleus quad LDD 128 bit atomic |
1024 | 83469015 | bellard | case 0x2c: // Nucleus quad LDD 128 bit atomic |
1025 | 83469015 | bellard | case 0x4a: // UPA config |
1026 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
1027 | 83469015 | bellard | case 0x83: // Secondary no-fault |
1028 | 83469015 | bellard | case 0x89: // Secondary LE |
1029 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE |
1030 | 0f8a249a | blueswir1 | // XXX
|
1031 | 0f8a249a | blueswir1 | break;
|
1032 | 3475187d | bellard | case 0x45: // LSU |
1033 | 0f8a249a | blueswir1 | ret = env->lsu; |
1034 | 0f8a249a | blueswir1 | break;
|
1035 | 3475187d | bellard | case 0x50: // I-MMU regs |
1036 | 0f8a249a | blueswir1 | { |
1037 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
1038 | 3475187d | bellard | |
1039 | 0f8a249a | blueswir1 | ret = env->immuregs[reg]; |
1040 | 0f8a249a | blueswir1 | break;
|
1041 | 0f8a249a | blueswir1 | } |
1042 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer |
1043 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer |
1044 | 3475187d | bellard | case 0x55: // I-MMU data access |
1045 | 0f8a249a | blueswir1 | // XXX
|
1046 | 0f8a249a | blueswir1 | break;
|
1047 | 83469015 | bellard | case 0x56: // I-MMU tag read |
1048 | 0f8a249a | blueswir1 | { |
1049 | 0f8a249a | blueswir1 | unsigned int i; |
1050 | 0f8a249a | blueswir1 | |
1051 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
1052 | 0f8a249a | blueswir1 | // Valid, ctx match, vaddr match
|
1053 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
1054 | 1a2fb1c0 | blueswir1 | env->itlb_tag[i] == addr) { |
1055 | 0f8a249a | blueswir1 | ret = env->itlb_tag[i]; |
1056 | 0f8a249a | blueswir1 | break;
|
1057 | 0f8a249a | blueswir1 | } |
1058 | 0f8a249a | blueswir1 | } |
1059 | 0f8a249a | blueswir1 | break;
|
1060 | 0f8a249a | blueswir1 | } |
1061 | 3475187d | bellard | case 0x58: // D-MMU regs |
1062 | 0f8a249a | blueswir1 | { |
1063 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
1064 | 3475187d | bellard | |
1065 | 0f8a249a | blueswir1 | ret = env->dmmuregs[reg]; |
1066 | 0f8a249a | blueswir1 | break;
|
1067 | 0f8a249a | blueswir1 | } |
1068 | 83469015 | bellard | case 0x5e: // D-MMU tag read |
1069 | 0f8a249a | blueswir1 | { |
1070 | 0f8a249a | blueswir1 | unsigned int i; |
1071 | 0f8a249a | blueswir1 | |
1072 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
1073 | 0f8a249a | blueswir1 | // Valid, ctx match, vaddr match
|
1074 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
1075 | 1a2fb1c0 | blueswir1 | env->dtlb_tag[i] == addr) { |
1076 | 0f8a249a | blueswir1 | ret = env->dtlb_tag[i]; |
1077 | 0f8a249a | blueswir1 | break;
|
1078 | 0f8a249a | blueswir1 | } |
1079 | 0f8a249a | blueswir1 | } |
1080 | 0f8a249a | blueswir1 | break;
|
1081 | 0f8a249a | blueswir1 | } |
1082 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer |
1083 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer |
1084 | 3475187d | bellard | case 0x5b: // D-MMU data pointer |
1085 | 3475187d | bellard | case 0x5d: // D-MMU data access |
1086 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
1087 | 83469015 | bellard | case 0x49: // Interrupt data receive |
1088 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
1089 | 0f8a249a | blueswir1 | // XXX
|
1090 | 0f8a249a | blueswir1 | break;
|
1091 | 3475187d | bellard | case 0x54: // I-MMU data in, WO |
1092 | 3475187d | bellard | case 0x57: // I-MMU demap, WO |
1093 | 3475187d | bellard | case 0x5c: // D-MMU data in, WO |
1094 | 3475187d | bellard | case 0x5f: // D-MMU demap, WO |
1095 | 83469015 | bellard | case 0x77: // Interrupt vector, WO |
1096 | 3475187d | bellard | default:
|
1097 | 1a2fb1c0 | blueswir1 | do_unassigned_access(addr, 0, 0, 1); |
1098 | 0f8a249a | blueswir1 | ret = 0;
|
1099 | 0f8a249a | blueswir1 | break;
|
1100 | 3475187d | bellard | } |
1101 | 81ad8ba2 | blueswir1 | |
1102 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
1103 | 81ad8ba2 | blueswir1 | switch (asi) {
|
1104 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
1105 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
1106 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
1107 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
1108 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
1109 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
1110 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
1111 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
1112 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
1113 | 81ad8ba2 | blueswir1 | switch(size) {
|
1114 | 81ad8ba2 | blueswir1 | case 2: |
1115 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
1116 | e32664fb | blueswir1 | break;
|
1117 | 81ad8ba2 | blueswir1 | case 4: |
1118 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
1119 | e32664fb | blueswir1 | break;
|
1120 | 81ad8ba2 | blueswir1 | case 8: |
1121 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
1122 | e32664fb | blueswir1 | break;
|
1123 | 81ad8ba2 | blueswir1 | default:
|
1124 | 81ad8ba2 | blueswir1 | break;
|
1125 | 81ad8ba2 | blueswir1 | } |
1126 | 81ad8ba2 | blueswir1 | default:
|
1127 | 81ad8ba2 | blueswir1 | break;
|
1128 | 81ad8ba2 | blueswir1 | } |
1129 | 81ad8ba2 | blueswir1 | |
1130 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
1131 | 81ad8ba2 | blueswir1 | if (sign) {
|
1132 | 81ad8ba2 | blueswir1 | switch(size) {
|
1133 | 81ad8ba2 | blueswir1 | case 1: |
1134 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
1135 | e32664fb | blueswir1 | break;
|
1136 | 81ad8ba2 | blueswir1 | case 2: |
1137 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
1138 | e32664fb | blueswir1 | break;
|
1139 | 81ad8ba2 | blueswir1 | case 4: |
1140 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
1141 | e32664fb | blueswir1 | break;
|
1142 | 81ad8ba2 | blueswir1 | default:
|
1143 | 81ad8ba2 | blueswir1 | break;
|
1144 | 81ad8ba2 | blueswir1 | } |
1145 | 81ad8ba2 | blueswir1 | } |
1146 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
1147 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
1148 | 1a2fb1c0 | blueswir1 | #endif
|
1149 | 1a2fb1c0 | blueswir1 | return ret;
|
1150 | 3475187d | bellard | } |
1151 | 3475187d | bellard | |
1152 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
1153 | 3475187d | bellard | { |
1154 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
1155 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
1156 | 1a2fb1c0 | blueswir1 | #endif
|
1157 | 6f27aba6 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1158 | 20b749f6 | blueswir1 | || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
1159 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
1160 | 3475187d | bellard | |
1161 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
1162 | 81ad8ba2 | blueswir1 | switch (asi) {
|
1163 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
1164 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
1165 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
1166 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
1167 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
1168 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
1169 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
1170 | 81ad8ba2 | blueswir1 | switch(size) {
|
1171 | 81ad8ba2 | blueswir1 | case 2: |
1172 | 1a2fb1c0 | blueswir1 | addr = bswap16(addr); |
1173 | e32664fb | blueswir1 | break;
|
1174 | 81ad8ba2 | blueswir1 | case 4: |
1175 | 1a2fb1c0 | blueswir1 | addr = bswap32(addr); |
1176 | e32664fb | blueswir1 | break;
|
1177 | 81ad8ba2 | blueswir1 | case 8: |
1178 | 1a2fb1c0 | blueswir1 | addr = bswap64(addr); |
1179 | e32664fb | blueswir1 | break;
|
1180 | 81ad8ba2 | blueswir1 | default:
|
1181 | 81ad8ba2 | blueswir1 | break;
|
1182 | 81ad8ba2 | blueswir1 | } |
1183 | 81ad8ba2 | blueswir1 | default:
|
1184 | 81ad8ba2 | blueswir1 | break;
|
1185 | 81ad8ba2 | blueswir1 | } |
1186 | 81ad8ba2 | blueswir1 | |
1187 | 3475187d | bellard | switch(asi) {
|
1188 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
1189 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
1190 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
1191 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
1192 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
1193 | 6f27aba6 | blueswir1 | if (env->hpstate & HS_PRIV) {
|
1194 | 6f27aba6 | blueswir1 | switch(size) {
|
1195 | 6f27aba6 | blueswir1 | case 1: |
1196 | 1a2fb1c0 | blueswir1 | stb_hypv(addr, val); |
1197 | 6f27aba6 | blueswir1 | break;
|
1198 | 6f27aba6 | blueswir1 | case 2: |
1199 | 1a2fb1c0 | blueswir1 | stw_hypv(addr & ~1, val);
|
1200 | 6f27aba6 | blueswir1 | break;
|
1201 | 6f27aba6 | blueswir1 | case 4: |
1202 | 1a2fb1c0 | blueswir1 | stl_hypv(addr & ~3, val);
|
1203 | 6f27aba6 | blueswir1 | break;
|
1204 | 6f27aba6 | blueswir1 | case 8: |
1205 | 6f27aba6 | blueswir1 | default:
|
1206 | 1a2fb1c0 | blueswir1 | stq_hypv(addr & ~7, val);
|
1207 | 6f27aba6 | blueswir1 | break;
|
1208 | 6f27aba6 | blueswir1 | } |
1209 | 6f27aba6 | blueswir1 | } else {
|
1210 | 6f27aba6 | blueswir1 | switch(size) {
|
1211 | 6f27aba6 | blueswir1 | case 1: |
1212 | 1a2fb1c0 | blueswir1 | stb_kernel(addr, val); |
1213 | 6f27aba6 | blueswir1 | break;
|
1214 | 6f27aba6 | blueswir1 | case 2: |
1215 | 1a2fb1c0 | blueswir1 | stw_kernel(addr & ~1, val);
|
1216 | 6f27aba6 | blueswir1 | break;
|
1217 | 6f27aba6 | blueswir1 | case 4: |
1218 | 1a2fb1c0 | blueswir1 | stl_kernel(addr & ~3, val);
|
1219 | 6f27aba6 | blueswir1 | break;
|
1220 | 6f27aba6 | blueswir1 | case 8: |
1221 | 6f27aba6 | blueswir1 | default:
|
1222 | 1a2fb1c0 | blueswir1 | stq_kernel(addr & ~7, val);
|
1223 | 6f27aba6 | blueswir1 | break;
|
1224 | 6f27aba6 | blueswir1 | } |
1225 | 81ad8ba2 | blueswir1 | } |
1226 | 81ad8ba2 | blueswir1 | } else {
|
1227 | 81ad8ba2 | blueswir1 | switch(size) {
|
1228 | 81ad8ba2 | blueswir1 | case 1: |
1229 | 1a2fb1c0 | blueswir1 | stb_user(addr, val); |
1230 | 81ad8ba2 | blueswir1 | break;
|
1231 | 81ad8ba2 | blueswir1 | case 2: |
1232 | 1a2fb1c0 | blueswir1 | stw_user(addr & ~1, val);
|
1233 | 81ad8ba2 | blueswir1 | break;
|
1234 | 81ad8ba2 | blueswir1 | case 4: |
1235 | 1a2fb1c0 | blueswir1 | stl_user(addr & ~3, val);
|
1236 | 81ad8ba2 | blueswir1 | break;
|
1237 | 81ad8ba2 | blueswir1 | case 8: |
1238 | 81ad8ba2 | blueswir1 | default:
|
1239 | 1a2fb1c0 | blueswir1 | stq_user(addr & ~7, val);
|
1240 | 81ad8ba2 | blueswir1 | break;
|
1241 | 81ad8ba2 | blueswir1 | } |
1242 | 81ad8ba2 | blueswir1 | } |
1243 | 81ad8ba2 | blueswir1 | break;
|
1244 | 3475187d | bellard | case 0x14: // Bypass |
1245 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
1246 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
1247 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
1248 | 0f8a249a | blueswir1 | { |
1249 | 02aab46a | bellard | switch(size) {
|
1250 | 02aab46a | bellard | case 1: |
1251 | 1a2fb1c0 | blueswir1 | stb_phys(addr, val); |
1252 | 02aab46a | bellard | break;
|
1253 | 02aab46a | bellard | case 2: |
1254 | 1a2fb1c0 | blueswir1 | stw_phys(addr & ~1, val);
|
1255 | 02aab46a | bellard | break;
|
1256 | 02aab46a | bellard | case 4: |
1257 | 1a2fb1c0 | blueswir1 | stl_phys(addr & ~3, val);
|
1258 | 02aab46a | bellard | break;
|
1259 | 02aab46a | bellard | case 8: |
1260 | 02aab46a | bellard | default:
|
1261 | 1a2fb1c0 | blueswir1 | stq_phys(addr & ~7, val);
|
1262 | 02aab46a | bellard | break;
|
1263 | 02aab46a | bellard | } |
1264 | 0f8a249a | blueswir1 | } |
1265 | 0f8a249a | blueswir1 | return;
|
1266 | 83469015 | bellard | case 0x04: // Nucleus |
1267 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
1268 | 83469015 | bellard | case 0x11: // As if user secondary |
1269 | 83469015 | bellard | case 0x19: // As if user secondary LE |
1270 | 83469015 | bellard | case 0x24: // Nucleus quad LDD 128 bit atomic |
1271 | 83469015 | bellard | case 0x2c: // Nucleus quad LDD 128 bit atomic |
1272 | 83469015 | bellard | case 0x4a: // UPA config |
1273 | 51996525 | blueswir1 | case 0x81: // Secondary |
1274 | 83469015 | bellard | case 0x89: // Secondary LE |
1275 | 0f8a249a | blueswir1 | // XXX
|
1276 | 0f8a249a | blueswir1 | return;
|
1277 | 3475187d | bellard | case 0x45: // LSU |
1278 | 0f8a249a | blueswir1 | { |
1279 | 0f8a249a | blueswir1 | uint64_t oldreg; |
1280 | 0f8a249a | blueswir1 | |
1281 | 0f8a249a | blueswir1 | oldreg = env->lsu; |
1282 | 1a2fb1c0 | blueswir1 | env->lsu = val & (DMMU_E | IMMU_E); |
1283 | 0f8a249a | blueswir1 | // Mappings generated during D/I MMU disabled mode are
|
1284 | 0f8a249a | blueswir1 | // invalid in normal mode
|
1285 | 0f8a249a | blueswir1 | if (oldreg != env->lsu) {
|
1286 | 952a328f | blueswir1 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
1287 | 83469015 | bellard | #ifdef DEBUG_MMU
|
1288 | 0f8a249a | blueswir1 | dump_mmu(env); |
1289 | 83469015 | bellard | #endif
|
1290 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
1291 | 0f8a249a | blueswir1 | } |
1292 | 0f8a249a | blueswir1 | return;
|
1293 | 0f8a249a | blueswir1 | } |
1294 | 3475187d | bellard | case 0x50: // I-MMU regs |
1295 | 0f8a249a | blueswir1 | { |
1296 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
1297 | 0f8a249a | blueswir1 | uint64_t oldreg; |
1298 | 3b46e624 | ths | |
1299 | 0f8a249a | blueswir1 | oldreg = env->immuregs[reg]; |
1300 | 3475187d | bellard | switch(reg) {
|
1301 | 3475187d | bellard | case 0: // RO |
1302 | 3475187d | bellard | case 4: |
1303 | 3475187d | bellard | return;
|
1304 | 3475187d | bellard | case 1: // Not in I-MMU |
1305 | 3475187d | bellard | case 2: |
1306 | 3475187d | bellard | case 7: |
1307 | 3475187d | bellard | case 8: |
1308 | 3475187d | bellard | return;
|
1309 | 3475187d | bellard | case 3: // SFSR |
1310 | 1a2fb1c0 | blueswir1 | if ((val & 1) == 0) |
1311 | 1a2fb1c0 | blueswir1 | val = 0; // Clear SFSR |
1312 | 3475187d | bellard | break;
|
1313 | 3475187d | bellard | case 5: // TSB access |
1314 | 3475187d | bellard | case 6: // Tag access |
1315 | 3475187d | bellard | default:
|
1316 | 3475187d | bellard | break;
|
1317 | 3475187d | bellard | } |
1318 | 1a2fb1c0 | blueswir1 | env->immuregs[reg] = val; |
1319 | 3475187d | bellard | if (oldreg != env->immuregs[reg]) {
|
1320 | 952a328f | blueswir1 | DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
1321 | 3475187d | bellard | } |
1322 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
1323 | 0f8a249a | blueswir1 | dump_mmu(env); |
1324 | 3475187d | bellard | #endif
|
1325 | 0f8a249a | blueswir1 | return;
|
1326 | 0f8a249a | blueswir1 | } |
1327 | 3475187d | bellard | case 0x54: // I-MMU data in |
1328 | 0f8a249a | blueswir1 | { |
1329 | 0f8a249a | blueswir1 | unsigned int i; |
1330 | 0f8a249a | blueswir1 | |
1331 | 0f8a249a | blueswir1 | // Try finding an invalid entry
|
1332 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
1333 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1334 | 0f8a249a | blueswir1 | env->itlb_tag[i] = env->immuregs[6];
|
1335 | 1a2fb1c0 | blueswir1 | env->itlb_tte[i] = val; |
1336 | 0f8a249a | blueswir1 | return;
|
1337 | 0f8a249a | blueswir1 | } |
1338 | 0f8a249a | blueswir1 | } |
1339 | 0f8a249a | blueswir1 | // Try finding an unlocked entry
|
1340 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
1341 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x40) == 0) { |
1342 | 0f8a249a | blueswir1 | env->itlb_tag[i] = env->immuregs[6];
|
1343 | 1a2fb1c0 | blueswir1 | env->itlb_tte[i] = val; |
1344 | 0f8a249a | blueswir1 | return;
|
1345 | 0f8a249a | blueswir1 | } |
1346 | 0f8a249a | blueswir1 | } |
1347 | 0f8a249a | blueswir1 | // error state?
|
1348 | 0f8a249a | blueswir1 | return;
|
1349 | 0f8a249a | blueswir1 | } |
1350 | 3475187d | bellard | case 0x55: // I-MMU data access |
1351 | 0f8a249a | blueswir1 | { |
1352 | 1a2fb1c0 | blueswir1 | unsigned int i = (addr >> 3) & 0x3f; |
1353 | 3475187d | bellard | |
1354 | 0f8a249a | blueswir1 | env->itlb_tag[i] = env->immuregs[6];
|
1355 | 1a2fb1c0 | blueswir1 | env->itlb_tte[i] = val; |
1356 | 0f8a249a | blueswir1 | return;
|
1357 | 0f8a249a | blueswir1 | } |
1358 | 3475187d | bellard | case 0x57: // I-MMU demap |
1359 | 0f8a249a | blueswir1 | // XXX
|
1360 | 0f8a249a | blueswir1 | return;
|
1361 | 3475187d | bellard | case 0x58: // D-MMU regs |
1362 | 0f8a249a | blueswir1 | { |
1363 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
1364 | 0f8a249a | blueswir1 | uint64_t oldreg; |
1365 | 3b46e624 | ths | |
1366 | 0f8a249a | blueswir1 | oldreg = env->dmmuregs[reg]; |
1367 | 3475187d | bellard | switch(reg) {
|
1368 | 3475187d | bellard | case 0: // RO |
1369 | 3475187d | bellard | case 4: |
1370 | 3475187d | bellard | return;
|
1371 | 3475187d | bellard | case 3: // SFSR |
1372 | 1a2fb1c0 | blueswir1 | if ((val & 1) == 0) { |
1373 | 1a2fb1c0 | blueswir1 | val = 0; // Clear SFSR, Fault address |
1374 | 0f8a249a | blueswir1 | env->dmmuregs[4] = 0; |
1375 | 0f8a249a | blueswir1 | } |
1376 | 1a2fb1c0 | blueswir1 | env->dmmuregs[reg] = val; |
1377 | 3475187d | bellard | break;
|
1378 | 3475187d | bellard | case 1: // Primary context |
1379 | 3475187d | bellard | case 2: // Secondary context |
1380 | 3475187d | bellard | case 5: // TSB access |
1381 | 3475187d | bellard | case 6: // Tag access |
1382 | 3475187d | bellard | case 7: // Virtual Watchpoint |
1383 | 3475187d | bellard | case 8: // Physical Watchpoint |
1384 | 3475187d | bellard | default:
|
1385 | 3475187d | bellard | break;
|
1386 | 3475187d | bellard | } |
1387 | 1a2fb1c0 | blueswir1 | env->dmmuregs[reg] = val; |
1388 | 3475187d | bellard | if (oldreg != env->dmmuregs[reg]) {
|
1389 | 952a328f | blueswir1 | DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
1390 | 3475187d | bellard | } |
1391 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
1392 | 0f8a249a | blueswir1 | dump_mmu(env); |
1393 | 3475187d | bellard | #endif
|
1394 | 0f8a249a | blueswir1 | return;
|
1395 | 0f8a249a | blueswir1 | } |
1396 | 3475187d | bellard | case 0x5c: // D-MMU data in |
1397 | 0f8a249a | blueswir1 | { |
1398 | 0f8a249a | blueswir1 | unsigned int i; |
1399 | 0f8a249a | blueswir1 | |
1400 | 0f8a249a | blueswir1 | // Try finding an invalid entry
|
1401 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
1402 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1403 | 0f8a249a | blueswir1 | env->dtlb_tag[i] = env->dmmuregs[6];
|
1404 | 1a2fb1c0 | blueswir1 | env->dtlb_tte[i] = val; |
1405 | 0f8a249a | blueswir1 | return;
|
1406 | 0f8a249a | blueswir1 | } |
1407 | 0f8a249a | blueswir1 | } |
1408 | 0f8a249a | blueswir1 | // Try finding an unlocked entry
|
1409 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
1410 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x40) == 0) { |
1411 | 0f8a249a | blueswir1 | env->dtlb_tag[i] = env->dmmuregs[6];
|
1412 | 1a2fb1c0 | blueswir1 | env->dtlb_tte[i] = val; |
1413 | 0f8a249a | blueswir1 | return;
|
1414 | 0f8a249a | blueswir1 | } |
1415 | 0f8a249a | blueswir1 | } |
1416 | 0f8a249a | blueswir1 | // error state?
|
1417 | 0f8a249a | blueswir1 | return;
|
1418 | 0f8a249a | blueswir1 | } |
1419 | 3475187d | bellard | case 0x5d: // D-MMU data access |
1420 | 0f8a249a | blueswir1 | { |
1421 | 1a2fb1c0 | blueswir1 | unsigned int i = (addr >> 3) & 0x3f; |
1422 | 3475187d | bellard | |
1423 | 0f8a249a | blueswir1 | env->dtlb_tag[i] = env->dmmuregs[6];
|
1424 | 1a2fb1c0 | blueswir1 | env->dtlb_tte[i] = val; |
1425 | 0f8a249a | blueswir1 | return;
|
1426 | 0f8a249a | blueswir1 | } |
1427 | 3475187d | bellard | case 0x5f: // D-MMU demap |
1428 | 83469015 | bellard | case 0x49: // Interrupt data receive |
1429 | 0f8a249a | blueswir1 | // XXX
|
1430 | 0f8a249a | blueswir1 | return;
|
1431 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer, RO |
1432 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer, RO |
1433 | 3475187d | bellard | case 0x56: // I-MMU tag read, RO |
1434 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer, RO |
1435 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer, RO |
1436 | 3475187d | bellard | case 0x5b: // D-MMU data pointer, RO |
1437 | 3475187d | bellard | case 0x5e: // D-MMU tag read, RO |
1438 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
1439 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
1440 | 83469015 | bellard | case 0x82: // Primary no-fault, RO |
1441 | 83469015 | bellard | case 0x83: // Secondary no-fault, RO |
1442 | 83469015 | bellard | case 0x8a: // Primary no-fault LE, RO |
1443 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE, RO |
1444 | 3475187d | bellard | default:
|
1445 | 1a2fb1c0 | blueswir1 | do_unassigned_access(addr, 1, 0, 1); |
1446 | 0f8a249a | blueswir1 | return;
|
1447 | 3475187d | bellard | } |
1448 | 3475187d | bellard | } |
1449 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
1450 | 3391c818 | blueswir1 | |
1451 | 1a2fb1c0 | blueswir1 | void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
1452 | 3391c818 | blueswir1 | { |
1453 | 3391c818 | blueswir1 | unsigned int i; |
1454 | 1a2fb1c0 | blueswir1 | target_ulong val; |
1455 | 3391c818 | blueswir1 | |
1456 | 3391c818 | blueswir1 | switch (asi) {
|
1457 | 3391c818 | blueswir1 | case 0xf0: // Block load primary |
1458 | 3391c818 | blueswir1 | case 0xf1: // Block load secondary |
1459 | 3391c818 | blueswir1 | case 0xf8: // Block load primary LE |
1460 | 3391c818 | blueswir1 | case 0xf9: // Block load secondary LE |
1461 | 51996525 | blueswir1 | if (rd & 7) { |
1462 | 51996525 | blueswir1 | raise_exception(TT_ILL_INSN); |
1463 | 51996525 | blueswir1 | return;
|
1464 | 51996525 | blueswir1 | } |
1465 | 1a2fb1c0 | blueswir1 | if (addr & 0x3f) { |
1466 | 51996525 | blueswir1 | raise_exception(TT_UNALIGNED); |
1467 | 51996525 | blueswir1 | return;
|
1468 | 51996525 | blueswir1 | } |
1469 | 51996525 | blueswir1 | for (i = 0; i < 16; i++) { |
1470 | 1a2fb1c0 | blueswir1 | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0); |
1471 | 1a2fb1c0 | blueswir1 | addr += 4;
|
1472 | 3391c818 | blueswir1 | } |
1473 | 3391c818 | blueswir1 | |
1474 | 3391c818 | blueswir1 | return;
|
1475 | 3391c818 | blueswir1 | default:
|
1476 | 3391c818 | blueswir1 | break;
|
1477 | 3391c818 | blueswir1 | } |
1478 | 3391c818 | blueswir1 | |
1479 | 1a2fb1c0 | blueswir1 | val = helper_ld_asi(addr, asi, size, 0);
|
1480 | 3391c818 | blueswir1 | switch(size) {
|
1481 | 3391c818 | blueswir1 | default:
|
1482 | 3391c818 | blueswir1 | case 4: |
1483 | 1a2fb1c0 | blueswir1 | *((uint32_t *)&FT0) = val; |
1484 | 3391c818 | blueswir1 | break;
|
1485 | 3391c818 | blueswir1 | case 8: |
1486 | 1a2fb1c0 | blueswir1 | *((int64_t *)&DT0) = val; |
1487 | 3391c818 | blueswir1 | break;
|
1488 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1489 | 1f587329 | blueswir1 | case 16: |
1490 | 1f587329 | blueswir1 | // XXX
|
1491 | 1f587329 | blueswir1 | break;
|
1492 | 1f587329 | blueswir1 | #endif
|
1493 | 3391c818 | blueswir1 | } |
1494 | 3391c818 | blueswir1 | } |
1495 | 3391c818 | blueswir1 | |
1496 | 1a2fb1c0 | blueswir1 | void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
1497 | 3391c818 | blueswir1 | { |
1498 | 3391c818 | blueswir1 | unsigned int i; |
1499 | 1a2fb1c0 | blueswir1 | target_ulong val = 0;
|
1500 | 3391c818 | blueswir1 | |
1501 | 3391c818 | blueswir1 | switch (asi) {
|
1502 | 3391c818 | blueswir1 | case 0xf0: // Block store primary |
1503 | 3391c818 | blueswir1 | case 0xf1: // Block store secondary |
1504 | 3391c818 | blueswir1 | case 0xf8: // Block store primary LE |
1505 | 3391c818 | blueswir1 | case 0xf9: // Block store secondary LE |
1506 | 51996525 | blueswir1 | if (rd & 7) { |
1507 | 51996525 | blueswir1 | raise_exception(TT_ILL_INSN); |
1508 | 51996525 | blueswir1 | return;
|
1509 | 51996525 | blueswir1 | } |
1510 | 1a2fb1c0 | blueswir1 | if (addr & 0x3f) { |
1511 | 51996525 | blueswir1 | raise_exception(TT_UNALIGNED); |
1512 | 51996525 | blueswir1 | return;
|
1513 | 51996525 | blueswir1 | } |
1514 | 51996525 | blueswir1 | for (i = 0; i < 16; i++) { |
1515 | 1a2fb1c0 | blueswir1 | val = *(uint32_t *)&env->fpr[rd++]; |
1516 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val, asi & 0x8f, 4); |
1517 | 1a2fb1c0 | blueswir1 | addr += 4;
|
1518 | 3391c818 | blueswir1 | } |
1519 | 3391c818 | blueswir1 | |
1520 | 3391c818 | blueswir1 | return;
|
1521 | 3391c818 | blueswir1 | default:
|
1522 | 3391c818 | blueswir1 | break;
|
1523 | 3391c818 | blueswir1 | } |
1524 | 3391c818 | blueswir1 | |
1525 | 3391c818 | blueswir1 | switch(size) {
|
1526 | 3391c818 | blueswir1 | default:
|
1527 | 3391c818 | blueswir1 | case 4: |
1528 | 1a2fb1c0 | blueswir1 | val = *((uint32_t *)&FT0); |
1529 | 3391c818 | blueswir1 | break;
|
1530 | 3391c818 | blueswir1 | case 8: |
1531 | 1a2fb1c0 | blueswir1 | val = *((int64_t *)&DT0); |
1532 | 3391c818 | blueswir1 | break;
|
1533 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1534 | 1f587329 | blueswir1 | case 16: |
1535 | 1f587329 | blueswir1 | // XXX
|
1536 | 1f587329 | blueswir1 | break;
|
1537 | 1f587329 | blueswir1 | #endif
|
1538 | 3391c818 | blueswir1 | } |
1539 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val, asi, size); |
1540 | 1a2fb1c0 | blueswir1 | } |
1541 | 1a2fb1c0 | blueswir1 | |
1542 | 1a2fb1c0 | blueswir1 | target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, |
1543 | 1a2fb1c0 | blueswir1 | target_ulong val2, uint32_t asi) |
1544 | 1a2fb1c0 | blueswir1 | { |
1545 | 1a2fb1c0 | blueswir1 | target_ulong ret; |
1546 | 1a2fb1c0 | blueswir1 | |
1547 | 1a2fb1c0 | blueswir1 | val1 &= 0xffffffffUL;
|
1548 | 1a2fb1c0 | blueswir1 | ret = helper_ld_asi(addr, asi, 4, 0); |
1549 | 1a2fb1c0 | blueswir1 | ret &= 0xffffffffUL;
|
1550 | 1a2fb1c0 | blueswir1 | if (val1 == ret)
|
1551 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4); |
1552 | 1a2fb1c0 | blueswir1 | return ret;
|
1553 | 3391c818 | blueswir1 | } |
1554 | 3391c818 | blueswir1 | |
1555 | 1a2fb1c0 | blueswir1 | target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
1556 | 1a2fb1c0 | blueswir1 | target_ulong val2, uint32_t asi) |
1557 | 1a2fb1c0 | blueswir1 | { |
1558 | 1a2fb1c0 | blueswir1 | target_ulong ret; |
1559 | 1a2fb1c0 | blueswir1 | |
1560 | 1a2fb1c0 | blueswir1 | ret = helper_ld_asi(addr, asi, 8, 0); |
1561 | 1a2fb1c0 | blueswir1 | if (val1 == ret)
|
1562 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val2, asi, 8);
|
1563 | 1a2fb1c0 | blueswir1 | return ret;
|
1564 | 1a2fb1c0 | blueswir1 | } |
1565 | 81ad8ba2 | blueswir1 | #endif /* TARGET_SPARC64 */ |
1566 | 3475187d | bellard | |
1567 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
1568 | 1a2fb1c0 | blueswir1 | void helper_rett(void) |
1569 | e8af50a3 | bellard | { |
1570 | af7bf89b | bellard | unsigned int cwp; |
1571 | af7bf89b | bellard | |
1572 | d4218d99 | blueswir1 | if (env->psret == 1) |
1573 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
1574 | d4218d99 | blueswir1 | |
1575 | e8af50a3 | bellard | env->psret = 1;
|
1576 | 5fafdf24 | ths | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
1577 | e8af50a3 | bellard | if (env->wim & (1 << cwp)) { |
1578 | e8af50a3 | bellard | raise_exception(TT_WIN_UNF); |
1579 | e8af50a3 | bellard | } |
1580 | e8af50a3 | bellard | set_cwp(cwp); |
1581 | e8af50a3 | bellard | env->psrs = env->psrps; |
1582 | e8af50a3 | bellard | } |
1583 | 3475187d | bellard | #endif
|
1584 | e8af50a3 | bellard | |
1585 | 1a2fb1c0 | blueswir1 | uint64_t helper_pack64(target_ulong high, target_ulong low) |
1586 | 1a2fb1c0 | blueswir1 | { |
1587 | 1a2fb1c0 | blueswir1 | return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff); |
1588 | 1a2fb1c0 | blueswir1 | } |
1589 | 1a2fb1c0 | blueswir1 | |
1590 | 8d5f07fa | bellard | void helper_ldfsr(void) |
1591 | e8af50a3 | bellard | { |
1592 | 7a0e1f41 | bellard | int rnd_mode;
|
1593 | e8af50a3 | bellard | switch (env->fsr & FSR_RD_MASK) {
|
1594 | e8af50a3 | bellard | case FSR_RD_NEAREST:
|
1595 | 7a0e1f41 | bellard | rnd_mode = float_round_nearest_even; |
1596 | 0f8a249a | blueswir1 | break;
|
1597 | ed910241 | bellard | default:
|
1598 | e8af50a3 | bellard | case FSR_RD_ZERO:
|
1599 | 7a0e1f41 | bellard | rnd_mode = float_round_to_zero; |
1600 | 0f8a249a | blueswir1 | break;
|
1601 | e8af50a3 | bellard | case FSR_RD_POS:
|
1602 | 7a0e1f41 | bellard | rnd_mode = float_round_up; |
1603 | 0f8a249a | blueswir1 | break;
|
1604 | e8af50a3 | bellard | case FSR_RD_NEG:
|
1605 | 7a0e1f41 | bellard | rnd_mode = float_round_down; |
1606 | 0f8a249a | blueswir1 | break;
|
1607 | e8af50a3 | bellard | } |
1608 | 7a0e1f41 | bellard | set_float_rounding_mode(rnd_mode, &env->fp_status); |
1609 | e8af50a3 | bellard | } |
1610 | e80cfcfc | bellard | |
1611 | e80cfcfc | bellard | void helper_debug()
|
1612 | e80cfcfc | bellard | { |
1613 | e80cfcfc | bellard | env->exception_index = EXCP_DEBUG; |
1614 | e80cfcfc | bellard | cpu_loop_exit(); |
1615 | e80cfcfc | bellard | } |
1616 | af7bf89b | bellard | |
1617 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
1618 | 1a2fb1c0 | blueswir1 | void helper_wrpsr(target_ulong new_psr)
|
1619 | af7bf89b | bellard | { |
1620 | 1a2fb1c0 | blueswir1 | if ((new_psr & PSR_CWP) >= NWINDOWS)
|
1621 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
1622 | d4218d99 | blueswir1 | else
|
1623 | 1a2fb1c0 | blueswir1 | PUT_PSR(env, new_psr); |
1624 | af7bf89b | bellard | } |
1625 | af7bf89b | bellard | |
1626 | 1a2fb1c0 | blueswir1 | target_ulong helper_rdpsr(void)
|
1627 | af7bf89b | bellard | { |
1628 | 1a2fb1c0 | blueswir1 | return GET_PSR(env);
|
1629 | af7bf89b | bellard | } |
1630 | 3475187d | bellard | |
1631 | 3475187d | bellard | #else
|
1632 | 3475187d | bellard | |
1633 | 1a2fb1c0 | blueswir1 | target_ulong helper_popc(target_ulong val) |
1634 | 3475187d | bellard | { |
1635 | 1a2fb1c0 | blueswir1 | return ctpop64(val);
|
1636 | 3475187d | bellard | } |
1637 | 83469015 | bellard | |
1638 | 83469015 | bellard | static inline uint64_t *get_gregset(uint64_t pstate) |
1639 | 83469015 | bellard | { |
1640 | 83469015 | bellard | switch (pstate) {
|
1641 | 83469015 | bellard | default:
|
1642 | 83469015 | bellard | case 0: |
1643 | 0f8a249a | blueswir1 | return env->bgregs;
|
1644 | 83469015 | bellard | case PS_AG:
|
1645 | 0f8a249a | blueswir1 | return env->agregs;
|
1646 | 83469015 | bellard | case PS_MG:
|
1647 | 0f8a249a | blueswir1 | return env->mgregs;
|
1648 | 83469015 | bellard | case PS_IG:
|
1649 | 0f8a249a | blueswir1 | return env->igregs;
|
1650 | 83469015 | bellard | } |
1651 | 83469015 | bellard | } |
1652 | 83469015 | bellard | |
1653 | 8f1f22f6 | blueswir1 | static inline void change_pstate(uint64_t new_pstate) |
1654 | 83469015 | bellard | { |
1655 | 8f1f22f6 | blueswir1 | uint64_t pstate_regs, new_pstate_regs; |
1656 | 83469015 | bellard | uint64_t *src, *dst; |
1657 | 83469015 | bellard | |
1658 | 83469015 | bellard | pstate_regs = env->pstate & 0xc01;
|
1659 | 83469015 | bellard | new_pstate_regs = new_pstate & 0xc01;
|
1660 | 83469015 | bellard | if (new_pstate_regs != pstate_regs) {
|
1661 | 0f8a249a | blueswir1 | // Switch global register bank
|
1662 | 0f8a249a | blueswir1 | src = get_gregset(new_pstate_regs); |
1663 | 0f8a249a | blueswir1 | dst = get_gregset(pstate_regs); |
1664 | 0f8a249a | blueswir1 | memcpy32(dst, env->gregs); |
1665 | 0f8a249a | blueswir1 | memcpy32(env->gregs, src); |
1666 | 83469015 | bellard | } |
1667 | 83469015 | bellard | env->pstate = new_pstate; |
1668 | 83469015 | bellard | } |
1669 | 83469015 | bellard | |
1670 | 1a2fb1c0 | blueswir1 | void helper_wrpstate(target_ulong new_state)
|
1671 | 8f1f22f6 | blueswir1 | { |
1672 | 1a2fb1c0 | blueswir1 | change_pstate(new_state & 0xf3f);
|
1673 | 8f1f22f6 | blueswir1 | } |
1674 | 8f1f22f6 | blueswir1 | |
1675 | 1a2fb1c0 | blueswir1 | void helper_done(void) |
1676 | 83469015 | bellard | { |
1677 | 83469015 | bellard | env->tl--; |
1678 | 375ee38b | blueswir1 | env->tsptr = &env->ts[env->tl]; |
1679 | 375ee38b | blueswir1 | env->pc = env->tsptr->tpc; |
1680 | 375ee38b | blueswir1 | env->npc = env->tsptr->tnpc + 4;
|
1681 | 375ee38b | blueswir1 | PUT_CCR(env, env->tsptr->tstate >> 32);
|
1682 | 375ee38b | blueswir1 | env->asi = (env->tsptr->tstate >> 24) & 0xff; |
1683 | 375ee38b | blueswir1 | change_pstate((env->tsptr->tstate >> 8) & 0xf3f); |
1684 | 375ee38b | blueswir1 | PUT_CWP64(env, env->tsptr->tstate & 0xff);
|
1685 | 83469015 | bellard | } |
1686 | 83469015 | bellard | |
1687 | 1a2fb1c0 | blueswir1 | void helper_retry(void) |
1688 | 83469015 | bellard | { |
1689 | 83469015 | bellard | env->tl--; |
1690 | 375ee38b | blueswir1 | env->tsptr = &env->ts[env->tl]; |
1691 | 375ee38b | blueswir1 | env->pc = env->tsptr->tpc; |
1692 | 375ee38b | blueswir1 | env->npc = env->tsptr->tnpc; |
1693 | 375ee38b | blueswir1 | PUT_CCR(env, env->tsptr->tstate >> 32);
|
1694 | 375ee38b | blueswir1 | env->asi = (env->tsptr->tstate >> 24) & 0xff; |
1695 | 375ee38b | blueswir1 | change_pstate((env->tsptr->tstate >> 8) & 0xf3f); |
1696 | 375ee38b | blueswir1 | PUT_CWP64(env, env->tsptr->tstate & 0xff);
|
1697 | 83469015 | bellard | } |
1698 | 3475187d | bellard | #endif
|
1699 | ee5bbe38 | bellard | |
1700 | ee5bbe38 | bellard | void set_cwp(int new_cwp) |
1701 | ee5bbe38 | bellard | { |
1702 | ee5bbe38 | bellard | /* put the modified wrap registers at their proper location */
|
1703 | ee5bbe38 | bellard | if (env->cwp == (NWINDOWS - 1)) |
1704 | ee5bbe38 | bellard | memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
1705 | ee5bbe38 | bellard | env->cwp = new_cwp; |
1706 | ee5bbe38 | bellard | /* put the wrap registers at their temporary location */
|
1707 | ee5bbe38 | bellard | if (new_cwp == (NWINDOWS - 1)) |
1708 | ee5bbe38 | bellard | memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
1709 | ee5bbe38 | bellard | env->regwptr = env->regbase + (new_cwp * 16);
|
1710 | ee5bbe38 | bellard | REGWPTR = env->regwptr; |
1711 | ee5bbe38 | bellard | } |
1712 | ee5bbe38 | bellard | |
1713 | ee5bbe38 | bellard | void cpu_set_cwp(CPUState *env1, int new_cwp) |
1714 | ee5bbe38 | bellard | { |
1715 | ee5bbe38 | bellard | CPUState *saved_env; |
1716 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
1717 | ee5bbe38 | bellard | target_ulong *saved_regwptr; |
1718 | ee5bbe38 | bellard | #endif
|
1719 | ee5bbe38 | bellard | |
1720 | ee5bbe38 | bellard | saved_env = env; |
1721 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
1722 | ee5bbe38 | bellard | saved_regwptr = REGWPTR; |
1723 | ee5bbe38 | bellard | #endif
|
1724 | ee5bbe38 | bellard | env = env1; |
1725 | ee5bbe38 | bellard | set_cwp(new_cwp); |
1726 | ee5bbe38 | bellard | env = saved_env; |
1727 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
1728 | ee5bbe38 | bellard | REGWPTR = saved_regwptr; |
1729 | ee5bbe38 | bellard | #endif
|
1730 | ee5bbe38 | bellard | } |
1731 | ee5bbe38 | bellard | |
1732 | ee5bbe38 | bellard | #ifdef TARGET_SPARC64
|
1733 | 0b09be2b | blueswir1 | #ifdef DEBUG_PCALL
|
1734 | 0b09be2b | blueswir1 | static const char * const excp_names[0x50] = { |
1735 | 0b09be2b | blueswir1 | [TT_TFAULT] = "Instruction Access Fault",
|
1736 | 0b09be2b | blueswir1 | [TT_TMISS] = "Instruction Access MMU Miss",
|
1737 | 0b09be2b | blueswir1 | [TT_CODE_ACCESS] = "Instruction Access Error",
|
1738 | 0b09be2b | blueswir1 | [TT_ILL_INSN] = "Illegal Instruction",
|
1739 | 0b09be2b | blueswir1 | [TT_PRIV_INSN] = "Privileged Instruction",
|
1740 | 0b09be2b | blueswir1 | [TT_NFPU_INSN] = "FPU Disabled",
|
1741 | 0b09be2b | blueswir1 | [TT_FP_EXCP] = "FPU Exception",
|
1742 | 0b09be2b | blueswir1 | [TT_TOVF] = "Tag Overflow",
|
1743 | 0b09be2b | blueswir1 | [TT_CLRWIN] = "Clean Windows",
|
1744 | 0b09be2b | blueswir1 | [TT_DIV_ZERO] = "Division By Zero",
|
1745 | 0b09be2b | blueswir1 | [TT_DFAULT] = "Data Access Fault",
|
1746 | 0b09be2b | blueswir1 | [TT_DMISS] = "Data Access MMU Miss",
|
1747 | 0b09be2b | blueswir1 | [TT_DATA_ACCESS] = "Data Access Error",
|
1748 | 0b09be2b | blueswir1 | [TT_DPROT] = "Data Protection Error",
|
1749 | 0b09be2b | blueswir1 | [TT_UNALIGNED] = "Unaligned Memory Access",
|
1750 | 0b09be2b | blueswir1 | [TT_PRIV_ACT] = "Privileged Action",
|
1751 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x1] = "External Interrupt 1", |
1752 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x2] = "External Interrupt 2", |
1753 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x3] = "External Interrupt 3", |
1754 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x4] = "External Interrupt 4", |
1755 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x5] = "External Interrupt 5", |
1756 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x6] = "External Interrupt 6", |
1757 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x7] = "External Interrupt 7", |
1758 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x8] = "External Interrupt 8", |
1759 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x9] = "External Interrupt 9", |
1760 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xa] = "External Interrupt 10", |
1761 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xb] = "External Interrupt 11", |
1762 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xc] = "External Interrupt 12", |
1763 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xd] = "External Interrupt 13", |
1764 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xe] = "External Interrupt 14", |
1765 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xf] = "External Interrupt 15", |
1766 | 0b09be2b | blueswir1 | }; |
1767 | 0b09be2b | blueswir1 | #endif
|
1768 | 0b09be2b | blueswir1 | |
1769 | ee5bbe38 | bellard | void do_interrupt(int intno) |
1770 | ee5bbe38 | bellard | { |
1771 | ee5bbe38 | bellard | #ifdef DEBUG_PCALL
|
1772 | ee5bbe38 | bellard | if (loglevel & CPU_LOG_INT) {
|
1773 | 0f8a249a | blueswir1 | static int count; |
1774 | 0b09be2b | blueswir1 | const char *name; |
1775 | 0b09be2b | blueswir1 | |
1776 | 0b09be2b | blueswir1 | if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80)) |
1777 | 0b09be2b | blueswir1 | name = "Unknown";
|
1778 | 0b09be2b | blueswir1 | else if (intno >= 0x100) |
1779 | 0b09be2b | blueswir1 | name = "Trap Instruction";
|
1780 | 0b09be2b | blueswir1 | else if (intno >= 0xc0) |
1781 | 0b09be2b | blueswir1 | name = "Window Fill";
|
1782 | 0b09be2b | blueswir1 | else if (intno >= 0x80) |
1783 | 0b09be2b | blueswir1 | name = "Window Spill";
|
1784 | 0b09be2b | blueswir1 | else {
|
1785 | 0b09be2b | blueswir1 | name = excp_names[intno]; |
1786 | 0b09be2b | blueswir1 | if (!name)
|
1787 | 0b09be2b | blueswir1 | name = "Unknown";
|
1788 | 0b09be2b | blueswir1 | } |
1789 | 0b09be2b | blueswir1 | |
1790 | 0b09be2b | blueswir1 | fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
1791 | 0b09be2b | blueswir1 | " SP=%016" PRIx64 "\n", |
1792 | 0b09be2b | blueswir1 | count, name, intno, |
1793 | ee5bbe38 | bellard | env->pc, |
1794 | ee5bbe38 | bellard | env->npc, env->regwptr[6]);
|
1795 | 0f8a249a | blueswir1 | cpu_dump_state(env, logfile, fprintf, 0);
|
1796 | ee5bbe38 | bellard | #if 0
|
1797 | 0f8a249a | blueswir1 | {
|
1798 | 0f8a249a | blueswir1 | int i;
|
1799 | 0f8a249a | blueswir1 | uint8_t *ptr;
|
1800 | 0f8a249a | blueswir1 | |
1801 | 0f8a249a | blueswir1 | fprintf(logfile, " code=");
|
1802 | 0f8a249a | blueswir1 | ptr = (uint8_t *)env->pc;
|
1803 | 0f8a249a | blueswir1 | for(i = 0; i < 16; i++) {
|
1804 | 0f8a249a | blueswir1 | fprintf(logfile, " %02x", ldub(ptr + i));
|
1805 | 0f8a249a | blueswir1 | }
|
1806 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
1807 | 0f8a249a | blueswir1 | }
|
1808 | ee5bbe38 | bellard | #endif
|
1809 | 0f8a249a | blueswir1 | count++; |
1810 | ee5bbe38 | bellard | } |
1811 | ee5bbe38 | bellard | #endif
|
1812 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
1813 | 83469015 | bellard | if (env->tl == MAXTL) {
|
1814 | c68ea704 | bellard | cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
1815 | 0f8a249a | blueswir1 | return;
|
1816 | ee5bbe38 | bellard | } |
1817 | ee5bbe38 | bellard | #endif
|
1818 | 375ee38b | blueswir1 | env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
|
1819 | 375ee38b | blueswir1 | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
1820 | 375ee38b | blueswir1 | GET_CWP64(env); |
1821 | 375ee38b | blueswir1 | env->tsptr->tpc = env->pc; |
1822 | 375ee38b | blueswir1 | env->tsptr->tnpc = env->npc; |
1823 | 375ee38b | blueswir1 | env->tsptr->tt = intno; |
1824 | 8f1f22f6 | blueswir1 | change_pstate(PS_PEF | PS_PRIV | PS_AG); |
1825 | 8f1f22f6 | blueswir1 | |
1826 | 8f1f22f6 | blueswir1 | if (intno == TT_CLRWIN)
|
1827 | 8f1f22f6 | blueswir1 | set_cwp((env->cwp - 1) & (NWINDOWS - 1)); |
1828 | 8f1f22f6 | blueswir1 | else if ((intno & 0x1c0) == TT_SPILL) |
1829 | 8f1f22f6 | blueswir1 | set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
1830 | 8f1f22f6 | blueswir1 | else if ((intno & 0x1c0) == TT_FILL) |
1831 | 8f1f22f6 | blueswir1 | set_cwp((env->cwp + 1) & (NWINDOWS - 1)); |
1832 | 83469015 | bellard | env->tbr &= ~0x7fffULL;
|
1833 | 83469015 | bellard | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
1834 | 83469015 | bellard | if (env->tl < MAXTL - 1) { |
1835 | 0f8a249a | blueswir1 | env->tl++; |
1836 | 83469015 | bellard | } else {
|
1837 | 0f8a249a | blueswir1 | env->pstate |= PS_RED; |
1838 | 0f8a249a | blueswir1 | if (env->tl != MAXTL)
|
1839 | 0f8a249a | blueswir1 | env->tl++; |
1840 | 83469015 | bellard | } |
1841 | 375ee38b | blueswir1 | env->tsptr = &env->ts[env->tl]; |
1842 | ee5bbe38 | bellard | env->pc = env->tbr; |
1843 | ee5bbe38 | bellard | env->npc = env->pc + 4;
|
1844 | ee5bbe38 | bellard | env->exception_index = 0;
|
1845 | ee5bbe38 | bellard | } |
1846 | ee5bbe38 | bellard | #else
|
1847 | 0b09be2b | blueswir1 | #ifdef DEBUG_PCALL
|
1848 | 0b09be2b | blueswir1 | static const char * const excp_names[0x80] = { |
1849 | 0b09be2b | blueswir1 | [TT_TFAULT] = "Instruction Access Fault",
|
1850 | 0b09be2b | blueswir1 | [TT_ILL_INSN] = "Illegal Instruction",
|
1851 | 0b09be2b | blueswir1 | [TT_PRIV_INSN] = "Privileged Instruction",
|
1852 | 0b09be2b | blueswir1 | [TT_NFPU_INSN] = "FPU Disabled",
|
1853 | 0b09be2b | blueswir1 | [TT_WIN_OVF] = "Window Overflow",
|
1854 | 0b09be2b | blueswir1 | [TT_WIN_UNF] = "Window Underflow",
|
1855 | 0b09be2b | blueswir1 | [TT_UNALIGNED] = "Unaligned Memory Access",
|
1856 | 0b09be2b | blueswir1 | [TT_FP_EXCP] = "FPU Exception",
|
1857 | 0b09be2b | blueswir1 | [TT_DFAULT] = "Data Access Fault",
|
1858 | 0b09be2b | blueswir1 | [TT_TOVF] = "Tag Overflow",
|
1859 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x1] = "External Interrupt 1", |
1860 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x2] = "External Interrupt 2", |
1861 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x3] = "External Interrupt 3", |
1862 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x4] = "External Interrupt 4", |
1863 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x5] = "External Interrupt 5", |
1864 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x6] = "External Interrupt 6", |
1865 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x7] = "External Interrupt 7", |
1866 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x8] = "External Interrupt 8", |
1867 | 0b09be2b | blueswir1 | [TT_EXTINT | 0x9] = "External Interrupt 9", |
1868 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xa] = "External Interrupt 10", |
1869 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xb] = "External Interrupt 11", |
1870 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xc] = "External Interrupt 12", |
1871 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xd] = "External Interrupt 13", |
1872 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xe] = "External Interrupt 14", |
1873 | 0b09be2b | blueswir1 | [TT_EXTINT | 0xf] = "External Interrupt 15", |
1874 | 0b09be2b | blueswir1 | [TT_TOVF] = "Tag Overflow",
|
1875 | 0b09be2b | blueswir1 | [TT_CODE_ACCESS] = "Instruction Access Error",
|
1876 | 0b09be2b | blueswir1 | [TT_DATA_ACCESS] = "Data Access Error",
|
1877 | 0b09be2b | blueswir1 | [TT_DIV_ZERO] = "Division By Zero",
|
1878 | 0b09be2b | blueswir1 | [TT_NCP_INSN] = "Coprocessor Disabled",
|
1879 | 0b09be2b | blueswir1 | }; |
1880 | 0b09be2b | blueswir1 | #endif
|
1881 | 0b09be2b | blueswir1 | |
1882 | ee5bbe38 | bellard | void do_interrupt(int intno) |
1883 | ee5bbe38 | bellard | { |
1884 | ee5bbe38 | bellard | int cwp;
|
1885 | ee5bbe38 | bellard | |
1886 | ee5bbe38 | bellard | #ifdef DEBUG_PCALL
|
1887 | ee5bbe38 | bellard | if (loglevel & CPU_LOG_INT) {
|
1888 | 0f8a249a | blueswir1 | static int count; |
1889 | 0b09be2b | blueswir1 | const char *name; |
1890 | 0b09be2b | blueswir1 | |
1891 | 0b09be2b | blueswir1 | if (intno < 0 || intno >= 0x100) |
1892 | 0b09be2b | blueswir1 | name = "Unknown";
|
1893 | 0b09be2b | blueswir1 | else if (intno >= 0x80) |
1894 | 0b09be2b | blueswir1 | name = "Trap Instruction";
|
1895 | 0b09be2b | blueswir1 | else {
|
1896 | 0b09be2b | blueswir1 | name = excp_names[intno]; |
1897 | 0b09be2b | blueswir1 | if (!name)
|
1898 | 0b09be2b | blueswir1 | name = "Unknown";
|
1899 | 0b09be2b | blueswir1 | } |
1900 | 0b09be2b | blueswir1 | |
1901 | 0b09be2b | blueswir1 | fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
1902 | 0b09be2b | blueswir1 | count, name, intno, |
1903 | ee5bbe38 | bellard | env->pc, |
1904 | ee5bbe38 | bellard | env->npc, env->regwptr[6]);
|
1905 | 0f8a249a | blueswir1 | cpu_dump_state(env, logfile, fprintf, 0);
|
1906 | ee5bbe38 | bellard | #if 0
|
1907 | 0f8a249a | blueswir1 | {
|
1908 | 0f8a249a | blueswir1 | int i;
|
1909 | 0f8a249a | blueswir1 | uint8_t *ptr;
|
1910 | 0f8a249a | blueswir1 | |
1911 | 0f8a249a | blueswir1 | fprintf(logfile, " code=");
|
1912 | 0f8a249a | blueswir1 | ptr = (uint8_t *)env->pc;
|
1913 | 0f8a249a | blueswir1 | for(i = 0; i < 16; i++) {
|
1914 | 0f8a249a | blueswir1 | fprintf(logfile, " %02x", ldub(ptr + i));
|
1915 | 0f8a249a | blueswir1 | }
|
1916 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
1917 | 0f8a249a | blueswir1 | }
|
1918 | ee5bbe38 | bellard | #endif
|
1919 | 0f8a249a | blueswir1 | count++; |
1920 | ee5bbe38 | bellard | } |
1921 | ee5bbe38 | bellard | #endif
|
1922 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
1923 | ee5bbe38 | bellard | if (env->psret == 0) { |
1924 | c68ea704 | bellard | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
1925 | 0f8a249a | blueswir1 | return;
|
1926 | ee5bbe38 | bellard | } |
1927 | ee5bbe38 | bellard | #endif
|
1928 | ee5bbe38 | bellard | env->psret = 0;
|
1929 | 5fafdf24 | ths | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
1930 | ee5bbe38 | bellard | set_cwp(cwp); |
1931 | ee5bbe38 | bellard | env->regwptr[9] = env->pc;
|
1932 | ee5bbe38 | bellard | env->regwptr[10] = env->npc;
|
1933 | ee5bbe38 | bellard | env->psrps = env->psrs; |
1934 | ee5bbe38 | bellard | env->psrs = 1;
|
1935 | ee5bbe38 | bellard | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
1936 | ee5bbe38 | bellard | env->pc = env->tbr; |
1937 | ee5bbe38 | bellard | env->npc = env->pc + 4;
|
1938 | ee5bbe38 | bellard | env->exception_index = 0;
|
1939 | ee5bbe38 | bellard | } |
1940 | ee5bbe38 | bellard | #endif
|
1941 | ee5bbe38 | bellard | |
1942 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
1943 | ee5bbe38 | bellard | |
1944 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1945 | d2889a3e | blueswir1 | void *retaddr);
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1946 | d2889a3e | blueswir1 | |
1947 | ee5bbe38 | bellard | #define MMUSUFFIX _mmu
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1948 | d2889a3e | blueswir1 | #define ALIGNED_ONLY
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1949 | 273af660 | ths | #ifdef __s390__
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1950 | 273af660 | ths | # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
1951 | 273af660 | ths | #else
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1952 | 273af660 | ths | # define GETPC() (__builtin_return_address(0)) |
1953 | 273af660 | ths | #endif
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1954 | ee5bbe38 | bellard | |
1955 | ee5bbe38 | bellard | #define SHIFT 0 |
1956 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1957 | ee5bbe38 | bellard | |
1958 | ee5bbe38 | bellard | #define SHIFT 1 |
1959 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1960 | ee5bbe38 | bellard | |
1961 | ee5bbe38 | bellard | #define SHIFT 2 |
1962 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1963 | ee5bbe38 | bellard | |
1964 | ee5bbe38 | bellard | #define SHIFT 3 |
1965 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1966 | ee5bbe38 | bellard | |
1967 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1968 | d2889a3e | blueswir1 | void *retaddr)
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1969 | d2889a3e | blueswir1 | { |
1970 | 94554550 | blueswir1 | #ifdef DEBUG_UNALIGNED
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1971 | 94554550 | blueswir1 | printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
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1972 | 94554550 | blueswir1 | #endif
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1973 | 94554550 | blueswir1 | raise_exception(TT_UNALIGNED); |
1974 | d2889a3e | blueswir1 | } |
1975 | ee5bbe38 | bellard | |
1976 | ee5bbe38 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
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1977 | ee5bbe38 | bellard | NULL, it means that the function was called in C code (i.e. not
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1978 | ee5bbe38 | bellard | from generated code or from helper.c) */
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1979 | ee5bbe38 | bellard | /* XXX: fix it to restore all registers */
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1980 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
1981 | ee5bbe38 | bellard | { |
1982 | ee5bbe38 | bellard | TranslationBlock *tb; |
1983 | ee5bbe38 | bellard | int ret;
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1984 | ee5bbe38 | bellard | unsigned long pc; |
1985 | ee5bbe38 | bellard | CPUState *saved_env; |
1986 | ee5bbe38 | bellard | |
1987 | ee5bbe38 | bellard | /* XXX: hack to restore env in all cases, even if not called from
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1988 | ee5bbe38 | bellard | generated code */
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1989 | ee5bbe38 | bellard | saved_env = env; |
1990 | ee5bbe38 | bellard | env = cpu_single_env; |
1991 | ee5bbe38 | bellard | |
1992 | 6ebbf390 | j_mayer | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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1993 | ee5bbe38 | bellard | if (ret) {
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1994 | ee5bbe38 | bellard | if (retaddr) {
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1995 | ee5bbe38 | bellard | /* now we have a real cpu fault */
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1996 | ee5bbe38 | bellard | pc = (unsigned long)retaddr; |
1997 | ee5bbe38 | bellard | tb = tb_find_pc(pc); |
1998 | ee5bbe38 | bellard | if (tb) {
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1999 | ee5bbe38 | bellard | /* the PC is inside the translated code. It means that we have
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2000 | ee5bbe38 | bellard | a virtual CPU fault */
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2001 | ee5bbe38 | bellard | cpu_restore_state(tb, env, pc, (void *)T2);
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2002 | ee5bbe38 | bellard | } |
2003 | ee5bbe38 | bellard | } |
2004 | ee5bbe38 | bellard | cpu_loop_exit(); |
2005 | ee5bbe38 | bellard | } |
2006 | ee5bbe38 | bellard | env = saved_env; |
2007 | ee5bbe38 | bellard | } |
2008 | ee5bbe38 | bellard | |
2009 | ee5bbe38 | bellard | #endif
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2010 | 6c36d3fa | blueswir1 | |
2011 | 6c36d3fa | blueswir1 | #ifndef TARGET_SPARC64
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2012 | 5dcb6b91 | blueswir1 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
2013 | 6c36d3fa | blueswir1 | int is_asi)
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2014 | 6c36d3fa | blueswir1 | { |
2015 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
2016 | 6c36d3fa | blueswir1 | |
2017 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
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2018 | 6c36d3fa | blueswir1 | generated code */
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2019 | 6c36d3fa | blueswir1 | saved_env = env; |
2020 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
2021 | 8543e2cf | blueswir1 | #ifdef DEBUG_UNASSIGNED
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2022 | 8543e2cf | blueswir1 | if (is_asi)
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2023 | 8543e2cf | blueswir1 | printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from " |
2024 | 8543e2cf | blueswir1 | TARGET_FMT_lx "\n",
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2025 | 8543e2cf | blueswir1 | is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi, |
2026 | 8543e2cf | blueswir1 | env->pc); |
2027 | 8543e2cf | blueswir1 | else
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2028 | 8543e2cf | blueswir1 | printf("Unassigned mem %s access to " TARGET_FMT_plx " from " |
2029 | 8543e2cf | blueswir1 | TARGET_FMT_lx "\n",
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2030 | 8543e2cf | blueswir1 | is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc); |
2031 | 8543e2cf | blueswir1 | #endif
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2032 | 6c36d3fa | blueswir1 | if (env->mmuregs[3]) /* Fault status register */ |
2033 | 0f8a249a | blueswir1 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
2034 | 6c36d3fa | blueswir1 | if (is_asi)
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2035 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 16; |
2036 | 6c36d3fa | blueswir1 | if (env->psrs)
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2037 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 5; |
2038 | 6c36d3fa | blueswir1 | if (is_exec)
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2039 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 6; |
2040 | 6c36d3fa | blueswir1 | if (is_write)
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2041 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 7; |
2042 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= (5 << 2) | 2; |
2043 | 6c36d3fa | blueswir1 | env->mmuregs[4] = addr; /* Fault address register */ |
2044 | 6c36d3fa | blueswir1 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
2045 | 1b2e93c1 | blueswir1 | if (is_exec)
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2046 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
2047 | 1b2e93c1 | blueswir1 | else
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2048 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
2049 | 6c36d3fa | blueswir1 | } |
2050 | 6c36d3fa | blueswir1 | env = saved_env; |
2051 | 6c36d3fa | blueswir1 | } |
2052 | 6c36d3fa | blueswir1 | #else
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2053 | 5dcb6b91 | blueswir1 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
2054 | 6c36d3fa | blueswir1 | int is_asi)
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2055 | 6c36d3fa | blueswir1 | { |
2056 | 6c36d3fa | blueswir1 | #ifdef DEBUG_UNASSIGNED
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2057 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
2058 | 6c36d3fa | blueswir1 | |
2059 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
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2060 | 6c36d3fa | blueswir1 | generated code */
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2061 | 6c36d3fa | blueswir1 | saved_env = env; |
2062 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
2063 | 5dcb6b91 | blueswir1 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
2064 | 6c36d3fa | blueswir1 | addr, env->pc); |
2065 | 6c36d3fa | blueswir1 | env = saved_env; |
2066 | 6c36d3fa | blueswir1 | #endif
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2067 | 1b2e93c1 | blueswir1 | if (is_exec)
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2068 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
2069 | 1b2e93c1 | blueswir1 | else
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2070 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
2071 | 6c36d3fa | blueswir1 | } |
2072 | 6c36d3fa | blueswir1 | #endif
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