Archipelago » qemu

/*

   SPARC translation

   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>

   Copyright (C) 2003-2005 Fabrice Bellard

   This library is free software; you can redistribute it and/or

   modify it under the terms of the GNU Lesser General Public

   License as published by the Free Software Foundation; either

   version 2 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public

   License along with this library; if not, write to the Free Software

   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

/*

   TODO-list:

   Rest of V9 instructions, VIS instructions

   NPC/PC static optimisations (use JUMP_TB when possible)

   Optimize synthetic instructions

*/

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "helper.h"

#include "tcg-op.h"

#define DEBUG_DISAS

#define DYNAMIC_PC  1 /* dynamic pc value */

#define JUMP_PC     2 /* dynamic pc value which takes only two values

                         according to jump_pc[T2] */

/* global register indexes */

static TCGv cpu_env, cpu_T[3], cpu_regwptr;

/* local register indexes (only used inside old micro ops) */

static TCGv cpu_tmp0;

typedef struct DisasContext {

    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */

    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */

    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */

    int is_br;

    int mem_idx;

    int fpu_enabled;

    struct TranslationBlock *tb;

} DisasContext;

typedef struct sparc_def_t sparc_def_t;

struct sparc_def_t {

    const unsigned char *name;

    target_ulong iu_version;

    uint32_t fpu_version;

    uint32_t mmu_version;

    uint32_t mmu_bm;

    uint32_t mmu_ctpr_mask;

    uint32_t mmu_cxr_mask;

    uint32_t mmu_sfsr_mask;

    uint32_t mmu_trcr_mask;

};

static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);

extern FILE *logfile;

extern int loglevel;

// This function uses non-native bit order

#define GET_FIELD(X, FROM, TO) \

  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

// This function uses the order in the manuals, i.e. bit 0 is 2^0

#define GET_FIELD_SP(X, FROM, TO) \

    GET_FIELD(X, 31 - (TO), 31 - (FROM))

#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)

#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))

#ifdef TARGET_SPARC64

#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))

#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))

#else

#define DFPREG(r) (r & 0x1e)

#define QFPREG(r) (r & 0x1c)

#endif

static int sign_extend(int x, int len)

{

    len = 32 - len;

    return (x << len) >> len;

}

#define IS_IMM (insn & (1<<13))

static void disas_sparc_insn(DisasContext * dc);

#ifdef TARGET_SPARC64

#define GEN32(func, NAME) \

static GenOpFunc * const NAME ## _table [64] = {                              \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \

NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \

NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \

NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#else

#define GEN32(func, NAME) \

static GenOpFunc *const NAME ## _table [32] = {                               \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#endif

/* floating point registers moves */

GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);

GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);

GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);

GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);

GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);

GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);

GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);

GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);

#if defined(CONFIG_USER_ONLY)

GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);

GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);

GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);

GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);

#endif

/* moves */

#ifdef CONFIG_USER_ONLY

#define supervisor(dc) 0

#ifdef TARGET_SPARC64

#define hypervisor(dc) 0

#endif

#define gen_op_ldst(name)        gen_op_##name##_raw()

#else

#define supervisor(dc) (dc->mem_idx >= 1)

#ifdef TARGET_SPARC64

#define hypervisor(dc) (dc->mem_idx == 2)

#define OP_LD_TABLE(width)                                              \

    static GenOpFunc * const gen_op_##width[] = {                       \

        &gen_op_##width##_user,                                         \

        &gen_op_##width##_kernel,                                       \

        &gen_op_##width##_hypv,                                         \

    };

#else

#define OP_LD_TABLE(width)                                              \

    static GenOpFunc * const gen_op_##width[] = {                       \

        &gen_op_##width##_user,                                         \

        &gen_op_##width##_kernel,                                       \

    };

#endif

#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()

#endif

#ifndef CONFIG_USER_ONLY

#ifdef __i386__

OP_LD_TABLE(std);

#endif /* __i386__ */

OP_LD_TABLE(stf);

OP_LD_TABLE(stdf);

OP_LD_TABLE(ldf);

OP_LD_TABLE(lddf);

#endif

#ifdef TARGET_ABI32

#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);

#else

#define ABI32_MASK(addr)

#endif

static inline void gen_movl_simm_T1(int32_t val)

{

    tcg_gen_movi_tl(cpu_T[1], val);

}

static inline void gen_movl_reg_TN(int reg, TCGv tn)

{

    if (reg == 0)

        tcg_gen_movi_tl(tn, 0);

    else if (reg < 8)

        tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));

    else {

        tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX

        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

    }

}

static inline void gen_movl_reg_T0(int reg)

{

    gen_movl_reg_TN(reg, cpu_T[0]);

}

static inline void gen_movl_reg_T1(int reg)

{

    gen_movl_reg_TN(reg, cpu_T[1]);

}

#ifdef __i386__

static inline void gen_movl_reg_T2(int reg)

{

    gen_movl_reg_TN(reg, cpu_T[2]);

}

#endif /* __i386__ */

static inline void gen_movl_TN_reg(int reg, TCGv tn)

{

    if (reg == 0)

        return;

    else if (reg < 8)

        tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));

    else {

        tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX

        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

    }

}

static inline void gen_movl_T0_reg(int reg)

{

    gen_movl_TN_reg(reg, cpu_T[0]);

}

static inline void gen_movl_T1_reg(int reg)

{

    gen_movl_TN_reg(reg, cpu_T[1]);

}

static inline void gen_op_movl_T0_env(size_t offset)

{

    tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);

}

static inline void gen_op_movl_env_T0(size_t offset)

{

    tcg_gen_st_i32(cpu_T[0], cpu_env, offset);

}

static inline void gen_op_movtl_T0_env(size_t offset)

{

    tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);

}

static inline void gen_op_movtl_env_T0(size_t offset)

{

    tcg_gen_st_tl(cpu_T[0], cpu_env, offset);

}

static inline void gen_op_add_T1_T0(void)

{

    tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

}

static inline void gen_op_or_T1_T0(void)

{

    tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

}

static inline void gen_op_xor_T1_T0(void)

{

    tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

}

static inline void gen_jmp_im(target_ulong pc)

{

    tcg_gen_movi_tl(cpu_tmp0, pc);

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));

}

static inline void gen_movl_npc_im(target_ulong npc)

{

    tcg_gen_movi_tl(cpu_tmp0, npc);

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));

}

static inline void gen_goto_tb(DisasContext *s, int tb_num,

                               target_ulong pc, target_ulong npc)

{

    TranslationBlock *tb;

    tb = s->tb;

    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&

        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {

        /* jump to same page: we can use a direct jump */

        tcg_gen_goto_tb(tb_num);

        gen_jmp_im(pc);

        gen_movl_npc_im(npc);

        tcg_gen_exit_tb((long)tb + tb_num);

    } else {

        /* jump to another page: currently not optimized */

        gen_jmp_im(pc);

        gen_movl_npc_im(npc);

        tcg_gen_exit_tb(0);

    }

}

static inline void gen_branch2(DisasContext *dc, target_ulong pc1,

                               target_ulong pc2)

{

    int l1;

    l1 = gen_new_label();

    gen_op_jz_T2_label(l1);

    gen_goto_tb(dc, 0, pc1, pc1 + 4);

    gen_set_label(l1);

    gen_goto_tb(dc, 1, pc2, pc2 + 4);

}

static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,

                                target_ulong pc2)

{

    int l1;

    l1 = gen_new_label();

    gen_op_jz_T2_label(l1);

    gen_goto_tb(dc, 0, pc2, pc1);

    gen_set_label(l1);

    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);

}

static inline void gen_branch(DisasContext *dc, target_ulong pc,

                              target_ulong npc)

{

    gen_goto_tb(dc, 0, pc, npc);

}

static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    gen_op_jz_T2_label(l1);

    gen_movl_npc_im(npc1);

    gen_op_jmp_label(l2);

    gen_set_label(l1);

    gen_movl_npc_im(npc2);

    gen_set_label(l2);

}

/* call this function before using T2 as it may have been set for a jump */

static inline void flush_T2(DisasContext * dc)

{

    if (dc->npc == JUMP_PC) {

        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);

        dc->npc = DYNAMIC_PC;

    }

}

static inline void save_npc(DisasContext * dc)

{

    if (dc->npc == JUMP_PC) {

        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);

        dc->npc = DYNAMIC_PC;

    } else if (dc->npc != DYNAMIC_PC) {

        gen_movl_npc_im(dc->npc);

    }

}

static inline void save_state(DisasContext * dc)

{

    gen_jmp_im(dc->pc);

    save_npc(dc);

}

static inline void gen_mov_pc_npc(DisasContext * dc)

{

    if (dc->npc == JUMP_PC) {

        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);

        tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));

        tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));

        dc->pc = DYNAMIC_PC;

    } else if (dc->npc == DYNAMIC_PC) {

        tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));

        tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));

        dc->pc = DYNAMIC_PC;

    } else {

        dc->pc = dc->npc;

    }

}

static inline void gen_op_next_insn(void)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));

    tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));

}

static GenOpFunc * const gen_cond[2][16] = {

    {

        gen_op_eval_bn,

        gen_op_eval_be,

        gen_op_eval_ble,

        gen_op_eval_bl,

        gen_op_eval_bleu,

        gen_op_eval_bcs,

        gen_op_eval_bneg,

        gen_op_eval_bvs,

        gen_op_eval_ba,

        gen_op_eval_bne,

        gen_op_eval_bg,

        gen_op_eval_bge,

        gen_op_eval_bgu,

        gen_op_eval_bcc,

        gen_op_eval_bpos,

        gen_op_eval_bvc,

    },

    {

#ifdef TARGET_SPARC64

        gen_op_eval_bn,

        gen_op_eval_xbe,

        gen_op_eval_xble,

        gen_op_eval_xbl,

        gen_op_eval_xbleu,

        gen_op_eval_xbcs,

        gen_op_eval_xbneg,

        gen_op_eval_xbvs,

        gen_op_eval_ba,

        gen_op_eval_xbne,

        gen_op_eval_xbg,

        gen_op_eval_xbge,

        gen_op_eval_xbgu,

        gen_op_eval_xbcc,

        gen_op_eval_xbpos,

        gen_op_eval_xbvc,

#endif

    },

};

static GenOpFunc * const gen_fcond[4][16] = {

    {

        gen_op_eval_bn,

        gen_op_eval_fbne,

        gen_op_eval_fblg,

        gen_op_eval_fbul,

        gen_op_eval_fbl,

        gen_op_eval_fbug,

        gen_op_eval_fbg,

        gen_op_eval_fbu,

        gen_op_eval_ba,

        gen_op_eval_fbe,

        gen_op_eval_fbue,

        gen_op_eval_fbge,

        gen_op_eval_fbuge,

        gen_op_eval_fble,

        gen_op_eval_fbule,

        gen_op_eval_fbo,

    },

#ifdef TARGET_SPARC64

    {

        gen_op_eval_bn,

        gen_op_eval_fbne_fcc1,

        gen_op_eval_fblg_fcc1,

        gen_op_eval_fbul_fcc1,

        gen_op_eval_fbl_fcc1,

        gen_op_eval_fbug_fcc1,

        gen_op_eval_fbg_fcc1,

        gen_op_eval_fbu_fcc1,

        gen_op_eval_ba,

        gen_op_eval_fbe_fcc1,

        gen_op_eval_fbue_fcc1,

        gen_op_eval_fbge_fcc1,

        gen_op_eval_fbuge_fcc1,

        gen_op_eval_fble_fcc1,

        gen_op_eval_fbule_fcc1,

        gen_op_eval_fbo_fcc1,

    },

    {

        gen_op_eval_bn,

        gen_op_eval_fbne_fcc2,

        gen_op_eval_fblg_fcc2,

        gen_op_eval_fbul_fcc2,

        gen_op_eval_fbl_fcc2,

        gen_op_eval_fbug_fcc2,

        gen_op_eval_fbg_fcc2,

        gen_op_eval_fbu_fcc2,

        gen_op_eval_ba,

        gen_op_eval_fbe_fcc2,

        gen_op_eval_fbue_fcc2,

        gen_op_eval_fbge_fcc2,

        gen_op_eval_fbuge_fcc2,

        gen_op_eval_fble_fcc2,

        gen_op_eval_fbule_fcc2,

        gen_op_eval_fbo_fcc2,

    },

    {

        gen_op_eval_bn,

        gen_op_eval_fbne_fcc3,

        gen_op_eval_fblg_fcc3,

        gen_op_eval_fbul_fcc3,

        gen_op_eval_fbl_fcc3,

        gen_op_eval_fbug_fcc3,

        gen_op_eval_fbg_fcc3,

        gen_op_eval_fbu_fcc3,

        gen_op_eval_ba,

        gen_op_eval_fbe_fcc3,

        gen_op_eval_fbue_fcc3,

        gen_op_eval_fbge_fcc3,

        gen_op_eval_fbuge_fcc3,

        gen_op_eval_fble_fcc3,

        gen_op_eval_fbule_fcc3,

        gen_op_eval_fbo_fcc3,

    },

#else

    {}, {}, {},

#endif

};

#ifdef TARGET_SPARC64

static void gen_cond_reg(int cond)

{

        switch (cond) {

        case 0x1:

            gen_op_eval_brz();

            break;

        case 0x2:

            gen_op_eval_brlez();

            break;

        case 0x3:

            gen_op_eval_brlz();

            break;

        case 0x5:

            gen_op_eval_brnz();

            break;

        case 0x6:

            gen_op_eval_brgz();

            break;

        default:

        case 0x7:

            gen_op_eval_brgez();

            break;

        }

}

// Inverted logic

static const int gen_tcg_cond_reg[8] = {

    -1,

    TCG_COND_NE,

    TCG_COND_GT,

    TCG_COND_GE,

    -1,

    TCG_COND_EQ,

    TCG_COND_LE,

    TCG_COND_LT,

};

#endif

/* XXX: potentially incorrect if dynamic npc */

static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)

{

    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));

    target_ulong target = dc->pc + offset;

    if (cond == 0x0) {

        /* unconditional not taken */

        if (a) {

            dc->pc = dc->npc + 4;

            dc->npc = dc->pc + 4;

        } else {

            dc->pc = dc->npc;

            dc->npc = dc->pc + 4;

        }

    } else if (cond == 0x8) {

        /* unconditional taken */

        if (a) {

            dc->pc = target;

            dc->npc = dc->pc + 4;

        } else {

            dc->pc = dc->npc;

            dc->npc = target;

        }

    } else {

        flush_T2(dc);

        gen_cond[cc][cond]();

        if (a) {

            gen_branch_a(dc, target, dc->npc);

            dc->is_br = 1;

        } else {

            dc->pc = dc->npc;

            dc->jump_pc[0] = target;

            dc->jump_pc[1] = dc->npc + 4;

            dc->npc = JUMP_PC;

        }

    }

}

/* XXX: potentially incorrect if dynamic npc */

static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)

{

    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));

    target_ulong target = dc->pc + offset;

    if (cond == 0x0) {

        /* unconditional not taken */

        if (a) {

            dc->pc = dc->npc + 4;

            dc->npc = dc->pc + 4;

        } else {

            dc->pc = dc->npc;

            dc->npc = dc->pc + 4;

        }

    } else if (cond == 0x8) {

        /* unconditional taken */

        if (a) {

            dc->pc = target;

            dc->npc = dc->pc + 4;

        } else {

            dc->pc = dc->npc;

            dc->npc = target;

        }

    } else {

        flush_T2(dc);

        gen_fcond[cc][cond]();

        if (a) {

            gen_branch_a(dc, target, dc->npc);

            dc->is_br = 1;

        } else {

            dc->pc = dc->npc;

            dc->jump_pc[0] = target;

            dc->jump_pc[1] = dc->npc + 4;

            dc->npc = JUMP_PC;

        }

    }

}

#ifdef TARGET_SPARC64

/* XXX: potentially incorrect if dynamic npc */

static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)

{

    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));

    target_ulong target = dc->pc + offset;

    flush_T2(dc);

    gen_cond_reg(cond);

    if (a) {

        gen_branch_a(dc, target, dc->npc);

        dc->is_br = 1;

    } else {

        dc->pc = dc->npc;

        dc->jump_pc[0] = target;

        dc->jump_pc[1] = dc->npc + 4;

        dc->npc = JUMP_PC;

    }

}

static GenOpFunc * const gen_fcmps[4] = {

    helper_fcmps,

    helper_fcmps_fcc1,

    helper_fcmps_fcc2,

    helper_fcmps_fcc3,

};

static GenOpFunc * const gen_fcmpd[4] = {

    helper_fcmpd,

    helper_fcmpd_fcc1,

    helper_fcmpd_fcc2,

    helper_fcmpd_fcc3,

};

#if defined(CONFIG_USER_ONLY)

static GenOpFunc * const gen_fcmpq[4] = {

    helper_fcmpq,

    helper_fcmpq_fcc1,

    helper_fcmpq_fcc2,

    helper_fcmpq_fcc3,

};

#endif

static GenOpFunc * const gen_fcmpes[4] = {

    helper_fcmpes,

    helper_fcmpes_fcc1,

    helper_fcmpes_fcc2,

    helper_fcmpes_fcc3,

};

static GenOpFunc * const gen_fcmped[4] = {

    helper_fcmped,

    helper_fcmped_fcc1,

    helper_fcmped_fcc2,

    helper_fcmped_fcc3,

};

#if defined(CONFIG_USER_ONLY)

static GenOpFunc * const gen_fcmpeq[4] = {

    helper_fcmpeq,

    helper_fcmpeq_fcc1,

    helper_fcmpeq_fcc2,

    helper_fcmpeq_fcc3,

};

#endif

static inline void gen_op_fcmps(int fccno)

{

    tcg_gen_helper_0_0(gen_fcmps[fccno]);

}

static inline void gen_op_fcmpd(int fccno)

{

    tcg_gen_helper_0_0(gen_fcmpd[fccno]);

}

#if defined(CONFIG_USER_ONLY)

static inline void gen_op_fcmpq(int fccno)

{

    tcg_gen_helper_0_0(gen_fcmpq[fccno]);

}

#endif

static inline void gen_op_fcmpes(int fccno)

{

    tcg_gen_helper_0_0(gen_fcmpes[fccno]);

}

static inline void gen_op_fcmped(int fccno)

{

    tcg_gen_helper_0_0(gen_fcmped[fccno]);

}

#if defined(CONFIG_USER_ONLY)

static inline void gen_op_fcmpeq(int fccno)

{

    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);

}

#endif

#else

static inline void gen_op_fcmps(int fccno)

{

    tcg_gen_helper_0_0(helper_fcmps);

}

static inline void gen_op_fcmpd(int fccno)

{

    tcg_gen_helper_0_0(helper_fcmpd);

}

#if defined(CONFIG_USER_ONLY)

static inline void gen_op_fcmpq(int fccno)

{

    tcg_gen_helper_0_0(helper_fcmpq);

}

#endif

static inline void gen_op_fcmpes(int fccno)

{

    tcg_gen_helper_0_0(helper_fcmpes);

}

static inline void gen_op_fcmped(int fccno)

{

    tcg_gen_helper_0_0(helper_fcmped);

}

#if defined(CONFIG_USER_ONLY)

static inline void gen_op_fcmpeq(int fccno)

{

    tcg_gen_helper_0_0(helper_fcmpeq);

}

#endif

#endif

static int gen_trap_ifnofpu(DisasContext * dc)

{

#if !defined(CONFIG_USER_ONLY)

    if (!dc->fpu_enabled) {

        save_state(dc);

        gen_op_exception(TT_NFPU_INSN);

        dc->is_br = 1;

        return 1;

    }

#endif

    return 0;

}

static inline void gen_op_clear_ieee_excp_and_FTT(void)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~(FSR_FTT_MASK | FSR_CEXC_MASK));

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));

}

static inline void gen_clear_float_exceptions(void)

{

    tcg_gen_helper_0_0(helper_clear_float_exceptions);

}

/* asi moves */

#ifdef TARGET_SPARC64

static inline void gen_ld_asi(int insn, int size, int sign)

{

    int asi, offset;

    TCGv r_size, r_sign;

    r_size = tcg_temp_new(TCG_TYPE_I32);

    r_sign = tcg_temp_new(TCG_TYPE_I32);

    tcg_gen_movi_i32(r_size, size);

    tcg_gen_movi_i32(r_sign, sign);

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);

        tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));

    } else {

        asi = GET_FIELD(insn, 19, 26);

        tcg_gen_movi_i32(cpu_T[1], asi);

    }

    tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,

                       r_sign);

}

static inline void gen_st_asi(int insn, int size)

{

    int asi, offset;

    TCGv r_asi, r_size;

    r_asi = tcg_temp_new(TCG_TYPE_I32);

    r_size = tcg_temp_new(TCG_TYPE_I32);

    tcg_gen_movi_i32(r_size, size);

    if (IS_IMM) {

        offset = GET_FIELD(insn, 25, 31);

        tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);

        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));

    } else {

        asi = GET_FIELD(insn, 19, 26);

        tcg_gen_movi_i32(r_asi, asi);

    }

    tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);

}

static inline void gen_ldf_asi(int insn, int size, int rd)

{

    int asi, offset;

    TCGv r_asi, r_size, r_rd;

    r_asi = tcg_temp_new(TCG_TYPE_I32);

    r_size = tcg_temp_new(TCG_TYPE_I32);

    r_rd = tcg_temp_new(TCG_TYPE_I32);

    tcg_gen_movi_i32(r_size, size);

    tcg_gen_movi_i32(r_rd, rd);

    if (IS_IMM) {