Revision 375ee38b target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 1386 | 1386 |
rs1 = GET_FIELD(insn, 13, 17); |
| 1387 | 1387 |
switch (rs1) {
|
| 1388 | 1388 |
case 0: // tpc |
| 1389 |
gen_op_rdtpc(); |
|
| 1389 |
{
|
|
| 1390 |
TCGv r_tsptr; |
|
| 1391 |
|
|
| 1392 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1393 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 1394 |
offsetof(CPUState, tsptr)); |
|
| 1395 |
tcg_gen_ld_tl(cpu_T[0], r_tsptr, |
|
| 1396 |
offsetof(trap_state, tpc)); |
|
| 1397 |
} |
|
| 1390 | 1398 |
break; |
| 1391 | 1399 |
case 1: // tnpc |
| 1392 |
gen_op_rdtnpc(); |
|
| 1400 |
{
|
|
| 1401 |
TCGv r_tsptr; |
|
| 1402 |
|
|
| 1403 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1404 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 1405 |
offsetof(CPUState, tsptr)); |
|
| 1406 |
tcg_gen_ld_tl(cpu_T[0], r_tsptr, |
|
| 1407 |
offsetof(trap_state, tnpc)); |
|
| 1408 |
} |
|
| 1393 | 1409 |
break; |
| 1394 | 1410 |
case 2: // tstate |
| 1395 |
gen_op_rdtstate(); |
|
| 1411 |
{
|
|
| 1412 |
TCGv r_tsptr; |
|
| 1413 |
|
|
| 1414 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1415 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 1416 |
offsetof(CPUState, tsptr)); |
|
| 1417 |
tcg_gen_ld_tl(cpu_T[0], r_tsptr, |
|
| 1418 |
offsetof(trap_state, tstate)); |
|
| 1419 |
} |
|
| 1396 | 1420 |
break; |
| 1397 | 1421 |
case 3: // tt |
| 1398 |
gen_op_rdtt(); |
|
| 1422 |
{
|
|
| 1423 |
TCGv r_tsptr; |
|
| 1424 |
|
|
| 1425 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1426 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 1427 |
offsetof(CPUState, tsptr)); |
|
| 1428 |
tcg_gen_ld_i32(cpu_T[0], r_tsptr, |
|
| 1429 |
offsetof(trap_state, tt)); |
|
| 1430 |
} |
|
| 1399 | 1431 |
break; |
| 1400 | 1432 |
case 4: // tick |
| 1401 | 1433 |
{
|
| ... | ... | |
| 2536 | 2568 |
#ifdef TARGET_SPARC64 |
| 2537 | 2569 |
switch (rd) {
|
| 2538 | 2570 |
case 0: // tpc |
| 2539 |
gen_op_wrtpc(); |
|
| 2571 |
{
|
|
| 2572 |
TCGv r_tsptr; |
|
| 2573 |
|
|
| 2574 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2575 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 2576 |
offsetof(CPUState, tsptr)); |
|
| 2577 |
tcg_gen_st_tl(cpu_T[0], r_tsptr, |
|
| 2578 |
offsetof(trap_state, tpc)); |
|
| 2579 |
} |
|
| 2540 | 2580 |
break; |
| 2541 | 2581 |
case 1: // tnpc |
| 2542 |
gen_op_wrtnpc(); |
|
| 2582 |
{
|
|
| 2583 |
TCGv r_tsptr; |
|
| 2584 |
|
|
| 2585 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2586 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 2587 |
offsetof(CPUState, tsptr)); |
|
| 2588 |
tcg_gen_st_tl(cpu_T[0], r_tsptr, |
|
| 2589 |
offsetof(trap_state, tnpc)); |
|
| 2590 |
} |
|
| 2543 | 2591 |
break; |
| 2544 | 2592 |
case 2: // tstate |
| 2545 |
gen_op_wrtstate(); |
|
| 2593 |
{
|
|
| 2594 |
TCGv r_tsptr; |
|
| 2595 |
|
|
| 2596 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2597 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 2598 |
offsetof(CPUState, tsptr)); |
|
| 2599 |
tcg_gen_st_tl(cpu_T[0], r_tsptr, |
|
| 2600 |
offsetof(trap_state, tstate)); |
|
| 2601 |
} |
|
| 2546 | 2602 |
break; |
| 2547 | 2603 |
case 3: // tt |
| 2548 |
gen_op_wrtt(); |
|
| 2604 |
{
|
|
| 2605 |
TCGv r_tsptr; |
|
| 2606 |
|
|
| 2607 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2608 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
|
| 2609 |
offsetof(CPUState, tsptr)); |
|
| 2610 |
tcg_gen_st_i32(cpu_T[0], r_tsptr, |
|
| 2611 |
offsetof(trap_state, tt)); |
|
| 2612 |
} |
|
| 2549 | 2613 |
break; |
| 2550 | 2614 |
case 4: // tick |
| 2551 | 2615 |
{
|
| ... | ... | |
| 3921 | 3985 |
env->pstate = PS_PRIV; |
| 3922 | 3986 |
env->hpstate = HS_PRIV; |
| 3923 | 3987 |
env->pc = 0x1fff0000000ULL; |
| 3988 |
env->tsptr = &env->ts[env->tl]; |
|
| 3924 | 3989 |
#else |
| 3925 | 3990 |
env->pc = 0; |
| 3926 | 3991 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
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