root / opc-i386.h @ 378180d8
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| 1 |
DEF(end, 0)
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|---|---|
| 2 |
DEF(movl_A0_EAX, 0)
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| 3 |
DEF(addl_A0_EAX, 0)
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| 4 |
DEF(addl_A0_EAX_s1, 0)
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| 5 |
DEF(addl_A0_EAX_s2, 0)
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| 6 |
DEF(addl_A0_EAX_s3, 0)
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| 7 |
DEF(movl_T0_EAX, 0)
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| 8 |
DEF(movl_T1_EAX, 0)
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| 9 |
DEF(movh_T0_EAX, 0)
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| 10 |
DEF(movh_T1_EAX, 0)
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| 11 |
DEF(movl_EAX_T0, 0)
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| 12 |
DEF(movl_EAX_T1, 0)
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| 13 |
DEF(movl_EAX_A0, 0)
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| 14 |
DEF(cmovw_EAX_T1_T0, 0)
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| 15 |
DEF(cmovl_EAX_T1_T0, 0)
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| 16 |
DEF(movw_EAX_T0, 0)
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| 17 |
DEF(movw_EAX_T1, 0)
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| 18 |
DEF(movw_EAX_A0, 0)
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| 19 |
DEF(movb_EAX_T0, 0)
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| 20 |
DEF(movh_EAX_T0, 0)
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| 21 |
DEF(movb_EAX_T1, 0)
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| 22 |
DEF(movh_EAX_T1, 0)
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| 23 |
DEF(movl_A0_ECX, 0)
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| 24 |
DEF(addl_A0_ECX, 0)
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| 25 |
DEF(addl_A0_ECX_s1, 0)
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| 26 |
DEF(addl_A0_ECX_s2, 0)
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| 27 |
DEF(addl_A0_ECX_s3, 0)
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| 28 |
DEF(movl_T0_ECX, 0)
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| 29 |
DEF(movl_T1_ECX, 0)
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| 30 |
DEF(movh_T0_ECX, 0)
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| 31 |
DEF(movh_T1_ECX, 0)
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| 32 |
DEF(movl_ECX_T0, 0)
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| 33 |
DEF(movl_ECX_T1, 0)
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| 34 |
DEF(movl_ECX_A0, 0)
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| 35 |
DEF(cmovw_ECX_T1_T0, 0)
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| 36 |
DEF(cmovl_ECX_T1_T0, 0)
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| 37 |
DEF(movw_ECX_T0, 0)
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| 38 |
DEF(movw_ECX_T1, 0)
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| 39 |
DEF(movw_ECX_A0, 0)
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| 40 |
DEF(movb_ECX_T0, 0)
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| 41 |
DEF(movh_ECX_T0, 0)
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| 42 |
DEF(movb_ECX_T1, 0)
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| 43 |
DEF(movh_ECX_T1, 0)
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| 44 |
DEF(movl_A0_EDX, 0)
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| 45 |
DEF(addl_A0_EDX, 0)
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| 46 |
DEF(addl_A0_EDX_s1, 0)
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| 47 |
DEF(addl_A0_EDX_s2, 0)
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| 48 |
DEF(addl_A0_EDX_s3, 0)
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| 49 |
DEF(movl_T0_EDX, 0)
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| 50 |
DEF(movl_T1_EDX, 0)
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| 51 |
DEF(movh_T0_EDX, 0)
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| 52 |
DEF(movh_T1_EDX, 0)
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| 53 |
DEF(movl_EDX_T0, 0)
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| 54 |
DEF(movl_EDX_T1, 0)
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| 55 |
DEF(movl_EDX_A0, 0)
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| 56 |
DEF(cmovw_EDX_T1_T0, 0)
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| 57 |
DEF(cmovl_EDX_T1_T0, 0)
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| 58 |
DEF(movw_EDX_T0, 0)
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| 59 |
DEF(movw_EDX_T1, 0)
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| 60 |
DEF(movw_EDX_A0, 0)
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| 61 |
DEF(movb_EDX_T0, 0)
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| 62 |
DEF(movh_EDX_T0, 0)
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| 63 |
DEF(movb_EDX_T1, 0)
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| 64 |
DEF(movh_EDX_T1, 0)
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| 65 |
DEF(movl_A0_EBX, 0)
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| 66 |
DEF(addl_A0_EBX, 0)
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| 67 |
DEF(addl_A0_EBX_s1, 0)
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| 68 |
DEF(addl_A0_EBX_s2, 0)
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| 69 |
DEF(addl_A0_EBX_s3, 0)
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| 70 |
DEF(movl_T0_EBX, 0)
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| 71 |
DEF(movl_T1_EBX, 0)
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| 72 |
DEF(movh_T0_EBX, 0)
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| 73 |
DEF(movh_T1_EBX, 0)
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| 74 |
DEF(movl_EBX_T0, 0)
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| 75 |
DEF(movl_EBX_T1, 0)
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| 76 |
DEF(movl_EBX_A0, 0)
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| 77 |
DEF(cmovw_EBX_T1_T0, 0)
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| 78 |
DEF(cmovl_EBX_T1_T0, 0)
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| 79 |
DEF(movw_EBX_T0, 0)
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| 80 |
DEF(movw_EBX_T1, 0)
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| 81 |
DEF(movw_EBX_A0, 0)
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| 82 |
DEF(movb_EBX_T0, 0)
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| 83 |
DEF(movh_EBX_T0, 0)
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| 84 |
DEF(movb_EBX_T1, 0)
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| 85 |
DEF(movh_EBX_T1, 0)
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| 86 |
DEF(movl_A0_ESP, 0)
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| 87 |
DEF(addl_A0_ESP, 0)
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| 88 |
DEF(addl_A0_ESP_s1, 0)
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| 89 |
DEF(addl_A0_ESP_s2, 0)
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| 90 |
DEF(addl_A0_ESP_s3, 0)
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| 91 |
DEF(movl_T0_ESP, 0)
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| 92 |
DEF(movl_T1_ESP, 0)
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| 93 |
DEF(movh_T0_ESP, 0)
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| 94 |
DEF(movh_T1_ESP, 0)
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| 95 |
DEF(movl_ESP_T0, 0)
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| 96 |
DEF(movl_ESP_T1, 0)
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| 97 |
DEF(movl_ESP_A0, 0)
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| 98 |
DEF(cmovw_ESP_T1_T0, 0)
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| 99 |
DEF(cmovl_ESP_T1_T0, 0)
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| 100 |
DEF(movw_ESP_T0, 0)
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| 101 |
DEF(movw_ESP_T1, 0)
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| 102 |
DEF(movw_ESP_A0, 0)
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| 103 |
DEF(movb_ESP_T0, 0)
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| 104 |
DEF(movh_ESP_T0, 0)
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| 105 |
DEF(movb_ESP_T1, 0)
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| 106 |
DEF(movh_ESP_T1, 0)
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| 107 |
DEF(movl_A0_EBP, 0)
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| 108 |
DEF(addl_A0_EBP, 0)
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| 109 |
DEF(addl_A0_EBP_s1, 0)
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| 110 |
DEF(addl_A0_EBP_s2, 0)
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| 111 |
DEF(addl_A0_EBP_s3, 0)
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| 112 |
DEF(movl_T0_EBP, 0)
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| 113 |
DEF(movl_T1_EBP, 0)
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| 114 |
DEF(movh_T0_EBP, 0)
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| 115 |
DEF(movh_T1_EBP, 0)
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| 116 |
DEF(movl_EBP_T0, 0)
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| 117 |
DEF(movl_EBP_T1, 0)
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| 118 |
DEF(movl_EBP_A0, 0)
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| 119 |
DEF(cmovw_EBP_T1_T0, 0)
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| 120 |
DEF(cmovl_EBP_T1_T0, 0)
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| 121 |
DEF(movw_EBP_T0, 0)
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| 122 |
DEF(movw_EBP_T1, 0)
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| 123 |
DEF(movw_EBP_A0, 0)
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| 124 |
DEF(movb_EBP_T0, 0)
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| 125 |
DEF(movh_EBP_T0, 0)
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| 126 |
DEF(movb_EBP_T1, 0)
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| 127 |
DEF(movh_EBP_T1, 0)
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| 128 |
DEF(movl_A0_ESI, 0)
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| 129 |
DEF(addl_A0_ESI, 0)
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| 130 |
DEF(addl_A0_ESI_s1, 0)
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| 131 |
DEF(addl_A0_ESI_s2, 0)
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| 132 |
DEF(addl_A0_ESI_s3, 0)
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| 133 |
DEF(movl_T0_ESI, 0)
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| 134 |
DEF(movl_T1_ESI, 0)
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| 135 |
DEF(movh_T0_ESI, 0)
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| 136 |
DEF(movh_T1_ESI, 0)
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| 137 |
DEF(movl_ESI_T0, 0)
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| 138 |
DEF(movl_ESI_T1, 0)
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| 139 |
DEF(movl_ESI_A0, 0)
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| 140 |
DEF(cmovw_ESI_T1_T0, 0)
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| 141 |
DEF(cmovl_ESI_T1_T0, 0)
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| 142 |
DEF(movw_ESI_T0, 0)
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| 143 |
DEF(movw_ESI_T1, 0)
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| 144 |
DEF(movw_ESI_A0, 0)
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| 145 |
DEF(movb_ESI_T0, 0)
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| 146 |
DEF(movh_ESI_T0, 0)
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| 147 |
DEF(movb_ESI_T1, 0)
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| 148 |
DEF(movh_ESI_T1, 0)
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| 149 |
DEF(movl_A0_EDI, 0)
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| 150 |
DEF(addl_A0_EDI, 0)
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| 151 |
DEF(addl_A0_EDI_s1, 0)
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| 152 |
DEF(addl_A0_EDI_s2, 0)
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| 153 |
DEF(addl_A0_EDI_s3, 0)
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| 154 |
DEF(movl_T0_EDI, 0)
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| 155 |
DEF(movl_T1_EDI, 0)
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| 156 |
DEF(movh_T0_EDI, 0)
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| 157 |
DEF(movh_T1_EDI, 0)
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| 158 |
DEF(movl_EDI_T0, 0)
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| 159 |
DEF(movl_EDI_T1, 0)
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| 160 |
DEF(movl_EDI_A0, 0)
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| 161 |
DEF(cmovw_EDI_T1_T0, 0)
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| 162 |
DEF(cmovl_EDI_T1_T0, 0)
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| 163 |
DEF(movw_EDI_T0, 0)
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| 164 |
DEF(movw_EDI_T1, 0)
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| 165 |
DEF(movw_EDI_A0, 0)
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| 166 |
DEF(movb_EDI_T0, 0)
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| 167 |
DEF(movh_EDI_T0, 0)
|
| 168 |
DEF(movb_EDI_T1, 0)
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| 169 |
DEF(movh_EDI_T1, 0)
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| 170 |
DEF(addl_T0_T1_cc, 0)
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| 171 |
DEF(orl_T0_T1_cc, 0)
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| 172 |
DEF(andl_T0_T1_cc, 0)
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| 173 |
DEF(subl_T0_T1_cc, 0)
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| 174 |
DEF(xorl_T0_T1_cc, 0)
|
| 175 |
DEF(cmpl_T0_T1_cc, 0)
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| 176 |
DEF(negl_T0_cc, 0)
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| 177 |
DEF(incl_T0_cc, 0)
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| 178 |
DEF(decl_T0_cc, 0)
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| 179 |
DEF(testl_T0_T1_cc, 0)
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| 180 |
DEF(addl_T0_T1, 0)
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| 181 |
DEF(orl_T0_T1, 0)
|
| 182 |
DEF(andl_T0_T1, 0)
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| 183 |
DEF(subl_T0_T1, 0)
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| 184 |
DEF(xorl_T0_T1, 0)
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| 185 |
DEF(negl_T0, 0)
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| 186 |
DEF(incl_T0, 0)
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| 187 |
DEF(decl_T0, 0)
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| 188 |
DEF(notl_T0, 0)
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| 189 |
DEF(bswapl_T0, 0)
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| 190 |
DEF(mulb_AL_T0, 0)
|
| 191 |
DEF(imulb_AL_T0, 0)
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| 192 |
DEF(mulw_AX_T0, 0)
|
| 193 |
DEF(imulw_AX_T0, 0)
|
| 194 |
DEF(mull_EAX_T0, 0)
|
| 195 |
DEF(imull_EAX_T0, 0)
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| 196 |
DEF(imulw_T0_T1, 0)
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| 197 |
DEF(imull_T0_T1, 0)
|
| 198 |
DEF(divb_AL_T0, 0)
|
| 199 |
DEF(idivb_AL_T0, 0)
|
| 200 |
DEF(divw_AX_T0, 0)
|
| 201 |
DEF(idivw_AX_T0, 0)
|
| 202 |
DEF(divl_EAX_T0, 0)
|
| 203 |
DEF(idivl_EAX_T0, 0)
|
| 204 |
DEF(movl_T0_im, 1)
|
| 205 |
DEF(addl_T0_im, 1)
|
| 206 |
DEF(andl_T0_ffff, 0)
|
| 207 |
DEF(movl_T0_T1, 0)
|
| 208 |
DEF(movl_T1_im, 1)
|
| 209 |
DEF(addl_T1_im, 1)
|
| 210 |
DEF(movl_T1_A0, 0)
|
| 211 |
DEF(movl_A0_im, 1)
|
| 212 |
DEF(addl_A0_im, 1)
|
| 213 |
DEF(addl_A0_AL, 0)
|
| 214 |
DEF(andl_A0_ffff, 0)
|
| 215 |
DEF(ldub_T0_A0, 0)
|
| 216 |
DEF(ldsb_T0_A0, 0)
|
| 217 |
DEF(lduw_T0_A0, 0)
|
| 218 |
DEF(ldsw_T0_A0, 0)
|
| 219 |
DEF(ldl_T0_A0, 0)
|
| 220 |
DEF(ldub_T1_A0, 0)
|
| 221 |
DEF(ldsb_T1_A0, 0)
|
| 222 |
DEF(lduw_T1_A0, 0)
|
| 223 |
DEF(ldsw_T1_A0, 0)
|
| 224 |
DEF(ldl_T1_A0, 0)
|
| 225 |
DEF(stb_T0_A0, 0)
|
| 226 |
DEF(stw_T0_A0, 0)
|
| 227 |
DEF(stl_T0_A0, 0)
|
| 228 |
DEF(add_bitw_A0_T1, 0)
|
| 229 |
DEF(add_bitl_A0_T1, 0)
|
| 230 |
DEF(jmp_T0, 0)
|
| 231 |
DEF(jmp_im, 1)
|
| 232 |
DEF(int_im, 2)
|
| 233 |
DEF(raise_exception, 1)
|
| 234 |
DEF(into, 0)
|
| 235 |
DEF(cli, 0)
|
| 236 |
DEF(sti, 0)
|
| 237 |
DEF(boundw, 0)
|
| 238 |
DEF(boundl, 0)
|
| 239 |
DEF(cmpxchg8b, 0)
|
| 240 |
DEF(jb_subb, 2)
|
| 241 |
DEF(jz_subb, 2)
|
| 242 |
DEF(jbe_subb, 2)
|
| 243 |
DEF(js_subb, 2)
|
| 244 |
DEF(jl_subb, 2)
|
| 245 |
DEF(jle_subb, 2)
|
| 246 |
DEF(setb_T0_subb, 0)
|
| 247 |
DEF(setz_T0_subb, 0)
|
| 248 |
DEF(setbe_T0_subb, 0)
|
| 249 |
DEF(sets_T0_subb, 0)
|
| 250 |
DEF(setl_T0_subb, 0)
|
| 251 |
DEF(setle_T0_subb, 0)
|
| 252 |
DEF(rolb_T0_T1_cc, 0)
|
| 253 |
DEF(rolb_T0_T1, 0)
|
| 254 |
DEF(rorb_T0_T1_cc, 0)
|
| 255 |
DEF(rorb_T0_T1, 0)
|
| 256 |
DEF(rclb_T0_T1_cc, 0)
|
| 257 |
DEF(rcrb_T0_T1_cc, 0)
|
| 258 |
DEF(shlb_T0_T1_cc, 0)
|
| 259 |
DEF(shlb_T0_T1, 0)
|
| 260 |
DEF(shrb_T0_T1_cc, 0)
|
| 261 |
DEF(shrb_T0_T1, 0)
|
| 262 |
DEF(sarb_T0_T1_cc, 0)
|
| 263 |
DEF(sarb_T0_T1, 0)
|
| 264 |
DEF(adcb_T0_T1_cc, 0)
|
| 265 |
DEF(sbbb_T0_T1_cc, 0)
|
| 266 |
DEF(cmpxchgb_T0_T1_EAX_cc, 0)
|
| 267 |
DEF(movsb_fast, 0)
|
| 268 |
DEF(rep_movsb_fast, 0)
|
| 269 |
DEF(stosb_fast, 0)
|
| 270 |
DEF(rep_stosb_fast, 0)
|
| 271 |
DEF(lodsb_fast, 0)
|
| 272 |
DEF(rep_lodsb_fast, 0)
|
| 273 |
DEF(scasb_fast, 0)
|
| 274 |
DEF(repz_scasb_fast, 0)
|
| 275 |
DEF(repnz_scasb_fast, 0)
|
| 276 |
DEF(cmpsb_fast, 0)
|
| 277 |
DEF(repz_cmpsb_fast, 0)
|
| 278 |
DEF(repnz_cmpsb_fast, 0)
|
| 279 |
DEF(outsb_fast, 0)
|
| 280 |
DEF(rep_outsb_fast, 0)
|
| 281 |
DEF(insb_fast, 0)
|
| 282 |
DEF(rep_insb_fast, 0)
|
| 283 |
DEF(movsb_a32, 0)
|
| 284 |
DEF(rep_movsb_a32, 0)
|
| 285 |
DEF(stosb_a32, 0)
|
| 286 |
DEF(rep_stosb_a32, 0)
|
| 287 |
DEF(lodsb_a32, 0)
|
| 288 |
DEF(rep_lodsb_a32, 0)
|
| 289 |
DEF(scasb_a32, 0)
|
| 290 |
DEF(repz_scasb_a32, 0)
|
| 291 |
DEF(repnz_scasb_a32, 0)
|
| 292 |
DEF(cmpsb_a32, 0)
|
| 293 |
DEF(repz_cmpsb_a32, 0)
|
| 294 |
DEF(repnz_cmpsb_a32, 0)
|
| 295 |
DEF(outsb_a32, 0)
|
| 296 |
DEF(rep_outsb_a32, 0)
|
| 297 |
DEF(insb_a32, 0)
|
| 298 |
DEF(rep_insb_a32, 0)
|
| 299 |
DEF(movsb_a16, 0)
|
| 300 |
DEF(rep_movsb_a16, 0)
|
| 301 |
DEF(stosb_a16, 0)
|
| 302 |
DEF(rep_stosb_a16, 0)
|
| 303 |
DEF(lodsb_a16, 0)
|
| 304 |
DEF(rep_lodsb_a16, 0)
|
| 305 |
DEF(scasb_a16, 0)
|
| 306 |
DEF(repz_scasb_a16, 0)
|
| 307 |
DEF(repnz_scasb_a16, 0)
|
| 308 |
DEF(cmpsb_a16, 0)
|
| 309 |
DEF(repz_cmpsb_a16, 0)
|
| 310 |
DEF(repnz_cmpsb_a16, 0)
|
| 311 |
DEF(outsb_a16, 0)
|
| 312 |
DEF(rep_outsb_a16, 0)
|
| 313 |
DEF(insb_a16, 0)
|
| 314 |
DEF(rep_insb_a16, 0)
|
| 315 |
DEF(outb_T0_T1, 0)
|
| 316 |
DEF(inb_T0_T1, 0)
|
| 317 |
DEF(jb_subw, 2)
|
| 318 |
DEF(jz_subw, 2)
|
| 319 |
DEF(jbe_subw, 2)
|
| 320 |
DEF(js_subw, 2)
|
| 321 |
DEF(jl_subw, 2)
|
| 322 |
DEF(jle_subw, 2)
|
| 323 |
DEF(loopnzw, 2)
|
| 324 |
DEF(loopzw, 2)
|
| 325 |
DEF(loopw, 2)
|
| 326 |
DEF(jecxzw, 2)
|
| 327 |
DEF(setb_T0_subw, 0)
|
| 328 |
DEF(setz_T0_subw, 0)
|
| 329 |
DEF(setbe_T0_subw, 0)
|
| 330 |
DEF(sets_T0_subw, 0)
|
| 331 |
DEF(setl_T0_subw, 0)
|
| 332 |
DEF(setle_T0_subw, 0)
|
| 333 |
DEF(rolw_T0_T1_cc, 0)
|
| 334 |
DEF(rolw_T0_T1, 0)
|
| 335 |
DEF(rorw_T0_T1_cc, 0)
|
| 336 |
DEF(rorw_T0_T1, 0)
|
| 337 |
DEF(rclw_T0_T1_cc, 0)
|
| 338 |
DEF(rcrw_T0_T1_cc, 0)
|
| 339 |
DEF(shlw_T0_T1_cc, 0)
|
| 340 |
DEF(shlw_T0_T1, 0)
|
| 341 |
DEF(shrw_T0_T1_cc, 0)
|
| 342 |
DEF(shrw_T0_T1, 0)
|
| 343 |
DEF(sarw_T0_T1_cc, 0)
|
| 344 |
DEF(sarw_T0_T1, 0)
|
| 345 |
DEF(shldw_T0_T1_im_cc, 1)
|
| 346 |
DEF(shldw_T0_T1_ECX_cc, 0)
|
| 347 |
DEF(shrdw_T0_T1_im_cc, 1)
|
| 348 |
DEF(shrdw_T0_T1_ECX_cc, 0)
|
| 349 |
DEF(adcw_T0_T1_cc, 0)
|
| 350 |
DEF(sbbw_T0_T1_cc, 0)
|
| 351 |
DEF(cmpxchgw_T0_T1_EAX_cc, 0)
|
| 352 |
DEF(btw_T0_T1_cc, 0)
|
| 353 |
DEF(btsw_T0_T1_cc, 0)
|
| 354 |
DEF(btrw_T0_T1_cc, 0)
|
| 355 |
DEF(btcw_T0_T1_cc, 0)
|
| 356 |
DEF(bsfw_T0_cc, 0)
|
| 357 |
DEF(bsrw_T0_cc, 0)
|
| 358 |
DEF(movsw_fast, 0)
|
| 359 |
DEF(rep_movsw_fast, 0)
|
| 360 |
DEF(stosw_fast, 0)
|
| 361 |
DEF(rep_stosw_fast, 0)
|
| 362 |
DEF(lodsw_fast, 0)
|
| 363 |
DEF(rep_lodsw_fast, 0)
|
| 364 |
DEF(scasw_fast, 0)
|
| 365 |
DEF(repz_scasw_fast, 0)
|
| 366 |
DEF(repnz_scasw_fast, 0)
|
| 367 |
DEF(cmpsw_fast, 0)
|
| 368 |
DEF(repz_cmpsw_fast, 0)
|
| 369 |
DEF(repnz_cmpsw_fast, 0)
|
| 370 |
DEF(outsw_fast, 0)
|
| 371 |
DEF(rep_outsw_fast, 0)
|
| 372 |
DEF(insw_fast, 0)
|
| 373 |
DEF(rep_insw_fast, 0)
|
| 374 |
DEF(movsw_a32, 0)
|
| 375 |
DEF(rep_movsw_a32, 0)
|
| 376 |
DEF(stosw_a32, 0)
|
| 377 |
DEF(rep_stosw_a32, 0)
|
| 378 |
DEF(lodsw_a32, 0)
|
| 379 |
DEF(rep_lodsw_a32, 0)
|
| 380 |
DEF(scasw_a32, 0)
|
| 381 |
DEF(repz_scasw_a32, 0)
|
| 382 |
DEF(repnz_scasw_a32, 0)
|
| 383 |
DEF(cmpsw_a32, 0)
|
| 384 |
DEF(repz_cmpsw_a32, 0)
|
| 385 |
DEF(repnz_cmpsw_a32, 0)
|
| 386 |
DEF(outsw_a32, 0)
|
| 387 |
DEF(rep_outsw_a32, 0)
|
| 388 |
DEF(insw_a32, 0)
|
| 389 |
DEF(rep_insw_a32, 0)
|
| 390 |
DEF(movsw_a16, 0)
|
| 391 |
DEF(rep_movsw_a16, 0)
|
| 392 |
DEF(stosw_a16, 0)
|
| 393 |
DEF(rep_stosw_a16, 0)
|
| 394 |
DEF(lodsw_a16, 0)
|
| 395 |
DEF(rep_lodsw_a16, 0)
|
| 396 |
DEF(scasw_a16, 0)
|
| 397 |
DEF(repz_scasw_a16, 0)
|
| 398 |
DEF(repnz_scasw_a16, 0)
|
| 399 |
DEF(cmpsw_a16, 0)
|
| 400 |
DEF(repz_cmpsw_a16, 0)
|
| 401 |
DEF(repnz_cmpsw_a16, 0)
|
| 402 |
DEF(outsw_a16, 0)
|
| 403 |
DEF(rep_outsw_a16, 0)
|
| 404 |
DEF(insw_a16, 0)
|
| 405 |
DEF(rep_insw_a16, 0)
|
| 406 |
DEF(outw_T0_T1, 0)
|
| 407 |
DEF(inw_T0_T1, 0)
|
| 408 |
DEF(jb_subl, 2)
|
| 409 |
DEF(jz_subl, 2)
|
| 410 |
DEF(jbe_subl, 2)
|
| 411 |
DEF(js_subl, 2)
|
| 412 |
DEF(jl_subl, 2)
|
| 413 |
DEF(jle_subl, 2)
|
| 414 |
DEF(loopnzl, 2)
|
| 415 |
DEF(loopzl, 2)
|
| 416 |
DEF(loopl, 2)
|
| 417 |
DEF(jecxzl, 2)
|
| 418 |
DEF(setb_T0_subl, 0)
|
| 419 |
DEF(setz_T0_subl, 0)
|
| 420 |
DEF(setbe_T0_subl, 0)
|
| 421 |
DEF(sets_T0_subl, 0)
|
| 422 |
DEF(setl_T0_subl, 0)
|
| 423 |
DEF(setle_T0_subl, 0)
|
| 424 |
DEF(roll_T0_T1_cc, 0)
|
| 425 |
DEF(roll_T0_T1, 0)
|
| 426 |
DEF(rorl_T0_T1_cc, 0)
|
| 427 |
DEF(rorl_T0_T1, 0)
|
| 428 |
DEF(rcll_T0_T1_cc, 0)
|
| 429 |
DEF(rcrl_T0_T1_cc, 0)
|
| 430 |
DEF(shll_T0_T1_cc, 0)
|
| 431 |
DEF(shll_T0_T1, 0)
|
| 432 |
DEF(shrl_T0_T1_cc, 0)
|
| 433 |
DEF(shrl_T0_T1, 0)
|
| 434 |
DEF(sarl_T0_T1_cc, 0)
|
| 435 |
DEF(sarl_T0_T1, 0)
|
| 436 |
DEF(shldl_T0_T1_im_cc, 1)
|
| 437 |
DEF(shldl_T0_T1_ECX_cc, 0)
|
| 438 |
DEF(shrdl_T0_T1_im_cc, 1)
|
| 439 |
DEF(shrdl_T0_T1_ECX_cc, 0)
|
| 440 |
DEF(adcl_T0_T1_cc, 0)
|
| 441 |
DEF(sbbl_T0_T1_cc, 0)
|
| 442 |
DEF(cmpxchgl_T0_T1_EAX_cc, 0)
|
| 443 |
DEF(btl_T0_T1_cc, 0)
|
| 444 |
DEF(btsl_T0_T1_cc, 0)
|
| 445 |
DEF(btrl_T0_T1_cc, 0)
|
| 446 |
DEF(btcl_T0_T1_cc, 0)
|
| 447 |
DEF(bsfl_T0_cc, 0)
|
| 448 |
DEF(bsrl_T0_cc, 0)
|
| 449 |
DEF(movsl_fast, 0)
|
| 450 |
DEF(rep_movsl_fast, 0)
|
| 451 |
DEF(stosl_fast, 0)
|
| 452 |
DEF(rep_stosl_fast, 0)
|
| 453 |
DEF(lodsl_fast, 0)
|
| 454 |
DEF(rep_lodsl_fast, 0)
|
| 455 |
DEF(scasl_fast, 0)
|
| 456 |
DEF(repz_scasl_fast, 0)
|
| 457 |
DEF(repnz_scasl_fast, 0)
|
| 458 |
DEF(cmpsl_fast, 0)
|
| 459 |
DEF(repz_cmpsl_fast, 0)
|
| 460 |
DEF(repnz_cmpsl_fast, 0)
|
| 461 |
DEF(outsl_fast, 0)
|
| 462 |
DEF(rep_outsl_fast, 0)
|
| 463 |
DEF(insl_fast, 0)
|
| 464 |
DEF(rep_insl_fast, 0)
|
| 465 |
DEF(movsl_a32, 0)
|
| 466 |
DEF(rep_movsl_a32, 0)
|
| 467 |
DEF(stosl_a32, 0)
|
| 468 |
DEF(rep_stosl_a32, 0)
|
| 469 |
DEF(lodsl_a32, 0)
|
| 470 |
DEF(rep_lodsl_a32, 0)
|
| 471 |
DEF(scasl_a32, 0)
|
| 472 |
DEF(repz_scasl_a32, 0)
|
| 473 |
DEF(repnz_scasl_a32, 0)
|
| 474 |
DEF(cmpsl_a32, 0)
|
| 475 |
DEF(repz_cmpsl_a32, 0)
|
| 476 |
DEF(repnz_cmpsl_a32, 0)
|
| 477 |
DEF(outsl_a32, 0)
|
| 478 |
DEF(rep_outsl_a32, 0)
|
| 479 |
DEF(insl_a32, 0)
|
| 480 |
DEF(rep_insl_a32, 0)
|
| 481 |
DEF(movsl_a16, 0)
|
| 482 |
DEF(rep_movsl_a16, 0)
|
| 483 |
DEF(stosl_a16, 0)
|
| 484 |
DEF(rep_stosl_a16, 0)
|
| 485 |
DEF(lodsl_a16, 0)
|
| 486 |
DEF(rep_lodsl_a16, 0)
|
| 487 |
DEF(scasl_a16, 0)
|
| 488 |
DEF(repz_scasl_a16, 0)
|
| 489 |
DEF(repnz_scasl_a16, 0)
|
| 490 |
DEF(cmpsl_a16, 0)
|
| 491 |
DEF(repz_cmpsl_a16, 0)
|
| 492 |
DEF(repnz_cmpsl_a16, 0)
|
| 493 |
DEF(outsl_a16, 0)
|
| 494 |
DEF(rep_outsl_a16, 0)
|
| 495 |
DEF(insl_a16, 0)
|
| 496 |
DEF(rep_insl_a16, 0)
|
| 497 |
DEF(outl_T0_T1, 0)
|
| 498 |
DEF(inl_T0_T1, 0)
|
| 499 |
DEF(movsbl_T0_T0, 0)
|
| 500 |
DEF(movzbl_T0_T0, 0)
|
| 501 |
DEF(movswl_T0_T0, 0)
|
| 502 |
DEF(movzwl_T0_T0, 0)
|
| 503 |
DEF(movswl_EAX_AX, 0)
|
| 504 |
DEF(movsbw_AX_AL, 0)
|
| 505 |
DEF(movslq_EDX_EAX, 0)
|
| 506 |
DEF(movswl_DX_AX, 0)
|
| 507 |
DEF(pushl_T0, 0)
|
| 508 |
DEF(pushw_T0, 0)
|
| 509 |
DEF(pushl_ss32_T0, 0)
|
| 510 |
DEF(pushw_ss32_T0, 0)
|
| 511 |
DEF(pushl_ss16_T0, 0)
|
| 512 |
DEF(pushw_ss16_T0, 0)
|
| 513 |
DEF(popl_T0, 0)
|
| 514 |
DEF(popw_T0, 0)
|
| 515 |
DEF(popl_ss32_T0, 0)
|
| 516 |
DEF(popw_ss32_T0, 0)
|
| 517 |
DEF(popl_ss16_T0, 0)
|
| 518 |
DEF(popw_ss16_T0, 0)
|
| 519 |
DEF(addl_ESP_4, 0)
|
| 520 |
DEF(addl_ESP_2, 0)
|
| 521 |
DEF(addw_ESP_4, 0)
|
| 522 |
DEF(addw_ESP_2, 0)
|
| 523 |
DEF(addl_ESP_im, 1)
|
| 524 |
DEF(addw_ESP_im, 1)
|
| 525 |
DEF(rdtsc, 0)
|
| 526 |
DEF(cpuid, 0)
|
| 527 |
DEF(aam, 1)
|
| 528 |
DEF(aad, 1)
|
| 529 |
DEF(aaa, 0)
|
| 530 |
DEF(aas, 0)
|
| 531 |
DEF(daa, 0)
|
| 532 |
DEF(das, 0)
|
| 533 |
DEF(movl_seg_T0, 1)
|
| 534 |
DEF(movl_T0_seg, 1)
|
| 535 |
DEF(movl_A0_seg, 1)
|
| 536 |
DEF(addl_A0_seg, 1)
|
| 537 |
DEF(lsl, 0)
|
| 538 |
DEF(lar, 0)
|
| 539 |
DEF(jo_cc, 2)
|
| 540 |
DEF(jb_cc, 2)
|
| 541 |
DEF(jz_cc, 2)
|
| 542 |
DEF(jbe_cc, 2)
|
| 543 |
DEF(js_cc, 2)
|
| 544 |
DEF(jp_cc, 2)
|
| 545 |
DEF(jl_cc, 2)
|
| 546 |
DEF(jle_cc, 2)
|
| 547 |
DEF(seto_T0_cc, 0)
|
| 548 |
DEF(setb_T0_cc, 0)
|
| 549 |
DEF(setz_T0_cc, 0)
|
| 550 |
DEF(setbe_T0_cc, 0)
|
| 551 |
DEF(sets_T0_cc, 0)
|
| 552 |
DEF(setp_T0_cc, 0)
|
| 553 |
DEF(setl_T0_cc, 0)
|
| 554 |
DEF(setle_T0_cc, 0)
|
| 555 |
DEF(xor_T0_1, 0)
|
| 556 |
DEF(set_cc_op, 1)
|
| 557 |
DEF(movl_eflags_T0, 0)
|
| 558 |
DEF(movw_eflags_T0, 0)
|
| 559 |
DEF(movb_eflags_T0, 0)
|
| 560 |
DEF(movl_T0_eflags, 0)
|
| 561 |
DEF(cld, 0)
|
| 562 |
DEF(std, 0)
|
| 563 |
DEF(clc, 0)
|
| 564 |
DEF(stc, 0)
|
| 565 |
DEF(cmc, 0)
|
| 566 |
DEF(salc, 0)
|
| 567 |
DEF(flds_FT0_A0, 0)
|
| 568 |
DEF(fldl_FT0_A0, 0)
|
| 569 |
DEF(fild_FT0_A0, 0)
|
| 570 |
DEF(fildl_FT0_A0, 0)
|
| 571 |
DEF(fildll_FT0_A0, 0)
|
| 572 |
DEF(flds_ST0_A0, 0)
|
| 573 |
DEF(fldl_ST0_A0, 0)
|
| 574 |
DEF(fldt_ST0_A0, 0)
|
| 575 |
DEF(fild_ST0_A0, 0)
|
| 576 |
DEF(fildl_ST0_A0, 0)
|
| 577 |
DEF(fildll_ST0_A0, 0)
|
| 578 |
DEF(fsts_ST0_A0, 0)
|
| 579 |
DEF(fstl_ST0_A0, 0)
|
| 580 |
DEF(fstt_ST0_A0, 0)
|
| 581 |
DEF(fist_ST0_A0, 0)
|
| 582 |
DEF(fistl_ST0_A0, 0)
|
| 583 |
DEF(fistll_ST0_A0, 0)
|
| 584 |
DEF(fbld_ST0_A0, 0)
|
| 585 |
DEF(fbst_ST0_A0, 0)
|
| 586 |
DEF(fpush, 0)
|
| 587 |
DEF(fpop, 0)
|
| 588 |
DEF(fdecstp, 0)
|
| 589 |
DEF(fincstp, 0)
|
| 590 |
DEF(fmov_ST0_FT0, 0)
|
| 591 |
DEF(fmov_FT0_STN, 1)
|
| 592 |
DEF(fmov_ST0_STN, 1)
|
| 593 |
DEF(fmov_STN_ST0, 1)
|
| 594 |
DEF(fxchg_ST0_STN, 1)
|
| 595 |
DEF(fcom_ST0_FT0, 0)
|
| 596 |
DEF(fucom_ST0_FT0, 0)
|
| 597 |
DEF(fadd_ST0_FT0, 0)
|
| 598 |
DEF(fmul_ST0_FT0, 0)
|
| 599 |
DEF(fsub_ST0_FT0, 0)
|
| 600 |
DEF(fsubr_ST0_FT0, 0)
|
| 601 |
DEF(fdiv_ST0_FT0, 0)
|
| 602 |
DEF(fdivr_ST0_FT0, 0)
|
| 603 |
DEF(fadd_STN_ST0, 1)
|
| 604 |
DEF(fmul_STN_ST0, 1)
|
| 605 |
DEF(fsub_STN_ST0, 1)
|
| 606 |
DEF(fsubr_STN_ST0, 1)
|
| 607 |
DEF(fdiv_STN_ST0, 1)
|
| 608 |
DEF(fdivr_STN_ST0, 1)
|
| 609 |
DEF(fchs_ST0, 0)
|
| 610 |
DEF(fabs_ST0, 0)
|
| 611 |
DEF(fxam_ST0, 0)
|
| 612 |
DEF(fld1_ST0, 0)
|
| 613 |
DEF(fldl2t_ST0, 0)
|
| 614 |
DEF(fldl2e_ST0, 0)
|
| 615 |
DEF(fldpi_ST0, 0)
|
| 616 |
DEF(fldlg2_ST0, 0)
|
| 617 |
DEF(fldln2_ST0, 0)
|
| 618 |
DEF(fldz_ST0, 0)
|
| 619 |
DEF(fldz_FT0, 0)
|
| 620 |
DEF(f2xm1, 0)
|
| 621 |
DEF(fyl2x, 0)
|
| 622 |
DEF(fptan, 0)
|
| 623 |
DEF(fpatan, 0)
|
| 624 |
DEF(fxtract, 0)
|
| 625 |
DEF(fprem1, 0)
|
| 626 |
DEF(fprem, 0)
|
| 627 |
DEF(fyl2xp1, 0)
|
| 628 |
DEF(fsqrt, 0)
|
| 629 |
DEF(fsincos, 0)
|
| 630 |
DEF(frndint, 0)
|
| 631 |
DEF(fscale, 0)
|
| 632 |
DEF(fsin, 0)
|
| 633 |
DEF(fcos, 0)
|
| 634 |
DEF(fnstsw_A0, 0)
|
| 635 |
DEF(fnstsw_EAX, 0)
|
| 636 |
DEF(fnstcw_A0, 0)
|
| 637 |
DEF(fldcw_A0, 0)
|
| 638 |
DEF(fclex, 0)
|
| 639 |
DEF(fninit, 0)
|
| 640 |
DEF(lock, 0)
|
| 641 |
DEF(unlock, 0)
|