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1 | 7c23b892 | balrog | /*
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2 | 7c23b892 | balrog | * QEMU e1000 emulation
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3 | 7c23b892 | balrog | *
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4 | 2758aa52 | Michael S. Tsirkin | * Software developer's manual:
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5 | 2758aa52 | Michael S. Tsirkin | * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
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6 | 2758aa52 | Michael S. Tsirkin | *
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7 | 7c23b892 | balrog | * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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8 | 7c23b892 | balrog | * Copyright (c) 2008 Qumranet
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9 | 7c23b892 | balrog | * Based on work done by:
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10 | 7c23b892 | balrog | * Copyright (c) 2007 Dan Aloni
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11 | 7c23b892 | balrog | * Copyright (c) 2004 Antony T Curtis
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12 | 7c23b892 | balrog | *
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13 | 7c23b892 | balrog | * This library is free software; you can redistribute it and/or
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14 | 7c23b892 | balrog | * modify it under the terms of the GNU Lesser General Public
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15 | 7c23b892 | balrog | * License as published by the Free Software Foundation; either
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16 | 7c23b892 | balrog | * version 2 of the License, or (at your option) any later version.
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17 | 7c23b892 | balrog | *
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18 | 7c23b892 | balrog | * This library is distributed in the hope that it will be useful,
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19 | 7c23b892 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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20 | 7c23b892 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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21 | 7c23b892 | balrog | * Lesser General Public License for more details.
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22 | 7c23b892 | balrog | *
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23 | 7c23b892 | balrog | * You should have received a copy of the GNU Lesser General Public
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24 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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25 | 7c23b892 | balrog | */
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26 | 7c23b892 | balrog | |
27 | 7c23b892 | balrog | |
28 | 7c23b892 | balrog | #include "hw.h" |
29 | 7c23b892 | balrog | #include "pci.h" |
30 | 7c23b892 | balrog | #include "net.h" |
31 | 7200ac3c | Mark McLoughlin | #include "net/checksum.h" |
32 | fbdaa002 | Gerd Hoffmann | #include "loader.h" |
33 | 1ca4d09a | Gleb Natapov | #include "sysemu.h" |
34 | 62ecbd35 | Eduard - Gabriel Munteanu | #include "dma.h" |
35 | 7c23b892 | balrog | |
36 | 7c23b892 | balrog | #include "e1000_hw.h" |
37 | 7c23b892 | balrog | |
38 | 27124888 | Jes Sorensen | #define E1000_DEBUG
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39 | 7c23b892 | balrog | |
40 | 27124888 | Jes Sorensen | #ifdef E1000_DEBUG
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41 | 7c23b892 | balrog | enum {
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42 | 7c23b892 | balrog | DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT, |
43 | 7c23b892 | balrog | DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM, |
44 | 7c23b892 | balrog | DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR, |
45 | f9c1cdf4 | Jason Wang | DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET, |
46 | 7c23b892 | balrog | }; |
47 | 7c23b892 | balrog | #define DBGBIT(x) (1<<DEBUG_##x) |
48 | 7c23b892 | balrog | static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); |
49 | 7c23b892 | balrog | |
50 | 6c7f4b47 | Blue Swirl | #define DBGOUT(what, fmt, ...) do { \ |
51 | 7c23b892 | balrog | if (debugflags & DBGBIT(what)) \
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52 | 6c7f4b47 | Blue Swirl | fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \ |
53 | 7c23b892 | balrog | } while (0) |
54 | 7c23b892 | balrog | #else
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55 | 6c7f4b47 | Blue Swirl | #define DBGOUT(what, fmt, ...) do {} while (0) |
56 | 7c23b892 | balrog | #endif
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57 | 7c23b892 | balrog | |
58 | 7c23b892 | balrog | #define IOPORT_SIZE 0x40 |
59 | e94bbefe | aurel32 | #define PNPMMIO_SIZE 0x20000 |
60 | 78aeb23e | Stefan Hajnoczi | #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */ |
61 | 7c23b892 | balrog | |
62 | 7c23b892 | balrog | /*
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63 | 7c23b892 | balrog | * HW models:
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64 | 7c23b892 | balrog | * E1000_DEV_ID_82540EM works with Windows and Linux
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65 | 7c23b892 | balrog | * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
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66 | 7c23b892 | balrog | * appears to perform better than 82540EM, but breaks with Linux 2.6.18
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67 | 7c23b892 | balrog | * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
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68 | 7c23b892 | balrog | * Others never tested
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69 | 7c23b892 | balrog | */
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70 | 7c23b892 | balrog | enum { E1000_DEVID = E1000_DEV_ID_82540EM };
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71 | 7c23b892 | balrog | |
72 | 7c23b892 | balrog | /*
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73 | 7c23b892 | balrog | * May need to specify additional MAC-to-PHY entries --
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74 | 7c23b892 | balrog | * Intel's Windows driver refuses to initialize unless they match
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75 | 7c23b892 | balrog | */
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76 | 7c23b892 | balrog | enum {
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77 | 7c23b892 | balrog | PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
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78 | 7c23b892 | balrog | E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
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79 | 7c23b892 | balrog | /* default to E1000_DEV_ID_82540EM */ 0xc20 |
80 | 7c23b892 | balrog | }; |
81 | 7c23b892 | balrog | |
82 | 7c23b892 | balrog | typedef struct E1000State_st { |
83 | 7c23b892 | balrog | PCIDevice dev; |
84 | a03e2aec | Mark McLoughlin | NICState *nic; |
85 | fbdaa002 | Gerd Hoffmann | NICConf conf; |
86 | ad00a9b9 | Avi Kivity | MemoryRegion mmio; |
87 | ad00a9b9 | Avi Kivity | MemoryRegion io; |
88 | 7c23b892 | balrog | |
89 | 7c23b892 | balrog | uint32_t mac_reg[0x8000];
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90 | 7c23b892 | balrog | uint16_t phy_reg[0x20];
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91 | 7c23b892 | balrog | uint16_t eeprom_data[64];
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92 | 7c23b892 | balrog | |
93 | 7c23b892 | balrog | uint32_t rxbuf_size; |
94 | 7c23b892 | balrog | uint32_t rxbuf_min_shift; |
95 | 7c23b892 | balrog | int check_rxov;
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96 | 7c23b892 | balrog | struct e1000_tx {
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97 | 7c23b892 | balrog | unsigned char header[256]; |
98 | 8f2e8d1f | aliguori | unsigned char vlan_header[4]; |
99 | b10fec9b | Stefan Weil | /* Fields vlan and data must not be reordered or separated. */
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100 | 8f2e8d1f | aliguori | unsigned char vlan[4]; |
101 | 7c23b892 | balrog | unsigned char data[0x10000]; |
102 | 7c23b892 | balrog | uint16_t size; |
103 | 7c23b892 | balrog | unsigned char sum_needed; |
104 | 8f2e8d1f | aliguori | unsigned char vlan_needed; |
105 | 7c23b892 | balrog | uint8_t ipcss; |
106 | 7c23b892 | balrog | uint8_t ipcso; |
107 | 7c23b892 | balrog | uint16_t ipcse; |
108 | 7c23b892 | balrog | uint8_t tucss; |
109 | 7c23b892 | balrog | uint8_t tucso; |
110 | 7c23b892 | balrog | uint16_t tucse; |
111 | 7c23b892 | balrog | uint8_t hdr_len; |
112 | 7c23b892 | balrog | uint16_t mss; |
113 | 7c23b892 | balrog | uint32_t paylen; |
114 | 7c23b892 | balrog | uint16_t tso_frames; |
115 | 7c23b892 | balrog | char tse;
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116 | b6c4f71f | blueswir1 | int8_t ip; |
117 | b6c4f71f | blueswir1 | int8_t tcp; |
118 | 1b0009db | balrog | char cptse; // current packet tse bit |
119 | 7c23b892 | balrog | } tx; |
120 | 7c23b892 | balrog | |
121 | 7c23b892 | balrog | struct {
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122 | 7c23b892 | balrog | uint32_t val_in; // shifted in from guest driver
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123 | 7c23b892 | balrog | uint16_t bitnum_in; |
124 | 7c23b892 | balrog | uint16_t bitnum_out; |
125 | 7c23b892 | balrog | uint16_t reading; |
126 | 7c23b892 | balrog | uint32_t old_eecd; |
127 | 7c23b892 | balrog | } eecd_state; |
128 | b9d03e35 | Jason Wang | |
129 | b9d03e35 | Jason Wang | QEMUTimer *autoneg_timer; |
130 | 7c23b892 | balrog | } E1000State; |
131 | 7c23b892 | balrog | |
132 | 7c23b892 | balrog | #define defreg(x) x = (E1000_##x>>2) |
133 | 7c23b892 | balrog | enum {
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134 | 7c23b892 | balrog | defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC), |
135 | 7c23b892 | balrog | defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC), |
136 | 7c23b892 | balrog | defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC), |
137 | 7c23b892 | balrog | defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH), |
138 | 7c23b892 | balrog | defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT), |
139 | 7c23b892 | balrog | defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH), |
140 | 7c23b892 | balrog | defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT), |
141 | 7c23b892 | balrog | defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL), |
142 | 7c23b892 | balrog | defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC), |
143 | 8f2e8d1f | aliguori | defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA), |
144 | 8f2e8d1f | aliguori | defreg(VET), |
145 | 7c23b892 | balrog | }; |
146 | 7c23b892 | balrog | |
147 | 71aadd3c | Jason Wang | static void |
148 | 71aadd3c | Jason Wang | e1000_link_down(E1000State *s) |
149 | 71aadd3c | Jason Wang | { |
150 | 71aadd3c | Jason Wang | s->mac_reg[STATUS] &= ~E1000_STATUS_LU; |
151 | 71aadd3c | Jason Wang | s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS; |
152 | 71aadd3c | Jason Wang | } |
153 | 71aadd3c | Jason Wang | |
154 | 71aadd3c | Jason Wang | static void |
155 | 71aadd3c | Jason Wang | e1000_link_up(E1000State *s) |
156 | 71aadd3c | Jason Wang | { |
157 | 71aadd3c | Jason Wang | s->mac_reg[STATUS] |= E1000_STATUS_LU; |
158 | 71aadd3c | Jason Wang | s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS; |
159 | 71aadd3c | Jason Wang | } |
160 | 71aadd3c | Jason Wang | |
161 | b9d03e35 | Jason Wang | static void |
162 | b9d03e35 | Jason Wang | set_phy_ctrl(E1000State *s, int index, uint16_t val)
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163 | b9d03e35 | Jason Wang | { |
164 | b9d03e35 | Jason Wang | if ((val & MII_CR_AUTO_NEG_EN) && (val & MII_CR_RESTART_AUTO_NEG)) {
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165 | b9d03e35 | Jason Wang | s->nic->nc.link_down = true;
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166 | b9d03e35 | Jason Wang | e1000_link_down(s); |
167 | b9d03e35 | Jason Wang | s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE; |
168 | b9d03e35 | Jason Wang | DBGOUT(PHY, "Start link auto negotiation\n");
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169 | b9d03e35 | Jason Wang | qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
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170 | b9d03e35 | Jason Wang | } |
171 | b9d03e35 | Jason Wang | } |
172 | b9d03e35 | Jason Wang | |
173 | b9d03e35 | Jason Wang | static void |
174 | b9d03e35 | Jason Wang | e1000_autoneg_timer(void *opaque)
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175 | b9d03e35 | Jason Wang | { |
176 | b9d03e35 | Jason Wang | E1000State *s = opaque; |
177 | b9d03e35 | Jason Wang | s->nic->nc.link_down = false;
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178 | b9d03e35 | Jason Wang | e1000_link_up(s); |
179 | b9d03e35 | Jason Wang | s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE; |
180 | b9d03e35 | Jason Wang | DBGOUT(PHY, "Auto negotiation is completed\n");
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181 | b9d03e35 | Jason Wang | } |
182 | b9d03e35 | Jason Wang | |
183 | b9d03e35 | Jason Wang | static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = { |
184 | b9d03e35 | Jason Wang | [PHY_CTRL] = set_phy_ctrl, |
185 | b9d03e35 | Jason Wang | }; |
186 | b9d03e35 | Jason Wang | |
187 | b9d03e35 | Jason Wang | enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
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188 | b9d03e35 | Jason Wang | |
189 | 7c23b892 | balrog | enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W }; |
190 | 88b4e9db | blueswir1 | static const char phy_regcap[0x20] = { |
191 | 7c23b892 | balrog | [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW, |
192 | 7c23b892 | balrog | [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW, |
193 | 7c23b892 | balrog | [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW, |
194 | 7c23b892 | balrog | [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R, |
195 | 7c23b892 | balrog | [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R, |
196 | 700f6e2c | aurel32 | [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R |
197 | 7c23b892 | balrog | }; |
198 | 7c23b892 | balrog | |
199 | 814cd3ac | Michael S. Tsirkin | static const uint16_t phy_reg_init[] = { |
200 | b9d03e35 | Jason Wang | [PHY_CTRL] = 0x1140,
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201 | b9d03e35 | Jason Wang | [PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */ |
202 | 814cd3ac | Michael S. Tsirkin | [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
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203 | 814cd3ac | Michael S. Tsirkin | [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360, |
204 | 814cd3ac | Michael S. Tsirkin | [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1, |
205 | 814cd3ac | Michael S. Tsirkin | [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00, |
206 | 814cd3ac | Michael S. Tsirkin | [M88E1000_PHY_SPEC_STATUS] = 0xac00,
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207 | 814cd3ac | Michael S. Tsirkin | }; |
208 | 814cd3ac | Michael S. Tsirkin | |
209 | 814cd3ac | Michael S. Tsirkin | static const uint32_t mac_reg_init[] = { |
210 | 814cd3ac | Michael S. Tsirkin | [PBA] = 0x00100030,
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211 | 814cd3ac | Michael S. Tsirkin | [LEDCTL] = 0x602,
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212 | 814cd3ac | Michael S. Tsirkin | [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | |
213 | 814cd3ac | Michael S. Tsirkin | E1000_CTRL_SPD_1000 | E1000_CTRL_SLU, |
214 | 814cd3ac | Michael S. Tsirkin | [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
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215 | 814cd3ac | Michael S. Tsirkin | E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK | |
216 | 814cd3ac | Michael S. Tsirkin | E1000_STATUS_SPEED_1000 | E1000_STATUS_FD | |
217 | 814cd3ac | Michael S. Tsirkin | E1000_STATUS_LU, |
218 | 814cd3ac | Michael S. Tsirkin | [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN | |
219 | 814cd3ac | Michael S. Tsirkin | E1000_MANC_ARP_EN | E1000_MANC_0298_EN | |
220 | 814cd3ac | Michael S. Tsirkin | E1000_MANC_RMCP_EN, |
221 | 814cd3ac | Michael S. Tsirkin | }; |
222 | 814cd3ac | Michael S. Tsirkin | |
223 | 7c23b892 | balrog | static void |
224 | 7c23b892 | balrog | set_interrupt_cause(E1000State *s, int index, uint32_t val)
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225 | 7c23b892 | balrog | { |
226 | f1219091 | Jason Wang | if (val && (E1000_DEVID >= E1000_DEV_ID_82547EI_MOBILE)) {
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227 | f1219091 | Jason Wang | /* Only for 8257x */
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228 | 7c23b892 | balrog | val |= E1000_ICR_INT_ASSERTED; |
229 | f1219091 | Jason Wang | } |
230 | 7c23b892 | balrog | s->mac_reg[ICR] = val; |
231 | b1332393 | Bill Paul | s->mac_reg[ICS] = val; |
232 | bc26e55a | Blue Swirl | qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); |
233 | 7c23b892 | balrog | } |
234 | 7c23b892 | balrog | |
235 | 7c23b892 | balrog | static void |
236 | 7c23b892 | balrog | set_ics(E1000State *s, int index, uint32_t val)
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237 | 7c23b892 | balrog | { |
238 | 7c23b892 | balrog | DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
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239 | 7c23b892 | balrog | s->mac_reg[IMS]); |
240 | 7c23b892 | balrog | set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
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241 | 7c23b892 | balrog | } |
242 | 7c23b892 | balrog | |
243 | 7c23b892 | balrog | static int |
244 | 7c23b892 | balrog | rxbufsize(uint32_t v) |
245 | 7c23b892 | balrog | { |
246 | 7c23b892 | balrog | v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | |
247 | 7c23b892 | balrog | E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | |
248 | 7c23b892 | balrog | E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; |
249 | 7c23b892 | balrog | switch (v) {
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250 | 7c23b892 | balrog | case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
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251 | 7c23b892 | balrog | return 16384; |
252 | 7c23b892 | balrog | case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
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253 | 7c23b892 | balrog | return 8192; |
254 | 7c23b892 | balrog | case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
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255 | 7c23b892 | balrog | return 4096; |
256 | 7c23b892 | balrog | case E1000_RCTL_SZ_1024:
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257 | 7c23b892 | balrog | return 1024; |
258 | 7c23b892 | balrog | case E1000_RCTL_SZ_512:
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259 | 7c23b892 | balrog | return 512; |
260 | 7c23b892 | balrog | case E1000_RCTL_SZ_256:
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261 | 7c23b892 | balrog | return 256; |
262 | 7c23b892 | balrog | } |
263 | 7c23b892 | balrog | return 2048; |
264 | 7c23b892 | balrog | } |
265 | 7c23b892 | balrog | |
266 | 814cd3ac | Michael S. Tsirkin | static void e1000_reset(void *opaque) |
267 | 814cd3ac | Michael S. Tsirkin | { |
268 | 814cd3ac | Michael S. Tsirkin | E1000State *d = opaque; |
269 | 814cd3ac | Michael S. Tsirkin | |
270 | b9d03e35 | Jason Wang | qemu_del_timer(d->autoneg_timer); |
271 | 814cd3ac | Michael S. Tsirkin | memset(d->phy_reg, 0, sizeof d->phy_reg); |
272 | 814cd3ac | Michael S. Tsirkin | memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
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273 | 814cd3ac | Michael S. Tsirkin | memset(d->mac_reg, 0, sizeof d->mac_reg); |
274 | 814cd3ac | Michael S. Tsirkin | memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
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275 | 814cd3ac | Michael S. Tsirkin | d->rxbuf_min_shift = 1;
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276 | 814cd3ac | Michael S. Tsirkin | memset(&d->tx, 0, sizeof d->tx); |
277 | 814cd3ac | Michael S. Tsirkin | |
278 | 814cd3ac | Michael S. Tsirkin | if (d->nic->nc.link_down) {
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279 | 71aadd3c | Jason Wang | e1000_link_down(d); |
280 | 814cd3ac | Michael S. Tsirkin | } |
281 | 814cd3ac | Michael S. Tsirkin | } |
282 | 814cd3ac | Michael S. Tsirkin | |
283 | 7c23b892 | balrog | static void |
284 | cab3c825 | Kevin Wolf | set_ctrl(E1000State *s, int index, uint32_t val)
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285 | cab3c825 | Kevin Wolf | { |
286 | cab3c825 | Kevin Wolf | /* RST is self clearing */
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287 | cab3c825 | Kevin Wolf | s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; |
288 | cab3c825 | Kevin Wolf | } |
289 | cab3c825 | Kevin Wolf | |
290 | cab3c825 | Kevin Wolf | static void |
291 | 7c23b892 | balrog | set_rx_control(E1000State *s, int index, uint32_t val)
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292 | 7c23b892 | balrog | { |
293 | 7c23b892 | balrog | s->mac_reg[RCTL] = val; |
294 | 7c23b892 | balrog | s->rxbuf_size = rxbufsize(val); |
295 | 7c23b892 | balrog | s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; |
296 | 7c23b892 | balrog | DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
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297 | 7c23b892 | balrog | s->mac_reg[RCTL]); |
298 | 7c23b892 | balrog | } |
299 | 7c23b892 | balrog | |
300 | 7c23b892 | balrog | static void |
301 | 7c23b892 | balrog | set_mdic(E1000State *s, int index, uint32_t val)
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302 | 7c23b892 | balrog | { |
303 | 7c23b892 | balrog | uint32_t data = val & E1000_MDIC_DATA_MASK; |
304 | 7c23b892 | balrog | uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); |
305 | 7c23b892 | balrog | |
306 | 7c23b892 | balrog | if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy # |
307 | 7c23b892 | balrog | val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; |
308 | 7c23b892 | balrog | else if (val & E1000_MDIC_OP_READ) { |
309 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
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310 | 7c23b892 | balrog | if (!(phy_regcap[addr] & PHY_R)) {
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311 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
|
312 | 7c23b892 | balrog | val |= E1000_MDIC_ERROR; |
313 | 7c23b892 | balrog | } else
|
314 | 7c23b892 | balrog | val = (val ^ data) | s->phy_reg[addr]; |
315 | 7c23b892 | balrog | } else if (val & E1000_MDIC_OP_WRITE) { |
316 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
|
317 | 7c23b892 | balrog | if (!(phy_regcap[addr] & PHY_W)) {
|
318 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
|
319 | 7c23b892 | balrog | val |= E1000_MDIC_ERROR; |
320 | b9d03e35 | Jason Wang | } else {
|
321 | b9d03e35 | Jason Wang | if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
|
322 | b9d03e35 | Jason Wang | phyreg_writeops[addr](s, index, data); |
323 | b9d03e35 | Jason Wang | } |
324 | 7c23b892 | balrog | s->phy_reg[addr] = data; |
325 | b9d03e35 | Jason Wang | } |
326 | 7c23b892 | balrog | } |
327 | 7c23b892 | balrog | s->mac_reg[MDIC] = val | E1000_MDIC_READY; |
328 | 17fbbb0b | Jason Wang | |
329 | 17fbbb0b | Jason Wang | if (val & E1000_MDIC_INT_EN) {
|
330 | 17fbbb0b | Jason Wang | set_ics(s, 0, E1000_ICR_MDAC);
|
331 | 17fbbb0b | Jason Wang | } |
332 | 7c23b892 | balrog | } |
333 | 7c23b892 | balrog | |
334 | 7c23b892 | balrog | static uint32_t
|
335 | 7c23b892 | balrog | get_eecd(E1000State *s, int index)
|
336 | 7c23b892 | balrog | { |
337 | 7c23b892 | balrog | uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; |
338 | 7c23b892 | balrog | |
339 | 7c23b892 | balrog | DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
|
340 | 7c23b892 | balrog | s->eecd_state.bitnum_out, s->eecd_state.reading); |
341 | 7c23b892 | balrog | if (!s->eecd_state.reading ||
|
342 | 7c23b892 | balrog | ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> |
343 | 7c23b892 | balrog | ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) |
344 | 7c23b892 | balrog | ret |= E1000_EECD_DO; |
345 | 7c23b892 | balrog | return ret;
|
346 | 7c23b892 | balrog | } |
347 | 7c23b892 | balrog | |
348 | 7c23b892 | balrog | static void |
349 | 7c23b892 | balrog | set_eecd(E1000State *s, int index, uint32_t val)
|
350 | 7c23b892 | balrog | { |
351 | 7c23b892 | balrog | uint32_t oldval = s->eecd_state.old_eecd; |
352 | 7c23b892 | balrog | |
353 | 7c23b892 | balrog | s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | |
354 | 7c23b892 | balrog | E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ); |
355 | 9651ac55 | Izumi Tsutsui | if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do |
356 | 9651ac55 | Izumi Tsutsui | return;
|
357 | 9651ac55 | Izumi Tsutsui | if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state |
358 | 9651ac55 | Izumi Tsutsui | s->eecd_state.val_in = 0;
|
359 | 9651ac55 | Izumi Tsutsui | s->eecd_state.bitnum_in = 0;
|
360 | 9651ac55 | Izumi Tsutsui | s->eecd_state.bitnum_out = 0;
|
361 | 9651ac55 | Izumi Tsutsui | s->eecd_state.reading = 0;
|
362 | 9651ac55 | Izumi Tsutsui | } |
363 | 7c23b892 | balrog | if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge |
364 | 7c23b892 | balrog | return;
|
365 | 7c23b892 | balrog | if (!(E1000_EECD_SK & val)) { // falling edge |
366 | 7c23b892 | balrog | s->eecd_state.bitnum_out++; |
367 | 7c23b892 | balrog | return;
|
368 | 7c23b892 | balrog | } |
369 | 7c23b892 | balrog | s->eecd_state.val_in <<= 1;
|
370 | 7c23b892 | balrog | if (val & E1000_EECD_DI)
|
371 | 7c23b892 | balrog | s->eecd_state.val_in |= 1;
|
372 | 7c23b892 | balrog | if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { |
373 | 7c23b892 | balrog | s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; |
374 | 7c23b892 | balrog | s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == |
375 | 7c23b892 | balrog | EEPROM_READ_OPCODE_MICROWIRE); |
376 | 7c23b892 | balrog | } |
377 | 7c23b892 | balrog | DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
|
378 | 7c23b892 | balrog | s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, |
379 | 7c23b892 | balrog | s->eecd_state.reading); |
380 | 7c23b892 | balrog | } |
381 | 7c23b892 | balrog | |
382 | 7c23b892 | balrog | static uint32_t
|
383 | 7c23b892 | balrog | flash_eerd_read(E1000State *s, int x)
|
384 | 7c23b892 | balrog | { |
385 | 7c23b892 | balrog | unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; |
386 | 7c23b892 | balrog | |
387 | b1332393 | Bill Paul | if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) |
388 | b1332393 | Bill Paul | return (s->mac_reg[EERD]);
|
389 | b1332393 | Bill Paul | |
390 | 7c23b892 | balrog | if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
|
391 | b1332393 | Bill Paul | return (E1000_EEPROM_RW_REG_DONE | r);
|
392 | b1332393 | Bill Paul | |
393 | b1332393 | Bill Paul | return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
|
394 | b1332393 | Bill Paul | E1000_EEPROM_RW_REG_DONE | r); |
395 | 7c23b892 | balrog | } |
396 | 7c23b892 | balrog | |
397 | 7c23b892 | balrog | static void |
398 | 7c23b892 | balrog | putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) |
399 | 7c23b892 | balrog | { |
400 | c6a6a5e3 | aliguori | uint32_t sum; |
401 | c6a6a5e3 | aliguori | |
402 | 7c23b892 | balrog | if (cse && cse < n)
|
403 | 7c23b892 | balrog | n = cse + 1;
|
404 | c6a6a5e3 | aliguori | if (sloc < n-1) { |
405 | c6a6a5e3 | aliguori | sum = net_checksum_add(n-css, data+css); |
406 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(data + sloc), |
407 | c6a6a5e3 | aliguori | net_checksum_finish(sum)); |
408 | c6a6a5e3 | aliguori | } |
409 | 7c23b892 | balrog | } |
410 | 7c23b892 | balrog | |
411 | 8f2e8d1f | aliguori | static inline int |
412 | 8f2e8d1f | aliguori | vlan_enabled(E1000State *s) |
413 | 8f2e8d1f | aliguori | { |
414 | 8f2e8d1f | aliguori | return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0); |
415 | 8f2e8d1f | aliguori | } |
416 | 8f2e8d1f | aliguori | |
417 | 8f2e8d1f | aliguori | static inline int |
418 | 8f2e8d1f | aliguori | vlan_rx_filter_enabled(E1000State *s) |
419 | 8f2e8d1f | aliguori | { |
420 | 8f2e8d1f | aliguori | return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0); |
421 | 8f2e8d1f | aliguori | } |
422 | 8f2e8d1f | aliguori | |
423 | 8f2e8d1f | aliguori | static inline int |
424 | 8f2e8d1f | aliguori | is_vlan_packet(E1000State *s, const uint8_t *buf)
|
425 | 8f2e8d1f | aliguori | { |
426 | 8f2e8d1f | aliguori | return (be16_to_cpup((uint16_t *)(buf + 12)) == |
427 | 8f2e8d1f | aliguori | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); |
428 | 8f2e8d1f | aliguori | } |
429 | 8f2e8d1f | aliguori | |
430 | 8f2e8d1f | aliguori | static inline int |
431 | 8f2e8d1f | aliguori | is_vlan_txd(uint32_t txd_lower) |
432 | 8f2e8d1f | aliguori | { |
433 | 8f2e8d1f | aliguori | return ((txd_lower & E1000_TXD_CMD_VLE) != 0); |
434 | 8f2e8d1f | aliguori | } |
435 | 8f2e8d1f | aliguori | |
436 | 55e8d1ce | Michael S. Tsirkin | /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
|
437 | 55e8d1ce | Michael S. Tsirkin | * fill it in, just pad descriptor length by 4 bytes unless guest
|
438 | a05e8a6e | Michael S. Tsirkin | * told us to strip it off the packet. */
|
439 | 55e8d1ce | Michael S. Tsirkin | static inline int |
440 | 55e8d1ce | Michael S. Tsirkin | fcs_len(E1000State *s) |
441 | 55e8d1ce | Michael S. Tsirkin | { |
442 | 55e8d1ce | Michael S. Tsirkin | return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4; |
443 | 55e8d1ce | Michael S. Tsirkin | } |
444 | 55e8d1ce | Michael S. Tsirkin | |
445 | 7c23b892 | balrog | static void |
446 | 93e37d76 | Jason Wang | e1000_send_packet(E1000State *s, const uint8_t *buf, int size) |
447 | 93e37d76 | Jason Wang | { |
448 | 93e37d76 | Jason Wang | if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
|
449 | 93e37d76 | Jason Wang | s->nic->nc.info->receive(&s->nic->nc, buf, size); |
450 | 93e37d76 | Jason Wang | } else {
|
451 | 93e37d76 | Jason Wang | qemu_send_packet(&s->nic->nc, buf, size); |
452 | 93e37d76 | Jason Wang | } |
453 | 93e37d76 | Jason Wang | } |
454 | 93e37d76 | Jason Wang | |
455 | 93e37d76 | Jason Wang | static void |
456 | 7c23b892 | balrog | xmit_seg(E1000State *s) |
457 | 7c23b892 | balrog | { |
458 | 7c23b892 | balrog | uint16_t len, *sp; |
459 | 7c23b892 | balrog | unsigned int frames = s->tx.tso_frames, css, sofar, n; |
460 | 7c23b892 | balrog | struct e1000_tx *tp = &s->tx;
|
461 | 7c23b892 | balrog | |
462 | 1b0009db | balrog | if (tp->tse && tp->cptse) {
|
463 | 7c23b892 | balrog | css = tp->ipcss; |
464 | 7c23b892 | balrog | DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
|
465 | 7c23b892 | balrog | frames, tp->size, css); |
466 | 7c23b892 | balrog | if (tp->ip) { // IPv4 |
467 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+2),
|
468 | 7c23b892 | balrog | tp->size - css); |
469 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+4),
|
470 | 7c23b892 | balrog | be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
|
471 | 7c23b892 | balrog | } else // IPv6 |
472 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+4),
|
473 | 7c23b892 | balrog | tp->size - css); |
474 | 7c23b892 | balrog | css = tp->tucss; |
475 | 7c23b892 | balrog | len = tp->size - css; |
476 | 7c23b892 | balrog | DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
|
477 | 7c23b892 | balrog | if (tp->tcp) {
|
478 | 7c23b892 | balrog | sofar = frames * tp->mss; |
479 | 7c23b892 | balrog | cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq |
480 | 88738c09 | aurel32 | be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
|
481 | 7c23b892 | balrog | if (tp->paylen - sofar > tp->mss)
|
482 | 7c23b892 | balrog | tp->data[css + 13] &= ~9; // PSH, FIN |
483 | 7c23b892 | balrog | } else // UDP |
484 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
|
485 | 7c23b892 | balrog | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
|
486 | e685b4eb | Alex Williamson | unsigned int phsum; |
487 | 7c23b892 | balrog | // add pseudo-header length before checksum calculation
|
488 | 7c23b892 | balrog | sp = (uint16_t *)(tp->data + tp->tucso); |
489 | e685b4eb | Alex Williamson | phsum = be16_to_cpup(sp) + len; |
490 | e685b4eb | Alex Williamson | phsum = (phsum >> 16) + (phsum & 0xffff); |
491 | e685b4eb | Alex Williamson | cpu_to_be16wu(sp, phsum); |
492 | 7c23b892 | balrog | } |
493 | 7c23b892 | balrog | tp->tso_frames++; |
494 | 7c23b892 | balrog | } |
495 | 7c23b892 | balrog | |
496 | 7c23b892 | balrog | if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
|
497 | 7c23b892 | balrog | putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse); |
498 | 7c23b892 | balrog | if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
|
499 | 7c23b892 | balrog | putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse); |
500 | 8f2e8d1f | aliguori | if (tp->vlan_needed) {
|
501 | b10fec9b | Stefan Weil | memmove(tp->vlan, tp->data, 4);
|
502 | b10fec9b | Stefan Weil | memmove(tp->data, tp->data + 4, 8); |
503 | 8f2e8d1f | aliguori | memcpy(tp->data + 8, tp->vlan_header, 4); |
504 | 93e37d76 | Jason Wang | e1000_send_packet(s, tp->vlan, tp->size + 4);
|
505 | 8f2e8d1f | aliguori | } else
|
506 | 93e37d76 | Jason Wang | e1000_send_packet(s, tp->data, tp->size); |
507 | 7c23b892 | balrog | s->mac_reg[TPT]++; |
508 | 7c23b892 | balrog | s->mac_reg[GPTC]++; |
509 | 7c23b892 | balrog | n = s->mac_reg[TOTL]; |
510 | 7c23b892 | balrog | if ((s->mac_reg[TOTL] += s->tx.size) < n)
|
511 | 7c23b892 | balrog | s->mac_reg[TOTH]++; |
512 | 7c23b892 | balrog | } |
513 | 7c23b892 | balrog | |
514 | 7c23b892 | balrog | static void |
515 | 7c23b892 | balrog | process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
|
516 | 7c23b892 | balrog | { |
517 | 7c23b892 | balrog | uint32_t txd_lower = le32_to_cpu(dp->lower.data); |
518 | 7c23b892 | balrog | uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); |
519 | 7c23b892 | balrog | unsigned int split_size = txd_lower & 0xffff, bytes, sz, op; |
520 | 7c23b892 | balrog | unsigned int msh = 0xfffff, hdr = 0; |
521 | 7c23b892 | balrog | uint64_t addr; |
522 | 7c23b892 | balrog | struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; |
523 | 7c23b892 | balrog | struct e1000_tx *tp = &s->tx;
|
524 | 7c23b892 | balrog | |
525 | 7c23b892 | balrog | if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor |
526 | 7c23b892 | balrog | op = le32_to_cpu(xp->cmd_and_length); |
527 | 7c23b892 | balrog | tp->ipcss = xp->lower_setup.ip_fields.ipcss; |
528 | 7c23b892 | balrog | tp->ipcso = xp->lower_setup.ip_fields.ipcso; |
529 | 7c23b892 | balrog | tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse); |
530 | 7c23b892 | balrog | tp->tucss = xp->upper_setup.tcp_fields.tucss; |
531 | 7c23b892 | balrog | tp->tucso = xp->upper_setup.tcp_fields.tucso; |
532 | 7c23b892 | balrog | tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse); |
533 | 7c23b892 | balrog | tp->paylen = op & 0xfffff;
|
534 | 7c23b892 | balrog | tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len; |
535 | 7c23b892 | balrog | tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss); |
536 | 7c23b892 | balrog | tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; |
537 | 7c23b892 | balrog | tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; |
538 | 7c23b892 | balrog | tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; |
539 | 7c23b892 | balrog | tp->tso_frames = 0;
|
540 | 7c23b892 | balrog | if (tp->tucso == 0) { // this is probably wrong |
541 | 7c23b892 | balrog | DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
|
542 | 7c23b892 | balrog | tp->tucso = tp->tucss + (tp->tcp ? 16 : 6); |
543 | 7c23b892 | balrog | } |
544 | 7c23b892 | balrog | return;
|
545 | 1b0009db | balrog | } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { |
546 | 1b0009db | balrog | // data descriptor
|
547 | 735e77ec | Stefan Hajnoczi | if (tp->size == 0) { |
548 | 735e77ec | Stefan Hajnoczi | tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
|
549 | 735e77ec | Stefan Hajnoczi | } |
550 | 1b0009db | balrog | tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0; |
551 | 43ad7e3e | Jes Sorensen | } else {
|
552 | 1b0009db | balrog | // legacy descriptor
|
553 | 1b0009db | balrog | tp->cptse = 0;
|
554 | 43ad7e3e | Jes Sorensen | } |
555 | 7c23b892 | balrog | |
556 | 8f2e8d1f | aliguori | if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
|
557 | 8f2e8d1f | aliguori | (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) { |
558 | 8f2e8d1f | aliguori | tp->vlan_needed = 1;
|
559 | 8f2e8d1f | aliguori | cpu_to_be16wu((uint16_t *)(tp->vlan_header), |
560 | 8f2e8d1f | aliguori | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); |
561 | 8f2e8d1f | aliguori | cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
|
562 | 8f2e8d1f | aliguori | le16_to_cpu(dp->upper.fields.special)); |
563 | 8f2e8d1f | aliguori | } |
564 | 8f2e8d1f | aliguori | |
565 | 7c23b892 | balrog | addr = le64_to_cpu(dp->buffer_addr); |
566 | 1b0009db | balrog | if (tp->tse && tp->cptse) {
|
567 | 7c23b892 | balrog | hdr = tp->hdr_len; |
568 | 7c23b892 | balrog | msh = hdr + tp->mss; |
569 | 1b0009db | balrog | do {
|
570 | 1b0009db | balrog | bytes = split_size; |
571 | 1b0009db | balrog | if (tp->size + bytes > msh)
|
572 | 1b0009db | balrog | bytes = msh - tp->size; |
573 | 65f82df0 | Anthony Liguori | |
574 | 65f82df0 | Anthony Liguori | bytes = MIN(sizeof(tp->data) - tp->size, bytes);
|
575 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes); |
576 | 1b0009db | balrog | if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
|
577 | 1b0009db | balrog | memmove(tp->header, tp->data, hdr); |
578 | 1b0009db | balrog | tp->size = sz; |
579 | 1b0009db | balrog | addr += bytes; |
580 | 1b0009db | balrog | if (sz == msh) {
|
581 | 1b0009db | balrog | xmit_seg(s); |
582 | 1b0009db | balrog | memmove(tp->data, tp->header, hdr); |
583 | 1b0009db | balrog | tp->size = hdr; |
584 | 1b0009db | balrog | } |
585 | 1b0009db | balrog | } while (split_size -= bytes);
|
586 | 1b0009db | balrog | } else if (!tp->tse && tp->cptse) { |
587 | 1b0009db | balrog | // context descriptor TSE is not set, while data descriptor TSE is set
|
588 | 362f5fb5 | Stefan Weil | DBGOUT(TXERR, "TCP segmentation error\n");
|
589 | 1b0009db | balrog | } else {
|
590 | 65f82df0 | Anthony Liguori | split_size = MIN(sizeof(tp->data) - tp->size, split_size);
|
591 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size); |
592 | 1b0009db | balrog | tp->size += split_size; |
593 | 7c23b892 | balrog | } |
594 | 7c23b892 | balrog | |
595 | 7c23b892 | balrog | if (!(txd_lower & E1000_TXD_CMD_EOP))
|
596 | 7c23b892 | balrog | return;
|
597 | 1b0009db | balrog | if (!(tp->tse && tp->cptse && tp->size < hdr))
|
598 | 7c23b892 | balrog | xmit_seg(s); |
599 | 7c23b892 | balrog | tp->tso_frames = 0;
|
600 | 7c23b892 | balrog | tp->sum_needed = 0;
|
601 | 8f2e8d1f | aliguori | tp->vlan_needed = 0;
|
602 | 7c23b892 | balrog | tp->size = 0;
|
603 | 1b0009db | balrog | tp->cptse = 0;
|
604 | 7c23b892 | balrog | } |
605 | 7c23b892 | balrog | |
606 | 7c23b892 | balrog | static uint32_t
|
607 | 62ecbd35 | Eduard - Gabriel Munteanu | txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
|
608 | 7c23b892 | balrog | { |
609 | 7c23b892 | balrog | uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); |
610 | 7c23b892 | balrog | |
611 | 7c23b892 | balrog | if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
|
612 | 7c23b892 | balrog | return 0; |
613 | 7c23b892 | balrog | txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & |
614 | 7c23b892 | balrog | ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU); |
615 | 7c23b892 | balrog | dp->upper.data = cpu_to_le32(txd_upper); |
616 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp), |
617 | 00c3a05b | David Gibson | &dp->upper, sizeof(dp->upper));
|
618 | 7c23b892 | balrog | return E1000_ICR_TXDW;
|
619 | 7c23b892 | balrog | } |
620 | 7c23b892 | balrog | |
621 | d17161f6 | Kevin Wolf | static uint64_t tx_desc_base(E1000State *s)
|
622 | d17161f6 | Kevin Wolf | { |
623 | d17161f6 | Kevin Wolf | uint64_t bah = s->mac_reg[TDBAH]; |
624 | d17161f6 | Kevin Wolf | uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
|
625 | d17161f6 | Kevin Wolf | |
626 | d17161f6 | Kevin Wolf | return (bah << 32) + bal; |
627 | d17161f6 | Kevin Wolf | } |
628 | d17161f6 | Kevin Wolf | |
629 | 7c23b892 | balrog | static void |
630 | 7c23b892 | balrog | start_xmit(E1000State *s) |
631 | 7c23b892 | balrog | { |
632 | 62ecbd35 | Eduard - Gabriel Munteanu | dma_addr_t base; |
633 | 7c23b892 | balrog | struct e1000_tx_desc desc;
|
634 | 7c23b892 | balrog | uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; |
635 | 7c23b892 | balrog | |
636 | 7c23b892 | balrog | if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
|
637 | 7c23b892 | balrog | DBGOUT(TX, "tx disabled\n");
|
638 | 7c23b892 | balrog | return;
|
639 | 7c23b892 | balrog | } |
640 | 7c23b892 | balrog | |
641 | 7c23b892 | balrog | while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
|
642 | d17161f6 | Kevin Wolf | base = tx_desc_base(s) + |
643 | 7c23b892 | balrog | sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; |
644 | 00c3a05b | David Gibson | pci_dma_read(&s->dev, base, &desc, sizeof(desc));
|
645 | 7c23b892 | balrog | |
646 | 7c23b892 | balrog | DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
|
647 | 6106075b | ths | (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
|
648 | 7c23b892 | balrog | desc.upper.data); |
649 | 7c23b892 | balrog | |
650 | 7c23b892 | balrog | process_tx_desc(s, &desc); |
651 | 62ecbd35 | Eduard - Gabriel Munteanu | cause |= txdesc_writeback(s, base, &desc); |
652 | 7c23b892 | balrog | |
653 | 7c23b892 | balrog | if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) |
654 | 7c23b892 | balrog | s->mac_reg[TDH] = 0;
|
655 | 7c23b892 | balrog | /*
|
656 | 7c23b892 | balrog | * the following could happen only if guest sw assigns
|
657 | 7c23b892 | balrog | * bogus values to TDT/TDLEN.
|
658 | 7c23b892 | balrog | * there's nothing too intelligent we could do about this.
|
659 | 7c23b892 | balrog | */
|
660 | 7c23b892 | balrog | if (s->mac_reg[TDH] == tdh_start) {
|
661 | 7c23b892 | balrog | DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
|
662 | 7c23b892 | balrog | tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); |
663 | 7c23b892 | balrog | break;
|
664 | 7c23b892 | balrog | } |
665 | 7c23b892 | balrog | } |
666 | 7c23b892 | balrog | set_ics(s, 0, cause);
|
667 | 7c23b892 | balrog | } |
668 | 7c23b892 | balrog | |
669 | 7c23b892 | balrog | static int |
670 | 7c23b892 | balrog | receive_filter(E1000State *s, const uint8_t *buf, int size) |
671 | 7c23b892 | balrog | { |
672 | af2960f9 | Blue Swirl | static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; |
673 | af2960f9 | Blue Swirl | static const int mta_shift[] = {4, 3, 2, 0}; |
674 | 7c23b892 | balrog | uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
|
675 | 7c23b892 | balrog | |
676 | 8f2e8d1f | aliguori | if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
|
677 | 8f2e8d1f | aliguori | uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
|
678 | 8f2e8d1f | aliguori | uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) + |
679 | 8f2e8d1f | aliguori | ((vid >> 5) & 0x7f)); |
680 | 8f2e8d1f | aliguori | if ((vfta & (1 << (vid & 0x1f))) == 0) |
681 | 8f2e8d1f | aliguori | return 0; |
682 | 8f2e8d1f | aliguori | } |
683 | 8f2e8d1f | aliguori | |
684 | 7c23b892 | balrog | if (rctl & E1000_RCTL_UPE) // promiscuous |
685 | 7c23b892 | balrog | return 1; |
686 | 7c23b892 | balrog | |
687 | 7c23b892 | balrog | if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast |
688 | 7c23b892 | balrog | return 1; |
689 | 7c23b892 | balrog | |
690 | 7c23b892 | balrog | if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast)) |
691 | 7c23b892 | balrog | return 1; |
692 | 7c23b892 | balrog | |
693 | 7c23b892 | balrog | for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) { |
694 | 7c23b892 | balrog | if (!(rp[1] & E1000_RAH_AV)) |
695 | 7c23b892 | balrog | continue;
|
696 | 7c23b892 | balrog | ra[0] = cpu_to_le32(rp[0]); |
697 | 7c23b892 | balrog | ra[1] = cpu_to_le32(rp[1]); |
698 | 7c23b892 | balrog | if (!memcmp(buf, (uint8_t *)ra, 6)) { |
699 | 7c23b892 | balrog | DBGOUT(RXFILTER, |
700 | 7c23b892 | balrog | "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
701 | 7c23b892 | balrog | (int)(rp - s->mac_reg - RA)/2, |
702 | 7c23b892 | balrog | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
703 | 7c23b892 | balrog | return 1; |
704 | 7c23b892 | balrog | } |
705 | 7c23b892 | balrog | } |
706 | 7c23b892 | balrog | DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
707 | 7c23b892 | balrog | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
708 | 7c23b892 | balrog | |
709 | 7c23b892 | balrog | f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
|
710 | 7c23b892 | balrog | f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; |
711 | 7c23b892 | balrog | if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f))) |
712 | 7c23b892 | balrog | return 1; |
713 | 7c23b892 | balrog | DBGOUT(RXFILTER, |
714 | 7c23b892 | balrog | "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
|
715 | 7c23b892 | balrog | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
716 | 7c23b892 | balrog | (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5, |
717 | 7c23b892 | balrog | s->mac_reg[MTA + (f >> 5)]);
|
718 | 7c23b892 | balrog | |
719 | 7c23b892 | balrog | return 0; |
720 | 7c23b892 | balrog | } |
721 | 7c23b892 | balrog | |
722 | 99ed7e30 | aliguori | static void |
723 | a03e2aec | Mark McLoughlin | e1000_set_link_status(VLANClientState *nc) |
724 | 99ed7e30 | aliguori | { |
725 | a03e2aec | Mark McLoughlin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
726 | 99ed7e30 | aliguori | uint32_t old_status = s->mac_reg[STATUS]; |
727 | 99ed7e30 | aliguori | |
728 | d4044c2a | Bjørn Mork | if (nc->link_down) {
|
729 | 71aadd3c | Jason Wang | e1000_link_down(s); |
730 | d4044c2a | Bjørn Mork | } else {
|
731 | 71aadd3c | Jason Wang | e1000_link_up(s); |
732 | d4044c2a | Bjørn Mork | } |
733 | 99ed7e30 | aliguori | |
734 | 99ed7e30 | aliguori | if (s->mac_reg[STATUS] != old_status)
|
735 | 99ed7e30 | aliguori | set_ics(s, 0, E1000_ICR_LSC);
|
736 | 99ed7e30 | aliguori | } |
737 | 99ed7e30 | aliguori | |
738 | 322fd48a | Michael S. Tsirkin | static bool e1000_has_rxbufs(E1000State *s, size_t total_size) |
739 | 322fd48a | Michael S. Tsirkin | { |
740 | 322fd48a | Michael S. Tsirkin | int bufs;
|
741 | 322fd48a | Michael S. Tsirkin | /* Fast-path short packets */
|
742 | 322fd48a | Michael S. Tsirkin | if (total_size <= s->rxbuf_size) {
|
743 | 322fd48a | Michael S. Tsirkin | return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
|
744 | 322fd48a | Michael S. Tsirkin | } |
745 | 322fd48a | Michael S. Tsirkin | if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
|
746 | 322fd48a | Michael S. Tsirkin | bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; |
747 | 322fd48a | Michael S. Tsirkin | } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) { |
748 | 322fd48a | Michael S. Tsirkin | bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + |
749 | 322fd48a | Michael S. Tsirkin | s->mac_reg[RDT] - s->mac_reg[RDH]; |
750 | 322fd48a | Michael S. Tsirkin | } else {
|
751 | 322fd48a | Michael S. Tsirkin | return false; |
752 | 322fd48a | Michael S. Tsirkin | } |
753 | 322fd48a | Michael S. Tsirkin | return total_size <= bufs * s->rxbuf_size;
|
754 | 322fd48a | Michael S. Tsirkin | } |
755 | 322fd48a | Michael S. Tsirkin | |
756 | 6cdfab28 | Michael S. Tsirkin | static int |
757 | 6cdfab28 | Michael S. Tsirkin | e1000_can_receive(VLANClientState *nc) |
758 | 6cdfab28 | Michael S. Tsirkin | { |
759 | 6cdfab28 | Michael S. Tsirkin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
760 | 6cdfab28 | Michael S. Tsirkin | |
761 | 6cdfab28 | Michael S. Tsirkin | return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1); |
762 | 6cdfab28 | Michael S. Tsirkin | } |
763 | 6cdfab28 | Michael S. Tsirkin | |
764 | d17161f6 | Kevin Wolf | static uint64_t rx_desc_base(E1000State *s)
|
765 | d17161f6 | Kevin Wolf | { |
766 | d17161f6 | Kevin Wolf | uint64_t bah = s->mac_reg[RDBAH]; |
767 | d17161f6 | Kevin Wolf | uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
|
768 | d17161f6 | Kevin Wolf | |
769 | d17161f6 | Kevin Wolf | return (bah << 32) + bal; |
770 | d17161f6 | Kevin Wolf | } |
771 | d17161f6 | Kevin Wolf | |
772 | 4f1c942b | Mark McLoughlin | static ssize_t
|
773 | a03e2aec | Mark McLoughlin | e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
|
774 | 7c23b892 | balrog | { |
775 | a03e2aec | Mark McLoughlin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
776 | 7c23b892 | balrog | struct e1000_rx_desc desc;
|
777 | 62ecbd35 | Eduard - Gabriel Munteanu | dma_addr_t base; |
778 | 7c23b892 | balrog | unsigned int n, rdt; |
779 | 7c23b892 | balrog | uint32_t rdh_start; |
780 | 8f2e8d1f | aliguori | uint16_t vlan_special = 0;
|
781 | 8f2e8d1f | aliguori | uint8_t vlan_status = 0, vlan_offset = 0; |
782 | 78aeb23e | Stefan Hajnoczi | uint8_t min_buf[MIN_BUF_SIZE]; |
783 | b19487e2 | Michael S. Tsirkin | size_t desc_offset; |
784 | b19487e2 | Michael S. Tsirkin | size_t desc_size; |
785 | b19487e2 | Michael S. Tsirkin | size_t total_size; |
786 | 7c23b892 | balrog | |
787 | 7c23b892 | balrog | if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
|
788 | 4f1c942b | Mark McLoughlin | return -1; |
789 | 7c23b892 | balrog | |
790 | 78aeb23e | Stefan Hajnoczi | /* Pad to minimum Ethernet frame length */
|
791 | 78aeb23e | Stefan Hajnoczi | if (size < sizeof(min_buf)) { |
792 | 78aeb23e | Stefan Hajnoczi | memcpy(min_buf, buf, size); |
793 | 78aeb23e | Stefan Hajnoczi | memset(&min_buf[size], 0, sizeof(min_buf) - size); |
794 | 78aeb23e | Stefan Hajnoczi | buf = min_buf; |
795 | 78aeb23e | Stefan Hajnoczi | size = sizeof(min_buf);
|
796 | 78aeb23e | Stefan Hajnoczi | } |
797 | 78aeb23e | Stefan Hajnoczi | |
798 | 7c23b892 | balrog | if (!receive_filter(s, buf, size))
|
799 | 4f1c942b | Mark McLoughlin | return size;
|
800 | 7c23b892 | balrog | |
801 | 8f2e8d1f | aliguori | if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
|
802 | 8f2e8d1f | aliguori | vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
|
803 | 98835fe3 | Thomas Monjalon | memmove((uint8_t *)buf + 4, buf, 12); |
804 | 8f2e8d1f | aliguori | vlan_status = E1000_RXD_STAT_VP; |
805 | 8f2e8d1f | aliguori | vlan_offset = 4;
|
806 | 8f2e8d1f | aliguori | size -= 4;
|
807 | 8f2e8d1f | aliguori | } |
808 | 8f2e8d1f | aliguori | |
809 | 7c23b892 | balrog | rdh_start = s->mac_reg[RDH]; |
810 | b19487e2 | Michael S. Tsirkin | desc_offset = 0;
|
811 | b19487e2 | Michael S. Tsirkin | total_size = size + fcs_len(s); |
812 | 322fd48a | Michael S. Tsirkin | if (!e1000_has_rxbufs(s, total_size)) {
|
813 | 322fd48a | Michael S. Tsirkin | set_ics(s, 0, E1000_ICS_RXO);
|
814 | 322fd48a | Michael S. Tsirkin | return -1; |
815 | 322fd48a | Michael S. Tsirkin | } |
816 | 7c23b892 | balrog | do {
|
817 | b19487e2 | Michael S. Tsirkin | desc_size = total_size - desc_offset; |
818 | b19487e2 | Michael S. Tsirkin | if (desc_size > s->rxbuf_size) {
|
819 | b19487e2 | Michael S. Tsirkin | desc_size = s->rxbuf_size; |
820 | b19487e2 | Michael S. Tsirkin | } |
821 | d17161f6 | Kevin Wolf | base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
|
822 | 00c3a05b | David Gibson | pci_dma_read(&s->dev, base, &desc, sizeof(desc));
|
823 | 8f2e8d1f | aliguori | desc.special = vlan_special; |
824 | 8f2e8d1f | aliguori | desc.status |= (vlan_status | E1000_RXD_STAT_DD); |
825 | 7c23b892 | balrog | if (desc.buffer_addr) {
|
826 | b19487e2 | Michael S. Tsirkin | if (desc_offset < size) {
|
827 | b19487e2 | Michael S. Tsirkin | size_t copy_size = size - desc_offset; |
828 | b19487e2 | Michael S. Tsirkin | if (copy_size > s->rxbuf_size) {
|
829 | b19487e2 | Michael S. Tsirkin | copy_size = s->rxbuf_size; |
830 | b19487e2 | Michael S. Tsirkin | } |
831 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr), |
832 | 00c3a05b | David Gibson | buf + desc_offset + vlan_offset, copy_size); |
833 | b19487e2 | Michael S. Tsirkin | } |
834 | b19487e2 | Michael S. Tsirkin | desc_offset += desc_size; |
835 | ee912ccf | Michael S. Tsirkin | desc.length = cpu_to_le16(desc_size); |
836 | b19487e2 | Michael S. Tsirkin | if (desc_offset >= total_size) {
|
837 | b19487e2 | Michael S. Tsirkin | desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM; |
838 | b19487e2 | Michael S. Tsirkin | } else {
|
839 | ee912ccf | Michael S. Tsirkin | /* Guest zeroing out status is not a hardware requirement.
|
840 | ee912ccf | Michael S. Tsirkin | Clear EOP in case guest didn't do it. */
|
841 | ee912ccf | Michael S. Tsirkin | desc.status &= ~E1000_RXD_STAT_EOP; |
842 | b19487e2 | Michael S. Tsirkin | } |
843 | 43ad7e3e | Jes Sorensen | } else { // as per intel docs; skip descriptors with null buf addr |
844 | 7c23b892 | balrog | DBGOUT(RX, "Null RX descriptor!!\n");
|
845 | 43ad7e3e | Jes Sorensen | } |
846 | 00c3a05b | David Gibson | pci_dma_write(&s->dev, base, &desc, sizeof(desc));
|
847 | 7c23b892 | balrog | |
848 | 7c23b892 | balrog | if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) |
849 | 7c23b892 | balrog | s->mac_reg[RDH] = 0;
|
850 | 7c23b892 | balrog | s->check_rxov = 1;
|
851 | 7c23b892 | balrog | /* see comment in start_xmit; same here */
|
852 | 7c23b892 | balrog | if (s->mac_reg[RDH] == rdh_start) {
|
853 | 7c23b892 | balrog | DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
|
854 | 7c23b892 | balrog | rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); |
855 | 7c23b892 | balrog | set_ics(s, 0, E1000_ICS_RXO);
|
856 | 4f1c942b | Mark McLoughlin | return -1; |
857 | 7c23b892 | balrog | } |
858 | b19487e2 | Michael S. Tsirkin | } while (desc_offset < total_size);
|
859 | 7c23b892 | balrog | |
860 | 7c23b892 | balrog | s->mac_reg[GPRC]++; |
861 | 7c23b892 | balrog | s->mac_reg[TPR]++; |
862 | a05e8a6e | Michael S. Tsirkin | /* TOR - Total Octets Received:
|
863 | a05e8a6e | Michael S. Tsirkin | * This register includes bytes received in a packet from the <Destination
|
864 | a05e8a6e | Michael S. Tsirkin | * Address> field through the <CRC> field, inclusively.
|
865 | a05e8a6e | Michael S. Tsirkin | */
|
866 | a05e8a6e | Michael S. Tsirkin | n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4; |
867 | a05e8a6e | Michael S. Tsirkin | if (n < s->mac_reg[TORL])
|
868 | 7c23b892 | balrog | s->mac_reg[TORH]++; |
869 | a05e8a6e | Michael S. Tsirkin | s->mac_reg[TORL] = n; |
870 | 7c23b892 | balrog | |
871 | 7c23b892 | balrog | n = E1000_ICS_RXT0; |
872 | 7c23b892 | balrog | if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
|
873 | 7c23b892 | balrog | rdt += s->mac_reg[RDLEN] / sizeof(desc);
|
874 | bf16cc8f | aliguori | if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> |
875 | bf16cc8f | aliguori | s->rxbuf_min_shift) |
876 | 7c23b892 | balrog | n |= E1000_ICS_RXDMT0; |
877 | 7c23b892 | balrog | |
878 | 7c23b892 | balrog | set_ics(s, 0, n);
|
879 | 4f1c942b | Mark McLoughlin | |
880 | 4f1c942b | Mark McLoughlin | return size;
|
881 | 7c23b892 | balrog | } |
882 | 7c23b892 | balrog | |
883 | 7c23b892 | balrog | static uint32_t
|
884 | 7c23b892 | balrog | mac_readreg(E1000State *s, int index)
|
885 | 7c23b892 | balrog | { |
886 | 7c23b892 | balrog | return s->mac_reg[index];
|
887 | 7c23b892 | balrog | } |
888 | 7c23b892 | balrog | |
889 | 7c23b892 | balrog | static uint32_t
|
890 | 7c23b892 | balrog | mac_icr_read(E1000State *s, int index)
|
891 | 7c23b892 | balrog | { |
892 | 7c23b892 | balrog | uint32_t ret = s->mac_reg[ICR]; |
893 | 7c23b892 | balrog | |
894 | 7c23b892 | balrog | DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
|
895 | 7c23b892 | balrog | set_interrupt_cause(s, 0, 0); |
896 | 7c23b892 | balrog | return ret;
|
897 | 7c23b892 | balrog | } |
898 | 7c23b892 | balrog | |
899 | 7c23b892 | balrog | static uint32_t
|
900 | 7c23b892 | balrog | mac_read_clr4(E1000State *s, int index)
|
901 | 7c23b892 | balrog | { |
902 | 7c23b892 | balrog | uint32_t ret = s->mac_reg[index]; |
903 | 7c23b892 | balrog | |
904 | 7c23b892 | balrog | s->mac_reg[index] = 0;
|
905 | 7c23b892 | balrog | return ret;
|
906 | 7c23b892 | balrog | } |
907 | 7c23b892 | balrog | |
908 | 7c23b892 | balrog | static uint32_t
|
909 | 7c23b892 | balrog | mac_read_clr8(E1000State *s, int index)
|
910 | 7c23b892 | balrog | { |
911 | 7c23b892 | balrog | uint32_t ret = s->mac_reg[index]; |
912 | 7c23b892 | balrog | |
913 | 7c23b892 | balrog | s->mac_reg[index] = 0;
|
914 | 7c23b892 | balrog | s->mac_reg[index-1] = 0; |
915 | 7c23b892 | balrog | return ret;
|
916 | 7c23b892 | balrog | } |
917 | 7c23b892 | balrog | |
918 | 7c23b892 | balrog | static void |
919 | 7c23b892 | balrog | mac_writereg(E1000State *s, int index, uint32_t val)
|
920 | 7c23b892 | balrog | { |
921 | 7c23b892 | balrog | s->mac_reg[index] = val; |
922 | 7c23b892 | balrog | } |
923 | 7c23b892 | balrog | |
924 | 7c23b892 | balrog | static void |
925 | 7c23b892 | balrog | set_rdt(E1000State *s, int index, uint32_t val)
|
926 | 7c23b892 | balrog | { |
927 | 7c23b892 | balrog | s->check_rxov = 0;
|
928 | 7c23b892 | balrog | s->mac_reg[index] = val & 0xffff;
|
929 | 7c23b892 | balrog | } |
930 | 7c23b892 | balrog | |
931 | 7c23b892 | balrog | static void |
932 | 7c23b892 | balrog | set_16bit(E1000State *s, int index, uint32_t val)
|
933 | 7c23b892 | balrog | { |
934 | 7c23b892 | balrog | s->mac_reg[index] = val & 0xffff;
|
935 | 7c23b892 | balrog | } |
936 | 7c23b892 | balrog | |
937 | 7c23b892 | balrog | static void |
938 | 7c23b892 | balrog | set_dlen(E1000State *s, int index, uint32_t val)
|
939 | 7c23b892 | balrog | { |
940 | 7c23b892 | balrog | s->mac_reg[index] = val & 0xfff80;
|
941 | 7c23b892 | balrog | } |
942 | 7c23b892 | balrog | |
943 | 7c23b892 | balrog | static void |
944 | 7c23b892 | balrog | set_tctl(E1000State *s, int index, uint32_t val)
|
945 | 7c23b892 | balrog | { |
946 | 7c23b892 | balrog | s->mac_reg[index] = val; |
947 | 7c23b892 | balrog | s->mac_reg[TDT] &= 0xffff;
|
948 | 7c23b892 | balrog | start_xmit(s); |
949 | 7c23b892 | balrog | } |
950 | 7c23b892 | balrog | |
951 | 7c23b892 | balrog | static void |
952 | 7c23b892 | balrog | set_icr(E1000State *s, int index, uint32_t val)
|
953 | 7c23b892 | balrog | { |
954 | 7c23b892 | balrog | DBGOUT(INTERRUPT, "set_icr %x\n", val);
|
955 | 7c23b892 | balrog | set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
|
956 | 7c23b892 | balrog | } |
957 | 7c23b892 | balrog | |
958 | 7c23b892 | balrog | static void |
959 | 7c23b892 | balrog | set_imc(E1000State *s, int index, uint32_t val)
|
960 | 7c23b892 | balrog | { |
961 | 7c23b892 | balrog | s->mac_reg[IMS] &= ~val; |
962 | 7c23b892 | balrog | set_ics(s, 0, 0); |
963 | 7c23b892 | balrog | } |
964 | 7c23b892 | balrog | |
965 | 7c23b892 | balrog | static void |
966 | 7c23b892 | balrog | set_ims(E1000State *s, int index, uint32_t val)
|
967 | 7c23b892 | balrog | { |
968 | 7c23b892 | balrog | s->mac_reg[IMS] |= val; |
969 | 7c23b892 | balrog | set_ics(s, 0, 0); |
970 | 7c23b892 | balrog | } |
971 | 7c23b892 | balrog | |
972 | 7c23b892 | balrog | #define getreg(x) [x] = mac_readreg
|
973 | 7c23b892 | balrog | static uint32_t (*macreg_readops[])(E1000State *, int) = { |
974 | 7c23b892 | balrog | getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL), |
975 | 7c23b892 | balrog | getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL), |
976 | 7c23b892 | balrog | getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), |
977 | 7c23b892 | balrog | getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL), |
978 | b1332393 | Bill Paul | getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS), |
979 | a00b2335 | Kay Ackermann | getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL), |
980 | a00b2335 | Kay Ackermann | getreg(TDLEN), getreg(RDLEN), |
981 | 7c23b892 | balrog | |
982 | 7c23b892 | balrog | [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4, |
983 | 7c23b892 | balrog | [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4, |
984 | 7c23b892 | balrog | [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read, |
985 | 7c23b892 | balrog | [CRCERRS ... MPC] = &mac_readreg, |
986 | 7c23b892 | balrog | [RA ... RA+31] = &mac_readreg,
|
987 | 7c23b892 | balrog | [MTA ... MTA+127] = &mac_readreg,
|
988 | 8f2e8d1f | aliguori | [VFTA ... VFTA+127] = &mac_readreg,
|
989 | 7c23b892 | balrog | }; |
990 | b1503cda | malc | enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
|
991 | 7c23b892 | balrog | |
992 | 7c23b892 | balrog | #define putreg(x) [x] = mac_writereg
|
993 | 7c23b892 | balrog | static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { |
994 | 7c23b892 | balrog | putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), |
995 | 7c23b892 | balrog | putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), |
996 | cab3c825 | Kevin Wolf | putreg(RDBAL), putreg(LEDCTL), putreg(VET), |
997 | 7c23b892 | balrog | [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, |
998 | 7c23b892 | balrog | [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, |
999 | 7c23b892 | balrog | [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, |
1000 | 7c23b892 | balrog | [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, |
1001 | cab3c825 | Kevin Wolf | [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl, |
1002 | 7c23b892 | balrog | [RA ... RA+31] = &mac_writereg,
|
1003 | 7c23b892 | balrog | [MTA ... MTA+127] = &mac_writereg,
|
1004 | 8f2e8d1f | aliguori | [VFTA ... VFTA+127] = &mac_writereg,
|
1005 | 7c23b892 | balrog | }; |
1006 | b9d03e35 | Jason Wang | |
1007 | b1503cda | malc | enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
|
1008 | 7c23b892 | balrog | |
1009 | 7c23b892 | balrog | static void |
1010 | ad00a9b9 | Avi Kivity | e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
|
1011 | ad00a9b9 | Avi Kivity | unsigned size)
|
1012 | 7c23b892 | balrog | { |
1013 | 7c23b892 | balrog | E1000State *s = opaque; |
1014 | 8da3ff18 | pbrook | unsigned int index = (addr & 0x1ffff) >> 2; |
1015 | 7c23b892 | balrog | |
1016 | 43ad7e3e | Jes Sorensen | if (index < NWRITEOPS && macreg_writeops[index]) {
|
1017 | 6b59fc74 | aurel32 | macreg_writeops[index](s, index, val); |
1018 | 43ad7e3e | Jes Sorensen | } else if (index < NREADOPS && macreg_readops[index]) { |
1019 | ad00a9b9 | Avi Kivity | DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val); |
1020 | 43ad7e3e | Jes Sorensen | } else {
|
1021 | ad00a9b9 | Avi Kivity | DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n", |
1022 | 7c23b892 | balrog | index<<2, val);
|
1023 | 43ad7e3e | Jes Sorensen | } |
1024 | 7c23b892 | balrog | } |
1025 | 7c23b892 | balrog | |
1026 | ad00a9b9 | Avi Kivity | static uint64_t
|
1027 | ad00a9b9 | Avi Kivity | e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size) |
1028 | 7c23b892 | balrog | { |
1029 | 7c23b892 | balrog | E1000State *s = opaque; |
1030 | 8da3ff18 | pbrook | unsigned int index = (addr & 0x1ffff) >> 2; |
1031 | 7c23b892 | balrog | |
1032 | 7c23b892 | balrog | if (index < NREADOPS && macreg_readops[index])
|
1033 | 6b59fc74 | aurel32 | { |
1034 | 32600a30 | Alexander Graf | return macreg_readops[index](s, index);
|
1035 | 6b59fc74 | aurel32 | } |
1036 | 7c23b892 | balrog | DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); |
1037 | 7c23b892 | balrog | return 0; |
1038 | 7c23b892 | balrog | } |
1039 | 7c23b892 | balrog | |
1040 | ad00a9b9 | Avi Kivity | static const MemoryRegionOps e1000_mmio_ops = { |
1041 | ad00a9b9 | Avi Kivity | .read = e1000_mmio_read, |
1042 | ad00a9b9 | Avi Kivity | .write = e1000_mmio_write, |
1043 | ad00a9b9 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
1044 | ad00a9b9 | Avi Kivity | .impl = { |
1045 | ad00a9b9 | Avi Kivity | .min_access_size = 4,
|
1046 | ad00a9b9 | Avi Kivity | .max_access_size = 4,
|
1047 | ad00a9b9 | Avi Kivity | }, |
1048 | ad00a9b9 | Avi Kivity | }; |
1049 | ad00a9b9 | Avi Kivity | |
1050 | ad00a9b9 | Avi Kivity | static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr, |
1051 | ad00a9b9 | Avi Kivity | unsigned size)
|
1052 | 7c23b892 | balrog | { |
1053 | ad00a9b9 | Avi Kivity | E1000State *s = opaque; |
1054 | ad00a9b9 | Avi Kivity | |
1055 | ad00a9b9 | Avi Kivity | (void)s;
|
1056 | ad00a9b9 | Avi Kivity | return 0; |
1057 | 7c23b892 | balrog | } |
1058 | 7c23b892 | balrog | |
1059 | ad00a9b9 | Avi Kivity | static void e1000_io_write(void *opaque, target_phys_addr_t addr, |
1060 | ad00a9b9 | Avi Kivity | uint64_t val, unsigned size)
|
1061 | 7c23b892 | balrog | { |
1062 | ad00a9b9 | Avi Kivity | E1000State *s = opaque; |
1063 | ad00a9b9 | Avi Kivity | |
1064 | ad00a9b9 | Avi Kivity | (void)s;
|
1065 | 7c23b892 | balrog | } |
1066 | 7c23b892 | balrog | |
1067 | ad00a9b9 | Avi Kivity | static const MemoryRegionOps e1000_io_ops = { |
1068 | ad00a9b9 | Avi Kivity | .read = e1000_io_read, |
1069 | ad00a9b9 | Avi Kivity | .write = e1000_io_write, |
1070 | ad00a9b9 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
1071 | ad00a9b9 | Avi Kivity | }; |
1072 | ad00a9b9 | Avi Kivity | |
1073 | e482dc3e | Juan Quintela | static bool is_version_1(void *opaque, int version_id) |
1074 | 7c23b892 | balrog | { |
1075 | e482dc3e | Juan Quintela | return version_id == 1; |
1076 | 7c23b892 | balrog | } |
1077 | 7c23b892 | balrog | |
1078 | e482dc3e | Juan Quintela | static const VMStateDescription vmstate_e1000 = { |
1079 | e482dc3e | Juan Quintela | .name = "e1000",
|
1080 | e482dc3e | Juan Quintela | .version_id = 2,
|
1081 | e482dc3e | Juan Quintela | .minimum_version_id = 1,
|
1082 | e482dc3e | Juan Quintela | .minimum_version_id_old = 1,
|
1083 | e482dc3e | Juan Quintela | .fields = (VMStateField []) { |
1084 | e482dc3e | Juan Quintela | VMSTATE_PCI_DEVICE(dev, E1000State), |
1085 | e482dc3e | Juan Quintela | VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */ |
1086 | e482dc3e | Juan Quintela | VMSTATE_UNUSED(4), /* Was mmio_base. */ |
1087 | e482dc3e | Juan Quintela | VMSTATE_UINT32(rxbuf_size, E1000State), |
1088 | e482dc3e | Juan Quintela | VMSTATE_UINT32(rxbuf_min_shift, E1000State), |
1089 | e482dc3e | Juan Quintela | VMSTATE_UINT32(eecd_state.val_in, E1000State), |
1090 | e482dc3e | Juan Quintela | VMSTATE_UINT16(eecd_state.bitnum_in, E1000State), |
1091 | e482dc3e | Juan Quintela | VMSTATE_UINT16(eecd_state.bitnum_out, E1000State), |
1092 | e482dc3e | Juan Quintela | VMSTATE_UINT16(eecd_state.reading, E1000State), |
1093 | e482dc3e | Juan Quintela | VMSTATE_UINT32(eecd_state.old_eecd, E1000State), |
1094 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.ipcss, E1000State), |
1095 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.ipcso, E1000State), |
1096 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.ipcse, E1000State), |
1097 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.tucss, E1000State), |
1098 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.tucso, E1000State), |
1099 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.tucse, E1000State), |
1100 | e482dc3e | Juan Quintela | VMSTATE_UINT32(tx.paylen, E1000State), |
1101 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.hdr_len, E1000State), |
1102 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.mss, E1000State), |
1103 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.size, E1000State), |
1104 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.tso_frames, E1000State), |
1105 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.sum_needed, E1000State), |
1106 | e482dc3e | Juan Quintela | VMSTATE_INT8(tx.ip, E1000State), |
1107 | e482dc3e | Juan Quintela | VMSTATE_INT8(tx.tcp, E1000State), |
1108 | e482dc3e | Juan Quintela | VMSTATE_BUFFER(tx.header, E1000State), |
1109 | e482dc3e | Juan Quintela | VMSTATE_BUFFER(tx.data, E1000State), |
1110 | e482dc3e | Juan Quintela | VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
|
1111 | e482dc3e | Juan Quintela | VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
|
1112 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[CTRL], E1000State), |
1113 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[EECD], E1000State), |
1114 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[EERD], E1000State), |
1115 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[GPRC], E1000State), |
1116 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[GPTC], E1000State), |
1117 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[ICR], E1000State), |
1118 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[ICS], E1000State), |
1119 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[IMC], E1000State), |
1120 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[IMS], E1000State), |
1121 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[LEDCTL], E1000State), |
1122 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[MANC], E1000State), |
1123 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[MDIC], E1000State), |
1124 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[MPC], E1000State), |
1125 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[PBA], E1000State), |
1126 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RCTL], E1000State), |
1127 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDBAH], E1000State), |
1128 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDBAL], E1000State), |
1129 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDH], E1000State), |
1130 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDLEN], E1000State), |
1131 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDT], E1000State), |
1132 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[STATUS], E1000State), |
1133 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[SWSM], E1000State), |
1134 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TCTL], E1000State), |
1135 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDBAH], E1000State), |
1136 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDBAL], E1000State), |
1137 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDH], E1000State), |
1138 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDLEN], E1000State), |
1139 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDT], E1000State), |
1140 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TORH], E1000State), |
1141 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TORL], E1000State), |
1142 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TOTH], E1000State), |
1143 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TOTL], E1000State), |
1144 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TPR], E1000State), |
1145 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TPT], E1000State), |
1146 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TXDCTL], E1000State), |
1147 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[WUFC], E1000State), |
1148 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[VET], E1000State), |
1149 | e482dc3e | Juan Quintela | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
|
1150 | e482dc3e | Juan Quintela | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
|
1151 | e482dc3e | Juan Quintela | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
|
1152 | e482dc3e | Juan Quintela | VMSTATE_END_OF_LIST() |
1153 | e482dc3e | Juan Quintela | } |
1154 | e482dc3e | Juan Quintela | }; |
1155 | 7c23b892 | balrog | |
1156 | 88b4e9db | blueswir1 | static const uint16_t e1000_eeprom_template[64] = { |
1157 | 7c23b892 | balrog | 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000, |
1158 | 7c23b892 | balrog | 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040, |
1159 | 7c23b892 | balrog | 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700, |
1160 | 7c23b892 | balrog | 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706, |
1161 | 7c23b892 | balrog | 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff, |
1162 | 7c23b892 | balrog | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
1163 | 7c23b892 | balrog | 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
1164 | 7c23b892 | balrog | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, |
1165 | 7c23b892 | balrog | }; |
1166 | 7c23b892 | balrog | |
1167 | 7c23b892 | balrog | /* PCI interface */
|
1168 | 7c23b892 | balrog | |
1169 | 7c23b892 | balrog | static void |
1170 | ad00a9b9 | Avi Kivity | e1000_mmio_setup(E1000State *d) |
1171 | 7c23b892 | balrog | { |
1172 | f65ed4c1 | aliguori | int i;
|
1173 | f65ed4c1 | aliguori | const uint32_t excluded_regs[] = {
|
1174 | f65ed4c1 | aliguori | E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS, |
1175 | f65ed4c1 | aliguori | E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE |
1176 | f65ed4c1 | aliguori | }; |
1177 | f65ed4c1 | aliguori | |
1178 | ad00a9b9 | Avi Kivity | memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
|
1179 | ad00a9b9 | Avi Kivity | PNPMMIO_SIZE); |
1180 | ad00a9b9 | Avi Kivity | memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]); |
1181 | f65ed4c1 | aliguori | for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++) |
1182 | ad00a9b9 | Avi Kivity | memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
|
1183 | ad00a9b9 | Avi Kivity | excluded_regs[i+1] - excluded_regs[i] - 4); |
1184 | ad00a9b9 | Avi Kivity | memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
|
1185 | 7c23b892 | balrog | } |
1186 | 7c23b892 | balrog | |
1187 | b946a153 | aliguori | static void |
1188 | a03e2aec | Mark McLoughlin | e1000_cleanup(VLANClientState *nc) |
1189 | b946a153 | aliguori | { |
1190 | a03e2aec | Mark McLoughlin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1191 | b946a153 | aliguori | |
1192 | a03e2aec | Mark McLoughlin | s->nic = NULL;
|
1193 | b946a153 | aliguori | } |
1194 | b946a153 | aliguori | |
1195 | 4b09be85 | aliguori | static int |
1196 | 4b09be85 | aliguori | pci_e1000_uninit(PCIDevice *dev) |
1197 | 4b09be85 | aliguori | { |
1198 | 7d9e52bd | Juan Quintela | E1000State *d = DO_UPCAST(E1000State, dev, dev); |
1199 | 4b09be85 | aliguori | |
1200 | b9d03e35 | Jason Wang | qemu_del_timer(d->autoneg_timer); |
1201 | b9d03e35 | Jason Wang | qemu_free_timer(d->autoneg_timer); |
1202 | ad00a9b9 | Avi Kivity | memory_region_destroy(&d->mmio); |
1203 | ad00a9b9 | Avi Kivity | memory_region_destroy(&d->io); |
1204 | a03e2aec | Mark McLoughlin | qemu_del_vlan_client(&d->nic->nc); |
1205 | 4b09be85 | aliguori | return 0; |
1206 | 4b09be85 | aliguori | } |
1207 | 4b09be85 | aliguori | |
1208 | a03e2aec | Mark McLoughlin | static NetClientInfo net_e1000_info = {
|
1209 | a03e2aec | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
1210 | a03e2aec | Mark McLoughlin | .size = sizeof(NICState),
|
1211 | a03e2aec | Mark McLoughlin | .can_receive = e1000_can_receive, |
1212 | a03e2aec | Mark McLoughlin | .receive = e1000_receive, |
1213 | a03e2aec | Mark McLoughlin | .cleanup = e1000_cleanup, |
1214 | a03e2aec | Mark McLoughlin | .link_status_changed = e1000_set_link_status, |
1215 | a03e2aec | Mark McLoughlin | }; |
1216 | a03e2aec | Mark McLoughlin | |
1217 | 81a322d4 | Gerd Hoffmann | static int pci_e1000_init(PCIDevice *pci_dev) |
1218 | 7c23b892 | balrog | { |
1219 | 7d9e52bd | Juan Quintela | E1000State *d = DO_UPCAST(E1000State, dev, pci_dev); |
1220 | 7c23b892 | balrog | uint8_t *pci_conf; |
1221 | 7c23b892 | balrog | uint16_t checksum = 0;
|
1222 | 7c23b892 | balrog | int i;
|
1223 | fbdaa002 | Gerd Hoffmann | uint8_t *macaddr; |
1224 | aff427a1 | Chris Wright | |
1225 | 7c23b892 | balrog | pci_conf = d->dev.config; |
1226 | 7c23b892 | balrog | |
1227 | a9cbacb0 | Michael S. Tsirkin | /* TODO: RST# value should be 0, PCI spec 6.2.4 */
|
1228 | a9cbacb0 | Michael S. Tsirkin | pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
|
1229 | 7c23b892 | balrog | |
1230 | 817e0b6f | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
1231 | 7c23b892 | balrog | |
1232 | ad00a9b9 | Avi Kivity | e1000_mmio_setup(d); |
1233 | 7c23b892 | balrog | |
1234 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
|
1235 | 7c23b892 | balrog | |
1236 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
|
1237 | 7c23b892 | balrog | |
1238 | 7c23b892 | balrog | memmove(d->eeprom_data, e1000_eeprom_template, |
1239 | 7c23b892 | balrog | sizeof e1000_eeprom_template);
|
1240 | fbdaa002 | Gerd Hoffmann | qemu_macaddr_default_if_unset(&d->conf.macaddr); |
1241 | fbdaa002 | Gerd Hoffmann | macaddr = d->conf.macaddr.a; |
1242 | 7c23b892 | balrog | for (i = 0; i < 3; i++) |
1243 | 9d07d757 | Paul Brook | d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i]; |
1244 | 7c23b892 | balrog | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
1245 | 7c23b892 | balrog | checksum += d->eeprom_data[i]; |
1246 | 7c23b892 | balrog | checksum = (uint16_t) EEPROM_SUM - checksum; |
1247 | 7c23b892 | balrog | d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum; |
1248 | 7c23b892 | balrog | |
1249 | a03e2aec | Mark McLoughlin | d->nic = qemu_new_nic(&net_e1000_info, &d->conf, |
1250 | f79f2bfc | Anthony Liguori | object_get_typename(OBJECT(d)), d->dev.qdev.id, d); |
1251 | 7c23b892 | balrog | |
1252 | a03e2aec | Mark McLoughlin | qemu_format_nic_info_str(&d->nic->nc, macaddr); |
1253 | 1ca4d09a | Gleb Natapov | |
1254 | 1ca4d09a | Gleb Natapov | add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
1255 | 1ca4d09a | Gleb Natapov | |
1256 | b9d03e35 | Jason Wang | d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d); |
1257 | b9d03e35 | Jason Wang | |
1258 | 81a322d4 | Gerd Hoffmann | return 0; |
1259 | 9d07d757 | Paul Brook | } |
1260 | 72da4208 | aliguori | |
1261 | fbdaa002 | Gerd Hoffmann | static void qdev_e1000_reset(DeviceState *dev) |
1262 | fbdaa002 | Gerd Hoffmann | { |
1263 | fbdaa002 | Gerd Hoffmann | E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev); |
1264 | fbdaa002 | Gerd Hoffmann | e1000_reset(d); |
1265 | fbdaa002 | Gerd Hoffmann | } |
1266 | fbdaa002 | Gerd Hoffmann | |
1267 | 40021f08 | Anthony Liguori | static Property e1000_properties[] = {
|
1268 | 40021f08 | Anthony Liguori | DEFINE_NIC_PROPERTIES(E1000State, conf), |
1269 | 40021f08 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
1270 | 40021f08 | Anthony Liguori | }; |
1271 | 40021f08 | Anthony Liguori | |
1272 | 40021f08 | Anthony Liguori | static void e1000_class_init(ObjectClass *klass, void *data) |
1273 | 40021f08 | Anthony Liguori | { |
1274 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
1275 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1276 | 40021f08 | Anthony Liguori | |
1277 | 40021f08 | Anthony Liguori | k->init = pci_e1000_init; |
1278 | 40021f08 | Anthony Liguori | k->exit = pci_e1000_uninit; |
1279 | 40021f08 | Anthony Liguori | k->romfile = "pxe-e1000.rom";
|
1280 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_INTEL; |
1281 | 40021f08 | Anthony Liguori | k->device_id = E1000_DEVID; |
1282 | 40021f08 | Anthony Liguori | k->revision = 0x03;
|
1283 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_NETWORK_ETHERNET; |
1284 | 39bffca2 | Anthony Liguori | dc->desc = "Intel Gigabit Ethernet";
|
1285 | 39bffca2 | Anthony Liguori | dc->reset = qdev_e1000_reset; |
1286 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_e1000; |
1287 | 39bffca2 | Anthony Liguori | dc->props = e1000_properties; |
1288 | 40021f08 | Anthony Liguori | } |
1289 | 40021f08 | Anthony Liguori | |
1290 | 39bffca2 | Anthony Liguori | static TypeInfo e1000_info = {
|
1291 | 39bffca2 | Anthony Liguori | .name = "e1000",
|
1292 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
1293 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(E1000State),
|
1294 | 39bffca2 | Anthony Liguori | .class_init = e1000_class_init, |
1295 | 0aab0d3a | Gerd Hoffmann | }; |
1296 | 0aab0d3a | Gerd Hoffmann | |
1297 | 83f7d43a | Andreas Färber | static void e1000_register_types(void) |
1298 | 9d07d757 | Paul Brook | { |
1299 | 39bffca2 | Anthony Liguori | type_register_static(&e1000_info); |
1300 | 7c23b892 | balrog | } |
1301 | 9d07d757 | Paul Brook | |
1302 | 83f7d43a | Andreas Färber | type_init(e1000_register_types) |