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1 | 420557e8 | bellard | /*
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2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
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3 | 5fafdf24 | ths | *
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4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | f40070c3 | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "console.h" |
26 | 94470844 | blueswir1 | #include "pixel_ops.h" |
27 | f40070c3 | Blue Swirl | #include "sysbus.h" |
28 | ee6847d1 | Gerd Hoffmann | #include "qdev-addr.h" |
29 | 420557e8 | bellard | |
30 | 420557e8 | bellard | #define MAXX 1024 |
31 | 420557e8 | bellard | #define MAXY 768 |
32 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
33 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_8 0x081c |
34 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_24 0x1000 |
35 | 8508b89e | blueswir1 | #define TCX_TEC_NREGS 0x1000 |
36 | 420557e8 | bellard | |
37 | 420557e8 | bellard | typedef struct TCXState { |
38 | f40070c3 | Blue Swirl | SysBusDevice busdev; |
39 | c227f099 | Anthony Liguori | target_phys_addr_t addr; |
40 | 420557e8 | bellard | DisplayState *ds; |
41 | 8d5f07fa | bellard | uint8_t *vram; |
42 | eee0b836 | blueswir1 | uint32_t *vram24, *cplane; |
43 | d08151bf | Avi Kivity | MemoryRegion vram_mem; |
44 | d08151bf | Avi Kivity | MemoryRegion vram_8bit; |
45 | d08151bf | Avi Kivity | MemoryRegion vram_24bit; |
46 | d08151bf | Avi Kivity | MemoryRegion vram_cplane; |
47 | d08151bf | Avi Kivity | MemoryRegion dac; |
48 | d08151bf | Avi Kivity | MemoryRegion tec; |
49 | d08151bf | Avi Kivity | MemoryRegion thc24; |
50 | d08151bf | Avi Kivity | MemoryRegion thc8; |
51 | d08151bf | Avi Kivity | ram_addr_t vram24_offset, cplane_offset; |
52 | ee6847d1 | Gerd Hoffmann | uint32_t vram_size; |
53 | 21206a10 | bellard | uint32_t palette[256];
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54 | 427a66c3 | Blue Swirl | uint8_t r[256], g[256], b[256]; |
55 | 427a66c3 | Blue Swirl | uint16_t width, height, depth; |
56 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
57 | 420557e8 | bellard | } TCXState; |
58 | 420557e8 | bellard | |
59 | 45efb161 | Gerd Hoffmann | static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch); |
60 | 45efb161 | Gerd Hoffmann | static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch); |
61 | d3ffcafe | Blue Swirl | |
62 | d3ffcafe | Blue Swirl | static void tcx_set_dirty(TCXState *s) |
63 | d3ffcafe | Blue Swirl | { |
64 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
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65 | d3ffcafe | Blue Swirl | } |
66 | d3ffcafe | Blue Swirl | |
67 | d3ffcafe | Blue Swirl | static void tcx24_set_dirty(TCXState *s) |
68 | d3ffcafe | Blue Swirl | { |
69 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
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70 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
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71 | d3ffcafe | Blue Swirl | } |
72 | 95219897 | pbrook | |
73 | 21206a10 | bellard | static void update_palette_entries(TCXState *s, int start, int end) |
74 | 21206a10 | bellard | { |
75 | 21206a10 | bellard | int i;
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76 | 21206a10 | bellard | for(i = start; i < end; i++) {
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77 | 0e1f5a0c | aliguori | switch(ds_get_bits_per_pixel(s->ds)) {
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78 | 21206a10 | bellard | default:
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79 | 21206a10 | bellard | case 8: |
80 | 21206a10 | bellard | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
81 | 21206a10 | bellard | break;
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82 | 21206a10 | bellard | case 15: |
83 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
84 | 21206a10 | bellard | break;
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85 | 21206a10 | bellard | case 16: |
86 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
87 | 21206a10 | bellard | break;
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88 | 21206a10 | bellard | case 32: |
89 | 7b5d76da | aliguori | if (is_surface_bgr(s->ds->surface))
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90 | 7b5d76da | aliguori | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
91 | 7b5d76da | aliguori | else
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92 | 7b5d76da | aliguori | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
93 | 21206a10 | bellard | break;
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94 | 21206a10 | bellard | } |
95 | 21206a10 | bellard | } |
96 | d3ffcafe | Blue Swirl | if (s->depth == 24) { |
97 | d3ffcafe | Blue Swirl | tcx24_set_dirty(s); |
98 | d3ffcafe | Blue Swirl | } else {
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99 | d3ffcafe | Blue Swirl | tcx_set_dirty(s); |
100 | d3ffcafe | Blue Swirl | } |
101 | 21206a10 | bellard | } |
102 | 21206a10 | bellard | |
103 | 5fafdf24 | ths | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
104 | f930d07e | blueswir1 | const uint8_t *s, int width) |
105 | 420557e8 | bellard | { |
106 | e80cfcfc | bellard | int x;
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107 | e80cfcfc | bellard | uint8_t val; |
108 | 8bdc2159 | ths | uint32_t *p = (uint32_t *)d; |
109 | e80cfcfc | bellard | |
110 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
111 | f930d07e | blueswir1 | val = *s++; |
112 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
113 | e80cfcfc | bellard | } |
114 | 420557e8 | bellard | } |
115 | 420557e8 | bellard | |
116 | 5fafdf24 | ths | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
117 | f930d07e | blueswir1 | const uint8_t *s, int width) |
118 | e80cfcfc | bellard | { |
119 | e80cfcfc | bellard | int x;
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120 | e80cfcfc | bellard | uint8_t val; |
121 | 8bdc2159 | ths | uint16_t *p = (uint16_t *)d; |
122 | 8d5f07fa | bellard | |
123 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
124 | f930d07e | blueswir1 | val = *s++; |
125 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
126 | e80cfcfc | bellard | } |
127 | e80cfcfc | bellard | } |
128 | e80cfcfc | bellard | |
129 | 5fafdf24 | ths | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
130 | f930d07e | blueswir1 | const uint8_t *s, int width) |
131 | 420557e8 | bellard | { |
132 | e80cfcfc | bellard | int x;
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133 | e80cfcfc | bellard | uint8_t val; |
134 | e80cfcfc | bellard | |
135 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
136 | f930d07e | blueswir1 | val = *s++; |
137 | 21206a10 | bellard | *d++ = s1->palette[val]; |
138 | 420557e8 | bellard | } |
139 | 420557e8 | bellard | } |
140 | 420557e8 | bellard | |
141 | 688ea2eb | blueswir1 | /*
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142 | 688ea2eb | blueswir1 | XXX Could be much more optimal:
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143 | 688ea2eb | blueswir1 | * detect if line/page/whole screen is in 24 bit mode
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144 | 688ea2eb | blueswir1 | * if destination is also BGR, use memcpy
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145 | 688ea2eb | blueswir1 | */
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146 | eee0b836 | blueswir1 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
147 | eee0b836 | blueswir1 | const uint8_t *s, int width, |
148 | eee0b836 | blueswir1 | const uint32_t *cplane,
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149 | eee0b836 | blueswir1 | const uint32_t *s24)
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150 | eee0b836 | blueswir1 | { |
151 | 7b5d76da | aliguori | int x, bgr, r, g, b;
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152 | 688ea2eb | blueswir1 | uint8_t val, *p8; |
153 | eee0b836 | blueswir1 | uint32_t *p = (uint32_t *)d; |
154 | eee0b836 | blueswir1 | uint32_t dval; |
155 | eee0b836 | blueswir1 | |
156 | 7b5d76da | aliguori | bgr = is_surface_bgr(s1->ds->surface); |
157 | eee0b836 | blueswir1 | for(x = 0; x < width; x++, s++, s24++) { |
158 | 688ea2eb | blueswir1 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
159 | 688ea2eb | blueswir1 | // 24-bit direct, BGR order
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160 | 688ea2eb | blueswir1 | p8 = (uint8_t *)s24; |
161 | 688ea2eb | blueswir1 | p8++; |
162 | 688ea2eb | blueswir1 | b = *p8++; |
163 | 688ea2eb | blueswir1 | g = *p8++; |
164 | f7e683b8 | Blue Swirl | r = *p8; |
165 | 7b5d76da | aliguori | if (bgr)
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166 | 7b5d76da | aliguori | dval = rgb_to_pixel32bgr(r, g, b); |
167 | 7b5d76da | aliguori | else
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168 | 7b5d76da | aliguori | dval = rgb_to_pixel32(r, g, b); |
169 | eee0b836 | blueswir1 | } else {
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170 | eee0b836 | blueswir1 | val = *s; |
171 | eee0b836 | blueswir1 | dval = s1->palette[val]; |
172 | eee0b836 | blueswir1 | } |
173 | eee0b836 | blueswir1 | *p++ = dval; |
174 | eee0b836 | blueswir1 | } |
175 | eee0b836 | blueswir1 | } |
176 | eee0b836 | blueswir1 | |
177 | d08151bf | Avi Kivity | static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, |
178 | c227f099 | Anthony Liguori | ram_addr_t cpage) |
179 | eee0b836 | blueswir1 | { |
180 | eee0b836 | blueswir1 | int ret;
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181 | eee0b836 | blueswir1 | |
182 | cd7a45c9 | Blue Swirl | ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE, |
183 | cd7a45c9 | Blue Swirl | DIRTY_MEMORY_VGA); |
184 | cd7a45c9 | Blue Swirl | ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
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185 | cd7a45c9 | Blue Swirl | DIRTY_MEMORY_VGA); |
186 | cd7a45c9 | Blue Swirl | ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
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187 | cd7a45c9 | Blue Swirl | DIRTY_MEMORY_VGA); |
188 | eee0b836 | blueswir1 | return ret;
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189 | eee0b836 | blueswir1 | } |
190 | eee0b836 | blueswir1 | |
191 | c227f099 | Anthony Liguori | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
192 | c227f099 | Anthony Liguori | ram_addr_t page_max, ram_addr_t page24, |
193 | c227f099 | Anthony Liguori | ram_addr_t cpage) |
194 | eee0b836 | blueswir1 | { |
195 | d08151bf | Avi Kivity | memory_region_reset_dirty(&ts->vram_mem, |
196 | d08151bf | Avi Kivity | page_min, page_max + TARGET_PAGE_SIZE, |
197 | d08151bf | Avi Kivity | DIRTY_MEMORY_VGA); |
198 | d08151bf | Avi Kivity | memory_region_reset_dirty(&ts->vram_mem, |
199 | d08151bf | Avi Kivity | page24 + page_min * 4,
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200 | d08151bf | Avi Kivity | page24 + page_max * 4 + TARGET_PAGE_SIZE,
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201 | d08151bf | Avi Kivity | DIRTY_MEMORY_VGA); |
202 | d08151bf | Avi Kivity | memory_region_reset_dirty(&ts->vram_mem, |
203 | d08151bf | Avi Kivity | cpage + page_min * 4,
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204 | d08151bf | Avi Kivity | cpage + page_max * 4 + TARGET_PAGE_SIZE,
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205 | d08151bf | Avi Kivity | DIRTY_MEMORY_VGA); |
206 | eee0b836 | blueswir1 | } |
207 | eee0b836 | blueswir1 | |
208 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
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209 | e80cfcfc | bellard | VGA... */
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210 | 95219897 | pbrook | static void tcx_update_display(void *opaque) |
211 | 420557e8 | bellard | { |
212 | e80cfcfc | bellard | TCXState *ts = opaque; |
213 | c227f099 | Anthony Liguori | ram_addr_t page, page_min, page_max; |
214 | 550be127 | bellard | int y, y_start, dd, ds;
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215 | e80cfcfc | bellard | uint8_t *d, *s; |
216 | b3ceef24 | blueswir1 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
217 | e80cfcfc | bellard | |
218 | 0e1f5a0c | aliguori | if (ds_get_bits_per_pixel(ts->ds) == 0) |
219 | f930d07e | blueswir1 | return;
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220 | d08151bf | Avi Kivity | page = 0;
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221 | e80cfcfc | bellard | y_start = -1;
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222 | c0c440f3 | Blue Swirl | page_min = -1;
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223 | 550be127 | bellard | page_max = 0;
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224 | 0e1f5a0c | aliguori | d = ds_get_data(ts->ds); |
225 | 6f7e9aec | bellard | s = ts->vram; |
226 | 0e1f5a0c | aliguori | dd = ds_get_linesize(ts->ds); |
227 | e80cfcfc | bellard | ds = 1024;
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228 | e80cfcfc | bellard | |
229 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(ts->ds)) {
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230 | e80cfcfc | bellard | case 32: |
231 | f930d07e | blueswir1 | f = tcx_draw_line32; |
232 | f930d07e | blueswir1 | break;
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233 | 21206a10 | bellard | case 15: |
234 | 21206a10 | bellard | case 16: |
235 | f930d07e | blueswir1 | f = tcx_draw_line16; |
236 | f930d07e | blueswir1 | break;
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237 | e80cfcfc | bellard | default:
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238 | e80cfcfc | bellard | case 8: |
239 | f930d07e | blueswir1 | f = tcx_draw_line8; |
240 | f930d07e | blueswir1 | break;
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241 | e80cfcfc | bellard | case 0: |
242 | f930d07e | blueswir1 | return;
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243 | e80cfcfc | bellard | } |
244 | 3b46e624 | ths | |
245 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
246 | cd7a45c9 | Blue Swirl | if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
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247 | cd7a45c9 | Blue Swirl | DIRTY_MEMORY_VGA)) { |
248 | f930d07e | blueswir1 | if (y_start < 0) |
249 | e80cfcfc | bellard | y_start = y; |
250 | e80cfcfc | bellard | if (page < page_min)
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251 | e80cfcfc | bellard | page_min = page; |
252 | e80cfcfc | bellard | if (page > page_max)
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253 | e80cfcfc | bellard | page_max = page; |
254 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
255 | f930d07e | blueswir1 | d += dd; |
256 | f930d07e | blueswir1 | s += ds; |
257 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
258 | f930d07e | blueswir1 | d += dd; |
259 | f930d07e | blueswir1 | s += ds; |
260 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
261 | f930d07e | blueswir1 | d += dd; |
262 | f930d07e | blueswir1 | s += ds; |
263 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
264 | f930d07e | blueswir1 | d += dd; |
265 | f930d07e | blueswir1 | s += ds; |
266 | f930d07e | blueswir1 | } else {
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267 | e80cfcfc | bellard | if (y_start >= 0) { |
268 | e80cfcfc | bellard | /* flush to display */
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269 | 5fafdf24 | ths | dpy_update(ts->ds, 0, y_start,
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270 | 6f7e9aec | bellard | ts->width, y - y_start); |
271 | e80cfcfc | bellard | y_start = -1;
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272 | e80cfcfc | bellard | } |
273 | f930d07e | blueswir1 | d += dd * 4;
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274 | f930d07e | blueswir1 | s += ds * 4;
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275 | f930d07e | blueswir1 | } |
276 | e80cfcfc | bellard | } |
277 | e80cfcfc | bellard | if (y_start >= 0) { |
278 | f930d07e | blueswir1 | /* flush to display */
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279 | f930d07e | blueswir1 | dpy_update(ts->ds, 0, y_start,
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280 | f930d07e | blueswir1 | ts->width, y - y_start); |
281 | e80cfcfc | bellard | } |
282 | e80cfcfc | bellard | /* reset modified pages */
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283 | c0c440f3 | Blue Swirl | if (page_max >= page_min) {
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284 | d08151bf | Avi Kivity | memory_region_reset_dirty(&ts->vram_mem, |
285 | d08151bf | Avi Kivity | page_min, page_max + TARGET_PAGE_SIZE, |
286 | d08151bf | Avi Kivity | DIRTY_MEMORY_VGA); |
287 | e80cfcfc | bellard | } |
288 | 420557e8 | bellard | } |
289 | 420557e8 | bellard | |
290 | eee0b836 | blueswir1 | static void tcx24_update_display(void *opaque) |
291 | eee0b836 | blueswir1 | { |
292 | eee0b836 | blueswir1 | TCXState *ts = opaque; |
293 | c227f099 | Anthony Liguori | ram_addr_t page, page_min, page_max, cpage, page24; |
294 | eee0b836 | blueswir1 | int y, y_start, dd, ds;
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295 | eee0b836 | blueswir1 | uint8_t *d, *s; |
296 | eee0b836 | blueswir1 | uint32_t *cptr, *s24; |
297 | eee0b836 | blueswir1 | |
298 | 0e1f5a0c | aliguori | if (ds_get_bits_per_pixel(ts->ds) != 32) |
299 | eee0b836 | blueswir1 | return;
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300 | d08151bf | Avi Kivity | page = 0;
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301 | eee0b836 | blueswir1 | page24 = ts->vram24_offset; |
302 | eee0b836 | blueswir1 | cpage = ts->cplane_offset; |
303 | eee0b836 | blueswir1 | y_start = -1;
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304 | c0c440f3 | Blue Swirl | page_min = -1;
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305 | eee0b836 | blueswir1 | page_max = 0;
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306 | 0e1f5a0c | aliguori | d = ds_get_data(ts->ds); |
307 | eee0b836 | blueswir1 | s = ts->vram; |
308 | eee0b836 | blueswir1 | s24 = ts->vram24; |
309 | eee0b836 | blueswir1 | cptr = ts->cplane; |
310 | 0e1f5a0c | aliguori | dd = ds_get_linesize(ts->ds); |
311 | eee0b836 | blueswir1 | ds = 1024;
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312 | eee0b836 | blueswir1 | |
313 | eee0b836 | blueswir1 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
314 | eee0b836 | blueswir1 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
315 | d08151bf | Avi Kivity | if (check_dirty(ts, page, page24, cpage)) {
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316 | eee0b836 | blueswir1 | if (y_start < 0) |
317 | eee0b836 | blueswir1 | y_start = y; |
318 | eee0b836 | blueswir1 | if (page < page_min)
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319 | eee0b836 | blueswir1 | page_min = page; |
320 | eee0b836 | blueswir1 | if (page > page_max)
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321 | eee0b836 | blueswir1 | page_max = page; |
322 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
323 | eee0b836 | blueswir1 | d += dd; |
324 | eee0b836 | blueswir1 | s += ds; |
325 | eee0b836 | blueswir1 | cptr += ds; |
326 | eee0b836 | blueswir1 | s24 += ds; |
327 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
328 | eee0b836 | blueswir1 | d += dd; |
329 | eee0b836 | blueswir1 | s += ds; |
330 | eee0b836 | blueswir1 | cptr += ds; |
331 | eee0b836 | blueswir1 | s24 += ds; |
332 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
333 | eee0b836 | blueswir1 | d += dd; |
334 | eee0b836 | blueswir1 | s += ds; |
335 | eee0b836 | blueswir1 | cptr += ds; |
336 | eee0b836 | blueswir1 | s24 += ds; |
337 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
338 | eee0b836 | blueswir1 | d += dd; |
339 | eee0b836 | blueswir1 | s += ds; |
340 | eee0b836 | blueswir1 | cptr += ds; |
341 | eee0b836 | blueswir1 | s24 += ds; |
342 | eee0b836 | blueswir1 | } else {
|
343 | eee0b836 | blueswir1 | if (y_start >= 0) { |
344 | eee0b836 | blueswir1 | /* flush to display */
|
345 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
346 | eee0b836 | blueswir1 | ts->width, y - y_start); |
347 | eee0b836 | blueswir1 | y_start = -1;
|
348 | eee0b836 | blueswir1 | } |
349 | eee0b836 | blueswir1 | d += dd * 4;
|
350 | eee0b836 | blueswir1 | s += ds * 4;
|
351 | eee0b836 | blueswir1 | cptr += ds * 4;
|
352 | eee0b836 | blueswir1 | s24 += ds * 4;
|
353 | eee0b836 | blueswir1 | } |
354 | eee0b836 | blueswir1 | } |
355 | eee0b836 | blueswir1 | if (y_start >= 0) { |
356 | eee0b836 | blueswir1 | /* flush to display */
|
357 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
358 | eee0b836 | blueswir1 | ts->width, y - y_start); |
359 | eee0b836 | blueswir1 | } |
360 | eee0b836 | blueswir1 | /* reset modified pages */
|
361 | c0c440f3 | Blue Swirl | if (page_max >= page_min) {
|
362 | eee0b836 | blueswir1 | reset_dirty(ts, page_min, page_max, page24, cpage); |
363 | eee0b836 | blueswir1 | } |
364 | eee0b836 | blueswir1 | } |
365 | eee0b836 | blueswir1 | |
366 | 95219897 | pbrook | static void tcx_invalidate_display(void *opaque) |
367 | 420557e8 | bellard | { |
368 | e80cfcfc | bellard | TCXState *s = opaque; |
369 | e80cfcfc | bellard | |
370 | d3ffcafe | Blue Swirl | tcx_set_dirty(s); |
371 | d3ffcafe | Blue Swirl | qemu_console_resize(s->ds, s->width, s->height); |
372 | 420557e8 | bellard | } |
373 | 420557e8 | bellard | |
374 | eee0b836 | blueswir1 | static void tcx24_invalidate_display(void *opaque) |
375 | eee0b836 | blueswir1 | { |
376 | eee0b836 | blueswir1 | TCXState *s = opaque; |
377 | eee0b836 | blueswir1 | |
378 | d3ffcafe | Blue Swirl | tcx_set_dirty(s); |
379 | d3ffcafe | Blue Swirl | tcx24_set_dirty(s); |
380 | d3ffcafe | Blue Swirl | qemu_console_resize(s->ds, s->width, s->height); |
381 | eee0b836 | blueswir1 | } |
382 | eee0b836 | blueswir1 | |
383 | e59fb374 | Juan Quintela | static int vmstate_tcx_post_load(void *opaque, int version_id) |
384 | 420557e8 | bellard | { |
385 | 420557e8 | bellard | TCXState *s = opaque; |
386 | 3b46e624 | ths | |
387 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
388 | d3ffcafe | Blue Swirl | if (s->depth == 24) { |
389 | d3ffcafe | Blue Swirl | tcx24_set_dirty(s); |
390 | d3ffcafe | Blue Swirl | } else {
|
391 | d3ffcafe | Blue Swirl | tcx_set_dirty(s); |
392 | d3ffcafe | Blue Swirl | } |
393 | 5425a216 | blueswir1 | |
394 | e80cfcfc | bellard | return 0; |
395 | 420557e8 | bellard | } |
396 | 420557e8 | bellard | |
397 | c0c41a4b | Blue Swirl | static const VMStateDescription vmstate_tcx = { |
398 | c0c41a4b | Blue Swirl | .name ="tcx",
|
399 | c0c41a4b | Blue Swirl | .version_id = 4,
|
400 | c0c41a4b | Blue Swirl | .minimum_version_id = 4,
|
401 | c0c41a4b | Blue Swirl | .minimum_version_id_old = 4,
|
402 | 752ff2fa | Juan Quintela | .post_load = vmstate_tcx_post_load, |
403 | c0c41a4b | Blue Swirl | .fields = (VMStateField []) { |
404 | c0c41a4b | Blue Swirl | VMSTATE_UINT16(height, TCXState), |
405 | c0c41a4b | Blue Swirl | VMSTATE_UINT16(width, TCXState), |
406 | c0c41a4b | Blue Swirl | VMSTATE_UINT16(depth, TCXState), |
407 | c0c41a4b | Blue Swirl | VMSTATE_BUFFER(r, TCXState), |
408 | c0c41a4b | Blue Swirl | VMSTATE_BUFFER(g, TCXState), |
409 | c0c41a4b | Blue Swirl | VMSTATE_BUFFER(b, TCXState), |
410 | c0c41a4b | Blue Swirl | VMSTATE_UINT8(dac_index, TCXState), |
411 | c0c41a4b | Blue Swirl | VMSTATE_UINT8(dac_state, TCXState), |
412 | c0c41a4b | Blue Swirl | VMSTATE_END_OF_LIST() |
413 | c0c41a4b | Blue Swirl | } |
414 | c0c41a4b | Blue Swirl | }; |
415 | c0c41a4b | Blue Swirl | |
416 | 7f23f812 | Michael S. Tsirkin | static void tcx_reset(DeviceState *d) |
417 | 420557e8 | bellard | { |
418 | 7f23f812 | Michael S. Tsirkin | TCXState *s = container_of(d, TCXState, busdev.qdev); |
419 | e80cfcfc | bellard | |
420 | e80cfcfc | bellard | /* Initialize palette */
|
421 | e80cfcfc | bellard | memset(s->r, 0, 256); |
422 | e80cfcfc | bellard | memset(s->g, 0, 256); |
423 | e80cfcfc | bellard | memset(s->b, 0, 256); |
424 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
425 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
426 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
|
427 | d08151bf | Avi Kivity | memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), |
428 | d08151bf | Avi Kivity | DIRTY_MEMORY_VGA); |
429 | 6f7e9aec | bellard | s->dac_index = 0;
|
430 | 6f7e9aec | bellard | s->dac_state = 0;
|
431 | 6f7e9aec | bellard | } |
432 | 6f7e9aec | bellard | |
433 | d08151bf | Avi Kivity | static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr, |
434 | d08151bf | Avi Kivity | unsigned size)
|
435 | 6f7e9aec | bellard | { |
436 | 6f7e9aec | bellard | return 0; |
437 | 6f7e9aec | bellard | } |
438 | 6f7e9aec | bellard | |
439 | d08151bf | Avi Kivity | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val, |
440 | d08151bf | Avi Kivity | unsigned size)
|
441 | 6f7e9aec | bellard | { |
442 | 6f7e9aec | bellard | TCXState *s = opaque; |
443 | 6f7e9aec | bellard | |
444 | e64d7d59 | blueswir1 | switch (addr) {
|
445 | 6f7e9aec | bellard | case 0: |
446 | f930d07e | blueswir1 | s->dac_index = val >> 24;
|
447 | f930d07e | blueswir1 | s->dac_state = 0;
|
448 | f930d07e | blueswir1 | break;
|
449 | e64d7d59 | blueswir1 | case 4: |
450 | f930d07e | blueswir1 | switch (s->dac_state) {
|
451 | f930d07e | blueswir1 | case 0: |
452 | f930d07e | blueswir1 | s->r[s->dac_index] = val >> 24;
|
453 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
454 | f930d07e | blueswir1 | s->dac_state++; |
455 | f930d07e | blueswir1 | break;
|
456 | f930d07e | blueswir1 | case 1: |
457 | f930d07e | blueswir1 | s->g[s->dac_index] = val >> 24;
|
458 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
459 | f930d07e | blueswir1 | s->dac_state++; |
460 | f930d07e | blueswir1 | break;
|
461 | f930d07e | blueswir1 | case 2: |
462 | f930d07e | blueswir1 | s->b[s->dac_index] = val >> 24;
|
463 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
464 | 5c8cdbf8 | blueswir1 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
465 | f930d07e | blueswir1 | default:
|
466 | f930d07e | blueswir1 | s->dac_state = 0;
|
467 | f930d07e | blueswir1 | break;
|
468 | f930d07e | blueswir1 | } |
469 | f930d07e | blueswir1 | break;
|
470 | 6f7e9aec | bellard | default:
|
471 | f930d07e | blueswir1 | break;
|
472 | 6f7e9aec | bellard | } |
473 | 6f7e9aec | bellard | return;
|
474 | 420557e8 | bellard | } |
475 | 420557e8 | bellard | |
476 | d08151bf | Avi Kivity | static const MemoryRegionOps tcx_dac_ops = { |
477 | d08151bf | Avi Kivity | .read = tcx_dac_readl, |
478 | d08151bf | Avi Kivity | .write = tcx_dac_writel, |
479 | d08151bf | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
480 | d08151bf | Avi Kivity | .valid = { |
481 | d08151bf | Avi Kivity | .min_access_size = 4,
|
482 | d08151bf | Avi Kivity | .max_access_size = 4,
|
483 | d08151bf | Avi Kivity | }, |
484 | 6f7e9aec | bellard | }; |
485 | 6f7e9aec | bellard | |
486 | d08151bf | Avi Kivity | static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr, |
487 | d08151bf | Avi Kivity | unsigned size)
|
488 | 8508b89e | blueswir1 | { |
489 | 8508b89e | blueswir1 | return 0; |
490 | 8508b89e | blueswir1 | } |
491 | 8508b89e | blueswir1 | |
492 | d08151bf | Avi Kivity | static void dummy_writel(void *opaque, target_phys_addr_t addr, |
493 | d08151bf | Avi Kivity | uint64_t val, unsigned size)
|
494 | 8508b89e | blueswir1 | { |
495 | 8508b89e | blueswir1 | } |
496 | 8508b89e | blueswir1 | |
497 | d08151bf | Avi Kivity | static const MemoryRegionOps dummy_ops = { |
498 | d08151bf | Avi Kivity | .read = dummy_readl, |
499 | d08151bf | Avi Kivity | .write = dummy_writel, |
500 | d08151bf | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
501 | d08151bf | Avi Kivity | .valid = { |
502 | d08151bf | Avi Kivity | .min_access_size = 4,
|
503 | d08151bf | Avi Kivity | .max_access_size = 4,
|
504 | d08151bf | Avi Kivity | }, |
505 | 8508b89e | blueswir1 | }; |
506 | 8508b89e | blueswir1 | |
507 | 81a322d4 | Gerd Hoffmann | static int tcx_init1(SysBusDevice *dev) |
508 | f40070c3 | Blue Swirl | { |
509 | f40070c3 | Blue Swirl | TCXState *s = FROM_SYSBUS(TCXState, dev); |
510 | d08151bf | Avi Kivity | ram_addr_t vram_offset = 0;
|
511 | ee6847d1 | Gerd Hoffmann | int size;
|
512 | dc828ca1 | pbrook | uint8_t *vram_base; |
513 | dc828ca1 | pbrook | |
514 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->vram_mem, "tcx.vram",
|
515 | d08151bf | Avi Kivity | s->vram_size * (1 + 4 + 4)); |
516 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->vram_mem); |
517 | d08151bf | Avi Kivity | vram_base = memory_region_get_ram_ptr(&s->vram_mem); |
518 | eee0b836 | blueswir1 | |
519 | f40070c3 | Blue Swirl | /* 8-bit plane */
|
520 | eee0b836 | blueswir1 | s->vram = vram_base; |
521 | ee6847d1 | Gerd Hoffmann | size = s->vram_size; |
522 | d08151bf | Avi Kivity | memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
|
523 | d08151bf | Avi Kivity | &s->vram_mem, vram_offset, size); |
524 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->vram_8bit); |
525 | eee0b836 | blueswir1 | vram_offset += size; |
526 | eee0b836 | blueswir1 | vram_base += size; |
527 | e80cfcfc | bellard | |
528 | f40070c3 | Blue Swirl | /* DAC */
|
529 | d08151bf | Avi Kivity | memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
|
530 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->dac); |
531 | eee0b836 | blueswir1 | |
532 | f40070c3 | Blue Swirl | /* TEC (dummy) */
|
533 | d08151bf | Avi Kivity | memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
|
534 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->tec); |
535 | f40070c3 | Blue Swirl | /* THC: NetBSD writes here even with 8-bit display: dummy */
|
536 | d08151bf | Avi Kivity | memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
|
537 | d08151bf | Avi Kivity | TCX_THC_NREGS_24); |
538 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->thc24); |
539 | f40070c3 | Blue Swirl | |
540 | f40070c3 | Blue Swirl | if (s->depth == 24) { |
541 | f40070c3 | Blue Swirl | /* 24-bit plane */
|
542 | ee6847d1 | Gerd Hoffmann | size = s->vram_size * 4;
|
543 | eee0b836 | blueswir1 | s->vram24 = (uint32_t *)vram_base; |
544 | eee0b836 | blueswir1 | s->vram24_offset = vram_offset; |
545 | d08151bf | Avi Kivity | memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
|
546 | d08151bf | Avi Kivity | &s->vram_mem, vram_offset, size); |
547 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->vram_24bit); |
548 | eee0b836 | blueswir1 | vram_offset += size; |
549 | eee0b836 | blueswir1 | vram_base += size; |
550 | eee0b836 | blueswir1 | |
551 | f40070c3 | Blue Swirl | /* Control plane */
|
552 | ee6847d1 | Gerd Hoffmann | size = s->vram_size * 4;
|
553 | eee0b836 | blueswir1 | s->cplane = (uint32_t *)vram_base; |
554 | eee0b836 | blueswir1 | s->cplane_offset = vram_offset; |
555 | d08151bf | Avi Kivity | memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
|
556 | d08151bf | Avi Kivity | &s->vram_mem, vram_offset, size); |
557 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->vram_cplane); |
558 | f40070c3 | Blue Swirl | |
559 | 3023f332 | aliguori | s->ds = graphic_console_init(tcx24_update_display, |
560 | 3023f332 | aliguori | tcx24_invalidate_display, |
561 | 3023f332 | aliguori | tcx24_screen_dump, NULL, s);
|
562 | eee0b836 | blueswir1 | } else {
|
563 | f40070c3 | Blue Swirl | /* THC 8 bit (dummy) */
|
564 | d08151bf | Avi Kivity | memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
|
565 | d08151bf | Avi Kivity | TCX_THC_NREGS_8); |
566 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->thc8); |
567 | f40070c3 | Blue Swirl | |
568 | 3023f332 | aliguori | s->ds = graphic_console_init(tcx_update_display, |
569 | 3023f332 | aliguori | tcx_invalidate_display, |
570 | 3023f332 | aliguori | tcx_screen_dump, NULL, s);
|
571 | eee0b836 | blueswir1 | } |
572 | e80cfcfc | bellard | |
573 | f40070c3 | Blue Swirl | qemu_console_resize(s->ds, s->width, s->height); |
574 | 81a322d4 | Gerd Hoffmann | return 0; |
575 | 420557e8 | bellard | } |
576 | 420557e8 | bellard | |
577 | 45efb161 | Gerd Hoffmann | static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch) |
578 | 8d5f07fa | bellard | { |
579 | e80cfcfc | bellard | TCXState *s = opaque; |
580 | 8d5f07fa | bellard | FILE *f; |
581 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
582 | 8d5f07fa | bellard | int y, x;
|
583 | 8d5f07fa | bellard | |
584 | 8d5f07fa | bellard | f = fopen(filename, "wb");
|
585 | 8d5f07fa | bellard | if (!f)
|
586 | e80cfcfc | bellard | return;
|
587 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
588 | 6f7e9aec | bellard | d1 = s->vram; |
589 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
590 | 8d5f07fa | bellard | d = d1; |
591 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
592 | 8d5f07fa | bellard | v = *d; |
593 | e80cfcfc | bellard | fputc(s->r[v], f); |
594 | e80cfcfc | bellard | fputc(s->g[v], f); |
595 | e80cfcfc | bellard | fputc(s->b[v], f); |
596 | 8d5f07fa | bellard | d++; |
597 | 8d5f07fa | bellard | } |
598 | e80cfcfc | bellard | d1 += MAXX; |
599 | 8d5f07fa | bellard | } |
600 | 8d5f07fa | bellard | fclose(f); |
601 | 8d5f07fa | bellard | return;
|
602 | 8d5f07fa | bellard | } |
603 | 8d5f07fa | bellard | |
604 | 45efb161 | Gerd Hoffmann | static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch) |
605 | eee0b836 | blueswir1 | { |
606 | eee0b836 | blueswir1 | TCXState *s = opaque; |
607 | eee0b836 | blueswir1 | FILE *f; |
608 | eee0b836 | blueswir1 | uint8_t *d, *d1, v; |
609 | eee0b836 | blueswir1 | uint32_t *s24, *cptr, dval; |
610 | eee0b836 | blueswir1 | int y, x;
|
611 | 8d5f07fa | bellard | |
612 | eee0b836 | blueswir1 | f = fopen(filename, "wb");
|
613 | eee0b836 | blueswir1 | if (!f)
|
614 | eee0b836 | blueswir1 | return;
|
615 | eee0b836 | blueswir1 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
616 | eee0b836 | blueswir1 | d1 = s->vram; |
617 | eee0b836 | blueswir1 | s24 = s->vram24; |
618 | eee0b836 | blueswir1 | cptr = s->cplane; |
619 | eee0b836 | blueswir1 | for(y = 0; y < s->height; y++) { |
620 | eee0b836 | blueswir1 | d = d1; |
621 | eee0b836 | blueswir1 | for(x = 0; x < s->width; x++, d++, s24++) { |
622 | eee0b836 | blueswir1 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
623 | eee0b836 | blueswir1 | dval = *s24 & 0x00ffffff;
|
624 | eee0b836 | blueswir1 | fputc((dval >> 16) & 0xff, f); |
625 | eee0b836 | blueswir1 | fputc((dval >> 8) & 0xff, f); |
626 | eee0b836 | blueswir1 | fputc(dval & 0xff, f);
|
627 | eee0b836 | blueswir1 | } else {
|
628 | eee0b836 | blueswir1 | v = *d; |
629 | eee0b836 | blueswir1 | fputc(s->r[v], f); |
630 | eee0b836 | blueswir1 | fputc(s->g[v], f); |
631 | eee0b836 | blueswir1 | fputc(s->b[v], f); |
632 | eee0b836 | blueswir1 | } |
633 | eee0b836 | blueswir1 | } |
634 | eee0b836 | blueswir1 | d1 += MAXX; |
635 | eee0b836 | blueswir1 | } |
636 | eee0b836 | blueswir1 | fclose(f); |
637 | eee0b836 | blueswir1 | return;
|
638 | eee0b836 | blueswir1 | } |
639 | f40070c3 | Blue Swirl | |
640 | 999e12bb | Anthony Liguori | static Property tcx_properties[] = {
|
641 | 999e12bb | Anthony Liguori | DEFINE_PROP_TADDR("addr", TCXState, addr, -1), |
642 | 999e12bb | Anthony Liguori | DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), |
643 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT16("width", TCXState, width, -1), |
644 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT16("height", TCXState, height, -1), |
645 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT16("depth", TCXState, depth, -1), |
646 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
647 | 999e12bb | Anthony Liguori | }; |
648 | 999e12bb | Anthony Liguori | |
649 | 999e12bb | Anthony Liguori | static void tcx_class_init(ObjectClass *klass, void *data) |
650 | 999e12bb | Anthony Liguori | { |
651 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
652 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
653 | 999e12bb | Anthony Liguori | |
654 | 999e12bb | Anthony Liguori | k->init = tcx_init1; |
655 | 39bffca2 | Anthony Liguori | dc->reset = tcx_reset; |
656 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_tcx; |
657 | 39bffca2 | Anthony Liguori | dc->props = tcx_properties; |
658 | 999e12bb | Anthony Liguori | } |
659 | 999e12bb | Anthony Liguori | |
660 | 39bffca2 | Anthony Liguori | static TypeInfo tcx_info = {
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661 | 39bffca2 | Anthony Liguori | .name = "SUNW,tcx",
|
662 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
663 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(TCXState),
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664 | 39bffca2 | Anthony Liguori | .class_init = tcx_class_init, |
665 | ee6847d1 | Gerd Hoffmann | }; |
666 | ee6847d1 | Gerd Hoffmann | |
667 | 83f7d43a | Andreas Färber | static void tcx_register_types(void) |
668 | f40070c3 | Blue Swirl | { |
669 | 39bffca2 | Anthony Liguori | type_register_static(&tcx_info); |
670 | f40070c3 | Blue Swirl | } |
671 | f40070c3 | Blue Swirl | |
672 | 83f7d43a | Andreas Färber | type_init(tcx_register_types) |