root / hw / arm_timer.c @ 37952117
History | View | Annotate | Download (10.3 kB)
1 |
/*
|
---|---|
2 |
* ARM PrimeCell Timer modules.
|
3 |
*
|
4 |
* Copyright (c) 2005-2006 CodeSourcery.
|
5 |
* Written by Paul Brook
|
6 |
*
|
7 |
* This code is licensed under the GPL.
|
8 |
*/
|
9 |
|
10 |
#include "sysbus.h" |
11 |
#include "qemu-timer.h" |
12 |
#include "qemu-common.h" |
13 |
#include "qdev.h" |
14 |
#include "ptimer.h" |
15 |
|
16 |
/* Common timer implementation. */
|
17 |
|
18 |
#define TIMER_CTRL_ONESHOT (1 << 0) |
19 |
#define TIMER_CTRL_32BIT (1 << 1) |
20 |
#define TIMER_CTRL_DIV1 (0 << 2) |
21 |
#define TIMER_CTRL_DIV16 (1 << 2) |
22 |
#define TIMER_CTRL_DIV256 (2 << 2) |
23 |
#define TIMER_CTRL_IE (1 << 5) |
24 |
#define TIMER_CTRL_PERIODIC (1 << 6) |
25 |
#define TIMER_CTRL_ENABLE (1 << 7) |
26 |
|
27 |
typedef struct { |
28 |
ptimer_state *timer; |
29 |
uint32_t control; |
30 |
uint32_t limit; |
31 |
int freq;
|
32 |
int int_level;
|
33 |
qemu_irq irq; |
34 |
} arm_timer_state; |
35 |
|
36 |
/* Check all active timers, and schedule the next timer interrupt. */
|
37 |
|
38 |
static void arm_timer_update(arm_timer_state *s) |
39 |
{ |
40 |
/* Update interrupts. */
|
41 |
if (s->int_level && (s->control & TIMER_CTRL_IE)) {
|
42 |
qemu_irq_raise(s->irq); |
43 |
} else {
|
44 |
qemu_irq_lower(s->irq); |
45 |
} |
46 |
} |
47 |
|
48 |
static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset) |
49 |
{ |
50 |
arm_timer_state *s = (arm_timer_state *)opaque; |
51 |
|
52 |
switch (offset >> 2) { |
53 |
case 0: /* TimerLoad */ |
54 |
case 6: /* TimerBGLoad */ |
55 |
return s->limit;
|
56 |
case 1: /* TimerValue */ |
57 |
return ptimer_get_count(s->timer);
|
58 |
case 2: /* TimerControl */ |
59 |
return s->control;
|
60 |
case 4: /* TimerRIS */ |
61 |
return s->int_level;
|
62 |
case 5: /* TimerMIS */ |
63 |
if ((s->control & TIMER_CTRL_IE) == 0) |
64 |
return 0; |
65 |
return s->int_level;
|
66 |
default:
|
67 |
hw_error("%s: Bad offset %x\n", __func__, (int)offset); |
68 |
return 0; |
69 |
} |
70 |
} |
71 |
|
72 |
/* Reset the timer limit after settings have changed. */
|
73 |
static void arm_timer_recalibrate(arm_timer_state *s, int reload) |
74 |
{ |
75 |
uint32_t limit; |
76 |
|
77 |
if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
78 |
/* Free running. */
|
79 |
if (s->control & TIMER_CTRL_32BIT)
|
80 |
limit = 0xffffffff;
|
81 |
else
|
82 |
limit = 0xffff;
|
83 |
} else {
|
84 |
/* Periodic. */
|
85 |
limit = s->limit; |
86 |
} |
87 |
ptimer_set_limit(s->timer, limit, reload); |
88 |
} |
89 |
|
90 |
static void arm_timer_write(void *opaque, target_phys_addr_t offset, |
91 |
uint32_t value) |
92 |
{ |
93 |
arm_timer_state *s = (arm_timer_state *)opaque; |
94 |
int freq;
|
95 |
|
96 |
switch (offset >> 2) { |
97 |
case 0: /* TimerLoad */ |
98 |
s->limit = value; |
99 |
arm_timer_recalibrate(s, 1);
|
100 |
break;
|
101 |
case 1: /* TimerValue */ |
102 |
/* ??? Linux seems to want to write to this readonly register.
|
103 |
Ignore it. */
|
104 |
break;
|
105 |
case 2: /* TimerControl */ |
106 |
if (s->control & TIMER_CTRL_ENABLE) {
|
107 |
/* Pause the timer if it is running. This may cause some
|
108 |
inaccuracy dure to rounding, but avoids a whole lot of other
|
109 |
messyness. */
|
110 |
ptimer_stop(s->timer); |
111 |
} |
112 |
s->control = value; |
113 |
freq = s->freq; |
114 |
/* ??? Need to recalculate expiry time after changing divisor. */
|
115 |
switch ((value >> 2) & 3) { |
116 |
case 1: freq >>= 4; break; |
117 |
case 2: freq >>= 8; break; |
118 |
} |
119 |
arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
120 |
ptimer_set_freq(s->timer, freq); |
121 |
if (s->control & TIMER_CTRL_ENABLE) {
|
122 |
/* Restart the timer if still enabled. */
|
123 |
ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
|
124 |
} |
125 |
break;
|
126 |
case 3: /* TimerIntClr */ |
127 |
s->int_level = 0;
|
128 |
break;
|
129 |
case 6: /* TimerBGLoad */ |
130 |
s->limit = value; |
131 |
arm_timer_recalibrate(s, 0);
|
132 |
break;
|
133 |
default:
|
134 |
hw_error("%s: Bad offset %x\n", __func__, (int)offset); |
135 |
} |
136 |
arm_timer_update(s); |
137 |
} |
138 |
|
139 |
static void arm_timer_tick(void *opaque) |
140 |
{ |
141 |
arm_timer_state *s = (arm_timer_state *)opaque; |
142 |
s->int_level = 1;
|
143 |
arm_timer_update(s); |
144 |
} |
145 |
|
146 |
static const VMStateDescription vmstate_arm_timer = { |
147 |
.name = "arm_timer",
|
148 |
.version_id = 1,
|
149 |
.minimum_version_id = 1,
|
150 |
.minimum_version_id_old = 1,
|
151 |
.fields = (VMStateField[]) { |
152 |
VMSTATE_UINT32(control, arm_timer_state), |
153 |
VMSTATE_UINT32(limit, arm_timer_state), |
154 |
VMSTATE_INT32(int_level, arm_timer_state), |
155 |
VMSTATE_PTIMER(timer, arm_timer_state), |
156 |
VMSTATE_END_OF_LIST() |
157 |
} |
158 |
}; |
159 |
|
160 |
static arm_timer_state *arm_timer_init(uint32_t freq)
|
161 |
{ |
162 |
arm_timer_state *s; |
163 |
QEMUBH *bh; |
164 |
|
165 |
s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
|
166 |
s->freq = freq; |
167 |
s->control = TIMER_CTRL_IE; |
168 |
|
169 |
bh = qemu_bh_new(arm_timer_tick, s); |
170 |
s->timer = ptimer_init(bh); |
171 |
vmstate_register(NULL, -1, &vmstate_arm_timer, s); |
172 |
return s;
|
173 |
} |
174 |
|
175 |
/* ARM PrimeCell SP804 dual timer module.
|
176 |
* Docs at
|
177 |
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
|
178 |
*/
|
179 |
|
180 |
typedef struct { |
181 |
SysBusDevice busdev; |
182 |
MemoryRegion iomem; |
183 |
arm_timer_state *timer[2];
|
184 |
uint32_t freq0, freq1; |
185 |
int level[2]; |
186 |
qemu_irq irq; |
187 |
} sp804_state; |
188 |
|
189 |
static const uint8_t sp804_ids[] = { |
190 |
/* Timer ID */
|
191 |
0x04, 0x18, 0x14, 0, |
192 |
/* PrimeCell ID */
|
193 |
0xd, 0xf0, 0x05, 0xb1 |
194 |
}; |
195 |
|
196 |
/* Merge the IRQs from the two component devices. */
|
197 |
static void sp804_set_irq(void *opaque, int irq, int level) |
198 |
{ |
199 |
sp804_state *s = (sp804_state *)opaque; |
200 |
|
201 |
s->level[irq] = level; |
202 |
qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
203 |
} |
204 |
|
205 |
static uint64_t sp804_read(void *opaque, target_phys_addr_t offset, |
206 |
unsigned size)
|
207 |
{ |
208 |
sp804_state *s = (sp804_state *)opaque; |
209 |
|
210 |
if (offset < 0x20) { |
211 |
return arm_timer_read(s->timer[0], offset); |
212 |
} |
213 |
if (offset < 0x40) { |
214 |
return arm_timer_read(s->timer[1], offset - 0x20); |
215 |
} |
216 |
|
217 |
/* TimerPeriphID */
|
218 |
if (offset >= 0xfe0 && offset <= 0xffc) { |
219 |
return sp804_ids[(offset - 0xfe0) >> 2]; |
220 |
} |
221 |
|
222 |
switch (offset) {
|
223 |
/* Integration Test control registers, which we won't support */
|
224 |
case 0xf00: /* TimerITCR */ |
225 |
case 0xf04: /* TimerITOP (strictly write only but..) */ |
226 |
return 0; |
227 |
} |
228 |
|
229 |
hw_error("%s: Bad offset %x\n", __func__, (int)offset); |
230 |
return 0; |
231 |
} |
232 |
|
233 |
static void sp804_write(void *opaque, target_phys_addr_t offset, |
234 |
uint64_t value, unsigned size)
|
235 |
{ |
236 |
sp804_state *s = (sp804_state *)opaque; |
237 |
|
238 |
if (offset < 0x20) { |
239 |
arm_timer_write(s->timer[0], offset, value);
|
240 |
return;
|
241 |
} |
242 |
|
243 |
if (offset < 0x40) { |
244 |
arm_timer_write(s->timer[1], offset - 0x20, value); |
245 |
return;
|
246 |
} |
247 |
|
248 |
/* Technically we could be writing to the Test Registers, but not likely */
|
249 |
hw_error("%s: Bad offset %x\n", __func__, (int)offset); |
250 |
} |
251 |
|
252 |
static const MemoryRegionOps sp804_ops = { |
253 |
.read = sp804_read, |
254 |
.write = sp804_write, |
255 |
.endianness = DEVICE_NATIVE_ENDIAN, |
256 |
}; |
257 |
|
258 |
static const VMStateDescription vmstate_sp804 = { |
259 |
.name = "sp804",
|
260 |
.version_id = 1,
|
261 |
.minimum_version_id = 1,
|
262 |
.minimum_version_id_old = 1,
|
263 |
.fields = (VMStateField[]) { |
264 |
VMSTATE_INT32_ARRAY(level, sp804_state, 2),
|
265 |
VMSTATE_END_OF_LIST() |
266 |
} |
267 |
}; |
268 |
|
269 |
static int sp804_init(SysBusDevice *dev) |
270 |
{ |
271 |
sp804_state *s = FROM_SYSBUS(sp804_state, dev); |
272 |
qemu_irq *qi; |
273 |
|
274 |
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
|
275 |
sysbus_init_irq(dev, &s->irq); |
276 |
s->timer[0] = arm_timer_init(s->freq0);
|
277 |
s->timer[1] = arm_timer_init(s->freq1);
|
278 |
s->timer[0]->irq = qi[0]; |
279 |
s->timer[1]->irq = qi[1]; |
280 |
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); |
281 |
sysbus_init_mmio(dev, &s->iomem); |
282 |
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
|
283 |
return 0; |
284 |
} |
285 |
|
286 |
/* Integrator/CP timer module. */
|
287 |
|
288 |
typedef struct { |
289 |
SysBusDevice busdev; |
290 |
MemoryRegion iomem; |
291 |
arm_timer_state *timer[3];
|
292 |
} icp_pit_state; |
293 |
|
294 |
static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset, |
295 |
unsigned size)
|
296 |
{ |
297 |
icp_pit_state *s = (icp_pit_state *)opaque; |
298 |
int n;
|
299 |
|
300 |
/* ??? Don't know the PrimeCell ID for this device. */
|
301 |
n = offset >> 8;
|
302 |
if (n > 2) { |
303 |
hw_error("%s: Bad timer %d\n", __func__, n);
|
304 |
} |
305 |
|
306 |
return arm_timer_read(s->timer[n], offset & 0xff); |
307 |
} |
308 |
|
309 |
static void icp_pit_write(void *opaque, target_phys_addr_t offset, |
310 |
uint64_t value, unsigned size)
|
311 |
{ |
312 |
icp_pit_state *s = (icp_pit_state *)opaque; |
313 |
int n;
|
314 |
|
315 |
n = offset >> 8;
|
316 |
if (n > 2) { |
317 |
hw_error("%s: Bad timer %d\n", __func__, n);
|
318 |
} |
319 |
|
320 |
arm_timer_write(s->timer[n], offset & 0xff, value);
|
321 |
} |
322 |
|
323 |
static const MemoryRegionOps icp_pit_ops = { |
324 |
.read = icp_pit_read, |
325 |
.write = icp_pit_write, |
326 |
.endianness = DEVICE_NATIVE_ENDIAN, |
327 |
}; |
328 |
|
329 |
static int icp_pit_init(SysBusDevice *dev) |
330 |
{ |
331 |
icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); |
332 |
|
333 |
/* Timer 0 runs at the system clock speed (40MHz). */
|
334 |
s->timer[0] = arm_timer_init(40000000); |
335 |
/* The other two timers run at 1MHz. */
|
336 |
s->timer[1] = arm_timer_init(1000000); |
337 |
s->timer[2] = arm_timer_init(1000000); |
338 |
|
339 |
sysbus_init_irq(dev, &s->timer[0]->irq);
|
340 |
sysbus_init_irq(dev, &s->timer[1]->irq);
|
341 |
sysbus_init_irq(dev, &s->timer[2]->irq);
|
342 |
|
343 |
memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000); |
344 |
sysbus_init_mmio(dev, &s->iomem); |
345 |
/* This device has no state to save/restore. The component timers will
|
346 |
save themselves. */
|
347 |
return 0; |
348 |
} |
349 |
|
350 |
static void icp_pit_class_init(ObjectClass *klass, void *data) |
351 |
{ |
352 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
353 |
|
354 |
sdc->init = icp_pit_init; |
355 |
} |
356 |
|
357 |
static TypeInfo icp_pit_info = {
|
358 |
.name = "integrator_pit",
|
359 |
.parent = TYPE_SYS_BUS_DEVICE, |
360 |
.instance_size = sizeof(icp_pit_state),
|
361 |
.class_init = icp_pit_class_init, |
362 |
}; |
363 |
|
364 |
static Property sp804_properties[] = {
|
365 |
DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000), |
366 |
DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000), |
367 |
DEFINE_PROP_END_OF_LIST(), |
368 |
}; |
369 |
|
370 |
static void sp804_class_init(ObjectClass *klass, void *data) |
371 |
{ |
372 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
373 |
DeviceClass *k = DEVICE_CLASS(klass); |
374 |
|
375 |
sdc->init = sp804_init; |
376 |
k->props = sp804_properties; |
377 |
} |
378 |
|
379 |
static TypeInfo sp804_info = {
|
380 |
.name = "sp804",
|
381 |
.parent = TYPE_SYS_BUS_DEVICE, |
382 |
.instance_size = sizeof(sp804_state),
|
383 |
.class_init = sp804_class_init, |
384 |
}; |
385 |
|
386 |
static void arm_timer_register_types(void) |
387 |
{ |
388 |
type_register_static(&icp_pit_info); |
389 |
type_register_static(&sp804_info); |
390 |
} |
391 |
|
392 |
type_init(arm_timer_register_types) |