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/*
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* QEMU PowerPC 405 evaluation boards emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc405.h" |
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#include "nvram.h" |
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#include "flash.h" |
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#include "sysemu.h" |
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#include "block.h" |
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#include "boards.h" |
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#include "qemu-log.h" |
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#include "loader.h" |
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#include "blockdev.h" |
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#include "exec-memory.h" |
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#define BIOS_FILENAME "ppc405_rom.bin" |
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#define BIOS_SIZE (2048 * 1024) |
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#define KERNEL_LOAD_ADDR 0x00000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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#define USE_FLASH_BIOS
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#define DEBUG_BOARD_INIT
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/*****************************************************************************/
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/* PPC405EP reference board (IBM) */
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/* Standalone board with:
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* - PowerPC 405EP CPU
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* - SDRAM (0x00000000)
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* - Flash (0xFFF80000)
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* - SRAM (0xFFF00000)
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* - NVRAM (0xF0000000)
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* - FPGA (0xF0300000)
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*/
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typedef struct ref405ep_fpga_t ref405ep_fpga_t; |
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struct ref405ep_fpga_t {
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uint8_t reg0; |
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uint8_t reg1; |
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}; |
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static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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ref405ep_fpga_t *fpga; |
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uint32_t ret; |
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fpga = opaque; |
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switch (addr) {
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case 0x0: |
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ret = fpga->reg0; |
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break;
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case 0x1: |
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ret = fpga->reg1; |
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break;
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default:
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ret = 0;
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break;
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} |
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return ret;
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} |
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static void ref405ep_fpga_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ref405ep_fpga_t *fpga; |
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fpga = opaque; |
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switch (addr) {
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case 0x0: |
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/* Read only */
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break;
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case 0x1: |
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fpga->reg1 = value; |
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break;
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default:
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break;
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} |
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} |
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static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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ret = ref405ep_fpga_readb(opaque, addr) << 8;
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ret |= ref405ep_fpga_readb(opaque, addr + 1);
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return ret;
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} |
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static void ref405ep_fpga_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); |
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} |
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static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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ret = ref405ep_fpga_readb(opaque, addr) << 24;
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ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; |
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ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; |
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ret |= ref405ep_fpga_readb(opaque, addr + 3);
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return ret;
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} |
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static void ref405ep_fpga_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); |
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} |
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static const MemoryRegionOps ref405ep_fpga_ops = { |
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.old_mmio = { |
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.read = { |
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ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, |
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}, |
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.write = { |
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ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, |
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}, |
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}, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static void ref405ep_fpga_reset (void *opaque) |
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{ |
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ref405ep_fpga_t *fpga; |
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fpga = opaque; |
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fpga->reg0 = 0x00;
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fpga->reg1 = 0x0F;
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} |
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static void ref405ep_fpga_init (MemoryRegion *sysmem, uint32_t base) |
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{ |
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ref405ep_fpga_t *fpga; |
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MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
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fpga = g_malloc0(sizeof(ref405ep_fpga_t));
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memory_region_init_io(fpga_memory, &ref405ep_fpga_ops, fpga, |
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"fpga", 0x00000100); |
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memory_region_add_subregion(sysmem, base, fpga_memory); |
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qemu_register_reset(&ref405ep_fpga_reset, fpga); |
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} |
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static void ref405ep_init (ram_addr_t ram_size, |
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const char *boot_device, |
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const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename, |
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const char *cpu_model) |
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{ |
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char *filename;
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ppc4xx_bd_info_t bd; |
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CPUPPCState *env; |
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qemu_irq *pic; |
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MemoryRegion *bios; |
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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ram_addr_t bdloc; |
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MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
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target_phys_addr_t ram_bases[2], ram_sizes[2]; |
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target_ulong sram_size; |
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long bios_size;
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//int phy_addr = 0;
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//static int phy_addr = 1;
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target_ulong kernel_base, initrd_base; |
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long kernel_size, initrd_size;
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int linux_boot;
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int fl_idx, fl_sectors, len;
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DriveInfo *dinfo; |
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MemoryRegion *sysmem = get_system_memory(); |
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/* XXX: fix this */
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memory_region_init_ram(&ram_memories[0], "ef405ep.ram", 0x08000000); |
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vmstate_register_ram_global(&ram_memories[0]);
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ram_bases[0] = 0; |
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ram_sizes[0] = 0x08000000; |
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memory_region_init(&ram_memories[1], "ef405ep.ram1", 0); |
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ram_bases[1] = 0x00000000; |
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ram_sizes[1] = 0x00000000; |
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ram_size = 128 * 1024 * 1024; |
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register cpu\n", __func__);
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#endif
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env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, |
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33333333, &pic, kernel_filename == NULL ? 0 : 1); |
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/* allocate SRAM */
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sram_size = 512 * 1024; |
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memory_region_init_ram(sram, "ef405ep.sram", sram_size);
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vmstate_register_ram_global(sram); |
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memory_region_add_subregion(sysmem, 0xFFF00000, sram);
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/* allocate and load BIOS */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register BIOS\n", __func__);
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#endif
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fl_idx = 0;
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#ifdef USE_FLASH_BIOS
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dinfo = drive_get(IF_PFLASH, 0, fl_idx);
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if (dinfo) {
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bios_size = bdrv_getlength(dinfo->bdrv); |
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fl_sectors = (bios_size + 65535) >> 16; |
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size %lx"
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" at addr %lx '%s' %d\n",
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fl_idx, bios_size, -bios_size, |
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bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), |
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NULL, "ef405ep.bios", bios_size, |
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dinfo->bdrv, 65536, fl_sectors, 1, |
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
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1);
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fl_idx++; |
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} else
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#endif
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{ |
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#ifdef DEBUG_BOARD_INIT
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printf("Load BIOS from file\n");
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#endif
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bios = g_new(MemoryRegion, 1);
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memory_region_init_ram(bios, "ef405ep.bios", BIOS_SIZE);
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vmstate_register_ram_global(bios); |
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if (bios_name == NULL) |
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bios_name = BIOS_FILENAME; |
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
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if (filename) {
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bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); |
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g_free(filename); |
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} else {
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bios_size = -1;
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} |
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if (bios_size < 0 || bios_size > BIOS_SIZE) { |
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fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
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bios_name); |
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exit(1);
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} |
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bios_size = (bios_size + 0xfff) & ~0xfff; |
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memory_region_set_readonly(bios, true);
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memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); |
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} |
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/* Register FPGA */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register FPGA\n", __func__);
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#endif
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ref405ep_fpga_init(sysmem, 0xF0300000);
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/* Register NVRAM */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register NVRAM\n", __func__);
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#endif
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m48t59_init(NULL, 0xF0000000, 0, 8192, 8); |
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/* Load kernel */
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linux_boot = (kernel_filename != NULL);
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if (linux_boot) {
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#ifdef DEBUG_BOARD_INIT
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printf("%s: load kernel\n", __func__);
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#endif
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memset(&bd, 0, sizeof(bd)); |
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bd.bi_memstart = 0x00000000;
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bd.bi_memsize = ram_size; |
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bd.bi_flashstart = -bios_size; |
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bd.bi_flashsize = -bios_size; |
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bd.bi_flashoffset = 0;
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bd.bi_sramstart = 0xFFF00000;
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bd.bi_sramsize = sram_size; |
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bd.bi_bootflags = 0;
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bd.bi_intfreq = 133333333;
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bd.bi_busfreq = 33333333;
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bd.bi_baudrate = 115200;
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bd.bi_s_version[0] = 'Q'; |
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bd.bi_s_version[1] = 'M'; |
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bd.bi_s_version[2] = 'U'; |
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bd.bi_s_version[3] = '\0'; |
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bd.bi_r_version[0] = 'Q'; |
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bd.bi_r_version[1] = 'E'; |
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bd.bi_r_version[2] = 'M'; |
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bd.bi_r_version[3] = 'U'; |
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bd.bi_r_version[4] = '\0'; |
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bd.bi_procfreq = 133333333;
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bd.bi_plb_busfreq = 33333333;
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bd.bi_pci_busfreq = 33333333;
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bd.bi_opbfreq = 33333333;
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bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
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env->gpr[3] = bdloc;
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kernel_base = KERNEL_LOAD_ADDR; |
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/* now we can load the kernel */
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kernel_size = load_image_targphys(kernel_filename, kernel_base, |
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ram_size - kernel_base); |
315 |
if (kernel_size < 0) { |
316 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
318 |
exit(1);
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} |
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printf("Load kernel size %ld at " TARGET_FMT_lx,
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kernel_size, kernel_base); |
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR; |
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initrd_size = load_image_targphys(initrd_filename, initrd_base, |
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ram_size - initrd_base); |
327 |
if (initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
330 |
exit(1);
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} |
332 |
} else {
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initrd_base = 0;
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initrd_size = 0;
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} |
336 |
env->gpr[4] = initrd_base;
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env->gpr[5] = initrd_size;
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if (kernel_cmdline != NULL) { |
339 |
len = strlen(kernel_cmdline); |
340 |
bdloc -= ((len + 255) & ~255); |
341 |
cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1); |
342 |
env->gpr[6] = bdloc;
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env->gpr[7] = bdloc + len;
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} else {
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env->gpr[6] = 0; |
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env->gpr[7] = 0; |
347 |
} |
348 |
env->nip = KERNEL_LOAD_ADDR; |
349 |
} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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bdloc = 0;
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} |
356 |
#ifdef DEBUG_BOARD_INIT
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printf("%s: Done\n", __func__);
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#endif
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printf("bdloc " RAM_ADDR_FMT "\n", bdloc); |
360 |
} |
361 |
|
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static QEMUMachine ref405ep_machine = {
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.name = "ref405ep",
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364 |
.desc = "ref405ep",
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.init = ref405ep_init, |
366 |
}; |
367 |
|
368 |
/*****************************************************************************/
|
369 |
/* AMCC Taihu evaluation board */
|
370 |
/* - PowerPC 405EP processor
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371 |
* - SDRAM 128 MB at 0x00000000
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372 |
* - Boot flash 2 MB at 0xFFE00000
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* - Application flash 32 MB at 0xFC000000
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* - 2 serial ports
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375 |
* - 2 ethernet PHY
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376 |
* - 1 USB 1.1 device 0x50000000
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377 |
* - 1 LCD display 0x50100000
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378 |
* - 1 CPLD 0x50100000
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379 |
* - 1 I2C EEPROM
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380 |
* - 1 I2C thermal sensor
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381 |
* - a set of LEDs
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382 |
* - bit-bang SPI port using GPIOs
|
383 |
* - 1 EBC interface connector 0 0x50200000
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384 |
* - 1 cardbus controller + expansion slot.
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385 |
* - 1 PCI expansion slot.
|
386 |
*/
|
387 |
typedef struct taihu_cpld_t taihu_cpld_t; |
388 |
struct taihu_cpld_t {
|
389 |
uint8_t reg0; |
390 |
uint8_t reg1; |
391 |
}; |
392 |
|
393 |
static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) |
394 |
{ |
395 |
taihu_cpld_t *cpld; |
396 |
uint32_t ret; |
397 |
|
398 |
cpld = opaque; |
399 |
switch (addr) {
|
400 |
case 0x0: |
401 |
ret = cpld->reg0; |
402 |
break;
|
403 |
case 0x1: |
404 |
ret = cpld->reg1; |
405 |
break;
|
406 |
default:
|
407 |
ret = 0;
|
408 |
break;
|
409 |
} |
410 |
|
411 |
return ret;
|
412 |
} |
413 |
|
414 |
static void taihu_cpld_writeb (void *opaque, |
415 |
target_phys_addr_t addr, uint32_t value) |
416 |
{ |
417 |
taihu_cpld_t *cpld; |
418 |
|
419 |
cpld = opaque; |
420 |
switch (addr) {
|
421 |
case 0x0: |
422 |
/* Read only */
|
423 |
break;
|
424 |
case 0x1: |
425 |
cpld->reg1 = value; |
426 |
break;
|
427 |
default:
|
428 |
break;
|
429 |
} |
430 |
} |
431 |
|
432 |
static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) |
433 |
{ |
434 |
uint32_t ret; |
435 |
|
436 |
ret = taihu_cpld_readb(opaque, addr) << 8;
|
437 |
ret |= taihu_cpld_readb(opaque, addr + 1);
|
438 |
|
439 |
return ret;
|
440 |
} |
441 |
|
442 |
static void taihu_cpld_writew (void *opaque, |
443 |
target_phys_addr_t addr, uint32_t value) |
444 |
{ |
445 |
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); |
446 |
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); |
447 |
} |
448 |
|
449 |
static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) |
450 |
{ |
451 |
uint32_t ret; |
452 |
|
453 |
ret = taihu_cpld_readb(opaque, addr) << 24;
|
454 |
ret |= taihu_cpld_readb(opaque, addr + 1) << 16; |
455 |
ret |= taihu_cpld_readb(opaque, addr + 2) << 8; |
456 |
ret |= taihu_cpld_readb(opaque, addr + 3);
|
457 |
|
458 |
return ret;
|
459 |
} |
460 |
|
461 |
static void taihu_cpld_writel (void *opaque, |
462 |
target_phys_addr_t addr, uint32_t value) |
463 |
{ |
464 |
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); |
465 |
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); |
466 |
taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); |
467 |
taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); |
468 |
} |
469 |
|
470 |
static const MemoryRegionOps taihu_cpld_ops = { |
471 |
.old_mmio = { |
472 |
.read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, |
473 |
.write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, |
474 |
}, |
475 |
.endianness = DEVICE_NATIVE_ENDIAN, |
476 |
}; |
477 |
|
478 |
static void taihu_cpld_reset (void *opaque) |
479 |
{ |
480 |
taihu_cpld_t *cpld; |
481 |
|
482 |
cpld = opaque; |
483 |
cpld->reg0 = 0x01;
|
484 |
cpld->reg1 = 0x80;
|
485 |
} |
486 |
|
487 |
static void taihu_cpld_init (MemoryRegion *sysmem, uint32_t base) |
488 |
{ |
489 |
taihu_cpld_t *cpld; |
490 |
MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
|
491 |
|
492 |
cpld = g_malloc0(sizeof(taihu_cpld_t));
|
493 |
memory_region_init_io(cpld_memory, &taihu_cpld_ops, cpld, "cpld", 0x100); |
494 |
memory_region_add_subregion(sysmem, base, cpld_memory); |
495 |
qemu_register_reset(&taihu_cpld_reset, cpld); |
496 |
} |
497 |
|
498 |
static void taihu_405ep_init(ram_addr_t ram_size, |
499 |
const char *boot_device, |
500 |
const char *kernel_filename, |
501 |
const char *kernel_cmdline, |
502 |
const char *initrd_filename, |
503 |
const char *cpu_model) |
504 |
{ |
505 |
char *filename;
|
506 |
qemu_irq *pic; |
507 |
MemoryRegion *sysmem = get_system_memory(); |
508 |
MemoryRegion *bios; |
509 |
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
510 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
511 |
long bios_size;
|
512 |
target_ulong kernel_base, initrd_base; |
513 |
long kernel_size, initrd_size;
|
514 |
int linux_boot;
|
515 |
int fl_idx, fl_sectors;
|
516 |
DriveInfo *dinfo; |
517 |
|
518 |
/* RAM is soldered to the board so the size cannot be changed */
|
519 |
memory_region_init_ram(&ram_memories[0],
|
520 |
"taihu_405ep.ram-0", 0x04000000); |
521 |
vmstate_register_ram_global(&ram_memories[0]);
|
522 |
ram_bases[0] = 0; |
523 |
ram_sizes[0] = 0x04000000; |
524 |
memory_region_init_ram(&ram_memories[1],
|
525 |
"taihu_405ep.ram-1", 0x04000000); |
526 |
vmstate_register_ram_global(&ram_memories[1]);
|
527 |
ram_bases[1] = 0x04000000; |
528 |
ram_sizes[1] = 0x04000000; |
529 |
ram_size = 0x08000000;
|
530 |
#ifdef DEBUG_BOARD_INIT
|
531 |
printf("%s: register cpu\n", __func__);
|
532 |
#endif
|
533 |
ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, |
534 |
33333333, &pic, kernel_filename == NULL ? 0 : 1); |
535 |
/* allocate and load BIOS */
|
536 |
#ifdef DEBUG_BOARD_INIT
|
537 |
printf("%s: register BIOS\n", __func__);
|
538 |
#endif
|
539 |
fl_idx = 0;
|
540 |
#if defined(USE_FLASH_BIOS)
|
541 |
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
|
542 |
if (dinfo) {
|
543 |
bios_size = bdrv_getlength(dinfo->bdrv); |
544 |
/* XXX: should check that size is 2MB */
|
545 |
// bios_size = 2 * 1024 * 1024;
|
546 |
fl_sectors = (bios_size + 65535) >> 16; |
547 |
#ifdef DEBUG_BOARD_INIT
|
548 |
printf("Register parallel flash %d size %lx"
|
549 |
" at addr %lx '%s' %d\n",
|
550 |
fl_idx, bios_size, -bios_size, |
551 |
bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
552 |
#endif
|
553 |
pflash_cfi02_register((uint32_t)(-bios_size), |
554 |
NULL, "taihu_405ep.bios", bios_size, |
555 |
dinfo->bdrv, 65536, fl_sectors, 1, |
556 |
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
557 |
1);
|
558 |
fl_idx++; |
559 |
} else
|
560 |
#endif
|
561 |
{ |
562 |
#ifdef DEBUG_BOARD_INIT
|
563 |
printf("Load BIOS from file\n");
|
564 |
#endif
|
565 |
if (bios_name == NULL) |
566 |
bios_name = BIOS_FILENAME; |
567 |
bios = g_new(MemoryRegion, 1);
|
568 |
memory_region_init_ram(bios, "taihu_405ep.bios", BIOS_SIZE);
|
569 |
vmstate_register_ram_global(bios); |
570 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
571 |
if (filename) {
|
572 |
bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); |
573 |
g_free(filename); |
574 |
} else {
|
575 |
bios_size = -1;
|
576 |
} |
577 |
if (bios_size < 0 || bios_size > BIOS_SIZE) { |
578 |
fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
|
579 |
bios_name); |
580 |
exit(1);
|
581 |
} |
582 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
583 |
memory_region_set_readonly(bios, true);
|
584 |
memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); |
585 |
} |
586 |
/* Register Linux flash */
|
587 |
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
|
588 |
if (dinfo) {
|
589 |
bios_size = bdrv_getlength(dinfo->bdrv); |
590 |
/* XXX: should check that size is 32MB */
|
591 |
bios_size = 32 * 1024 * 1024; |
592 |
fl_sectors = (bios_size + 65535) >> 16; |
593 |
#ifdef DEBUG_BOARD_INIT
|
594 |
printf("Register parallel flash %d size %lx"
|
595 |
" at addr " TARGET_FMT_lx " '%s'\n", |
596 |
fl_idx, bios_size, (target_ulong)0xfc000000,
|
597 |
bdrv_get_device_name(dinfo->bdrv)); |
598 |
#endif
|
599 |
pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, |
600 |
dinfo->bdrv, 65536, fl_sectors, 1, |
601 |
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
602 |
1);
|
603 |
fl_idx++; |
604 |
} |
605 |
/* Register CLPD & LCD display */
|
606 |
#ifdef DEBUG_BOARD_INIT
|
607 |
printf("%s: register CPLD\n", __func__);
|
608 |
#endif
|
609 |
taihu_cpld_init(sysmem, 0x50100000);
|
610 |
/* Load kernel */
|
611 |
linux_boot = (kernel_filename != NULL);
|
612 |
if (linux_boot) {
|
613 |
#ifdef DEBUG_BOARD_INIT
|
614 |
printf("%s: load kernel\n", __func__);
|
615 |
#endif
|
616 |
kernel_base = KERNEL_LOAD_ADDR; |
617 |
/* now we can load the kernel */
|
618 |
kernel_size = load_image_targphys(kernel_filename, kernel_base, |
619 |
ram_size - kernel_base); |
620 |
if (kernel_size < 0) { |
621 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
622 |
kernel_filename); |
623 |
exit(1);
|
624 |
} |
625 |
/* load initrd */
|
626 |
if (initrd_filename) {
|
627 |
initrd_base = INITRD_LOAD_ADDR; |
628 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
629 |
ram_size - initrd_base); |
630 |
if (initrd_size < 0) { |
631 |
fprintf(stderr, |
632 |
"qemu: could not load initial ram disk '%s'\n",
|
633 |
initrd_filename); |
634 |
exit(1);
|
635 |
} |
636 |
} else {
|
637 |
initrd_base = 0;
|
638 |
initrd_size = 0;
|
639 |
} |
640 |
} else {
|
641 |
kernel_base = 0;
|
642 |
kernel_size = 0;
|
643 |
initrd_base = 0;
|
644 |
initrd_size = 0;
|
645 |
} |
646 |
#ifdef DEBUG_BOARD_INIT
|
647 |
printf("%s: Done\n", __func__);
|
648 |
#endif
|
649 |
} |
650 |
|
651 |
static QEMUMachine taihu_machine = {
|
652 |
.name = "taihu",
|
653 |
.desc = "taihu",
|
654 |
.init = taihu_405ep_init, |
655 |
}; |
656 |
|
657 |
static void ppc405_machine_init(void) |
658 |
{ |
659 |
qemu_register_machine(&ref405ep_machine); |
660 |
qemu_register_machine(&taihu_machine); |
661 |
} |
662 |
|
663 |
machine_init(ppc405_machine_init); |