root / target-sparc / translate.c @ 38482a77
History | View | Annotate | Download (195.1 kB)
1 | 7a3f1944 | bellard | /*
|
---|---|---|---|
2 | 7a3f1944 | bellard | SPARC translation
|
3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
|
5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
|
6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
|
8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
|
9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
|
10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
|
11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
|
13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 | 7a3f1944 | bellard | Lesser General Public License for more details.
|
16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
|
18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
|
19 | fad6cb1a | aurel32 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
20 | 7a3f1944 | bellard | */
|
21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | #include <stdarg.h> |
23 | 7a3f1944 | bellard | #include <stdlib.h> |
24 | 7a3f1944 | bellard | #include <stdio.h> |
25 | 7a3f1944 | bellard | #include <string.h> |
26 | 7a3f1944 | bellard | #include <inttypes.h> |
27 | 7a3f1944 | bellard | |
28 | 7a3f1944 | bellard | #include "cpu.h" |
29 | 7a3f1944 | bellard | #include "exec-all.h" |
30 | 7a3f1944 | bellard | #include "disas.h" |
31 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
32 | 57fec1fe | bellard | #include "tcg-op.h" |
33 | 7a3f1944 | bellard | |
34 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
35 | a7812ae4 | pbrook | #include "helper.h" |
36 | a7812ae4 | pbrook | |
37 | 7a3f1944 | bellard | #define DEBUG_DISAS
|
38 | 7a3f1944 | bellard | |
39 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
40 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
41 | 72cbca10 | bellard | according to jump_pc[T2] */
|
42 | 72cbca10 | bellard | |
43 | 1a2fb1c0 | blueswir1 | /* global register indexes */
|
44 | a7812ae4 | pbrook | static TCGv_ptr cpu_env, cpu_regwptr;
|
45 | 8393617c | Blue Swirl | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst, cpu_cc_op;
|
46 | a7812ae4 | pbrook | static TCGv_i32 cpu_psr;
|
47 | a7812ae4 | pbrook | static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
48 | 255e1fcb | blueswir1 | static TCGv cpu_y;
|
49 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
50 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
|
51 | 255e1fcb | blueswir1 | #endif
|
52 | 6ae20372 | blueswir1 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
|
53 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
54 | a7812ae4 | pbrook | static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
|
55 | a7812ae4 | pbrook | static TCGv cpu_gsr;
|
56 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
|
57 | a7812ae4 | pbrook | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
|
58 | a7812ae4 | pbrook | static TCGv_i32 cpu_softint;
|
59 | 255e1fcb | blueswir1 | #else
|
60 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
|
61 | dc99a3f2 | blueswir1 | #endif
|
62 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
|
63 | a7812ae4 | pbrook | static TCGv cpu_tmp0;
|
64 | a7812ae4 | pbrook | static TCGv_i32 cpu_tmp32;
|
65 | a7812ae4 | pbrook | static TCGv_i64 cpu_tmp64;
|
66 | 714547bb | blueswir1 | /* Floating point registers */
|
67 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpr[TARGET_FPREGS];
|
68 | 1a2fb1c0 | blueswir1 | |
69 | 2e70f6ef | pbrook | #include "gen-icount.h" |
70 | 2e70f6ef | pbrook | |
71 | 7a3f1944 | bellard | typedef struct DisasContext { |
72 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
|
73 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
|
74 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
75 | cf495bcf | bellard | int is_br;
|
76 | e8af50a3 | bellard | int mem_idx;
|
77 | a80dde08 | bellard | int fpu_enabled;
|
78 | 2cade6a3 | blueswir1 | int address_mask_32bit;
|
79 | 8393617c | Blue Swirl | uint32_t cc_op; /* current CC operation */
|
80 | cf495bcf | bellard | struct TranslationBlock *tb;
|
81 | 5578ceab | blueswir1 | sparc_def_t *def; |
82 | 7a3f1944 | bellard | } DisasContext; |
83 | 7a3f1944 | bellard | |
84 | 3475187d | bellard | // This function uses non-native bit order
|
85 | dc1a6971 | Blue Swirl | #define GET_FIELD(X, FROM, TO) \
|
86 | dc1a6971 | Blue Swirl | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
87 | 7a3f1944 | bellard | |
88 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
|
89 | dc1a6971 | Blue Swirl | #define GET_FIELD_SP(X, FROM, TO) \
|
90 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
91 | 3475187d | bellard | |
92 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
93 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
94 | 3475187d | bellard | |
95 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
96 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
97 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
98 | 3475187d | bellard | #else
|
99 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
100 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
101 | 3475187d | bellard | #endif
|
102 | 3475187d | bellard | |
103 | b158a785 | blueswir1 | #define UA2005_HTRAP_MASK 0xff |
104 | b158a785 | blueswir1 | #define V8_TRAP_MASK 0x7f |
105 | b158a785 | blueswir1 | |
106 | 3475187d | bellard | static int sign_extend(int x, int len) |
107 | 3475187d | bellard | { |
108 | 3475187d | bellard | len = 32 - len;
|
109 | 3475187d | bellard | return (x << len) >> len;
|
110 | 3475187d | bellard | } |
111 | 3475187d | bellard | |
112 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
113 | 7a3f1944 | bellard | |
114 | ff07ec83 | blueswir1 | /* floating point registers moves */
|
115 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
116 | ff07ec83 | blueswir1 | { |
117 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + |
118 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
119 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
|
120 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
121 | ff07ec83 | blueswir1 | } |
122 | ff07ec83 | blueswir1 | |
123 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
124 | ff07ec83 | blueswir1 | { |
125 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + |
126 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
127 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
|
128 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
129 | ff07ec83 | blueswir1 | } |
130 | ff07ec83 | blueswir1 | |
131 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
132 | ff07ec83 | blueswir1 | { |
133 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + |
134 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
135 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
|
136 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
137 | ff07ec83 | blueswir1 | } |
138 | ff07ec83 | blueswir1 | |
139 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
140 | ff07ec83 | blueswir1 | { |
141 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
142 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
143 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
|
144 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
145 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
|
146 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
147 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
|
148 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
149 | ff07ec83 | blueswir1 | } |
150 | ff07ec83 | blueswir1 | |
151 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
152 | ff07ec83 | blueswir1 | { |
153 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
154 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
155 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
|
156 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
157 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
|
158 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
159 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
|
160 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
161 | ff07ec83 | blueswir1 | } |
162 | ff07ec83 | blueswir1 | |
163 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
164 | ff07ec83 | blueswir1 | { |
165 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
166 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
167 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
|
168 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
169 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
|
170 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
171 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
|
172 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
173 | ff07ec83 | blueswir1 | } |
174 | 1f587329 | blueswir1 | |
175 | 81ad8ba2 | blueswir1 | /* moves */
|
176 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
177 | 3475187d | bellard | #define supervisor(dc) 0 |
178 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
179 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
180 | 81ad8ba2 | blueswir1 | #endif
|
181 | 3475187d | bellard | #else
|
182 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
183 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
184 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
185 | 6f27aba6 | blueswir1 | #else
|
186 | 3475187d | bellard | #endif
|
187 | 81ad8ba2 | blueswir1 | #endif
|
188 | 81ad8ba2 | blueswir1 | |
189 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
190 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
|
191 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
|
192 | 1a2fb1c0 | blueswir1 | #else
|
193 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
194 | 2cade6a3 | blueswir1 | #endif
|
195 | 1a2fb1c0 | blueswir1 | #endif
|
196 | 3391c818 | blueswir1 | |
197 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
198 | 2cade6a3 | blueswir1 | { |
199 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
200 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
|
201 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
|
202 | 2cade6a3 | blueswir1 | #endif
|
203 | 2cade6a3 | blueswir1 | } |
204 | 2cade6a3 | blueswir1 | |
205 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
206 | 81ad8ba2 | blueswir1 | { |
207 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
208 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
|
209 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
210 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
211 | 1a2fb1c0 | blueswir1 | else {
|
212 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
213 | 81ad8ba2 | blueswir1 | } |
214 | 81ad8ba2 | blueswir1 | } |
215 | 81ad8ba2 | blueswir1 | |
216 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
217 | 81ad8ba2 | blueswir1 | { |
218 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
219 | 1a2fb1c0 | blueswir1 | return;
|
220 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
221 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
222 | 1a2fb1c0 | blueswir1 | else {
|
223 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
224 | 81ad8ba2 | blueswir1 | } |
225 | 81ad8ba2 | blueswir1 | } |
226 | 81ad8ba2 | blueswir1 | |
227 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
228 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
229 | 6e256c93 | bellard | { |
230 | 6e256c93 | bellard | TranslationBlock *tb; |
231 | 6e256c93 | bellard | |
232 | 6e256c93 | bellard | tb = s->tb; |
233 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
|
234 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
235 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
|
236 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
237 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
238 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
239 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
|
240 | 6e256c93 | bellard | } else {
|
241 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
|
242 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
243 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
244 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
245 | 6e256c93 | bellard | } |
246 | 6e256c93 | bellard | } |
247 | 6e256c93 | bellard | |
248 | 19f329ad | blueswir1 | // XXX suboptimal
|
249 | a7812ae4 | pbrook | static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) |
250 | 19f329ad | blueswir1 | { |
251 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
252 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
253 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
254 | 19f329ad | blueswir1 | } |
255 | 19f329ad | blueswir1 | |
256 | a7812ae4 | pbrook | static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) |
257 | 19f329ad | blueswir1 | { |
258 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
259 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
260 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
261 | 19f329ad | blueswir1 | } |
262 | 19f329ad | blueswir1 | |
263 | a7812ae4 | pbrook | static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) |
264 | 19f329ad | blueswir1 | { |
265 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
266 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
267 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
268 | 19f329ad | blueswir1 | } |
269 | 19f329ad | blueswir1 | |
270 | a7812ae4 | pbrook | static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) |
271 | 19f329ad | blueswir1 | { |
272 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
273 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
274 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
275 | 19f329ad | blueswir1 | } |
276 | 19f329ad | blueswir1 | |
277 | ce5b3c3d | blueswir1 | static inline void gen_cc_clear_icc(void) |
278 | dc99a3f2 | blueswir1 | { |
279 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_psr, 0);
|
280 | ce5b3c3d | blueswir1 | } |
281 | ce5b3c3d | blueswir1 | |
282 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
283 | ce5b3c3d | blueswir1 | static inline void gen_cc_clear_xcc(void) |
284 | ce5b3c3d | blueswir1 | { |
285 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_xcc, 0);
|
286 | dc99a3f2 | blueswir1 | } |
287 | ce5b3c3d | blueswir1 | #endif
|
288 | dc99a3f2 | blueswir1 | |
289 | dc99a3f2 | blueswir1 | /* old op:
|
290 | dc99a3f2 | blueswir1 | if (!T0)
|
291 | dc99a3f2 | blueswir1 | env->psr |= PSR_ZERO;
|
292 | dc99a3f2 | blueswir1 | if ((int32_t) T0 < 0)
|
293 | dc99a3f2 | blueswir1 | env->psr |= PSR_NEG;
|
294 | dc99a3f2 | blueswir1 | */
|
295 | ce5b3c3d | blueswir1 | static inline void gen_cc_NZ_icc(TCGv dst) |
296 | dc99a3f2 | blueswir1 | { |
297 | 8911f501 | blueswir1 | TCGv r_temp; |
298 | dc99a3f2 | blueswir1 | int l1, l2;
|
299 | dc99a3f2 | blueswir1 | |
300 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
301 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
302 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
303 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
|
304 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
305 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
306 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
307 | 527067d8 | blueswir1 | tcg_gen_ext32s_tl(r_temp, dst); |
308 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
|
309 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
310 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
311 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
312 | ce5b3c3d | blueswir1 | } |
313 | ce5b3c3d | blueswir1 | |
314 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
315 | ce5b3c3d | blueswir1 | static inline void gen_cc_NZ_xcc(TCGv dst) |
316 | ce5b3c3d | blueswir1 | { |
317 | ce5b3c3d | blueswir1 | int l1, l2;
|
318 | ce5b3c3d | blueswir1 | |
319 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
320 | ce5b3c3d | blueswir1 | l2 = gen_new_label(); |
321 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
|
322 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
323 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
324 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
|
325 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
326 | ce5b3c3d | blueswir1 | gen_set_label(l2); |
327 | dc99a3f2 | blueswir1 | } |
328 | ce5b3c3d | blueswir1 | #endif
|
329 | dc99a3f2 | blueswir1 | |
330 | dc99a3f2 | blueswir1 | /* old op:
|
331 | dc99a3f2 | blueswir1 | if (T0 < src1)
|
332 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
333 | dc99a3f2 | blueswir1 | */
|
334 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
335 | dc99a3f2 | blueswir1 | { |
336 | 2ae72bce | blueswir1 | TCGv r_temp1, r_temp2; |
337 | dc99a3f2 | blueswir1 | int l1;
|
338 | dc99a3f2 | blueswir1 | |
339 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
340 | a7812ae4 | pbrook | r_temp1 = tcg_temp_new(); |
341 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new(); |
342 | 2ae72bce | blueswir1 | tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
|
343 | 2ae72bce | blueswir1 | tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
|
344 | 2ae72bce | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
345 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
346 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
347 | 2ae72bce | blueswir1 | tcg_temp_free(r_temp1); |
348 | 2ae72bce | blueswir1 | tcg_temp_free(r_temp2); |
349 | ce5b3c3d | blueswir1 | } |
350 | ce5b3c3d | blueswir1 | |
351 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
352 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
353 | ce5b3c3d | blueswir1 | { |
354 | ce5b3c3d | blueswir1 | int l1;
|
355 | dc99a3f2 | blueswir1 | |
356 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
357 | ce5b3c3d | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
358 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
359 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
360 | dc99a3f2 | blueswir1 | } |
361 | ce5b3c3d | blueswir1 | #endif
|
362 | dc99a3f2 | blueswir1 | |
363 | dc99a3f2 | blueswir1 | /* old op:
|
364 | dc99a3f2 | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
|
365 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
366 | dc99a3f2 | blueswir1 | */
|
367 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
368 | dc99a3f2 | blueswir1 | { |
369 | 0425bee5 | blueswir1 | TCGv r_temp; |
370 | dc99a3f2 | blueswir1 | |
371 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
372 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
373 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
374 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
375 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
376 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
377 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
|
378 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
379 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
380 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
381 | ce5b3c3d | blueswir1 | } |
382 | ce5b3c3d | blueswir1 | |
383 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
384 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
385 | ce5b3c3d | blueswir1 | { |
386 | ce5b3c3d | blueswir1 | TCGv r_temp; |
387 | ce5b3c3d | blueswir1 | |
388 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
389 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
390 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
391 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
392 | ce5b3c3d | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
393 | ce5b3c3d | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
394 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
|
395 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
396 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
397 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
398 | dc99a3f2 | blueswir1 | } |
399 | ce5b3c3d | blueswir1 | #endif
|
400 | dc99a3f2 | blueswir1 | |
401 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
402 | dc99a3f2 | blueswir1 | { |
403 | a7812ae4 | pbrook | TCGv r_temp; |
404 | a7812ae4 | pbrook | TCGv_i32 r_const; |
405 | dc99a3f2 | blueswir1 | int l1;
|
406 | dc99a3f2 | blueswir1 | |
407 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
408 | dc99a3f2 | blueswir1 | |
409 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
410 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
411 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
412 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
413 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
414 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
415 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
416 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
417 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
418 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
419 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
420 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
421 | dc99a3f2 | blueswir1 | } |
422 | dc99a3f2 | blueswir1 | |
423 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
424 | dc99a3f2 | blueswir1 | { |
425 | dc99a3f2 | blueswir1 | int l1;
|
426 | dc99a3f2 | blueswir1 | |
427 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
428 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
429 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
430 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
431 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
432 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
433 | dc99a3f2 | blueswir1 | } |
434 | dc99a3f2 | blueswir1 | |
435 | 719f66a7 | Blue Swirl | static inline void gen_op_logic_cc(TCGv dst) |
436 | 719f66a7 | Blue Swirl | { |
437 | 719f66a7 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, dst); |
438 | 719f66a7 | Blue Swirl | |
439 | 719f66a7 | Blue Swirl | gen_cc_clear_icc(); |
440 | 719f66a7 | Blue Swirl | gen_cc_NZ_icc(cpu_cc_dst); |
441 | 719f66a7 | Blue Swirl | #ifdef TARGET_SPARC64
|
442 | 719f66a7 | Blue Swirl | gen_cc_clear_xcc(); |
443 | 719f66a7 | Blue Swirl | gen_cc_NZ_xcc(cpu_cc_dst); |
444 | 719f66a7 | Blue Swirl | #endif
|
445 | 719f66a7 | Blue Swirl | } |
446 | 719f66a7 | Blue Swirl | |
447 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
448 | dc99a3f2 | blueswir1 | { |
449 | dc99a3f2 | blueswir1 | int l1;
|
450 | a7812ae4 | pbrook | TCGv_i32 r_const; |
451 | dc99a3f2 | blueswir1 | |
452 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
453 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
454 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
455 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
456 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
457 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
458 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
459 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
460 | dc99a3f2 | blueswir1 | } |
461 | dc99a3f2 | blueswir1 | |
462 | 41d72852 | Blue Swirl | static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2) |
463 | 41d72852 | Blue Swirl | { |
464 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
465 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
466 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2); |
467 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
468 | 41d72852 | Blue Swirl | } |
469 | 41d72852 | Blue Swirl | |
470 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
471 | dc99a3f2 | blueswir1 | { |
472 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
473 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
474 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
475 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
476 | 41d72852 | Blue Swirl | } |
477 | 41d72852 | Blue Swirl | |
478 | 41d72852 | Blue Swirl | static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2) |
479 | dc99a3f2 | blueswir1 | { |
480 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
481 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
482 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
483 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
484 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
485 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
486 | 41d72852 | Blue Swirl | } |
487 | 41d72852 | Blue Swirl | |
488 | 41d72852 | Blue Swirl | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
489 | 41d72852 | Blue Swirl | { |
490 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
491 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
492 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
493 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
494 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
495 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
496 | dc99a3f2 | blueswir1 | } |
497 | dc99a3f2 | blueswir1 | |
498 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
499 | dc99a3f2 | blueswir1 | { |
500 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
501 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
502 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
503 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
504 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
505 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
506 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
507 | 6f551262 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
508 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
509 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
510 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
511 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
512 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
513 | ce5b3c3d | blueswir1 | #endif
|
514 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
515 | dc99a3f2 | blueswir1 | } |
516 | dc99a3f2 | blueswir1 | |
517 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
518 | dc99a3f2 | blueswir1 | { |
519 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
520 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
521 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
522 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
523 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
524 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
525 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
526 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
527 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
528 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
529 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
530 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
531 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
532 | ce5b3c3d | blueswir1 | #endif
|
533 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
534 | dc99a3f2 | blueswir1 | } |
535 | dc99a3f2 | blueswir1 | |
536 | dc99a3f2 | blueswir1 | /* old op:
|
537 | dc99a3f2 | blueswir1 | if (src1 < T1)
|
538 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
539 | dc99a3f2 | blueswir1 | */
|
540 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
541 | dc99a3f2 | blueswir1 | { |
542 | 8911f501 | blueswir1 | TCGv r_temp1, r_temp2; |
543 | dc99a3f2 | blueswir1 | int l1;
|
544 | dc99a3f2 | blueswir1 | |
545 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
546 | a7812ae4 | pbrook | r_temp1 = tcg_temp_new(); |
547 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new(); |
548 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
|
549 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
|
550 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
551 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
552 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
553 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp1); |
554 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
555 | ce5b3c3d | blueswir1 | } |
556 | ce5b3c3d | blueswir1 | |
557 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
558 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
559 | ce5b3c3d | blueswir1 | { |
560 | ce5b3c3d | blueswir1 | int l1;
|
561 | dc99a3f2 | blueswir1 | |
562 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
563 | ce5b3c3d | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); |
564 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
565 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
566 | dc99a3f2 | blueswir1 | } |
567 | ce5b3c3d | blueswir1 | #endif
|
568 | dc99a3f2 | blueswir1 | |
569 | dc99a3f2 | blueswir1 | /* old op:
|
570 | dc99a3f2 | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
|
571 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
572 | dc99a3f2 | blueswir1 | */
|
573 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
574 | dc99a3f2 | blueswir1 | { |
575 | 0425bee5 | blueswir1 | TCGv r_temp; |
576 | dc99a3f2 | blueswir1 | |
577 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
578 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
579 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
580 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
581 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
582 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
|
583 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
584 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
585 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
586 | ce5b3c3d | blueswir1 | } |
587 | ce5b3c3d | blueswir1 | |
588 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
589 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
590 | ce5b3c3d | blueswir1 | { |
591 | ce5b3c3d | blueswir1 | TCGv r_temp; |
592 | ce5b3c3d | blueswir1 | |
593 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
594 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
595 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
596 | ce5b3c3d | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
597 | ce5b3c3d | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
598 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
|
599 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
600 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
601 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
602 | dc99a3f2 | blueswir1 | } |
603 | ce5b3c3d | blueswir1 | #endif
|
604 | dc99a3f2 | blueswir1 | |
605 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
606 | dc99a3f2 | blueswir1 | { |
607 | a7812ae4 | pbrook | TCGv r_temp; |
608 | a7812ae4 | pbrook | TCGv_i32 r_const; |
609 | dc99a3f2 | blueswir1 | int l1;
|
610 | dc99a3f2 | blueswir1 | |
611 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
612 | dc99a3f2 | blueswir1 | |
613 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
614 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
615 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
616 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
617 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
618 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
619 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
620 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
621 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
622 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
623 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
624 | dc99a3f2 | blueswir1 | } |
625 | dc99a3f2 | blueswir1 | |
626 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc2(TCGv dst) |
627 | dc99a3f2 | blueswir1 | { |
628 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
629 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
630 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
631 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
632 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
633 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
634 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
635 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
636 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
637 | ce5b3c3d | blueswir1 | #endif
|
638 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
639 | dc99a3f2 | blueswir1 | } |
640 | dc99a3f2 | blueswir1 | |
641 | 41d72852 | Blue Swirl | static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2) |
642 | 41d72852 | Blue Swirl | { |
643 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
644 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
645 | 719f66a7 | Blue Swirl | if (src2 == 0) { |
646 | 719f66a7 | Blue Swirl | tcg_gen_mov_tl(dst, src1); |
647 | 719f66a7 | Blue Swirl | gen_op_logic_cc(dst); |
648 | 719f66a7 | Blue Swirl | } else {
|
649 | 719f66a7 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2); |
650 | 719f66a7 | Blue Swirl | gen_op_sub_cc2(dst); |
651 | 719f66a7 | Blue Swirl | } |
652 | 41d72852 | Blue Swirl | } |
653 | 41d72852 | Blue Swirl | |
654 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
655 | dc99a3f2 | blueswir1 | { |
656 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
657 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
658 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
659 | 41d72852 | Blue Swirl | gen_op_sub_cc2(dst); |
660 | 41d72852 | Blue Swirl | } |
661 | 41d72852 | Blue Swirl | |
662 | 41d72852 | Blue Swirl | static inline void gen_op_subx_cc2(TCGv dst) |
663 | 41d72852 | Blue Swirl | { |
664 | 41d72852 | Blue Swirl | gen_cc_NZ_icc(cpu_cc_dst); |
665 | 41d72852 | Blue Swirl | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
666 | 41d72852 | Blue Swirl | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
667 | 41d72852 | Blue Swirl | #ifdef TARGET_SPARC64
|
668 | 41d72852 | Blue Swirl | gen_cc_NZ_xcc(cpu_cc_dst); |
669 | 41d72852 | Blue Swirl | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
670 | 41d72852 | Blue Swirl | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
671 | 41d72852 | Blue Swirl | #endif
|
672 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
673 | 41d72852 | Blue Swirl | } |
674 | 41d72852 | Blue Swirl | |
675 | 41d72852 | Blue Swirl | static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) |
676 | 41d72852 | Blue Swirl | { |
677 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
678 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
679 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
680 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
681 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
682 | 5c6a0628 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
683 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
684 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
685 | 5c6a0628 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
686 | ce5b3c3d | blueswir1 | #endif
|
687 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
688 | 41d72852 | Blue Swirl | gen_op_subx_cc2(dst); |
689 | 41d72852 | Blue Swirl | } |
690 | 41d72852 | Blue Swirl | |
691 | 41d72852 | Blue Swirl | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
692 | 41d72852 | Blue Swirl | { |
693 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
694 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
695 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
696 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
697 | 41d72852 | Blue Swirl | gen_cc_clear_icc(); |
698 | ba28189b | blueswir1 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
699 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
700 | 41d72852 | Blue Swirl | gen_cc_clear_xcc(); |
701 | ba28189b | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
702 | ce5b3c3d | blueswir1 | #endif
|
703 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
704 | 41d72852 | Blue Swirl | gen_op_subx_cc2(dst); |
705 | dc99a3f2 | blueswir1 | } |
706 | dc99a3f2 | blueswir1 | |
707 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
708 | dc99a3f2 | blueswir1 | { |
709 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
710 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
711 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
712 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
713 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
714 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
715 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
716 | 6f551262 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
717 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
718 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
719 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
720 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
721 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
722 | ce5b3c3d | blueswir1 | #endif
|
723 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
724 | dc99a3f2 | blueswir1 | } |
725 | dc99a3f2 | blueswir1 | |
726 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
727 | dc99a3f2 | blueswir1 | { |
728 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
729 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
730 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
731 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
732 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
733 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
734 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
735 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
736 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
737 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
738 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
739 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
740 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
741 | ce5b3c3d | blueswir1 | #endif
|
742 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
743 | dc99a3f2 | blueswir1 | } |
744 | dc99a3f2 | blueswir1 | |
745 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
746 | d9bdab86 | blueswir1 | { |
747 | 105a1f04 | blueswir1 | TCGv r_temp; |
748 | 6f551262 | blueswir1 | int l1;
|
749 | d9bdab86 | blueswir1 | |
750 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
751 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
752 | d9bdab86 | blueswir1 | |
753 | d9bdab86 | blueswir1 | /* old op:
|
754 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
755 | d9bdab86 | blueswir1 | T1 = 0;
|
756 | d9bdab86 | blueswir1 | */
|
757 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
758 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
759 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
760 | 105a1f04 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
761 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
762 | 6f551262 | blueswir1 | gen_set_label(l1); |
763 | d9bdab86 | blueswir1 | |
764 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
765 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
766 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
767 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
768 | 255e1fcb | blueswir1 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
|
769 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
|
770 | 5068cbd9 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
771 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
772 | d9bdab86 | blueswir1 | |
773 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
774 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
775 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
776 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
777 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
778 | d9bdab86 | blueswir1 | |
779 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
780 | d9bdab86 | blueswir1 | // src1 = T0;
|
781 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
782 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
783 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
784 | d9bdab86 | blueswir1 | |
785 | d9bdab86 | blueswir1 | /* do addition and update flags */
|
786 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
787 | d9bdab86 | blueswir1 | |
788 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
789 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
790 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
791 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
792 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
793 | d9bdab86 | blueswir1 | } |
794 | d9bdab86 | blueswir1 | |
795 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
796 | 8879d139 | blueswir1 | { |
797 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
798 | 8879d139 | blueswir1 | |
799 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
800 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
801 | 8879d139 | blueswir1 | |
802 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, src2); |
803 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, src1); |
804 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
805 | 8879d139 | blueswir1 | |
806 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
807 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
808 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
809 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
810 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
811 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
812 | 8879d139 | blueswir1 | #else
|
813 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
814 | 8879d139 | blueswir1 | #endif
|
815 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
816 | 8879d139 | blueswir1 | } |
817 | 8879d139 | blueswir1 | |
818 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
819 | 8879d139 | blueswir1 | { |
820 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
821 | 8879d139 | blueswir1 | |
822 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
823 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
824 | 8879d139 | blueswir1 | |
825 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, src2); |
826 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, src1); |
827 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
828 | 8879d139 | blueswir1 | |
829 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
830 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
831 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
832 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
833 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
834 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
835 | 8879d139 | blueswir1 | #else
|
836 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
837 | 8879d139 | blueswir1 | #endif
|
838 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
839 | 8879d139 | blueswir1 | } |
840 | 8879d139 | blueswir1 | |
841 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
842 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
843 | 1a7b60e7 | blueswir1 | { |
844 | a7812ae4 | pbrook | TCGv_i32 r_const; |
845 | 1a7b60e7 | blueswir1 | int l1;
|
846 | 1a7b60e7 | blueswir1 | |
847 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
848 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
849 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
850 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
851 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
852 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
853 | 1a7b60e7 | blueswir1 | } |
854 | 1a7b60e7 | blueswir1 | |
855 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
856 | 1a7b60e7 | blueswir1 | { |
857 | 1a7b60e7 | blueswir1 | int l1, l2;
|
858 | 1a7b60e7 | blueswir1 | |
859 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
860 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
861 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
862 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
863 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
864 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
865 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
866 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
867 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
868 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
869 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
870 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
871 | 1a7b60e7 | blueswir1 | } |
872 | 1a7b60e7 | blueswir1 | #endif
|
873 | 1a7b60e7 | blueswir1 | |
874 | 4af984a7 | blueswir1 | static inline void gen_op_div_cc(TCGv dst) |
875 | dc99a3f2 | blueswir1 | { |
876 | dc99a3f2 | blueswir1 | int l1;
|
877 | dc99a3f2 | blueswir1 | |
878 | ba28189b | blueswir1 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
879 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
880 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
881 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
882 | 5c6a0628 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
|
883 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
884 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
885 | dc99a3f2 | blueswir1 | } |
886 | dc99a3f2 | blueswir1 | |
887 | 19f329ad | blueswir1 | // 1
|
888 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
889 | 19f329ad | blueswir1 | { |
890 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
891 | 19f329ad | blueswir1 | } |
892 | 19f329ad | blueswir1 | |
893 | 19f329ad | blueswir1 | // Z
|
894 | a7812ae4 | pbrook | static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) |
895 | 19f329ad | blueswir1 | { |
896 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
897 | 19f329ad | blueswir1 | } |
898 | 19f329ad | blueswir1 | |
899 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
900 | a7812ae4 | pbrook | static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) |
901 | 19f329ad | blueswir1 | { |
902 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
903 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
904 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
905 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
906 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
907 | 19f329ad | blueswir1 | } |
908 | 19f329ad | blueswir1 | |
909 | 19f329ad | blueswir1 | // N ^ V
|
910 | a7812ae4 | pbrook | static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) |
911 | 19f329ad | blueswir1 | { |
912 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
913 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
914 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
915 | 19f329ad | blueswir1 | } |
916 | 19f329ad | blueswir1 | |
917 | 19f329ad | blueswir1 | // C | Z
|
918 | a7812ae4 | pbrook | static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) |
919 | 19f329ad | blueswir1 | { |
920 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
921 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
922 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
923 | 19f329ad | blueswir1 | } |
924 | 19f329ad | blueswir1 | |
925 | 19f329ad | blueswir1 | // C
|
926 | a7812ae4 | pbrook | static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) |
927 | 19f329ad | blueswir1 | { |
928 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
929 | 19f329ad | blueswir1 | } |
930 | 19f329ad | blueswir1 | |
931 | 19f329ad | blueswir1 | // V
|
932 | a7812ae4 | pbrook | static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) |
933 | 19f329ad | blueswir1 | { |
934 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
935 | 19f329ad | blueswir1 | } |
936 | 19f329ad | blueswir1 | |
937 | 19f329ad | blueswir1 | // 0
|
938 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
939 | 19f329ad | blueswir1 | { |
940 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
941 | 19f329ad | blueswir1 | } |
942 | 19f329ad | blueswir1 | |
943 | 19f329ad | blueswir1 | // N
|
944 | a7812ae4 | pbrook | static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) |
945 | 19f329ad | blueswir1 | { |
946 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
947 | 19f329ad | blueswir1 | } |
948 | 19f329ad | blueswir1 | |
949 | 19f329ad | blueswir1 | // !Z
|
950 | a7812ae4 | pbrook | static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) |
951 | 19f329ad | blueswir1 | { |
952 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
953 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
954 | 19f329ad | blueswir1 | } |
955 | 19f329ad | blueswir1 | |
956 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
957 | a7812ae4 | pbrook | static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) |
958 | 19f329ad | blueswir1 | { |
959 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
960 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
961 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
962 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
963 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
964 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
965 | 19f329ad | blueswir1 | } |
966 | 19f329ad | blueswir1 | |
967 | 19f329ad | blueswir1 | // !(N ^ V)
|
968 | a7812ae4 | pbrook | static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) |
969 | 19f329ad | blueswir1 | { |
970 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
971 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
972 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
973 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
974 | 19f329ad | blueswir1 | } |
975 | 19f329ad | blueswir1 | |
976 | 19f329ad | blueswir1 | // !(C | Z)
|
977 | a7812ae4 | pbrook | static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) |
978 | 19f329ad | blueswir1 | { |
979 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
980 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
981 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
982 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
983 | 19f329ad | blueswir1 | } |
984 | 19f329ad | blueswir1 | |
985 | 19f329ad | blueswir1 | // !C
|
986 | a7812ae4 | pbrook | static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) |
987 | 19f329ad | blueswir1 | { |
988 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
989 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
990 | 19f329ad | blueswir1 | } |
991 | 19f329ad | blueswir1 | |
992 | 19f329ad | blueswir1 | // !N
|
993 | a7812ae4 | pbrook | static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) |
994 | 19f329ad | blueswir1 | { |
995 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
996 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
997 | 19f329ad | blueswir1 | } |
998 | 19f329ad | blueswir1 | |
999 | 19f329ad | blueswir1 | // !V
|
1000 | a7812ae4 | pbrook | static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) |
1001 | 19f329ad | blueswir1 | { |
1002 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
1003 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1004 | 19f329ad | blueswir1 | } |
1005 | 19f329ad | blueswir1 | |
1006 | 19f329ad | blueswir1 | /*
|
1007 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
1008 | 19f329ad | blueswir1 | 0 =
|
1009 | 19f329ad | blueswir1 | 1 <
|
1010 | 19f329ad | blueswir1 | 2 >
|
1011 | 19f329ad | blueswir1 | 3 unordered
|
1012 | 19f329ad | blueswir1 | */
|
1013 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
1014 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1015 | 19f329ad | blueswir1 | { |
1016 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
1017 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1018 | 19f329ad | blueswir1 | } |
1019 | 19f329ad | blueswir1 | |
1020 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
1021 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1022 | 19f329ad | blueswir1 | { |
1023 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
1024 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1025 | 19f329ad | blueswir1 | } |
1026 | 19f329ad | blueswir1 | |
1027 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
1028 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
1029 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1030 | 19f329ad | blueswir1 | { |
1031 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1032 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1033 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1034 | 19f329ad | blueswir1 | } |
1035 | 19f329ad | blueswir1 | |
1036 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
1037 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
1038 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1039 | 19f329ad | blueswir1 | { |
1040 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1041 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1042 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1043 | 19f329ad | blueswir1 | } |
1044 | 19f329ad | blueswir1 | |
1045 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
1046 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
1047 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1048 | 19f329ad | blueswir1 | { |
1049 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1050 | 19f329ad | blueswir1 | } |
1051 | 19f329ad | blueswir1 | |
1052 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
1053 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
1054 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1055 | 19f329ad | blueswir1 | { |
1056 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1057 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1058 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1059 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1060 | 19f329ad | blueswir1 | } |
1061 | 19f329ad | blueswir1 | |
1062 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
1063 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
1064 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1065 | 19f329ad | blueswir1 | { |
1066 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1067 | 19f329ad | blueswir1 | } |
1068 | 19f329ad | blueswir1 | |
1069 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
1070 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
1071 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1072 | 19f329ad | blueswir1 | { |
1073 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1074 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1075 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1076 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1077 | 19f329ad | blueswir1 | } |
1078 | 19f329ad | blueswir1 | |
1079 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
1080 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
1081 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1082 | 19f329ad | blueswir1 | { |
1083 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1084 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1085 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1086 | 19f329ad | blueswir1 | } |
1087 | 19f329ad | blueswir1 | |
1088 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
1089 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
1090 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1091 | 19f329ad | blueswir1 | { |
1092 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1093 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1094 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1095 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1096 | 19f329ad | blueswir1 | } |
1097 | 19f329ad | blueswir1 | |
1098 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
1099 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
1100 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1101 | 19f329ad | blueswir1 | { |
1102 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1103 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1104 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1105 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1106 | 19f329ad | blueswir1 | } |
1107 | 19f329ad | blueswir1 | |
1108 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
1109 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
1110 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1111 | 19f329ad | blueswir1 | { |
1112 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1113 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1114 | 19f329ad | blueswir1 | } |
1115 | 19f329ad | blueswir1 | |
1116 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
1117 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
1118 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1119 | 19f329ad | blueswir1 | { |
1120 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1121 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1122 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1123 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1124 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1125 | 19f329ad | blueswir1 | } |
1126 | 19f329ad | blueswir1 | |
1127 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
1128 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
1129 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1130 | 19f329ad | blueswir1 | { |
1131 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1132 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1133 | 19f329ad | blueswir1 | } |
1134 | 19f329ad | blueswir1 | |
1135 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
1136 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
1137 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1138 | 19f329ad | blueswir1 | { |
1139 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1140 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1141 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1142 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1143 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1144 | 19f329ad | blueswir1 | } |
1145 | 19f329ad | blueswir1 | |
1146 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
1147 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
1148 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1149 | 19f329ad | blueswir1 | { |
1150 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1151 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1152 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1153 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1154 | 19f329ad | blueswir1 | } |
1155 | 19f329ad | blueswir1 | |
1156 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
1157 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1158 | 83469015 | bellard | { |
1159 | 83469015 | bellard | int l1;
|
1160 | 83469015 | bellard | |
1161 | 83469015 | bellard | l1 = gen_new_label(); |
1162 | 83469015 | bellard | |
1163 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1164 | 83469015 | bellard | |
1165 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
1166 | 83469015 | bellard | |
1167 | 83469015 | bellard | gen_set_label(l1); |
1168 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
1169 | 83469015 | bellard | } |
1170 | 83469015 | bellard | |
1171 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1172 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1173 | 83469015 | bellard | { |
1174 | 83469015 | bellard | int l1;
|
1175 | 83469015 | bellard | |
1176 | 83469015 | bellard | l1 = gen_new_label(); |
1177 | 83469015 | bellard | |
1178 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1179 | 83469015 | bellard | |
1180 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1181 | 83469015 | bellard | |
1182 | 83469015 | bellard | gen_set_label(l1); |
1183 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1184 | 83469015 | bellard | } |
1185 | 83469015 | bellard | |
1186 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1187 | 19f329ad | blueswir1 | TCGv r_cond) |
1188 | 83469015 | bellard | { |
1189 | 83469015 | bellard | int l1, l2;
|
1190 | 83469015 | bellard | |
1191 | 83469015 | bellard | l1 = gen_new_label(); |
1192 | 83469015 | bellard | l2 = gen_new_label(); |
1193 | 19f329ad | blueswir1 | |
1194 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1195 | 83469015 | bellard | |
1196 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
1197 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
1198 | 83469015 | bellard | |
1199 | 83469015 | bellard | gen_set_label(l1); |
1200 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
1201 | 83469015 | bellard | gen_set_label(l2); |
1202 | 83469015 | bellard | } |
1203 | 83469015 | bellard | |
1204 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
1205 | 4af984a7 | blueswir1 | have been set for a jump */
|
1206 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
1207 | 83469015 | bellard | { |
1208 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1209 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1210 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1211 | 83469015 | bellard | } |
1212 | 83469015 | bellard | } |
1213 | 83469015 | bellard | |
1214 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
1215 | 72cbca10 | bellard | { |
1216 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1217 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1218 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1219 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1220 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
1221 | 72cbca10 | bellard | } |
1222 | 72cbca10 | bellard | } |
1223 | 72cbca10 | bellard | |
1224 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
1225 | 72cbca10 | bellard | { |
1226 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
1227 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
1228 | 72cbca10 | bellard | } |
1229 | 72cbca10 | bellard | |
1230 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
1231 | 0bee699e | bellard | { |
1232 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1233 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1234 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1235 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1236 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1237 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1238 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1239 | 0bee699e | bellard | } else {
|
1240 | 0bee699e | bellard | dc->pc = dc->npc; |
1241 | 0bee699e | bellard | } |
1242 | 0bee699e | bellard | } |
1243 | 0bee699e | bellard | |
1244 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1245 | 38bc628b | blueswir1 | { |
1246 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1247 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1248 | 38bc628b | blueswir1 | } |
1249 | 38bc628b | blueswir1 | |
1250 | 8393617c | Blue Swirl | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, |
1251 | 8393617c | Blue Swirl | DisasContext *dc) |
1252 | 19f329ad | blueswir1 | { |
1253 | a7812ae4 | pbrook | TCGv_i32 r_src; |
1254 | 3475187d | bellard | |
1255 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1256 | 19f329ad | blueswir1 | if (cc)
|
1257 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1258 | 19f329ad | blueswir1 | else
|
1259 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1260 | 3475187d | bellard | #else
|
1261 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1262 | 3475187d | bellard | #endif
|
1263 | 8393617c | Blue Swirl | switch (dc->cc_op) {
|
1264 | 8393617c | Blue Swirl | case CC_OP_FLAGS:
|
1265 | 8393617c | Blue Swirl | break;
|
1266 | 8393617c | Blue Swirl | default:
|
1267 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1268 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1269 | 8393617c | Blue Swirl | break;
|
1270 | 8393617c | Blue Swirl | } |
1271 | 19f329ad | blueswir1 | switch (cond) {
|
1272 | 19f329ad | blueswir1 | case 0x0: |
1273 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1274 | 19f329ad | blueswir1 | break;
|
1275 | 19f329ad | blueswir1 | case 0x1: |
1276 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
1277 | 19f329ad | blueswir1 | break;
|
1278 | 19f329ad | blueswir1 | case 0x2: |
1279 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
1280 | 19f329ad | blueswir1 | break;
|
1281 | 19f329ad | blueswir1 | case 0x3: |
1282 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
1283 | 19f329ad | blueswir1 | break;
|
1284 | 19f329ad | blueswir1 | case 0x4: |
1285 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
1286 | 19f329ad | blueswir1 | break;
|
1287 | 19f329ad | blueswir1 | case 0x5: |
1288 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
1289 | 19f329ad | blueswir1 | break;
|
1290 | 19f329ad | blueswir1 | case 0x6: |
1291 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
1292 | 19f329ad | blueswir1 | break;
|
1293 | 19f329ad | blueswir1 | case 0x7: |
1294 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
1295 | 19f329ad | blueswir1 | break;
|
1296 | 19f329ad | blueswir1 | case 0x8: |
1297 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1298 | 19f329ad | blueswir1 | break;
|
1299 | 19f329ad | blueswir1 | case 0x9: |
1300 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
1301 | 19f329ad | blueswir1 | break;
|
1302 | 19f329ad | blueswir1 | case 0xa: |
1303 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1304 | 19f329ad | blueswir1 | break;
|
1305 | 19f329ad | blueswir1 | case 0xb: |
1306 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1307 | 19f329ad | blueswir1 | break;
|
1308 | 19f329ad | blueswir1 | case 0xc: |
1309 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1310 | 19f329ad | blueswir1 | break;
|
1311 | 19f329ad | blueswir1 | case 0xd: |
1312 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1313 | 19f329ad | blueswir1 | break;
|
1314 | 19f329ad | blueswir1 | case 0xe: |
1315 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1316 | 19f329ad | blueswir1 | break;
|
1317 | 19f329ad | blueswir1 | case 0xf: |
1318 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1319 | 19f329ad | blueswir1 | break;
|
1320 | 19f329ad | blueswir1 | } |
1321 | 19f329ad | blueswir1 | } |
1322 | 7a3f1944 | bellard | |
1323 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1324 | e8af50a3 | bellard | { |
1325 | 19f329ad | blueswir1 | unsigned int offset; |
1326 | 19f329ad | blueswir1 | |
1327 | 19f329ad | blueswir1 | switch (cc) {
|
1328 | 19f329ad | blueswir1 | default:
|
1329 | 19f329ad | blueswir1 | case 0x0: |
1330 | 19f329ad | blueswir1 | offset = 0;
|
1331 | 19f329ad | blueswir1 | break;
|
1332 | 19f329ad | blueswir1 | case 0x1: |
1333 | 19f329ad | blueswir1 | offset = 32 - 10; |
1334 | 19f329ad | blueswir1 | break;
|
1335 | 19f329ad | blueswir1 | case 0x2: |
1336 | 19f329ad | blueswir1 | offset = 34 - 10; |
1337 | 19f329ad | blueswir1 | break;
|
1338 | 19f329ad | blueswir1 | case 0x3: |
1339 | 19f329ad | blueswir1 | offset = 36 - 10; |
1340 | 19f329ad | blueswir1 | break;
|
1341 | 19f329ad | blueswir1 | } |
1342 | 19f329ad | blueswir1 | |
1343 | 19f329ad | blueswir1 | switch (cond) {
|
1344 | 19f329ad | blueswir1 | case 0x0: |
1345 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1346 | 19f329ad | blueswir1 | break;
|
1347 | 19f329ad | blueswir1 | case 0x1: |
1348 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1349 | 19f329ad | blueswir1 | break;
|
1350 | 19f329ad | blueswir1 | case 0x2: |
1351 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1352 | 19f329ad | blueswir1 | break;
|
1353 | 19f329ad | blueswir1 | case 0x3: |
1354 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1355 | 19f329ad | blueswir1 | break;
|
1356 | 19f329ad | blueswir1 | case 0x4: |
1357 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1358 | 19f329ad | blueswir1 | break;
|
1359 | 19f329ad | blueswir1 | case 0x5: |
1360 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1361 | 19f329ad | blueswir1 | break;
|
1362 | 19f329ad | blueswir1 | case 0x6: |
1363 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1364 | 19f329ad | blueswir1 | break;
|
1365 | 19f329ad | blueswir1 | case 0x7: |
1366 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1367 | 19f329ad | blueswir1 | break;
|
1368 | 19f329ad | blueswir1 | case 0x8: |
1369 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1370 | 19f329ad | blueswir1 | break;
|
1371 | 19f329ad | blueswir1 | case 0x9: |
1372 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1373 | 19f329ad | blueswir1 | break;
|
1374 | 19f329ad | blueswir1 | case 0xa: |
1375 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1376 | 19f329ad | blueswir1 | break;
|
1377 | 19f329ad | blueswir1 | case 0xb: |
1378 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1379 | 19f329ad | blueswir1 | break;
|
1380 | 19f329ad | blueswir1 | case 0xc: |
1381 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1382 | 19f329ad | blueswir1 | break;
|
1383 | 19f329ad | blueswir1 | case 0xd: |
1384 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1385 | 19f329ad | blueswir1 | break;
|
1386 | 19f329ad | blueswir1 | case 0xe: |
1387 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1388 | 19f329ad | blueswir1 | break;
|
1389 | 19f329ad | blueswir1 | case 0xf: |
1390 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1391 | 19f329ad | blueswir1 | break;
|
1392 | 19f329ad | blueswir1 | } |
1393 | e8af50a3 | bellard | } |
1394 | 00f219bf | blueswir1 | |
1395 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1396 | 00f219bf | blueswir1 | // Inverted logic
|
1397 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1398 | 00f219bf | blueswir1 | -1,
|
1399 | 00f219bf | blueswir1 | TCG_COND_NE, |
1400 | 00f219bf | blueswir1 | TCG_COND_GT, |
1401 | 00f219bf | blueswir1 | TCG_COND_GE, |
1402 | 00f219bf | blueswir1 | -1,
|
1403 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1404 | 00f219bf | blueswir1 | TCG_COND_LE, |
1405 | 00f219bf | blueswir1 | TCG_COND_LT, |
1406 | 00f219bf | blueswir1 | }; |
1407 | 19f329ad | blueswir1 | |
1408 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1409 | 19f329ad | blueswir1 | { |
1410 | 19f329ad | blueswir1 | int l1;
|
1411 | 19f329ad | blueswir1 | |
1412 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1413 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1414 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1415 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1416 | 19f329ad | blueswir1 | gen_set_label(l1); |
1417 | 19f329ad | blueswir1 | } |
1418 | 3475187d | bellard | #endif
|
1419 | cf495bcf | bellard | |
1420 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1421 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1422 | 4af984a7 | blueswir1 | TCGv r_cond) |
1423 | 7a3f1944 | bellard | { |
1424 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1425 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1426 | 5fafdf24 | ths | |
1427 | cf495bcf | bellard | if (cond == 0x0) { |
1428 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1429 | 0f8a249a | blueswir1 | if (a) {
|
1430 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1431 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1432 | 0f8a249a | blueswir1 | } else {
|
1433 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1434 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1435 | 0f8a249a | blueswir1 | } |
1436 | cf495bcf | bellard | } else if (cond == 0x8) { |
1437 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1438 | 0f8a249a | blueswir1 | if (a) {
|
1439 | 0f8a249a | blueswir1 | dc->pc = target; |
1440 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1441 | 0f8a249a | blueswir1 | } else {
|
1442 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1443 | 0f8a249a | blueswir1 | dc->npc = target; |
1444 | 0f8a249a | blueswir1 | } |
1445 | cf495bcf | bellard | } else {
|
1446 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1447 | 8393617c | Blue Swirl | gen_cond(r_cond, cc, cond, dc); |
1448 | 0f8a249a | blueswir1 | if (a) {
|
1449 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1450 | cf495bcf | bellard | dc->is_br = 1;
|
1451 | 0f8a249a | blueswir1 | } else {
|
1452 | cf495bcf | bellard | dc->pc = dc->npc; |
1453 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1454 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1455 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1456 | 0f8a249a | blueswir1 | } |
1457 | cf495bcf | bellard | } |
1458 | 7a3f1944 | bellard | } |
1459 | 7a3f1944 | bellard | |
1460 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1461 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1462 | 4af984a7 | blueswir1 | TCGv r_cond) |
1463 | e8af50a3 | bellard | { |
1464 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1465 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1466 | af7bf89b | bellard | |
1467 | e8af50a3 | bellard | if (cond == 0x0) { |
1468 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1469 | 0f8a249a | blueswir1 | if (a) {
|
1470 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1471 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1472 | 0f8a249a | blueswir1 | } else {
|
1473 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1474 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1475 | 0f8a249a | blueswir1 | } |
1476 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1477 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1478 | 0f8a249a | blueswir1 | if (a) {
|
1479 | 0f8a249a | blueswir1 | dc->pc = target; |
1480 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1481 | 0f8a249a | blueswir1 | } else {
|
1482 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1483 | 0f8a249a | blueswir1 | dc->npc = target; |
1484 | 0f8a249a | blueswir1 | } |
1485 | e8af50a3 | bellard | } else {
|
1486 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1487 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1488 | 0f8a249a | blueswir1 | if (a) {
|
1489 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1490 | e8af50a3 | bellard | dc->is_br = 1;
|
1491 | 0f8a249a | blueswir1 | } else {
|
1492 | e8af50a3 | bellard | dc->pc = dc->npc; |
1493 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1494 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1495 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1496 | 0f8a249a | blueswir1 | } |
1497 | e8af50a3 | bellard | } |
1498 | e8af50a3 | bellard | } |
1499 | e8af50a3 | bellard | |
1500 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1501 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1502 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1503 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1504 | 7a3f1944 | bellard | { |
1505 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1506 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1507 | 3475187d | bellard | |
1508 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1509 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1510 | 3475187d | bellard | if (a) {
|
1511 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1512 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1513 | 3475187d | bellard | } else {
|
1514 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1515 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1516 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1517 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1518 | 3475187d | bellard | } |
1519 | 7a3f1944 | bellard | } |
1520 | 7a3f1944 | bellard | |
1521 | a7812ae4 | pbrook | static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1522 | 7e8c2b6c | blueswir1 | { |
1523 | 714547bb | blueswir1 | switch (fccno) {
|
1524 | 714547bb | blueswir1 | case 0: |
1525 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1526 | 714547bb | blueswir1 | break;
|
1527 | 714547bb | blueswir1 | case 1: |
1528 | a7812ae4 | pbrook | gen_helper_fcmps_fcc1(r_rs1, r_rs2); |
1529 | 714547bb | blueswir1 | break;
|
1530 | 714547bb | blueswir1 | case 2: |
1531 | a7812ae4 | pbrook | gen_helper_fcmps_fcc2(r_rs1, r_rs2); |
1532 | 714547bb | blueswir1 | break;
|
1533 | 714547bb | blueswir1 | case 3: |
1534 | a7812ae4 | pbrook | gen_helper_fcmps_fcc3(r_rs1, r_rs2); |
1535 | 714547bb | blueswir1 | break;
|
1536 | 714547bb | blueswir1 | } |
1537 | 7e8c2b6c | blueswir1 | } |
1538 | 7e8c2b6c | blueswir1 | |
1539 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1540 | 7e8c2b6c | blueswir1 | { |
1541 | a7812ae4 | pbrook | switch (fccno) {
|
1542 | a7812ae4 | pbrook | case 0: |
1543 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1544 | a7812ae4 | pbrook | break;
|
1545 | a7812ae4 | pbrook | case 1: |
1546 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc1(); |
1547 | a7812ae4 | pbrook | break;
|
1548 | a7812ae4 | pbrook | case 2: |
1549 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc2(); |
1550 | a7812ae4 | pbrook | break;
|
1551 | a7812ae4 | pbrook | case 3: |
1552 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc3(); |
1553 | a7812ae4 | pbrook | break;
|
1554 | a7812ae4 | pbrook | } |
1555 | 7e8c2b6c | blueswir1 | } |
1556 | 7e8c2b6c | blueswir1 | |
1557 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1558 | 7e8c2b6c | blueswir1 | { |
1559 | a7812ae4 | pbrook | switch (fccno) {
|
1560 | a7812ae4 | pbrook | case 0: |
1561 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1562 | a7812ae4 | pbrook | break;
|
1563 | a7812ae4 | pbrook | case 1: |
1564 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc1(); |
1565 | a7812ae4 | pbrook | break;
|
1566 | a7812ae4 | pbrook | case 2: |
1567 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc2(); |
1568 | a7812ae4 | pbrook | break;
|
1569 | a7812ae4 | pbrook | case 3: |
1570 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc3(); |
1571 | a7812ae4 | pbrook | break;
|
1572 | a7812ae4 | pbrook | } |
1573 | 7e8c2b6c | blueswir1 | } |
1574 | 7e8c2b6c | blueswir1 | |
1575 | a7812ae4 | pbrook | static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1576 | 7e8c2b6c | blueswir1 | { |
1577 | 714547bb | blueswir1 | switch (fccno) {
|
1578 | 714547bb | blueswir1 | case 0: |
1579 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1580 | 714547bb | blueswir1 | break;
|
1581 | 714547bb | blueswir1 | case 1: |
1582 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc1(r_rs1, r_rs2); |
1583 | 714547bb | blueswir1 | break;
|
1584 | 714547bb | blueswir1 | case 2: |
1585 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc2(r_rs1, r_rs2); |
1586 | 714547bb | blueswir1 | break;
|
1587 | 714547bb | blueswir1 | case 3: |
1588 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc3(r_rs1, r_rs2); |
1589 | 714547bb | blueswir1 | break;
|
1590 | 714547bb | blueswir1 | } |
1591 | 7e8c2b6c | blueswir1 | } |
1592 | 7e8c2b6c | blueswir1 | |
1593 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1594 | 7e8c2b6c | blueswir1 | { |
1595 | a7812ae4 | pbrook | switch (fccno) {
|
1596 | a7812ae4 | pbrook | case 0: |
1597 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1598 | a7812ae4 | pbrook | break;
|
1599 | a7812ae4 | pbrook | case 1: |
1600 | a7812ae4 | pbrook | gen_helper_fcmped_fcc1(); |
1601 | a7812ae4 | pbrook | break;
|
1602 | a7812ae4 | pbrook | case 2: |
1603 | a7812ae4 | pbrook | gen_helper_fcmped_fcc2(); |
1604 | a7812ae4 | pbrook | break;
|
1605 | a7812ae4 | pbrook | case 3: |
1606 | a7812ae4 | pbrook | gen_helper_fcmped_fcc3(); |
1607 | a7812ae4 | pbrook | break;
|
1608 | a7812ae4 | pbrook | } |
1609 | 7e8c2b6c | blueswir1 | } |
1610 | 7e8c2b6c | blueswir1 | |
1611 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1612 | 7e8c2b6c | blueswir1 | { |
1613 | a7812ae4 | pbrook | switch (fccno) {
|
1614 | a7812ae4 | pbrook | case 0: |
1615 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1616 | a7812ae4 | pbrook | break;
|
1617 | a7812ae4 | pbrook | case 1: |
1618 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc1(); |
1619 | a7812ae4 | pbrook | break;
|
1620 | a7812ae4 | pbrook | case 2: |
1621 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc2(); |
1622 | a7812ae4 | pbrook | break;
|
1623 | a7812ae4 | pbrook | case 3: |
1624 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc3(); |
1625 | a7812ae4 | pbrook | break;
|
1626 | a7812ae4 | pbrook | } |
1627 | 7e8c2b6c | blueswir1 | } |
1628 | 7e8c2b6c | blueswir1 | |
1629 | 7e8c2b6c | blueswir1 | #else
|
1630 | 7e8c2b6c | blueswir1 | |
1631 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1632 | 7e8c2b6c | blueswir1 | { |
1633 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1634 | 7e8c2b6c | blueswir1 | } |
1635 | 7e8c2b6c | blueswir1 | |
1636 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1637 | 7e8c2b6c | blueswir1 | { |
1638 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1639 | 7e8c2b6c | blueswir1 | } |
1640 | 7e8c2b6c | blueswir1 | |
1641 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1642 | 7e8c2b6c | blueswir1 | { |
1643 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1644 | 7e8c2b6c | blueswir1 | } |
1645 | 7e8c2b6c | blueswir1 | |
1646 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1647 | 7e8c2b6c | blueswir1 | { |
1648 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1649 | 7e8c2b6c | blueswir1 | } |
1650 | 7e8c2b6c | blueswir1 | |
1651 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1652 | 7e8c2b6c | blueswir1 | { |
1653 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1654 | 7e8c2b6c | blueswir1 | } |
1655 | 7e8c2b6c | blueswir1 | |
1656 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1657 | 7e8c2b6c | blueswir1 | { |
1658 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1659 | 7e8c2b6c | blueswir1 | } |
1660 | 7e8c2b6c | blueswir1 | #endif
|
1661 | 7e8c2b6c | blueswir1 | |
1662 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1663 | 134d77a1 | blueswir1 | { |
1664 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1665 | 2ea815ca | blueswir1 | |
1666 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1667 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1668 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1669 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1670 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1671 | 134d77a1 | blueswir1 | } |
1672 | 134d77a1 | blueswir1 | |
1673 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1674 | a80dde08 | bellard | { |
1675 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1676 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1677 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1678 | 2ea815ca | blueswir1 | |
1679 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1680 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1681 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1682 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1683 | a80dde08 | bellard | dc->is_br = 1;
|
1684 | a80dde08 | bellard | return 1; |
1685 | a80dde08 | bellard | } |
1686 | a80dde08 | bellard | #endif
|
1687 | a80dde08 | bellard | return 0; |
1688 | a80dde08 | bellard | } |
1689 | a80dde08 | bellard | |
1690 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1691 | 7e8c2b6c | blueswir1 | { |
1692 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1693 | 7e8c2b6c | blueswir1 | } |
1694 | 7e8c2b6c | blueswir1 | |
1695 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1696 | 7e8c2b6c | blueswir1 | { |
1697 | a7812ae4 | pbrook | gen_helper_clear_float_exceptions(); |
1698 | 7e8c2b6c | blueswir1 | } |
1699 | 7e8c2b6c | blueswir1 | |
1700 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1701 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1702 | a7812ae4 | pbrook | static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) |
1703 | 1a2fb1c0 | blueswir1 | { |
1704 | 95f9397c | blueswir1 | int asi;
|
1705 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1706 | 1a2fb1c0 | blueswir1 | |
1707 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1708 | a7812ae4 | pbrook | r_asi = tcg_temp_new_i32(); |
1709 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1710 | 1a2fb1c0 | blueswir1 | } else {
|
1711 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1712 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1713 | 1a2fb1c0 | blueswir1 | } |
1714 | 0425bee5 | blueswir1 | return r_asi;
|
1715 | 0425bee5 | blueswir1 | } |
1716 | 0425bee5 | blueswir1 | |
1717 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1718 | 77f193da | blueswir1 | int sign)
|
1719 | 0425bee5 | blueswir1 | { |
1720 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1721 | 0425bee5 | blueswir1 | |
1722 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1723 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1724 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1725 | a7812ae4 | pbrook | gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign); |
1726 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1727 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1728 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1729 | 1a2fb1c0 | blueswir1 | } |
1730 | 1a2fb1c0 | blueswir1 | |
1731 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1732 | 1a2fb1c0 | blueswir1 | { |
1733 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1734 | 1a2fb1c0 | blueswir1 | |
1735 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1736 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1737 | a7812ae4 | pbrook | gen_helper_st_asi(addr, src, r_asi, r_size); |
1738 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1739 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1740 | 1a2fb1c0 | blueswir1 | } |
1741 | 1a2fb1c0 | blueswir1 | |
1742 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1743 | 1a2fb1c0 | blueswir1 | { |
1744 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1745 | 1a2fb1c0 | blueswir1 | |
1746 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1747 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1748 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1749 | a7812ae4 | pbrook | gen_helper_ldf_asi(addr, r_asi, r_size, r_rd); |
1750 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1751 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1752 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1753 | 1a2fb1c0 | blueswir1 | } |
1754 | 1a2fb1c0 | blueswir1 | |
1755 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1756 | 1a2fb1c0 | blueswir1 | { |
1757 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1758 | 1a2fb1c0 | blueswir1 | |
1759 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1760 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1761 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1762 | a7812ae4 | pbrook | gen_helper_stf_asi(addr, r_asi, r_size, r_rd); |
1763 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1764 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1765 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1766 | 1a2fb1c0 | blueswir1 | } |
1767 | 1a2fb1c0 | blueswir1 | |
1768 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1769 | 1a2fb1c0 | blueswir1 | { |
1770 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1771 | 1a2fb1c0 | blueswir1 | |
1772 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1773 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1774 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1775 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1776 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1777 | a7812ae4 | pbrook | gen_helper_st_asi(addr, dst, r_asi, r_size); |
1778 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1779 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1780 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1781 | 1a2fb1c0 | blueswir1 | } |
1782 | 1a2fb1c0 | blueswir1 | |
1783 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1784 | 1a2fb1c0 | blueswir1 | { |
1785 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_rd; |
1786 | 1a2fb1c0 | blueswir1 | |
1787 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1788 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1789 | a7812ae4 | pbrook | gen_helper_ldda_asi(addr, r_asi, r_rd); |
1790 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1791 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1792 | 0425bee5 | blueswir1 | } |
1793 | 0425bee5 | blueswir1 | |
1794 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1795 | 0425bee5 | blueswir1 | { |
1796 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1797 | a7ec4229 | blueswir1 | |
1798 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1799 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1800 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1801 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1802 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1803 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1804 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1805 | 1a2fb1c0 | blueswir1 | } |
1806 | 1a2fb1c0 | blueswir1 | |
1807 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1808 | 77f193da | blueswir1 | int rd)
|
1809 | 1a2fb1c0 | blueswir1 | { |
1810 | a7812ae4 | pbrook | TCGv r_val1; |
1811 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1812 | 1a2fb1c0 | blueswir1 | |
1813 | a7812ae4 | pbrook | r_val1 = tcg_temp_new(); |
1814 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1815 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1816 | a7812ae4 | pbrook | gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi); |
1817 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1818 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1819 | 1a2fb1c0 | blueswir1 | } |
1820 | 1a2fb1c0 | blueswir1 | |
1821 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1822 | 77f193da | blueswir1 | int rd)
|
1823 | 1a2fb1c0 | blueswir1 | { |
1824 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1825 | 1a2fb1c0 | blueswir1 | |
1826 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1827 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1828 | a7812ae4 | pbrook | gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi); |
1829 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1830 | 1a2fb1c0 | blueswir1 | } |
1831 | 1a2fb1c0 | blueswir1 | |
1832 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1833 | 1a2fb1c0 | blueswir1 | |
1834 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1835 | 77f193da | blueswir1 | int sign)
|
1836 | 1a2fb1c0 | blueswir1 | { |
1837 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1838 | 1a2fb1c0 | blueswir1 | |
1839 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1840 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1841 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1842 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1843 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1844 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1845 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1846 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1847 | 1a2fb1c0 | blueswir1 | } |
1848 | 1a2fb1c0 | blueswir1 | |
1849 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1850 | 1a2fb1c0 | blueswir1 | { |
1851 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1852 | 1a2fb1c0 | blueswir1 | |
1853 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1854 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1855 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1856 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1857 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1858 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1859 | 1a2fb1c0 | blueswir1 | } |
1860 | 1a2fb1c0 | blueswir1 | |
1861 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1862 | 1a2fb1c0 | blueswir1 | { |
1863 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1864 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1865 | 1a2fb1c0 | blueswir1 | |
1866 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1867 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1868 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1869 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1870 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1871 | a7812ae4 | pbrook | r_val = tcg_temp_new_i64(); |
1872 | a7812ae4 | pbrook | tcg_gen_extu_tl_i64(r_val, dst); |
1873 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1874 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1875 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1876 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1877 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1878 | 1a2fb1c0 | blueswir1 | } |
1879 | 1a2fb1c0 | blueswir1 | |
1880 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1881 | 1a2fb1c0 | blueswir1 | { |
1882 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1883 | 1a2fb1c0 | blueswir1 | |
1884 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1885 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1886 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1887 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1888 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1889 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1890 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1891 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1892 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1893 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1894 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1895 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1896 | 0425bee5 | blueswir1 | } |
1897 | 0425bee5 | blueswir1 | |
1898 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1899 | 0425bee5 | blueswir1 | { |
1900 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1901 | a7ec4229 | blueswir1 | |
1902 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1903 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1904 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1905 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1906 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1907 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1908 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1909 | 1a2fb1c0 | blueswir1 | } |
1910 | 1a2fb1c0 | blueswir1 | #endif
|
1911 | 1a2fb1c0 | blueswir1 | |
1912 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1913 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1914 | 1a2fb1c0 | blueswir1 | { |
1915 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1916 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1917 | 1a2fb1c0 | blueswir1 | |
1918 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1919 | 1a2fb1c0 | blueswir1 | |
1920 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1921 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1922 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1923 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1924 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1925 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1926 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1927 | 1a2fb1c0 | blueswir1 | } |
1928 | 1a2fb1c0 | blueswir1 | #endif
|
1929 | 1a2fb1c0 | blueswir1 | |
1930 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1931 | 9322a4bf | blueswir1 | { |
1932 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1933 | 9322a4bf | blueswir1 | unsigned int rs1; |
1934 | 9322a4bf | blueswir1 | |
1935 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1936 | 9322a4bf | blueswir1 | if (rs1 == 0) |
1937 | 5c6a0628 | blueswir1 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
1938 | 9322a4bf | blueswir1 | else if (rs1 < 8) |
1939 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1940 | 9322a4bf | blueswir1 | else
|
1941 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1942 | 9322a4bf | blueswir1 | return r_rs1;
|
1943 | 9322a4bf | blueswir1 | } |
1944 | 9322a4bf | blueswir1 | |
1945 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1946 | a49d9390 | blueswir1 | { |
1947 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1948 | a49d9390 | blueswir1 | |
1949 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1950 | 67526b20 | Blue Swirl | target_long simm; |
1951 | 67526b20 | Blue Swirl | |
1952 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
1953 | 67526b20 | Blue Swirl | r_rs2 = tcg_const_tl(simm); // XXX how to free?
|
1954 | a49d9390 | blueswir1 | } else { /* register */ |
1955 | 67526b20 | Blue Swirl | unsigned int rs2; |
1956 | 67526b20 | Blue Swirl | |
1957 | a49d9390 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1958 | a49d9390 | blueswir1 | if (rs2 == 0) |
1959 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
1960 | a49d9390 | blueswir1 | else if (rs2 < 8) |
1961 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1962 | a49d9390 | blueswir1 | else
|
1963 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1964 | a49d9390 | blueswir1 | } |
1965 | a49d9390 | blueswir1 | return r_rs2;
|
1966 | a49d9390 | blueswir1 | } |
1967 | a49d9390 | blueswir1 | |
1968 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1969 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1970 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1971 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1972 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1973 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1974 | 64a88d5d | blueswir1 | |
1975 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1976 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1977 | cf495bcf | bellard | { |
1978 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1979 | 67526b20 | Blue Swirl | target_long simm; |
1980 | 7a3f1944 | bellard | |
1981 | 8fec2b8c | aliguori | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1982 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1983 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1984 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1985 | 7a3f1944 | bellard | |
1986 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1987 | 6ae20372 | blueswir1 | |
1988 | a7812ae4 | pbrook | cpu_src1 = tcg_temp_new(); // const
|
1989 | a7812ae4 | pbrook | cpu_src2 = tcg_temp_new(); // const
|
1990 | 6ae20372 | blueswir1 | |
1991 | cf495bcf | bellard | switch (opc) {
|
1992 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1993 | 0f8a249a | blueswir1 | { |
1994 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1995 | 0f8a249a | blueswir1 | int32_t target; |
1996 | 0f8a249a | blueswir1 | switch (xop) {
|
1997 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1998 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1999 | 0f8a249a | blueswir1 | { |
2000 | 0f8a249a | blueswir1 | int cc;
|
2001 | 0f8a249a | blueswir1 | |
2002 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
2003 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
2004 | 0f8a249a | blueswir1 | target <<= 2;
|
2005 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
2006 | 0f8a249a | blueswir1 | if (cc == 0) |
2007 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
2008 | 0f8a249a | blueswir1 | else if (cc == 2) |
2009 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
2010 | 0f8a249a | blueswir1 | else
|
2011 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2012 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2013 | 0f8a249a | blueswir1 | } |
2014 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
2015 | 0f8a249a | blueswir1 | { |
2016 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
2017 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
2018 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
2019 | 0f8a249a | blueswir1 | target <<= 2;
|
2020 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2021 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
2022 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2023 | 0f8a249a | blueswir1 | } |
2024 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
2025 | 0f8a249a | blueswir1 | { |
2026 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
2027 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2028 | a80dde08 | bellard | goto jmp_insn;
|
2029 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
2030 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
2031 | 0f8a249a | blueswir1 | target <<= 2;
|
2032 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
2033 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2034 | 0f8a249a | blueswir1 | } |
2035 | a4d17f19 | blueswir1 | #else
|
2036 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
2037 | 0f8a249a | blueswir1 | { |
2038 | 0f8a249a | blueswir1 | goto ncp_insn;
|
2039 | 0f8a249a | blueswir1 | } |
2040 | 0f8a249a | blueswir1 | #endif
|
2041 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
2042 | 0f8a249a | blueswir1 | { |
2043 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
2044 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
2045 | 0f8a249a | blueswir1 | target <<= 2;
|
2046 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
2047 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2048 | 0f8a249a | blueswir1 | } |
2049 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
2050 | 0f8a249a | blueswir1 | { |
2051 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2052 | a80dde08 | bellard | goto jmp_insn;
|
2053 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
2054 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
2055 | 0f8a249a | blueswir1 | target <<= 2;
|
2056 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
2057 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2058 | 0f8a249a | blueswir1 | } |
2059 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
2060 | 0f8a249a | blueswir1 | if (rd) { // nop |
2061 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
2062 | 2ea815ca | blueswir1 | TCGv r_const; |
2063 | 2ea815ca | blueswir1 | |
2064 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
2065 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2066 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2067 | 0f8a249a | blueswir1 | } |
2068 | 0f8a249a | blueswir1 | break;
|
2069 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
2070 | 0f8a249a | blueswir1 | default:
|
2071 | 3475187d | bellard | goto illegal_insn;
|
2072 | 0f8a249a | blueswir1 | } |
2073 | 0f8a249a | blueswir1 | break;
|
2074 | 0f8a249a | blueswir1 | } |
2075 | 0f8a249a | blueswir1 | break;
|
2076 | dc1a6971 | Blue Swirl | case 1: /*CALL*/ |
2077 | dc1a6971 | Blue Swirl | { |
2078 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
2079 | 2ea815ca | blueswir1 | TCGv r_const; |
2080 | cf495bcf | bellard | |
2081 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2082 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
2083 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2084 | 0f8a249a | blueswir1 | target += dc->pc; |
2085 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
2086 | 0f8a249a | blueswir1 | dc->npc = target; |
2087 | 0f8a249a | blueswir1 | } |
2088 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2089 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
2090 | 0f8a249a | blueswir1 | { |
2091 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
2092 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
2093 | cf495bcf | bellard | int cond;
|
2094 | 3475187d | bellard | |
2095 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2096 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
2097 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
2098 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
2099 | cf495bcf | bellard | } else {
|
2100 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2101 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2102 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2103 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2104 | 6f551262 | blueswir1 | } else
|
2105 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
2106 | cf495bcf | bellard | } |
2107 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
2108 | cf495bcf | bellard | if (cond == 0x8) { |
2109 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2110 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
2111 | b158a785 | blueswir1 | supervisor(dc)) |
2112 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
2113 | b158a785 | blueswir1 | else
|
2114 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
2115 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
2116 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
2117 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
2118 | af7bf89b | bellard | } else if (cond != 0) { |
2119 | a7812ae4 | pbrook | TCGv r_cond = tcg_temp_new(); |
2120 | b158a785 | blueswir1 | int l1;
|
2121 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2122 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2123 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2124 | 748b9d8e | blueswir1 | |
2125 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2126 | 0f8a249a | blueswir1 | if (cc == 0) |
2127 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
2128 | 0f8a249a | blueswir1 | else if (cc == 2) |
2129 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
2130 | 0f8a249a | blueswir1 | else
|
2131 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2132 | 3475187d | bellard | #else
|
2133 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2134 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
2135 | 3475187d | bellard | #endif
|
2136 | b158a785 | blueswir1 | l1 = gen_new_label(); |
2137 | b158a785 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
2138 | b158a785 | blueswir1 | |
2139 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
2140 | b158a785 | blueswir1 | supervisor(dc)) |
2141 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
2142 | b158a785 | blueswir1 | else
|
2143 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
2144 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
2145 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
2146 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
2147 | b158a785 | blueswir1 | |
2148 | b158a785 | blueswir1 | gen_set_label(l1); |
2149 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
2150 | cf495bcf | bellard | } |
2151 | a80dde08 | bellard | gen_op_next_insn(); |
2152 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2153 | a80dde08 | bellard | dc->is_br = 1;
|
2154 | a80dde08 | bellard | goto jmp_insn;
|
2155 | cf495bcf | bellard | } else if (xop == 0x28) { |
2156 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2157 | cf495bcf | bellard | switch(rs1) {
|
2158 | cf495bcf | bellard | case 0: /* rdy */ |
2159 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2160 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2161 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2162 | 65fe7b09 | blueswir1 | II */
|
2163 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2164 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2165 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2166 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2167 | 65fe7b09 | blueswir1 | microSPARC II */
|
2168 | 65fe7b09 | blueswir1 | #endif
|
2169 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_y); |
2170 | cf495bcf | bellard | break;
|
2171 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2172 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2173 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2174 | a7812ae4 | pbrook | gen_helper_rdccr(cpu_dst); |
2175 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2176 | 3475187d | bellard | break;
|
2177 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2178 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
2179 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2180 | 3475187d | bellard | break;
|
2181 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2182 | ccd4a219 | blueswir1 | { |
2183 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2184 | ccd4a219 | blueswir1 | |
2185 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2186 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2187 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2188 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
2189 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2190 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2191 | ccd4a219 | blueswir1 | } |
2192 | 3475187d | bellard | break;
|
2193 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2194 | 2ea815ca | blueswir1 | { |
2195 | 2ea815ca | blueswir1 | TCGv r_const; |
2196 | 2ea815ca | blueswir1 | |
2197 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2198 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2199 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2200 | 2ea815ca | blueswir1 | } |
2201 | 0f8a249a | blueswir1 | break;
|
2202 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2203 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
2204 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2205 | 3475187d | bellard | break;
|
2206 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2207 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2208 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2209 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2210 | 725cb90b | bellard | goto jmp_insn;
|
2211 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_gsr); |
2212 | 725cb90b | bellard | break;
|
2213 | 9d926598 | blueswir1 | case 0x16: /* Softint */ |
2214 | 9d926598 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); |
2215 | 9d926598 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2216 | 9d926598 | blueswir1 | break;
|
2217 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2218 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
2219 | 83469015 | bellard | break;
|
2220 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2221 | ccd4a219 | blueswir1 | { |
2222 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2223 | ccd4a219 | blueswir1 | |
2224 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2225 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2226 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
2227 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
2228 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2229 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2230 | ccd4a219 | blueswir1 | } |
2231 | 83469015 | bellard | break;
|
2232 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2233 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
2234 | 83469015 | bellard | break;
|
2235 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2236 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2237 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2238 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2239 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2240 | 3475187d | bellard | #endif
|
2241 | 3475187d | bellard | default:
|
2242 | cf495bcf | bellard | goto illegal_insn;
|
2243 | cf495bcf | bellard | } |
2244 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2245 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2246 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2247 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2248 | 0f8a249a | blueswir1 | goto priv_insn;
|
2249 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2250 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
2251 | a7812ae4 | pbrook | gen_helper_rdpsr(cpu_dst); |
2252 | e9ebed4d | blueswir1 | #else
|
2253 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2254 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2255 | e9ebed4d | blueswir1 | goto priv_insn;
|
2256 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2257 | e9ebed4d | blueswir1 | switch (rs1) {
|
2258 | e9ebed4d | blueswir1 | case 0: // hpstate |
2259 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2260 | e9ebed4d | blueswir1 | break;
|
2261 | e9ebed4d | blueswir1 | case 1: // htstate |
2262 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2263 | e9ebed4d | blueswir1 | break;
|
2264 | e9ebed4d | blueswir1 | case 3: // hintp |
2265 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
2266 | e9ebed4d | blueswir1 | break;
|
2267 | e9ebed4d | blueswir1 | case 5: // htba |
2268 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
2269 | e9ebed4d | blueswir1 | break;
|
2270 | e9ebed4d | blueswir1 | case 6: // hver |
2271 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
2272 | e9ebed4d | blueswir1 | break;
|
2273 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2274 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
2275 | e9ebed4d | blueswir1 | break;
|
2276 | e9ebed4d | blueswir1 | default:
|
2277 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2278 | e9ebed4d | blueswir1 | } |
2279 | e9ebed4d | blueswir1 | #endif
|
2280 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2281 | e8af50a3 | bellard | break;
|
2282 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2283 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2284 | 0f8a249a | blueswir1 | goto priv_insn;
|
2285 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2286 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2287 | 0f8a249a | blueswir1 | switch (rs1) {
|
2288 | 0f8a249a | blueswir1 | case 0: // tpc |
2289 | 375ee38b | blueswir1 | { |
2290 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2291 | 375ee38b | blueswir1 | |
2292 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2293 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2294 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2295 | a7812ae4 | pbrook | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2296 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2297 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2298 | 375ee38b | blueswir1 | } |
2299 | 0f8a249a | blueswir1 | break;
|
2300 | 0f8a249a | blueswir1 | case 1: // tnpc |
2301 | 375ee38b | blueswir1 | { |
2302 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2303 | 375ee38b | blueswir1 | |
2304 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2305 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2306 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2307 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2308 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2309 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2310 | 375ee38b | blueswir1 | } |
2311 | 0f8a249a | blueswir1 | break;
|
2312 | 0f8a249a | blueswir1 | case 2: // tstate |
2313 | 375ee38b | blueswir1 | { |
2314 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2315 | 375ee38b | blueswir1 | |
2316 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2317 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2318 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2319 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2320 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2321 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2322 | 375ee38b | blueswir1 | } |
2323 | 0f8a249a | blueswir1 | break;
|
2324 | 0f8a249a | blueswir1 | case 3: // tt |
2325 | 375ee38b | blueswir1 | { |
2326 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2327 | 375ee38b | blueswir1 | |
2328 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2329 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2330 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2331 | a7812ae4 | pbrook | tcg_gen_ld_i32(cpu_tmp32, r_tsptr, |
2332 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2333 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2334 | a7812ae4 | pbrook | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2335 | 375ee38b | blueswir1 | } |
2336 | 0f8a249a | blueswir1 | break;
|
2337 | 0f8a249a | blueswir1 | case 4: // tick |
2338 | ccd4a219 | blueswir1 | { |
2339 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2340 | ccd4a219 | blueswir1 | |
2341 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2342 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2343 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2344 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
2345 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2346 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2347 | ccd4a219 | blueswir1 | } |
2348 | 0f8a249a | blueswir1 | break;
|
2349 | 0f8a249a | blueswir1 | case 5: // tba |
2350 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2351 | 0f8a249a | blueswir1 | break;
|
2352 | 0f8a249a | blueswir1 | case 6: // pstate |
2353 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2354 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2355 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2356 | 0f8a249a | blueswir1 | break;
|
2357 | 0f8a249a | blueswir1 | case 7: // tl |
2358 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2359 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2360 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2361 | 0f8a249a | blueswir1 | break;
|
2362 | 0f8a249a | blueswir1 | case 8: // pil |
2363 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2364 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2365 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2366 | 0f8a249a | blueswir1 | break;
|
2367 | 0f8a249a | blueswir1 | case 9: // cwp |
2368 | a7812ae4 | pbrook | gen_helper_rdcwp(cpu_tmp0); |
2369 | 0f8a249a | blueswir1 | break;
|
2370 | 0f8a249a | blueswir1 | case 10: // cansave |
2371 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2372 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2373 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2374 | 0f8a249a | blueswir1 | break;
|
2375 | 0f8a249a | blueswir1 | case 11: // canrestore |
2376 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2377 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2378 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2379 | 0f8a249a | blueswir1 | break;
|
2380 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2381 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2382 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2383 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2384 | 0f8a249a | blueswir1 | break;
|
2385 | 0f8a249a | blueswir1 | case 13: // otherwin |
2386 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2387 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2388 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2389 | 0f8a249a | blueswir1 | break;
|
2390 | 0f8a249a | blueswir1 | case 14: // wstate |
2391 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2392 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2393 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2394 | 0f8a249a | blueswir1 | break;
|
2395 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2396 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2397 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2398 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2399 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2400 | e9ebed4d | blueswir1 | break;
|
2401 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2402 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2403 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2404 | e9ebed4d | blueswir1 | goto priv_insn;
|
2405 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); |
2406 | e9ebed4d | blueswir1 | break;
|
2407 | 0f8a249a | blueswir1 | case 31: // ver |
2408 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2409 | 0f8a249a | blueswir1 | break;
|
2410 | 0f8a249a | blueswir1 | case 15: // fq |
2411 | 0f8a249a | blueswir1 | default:
|
2412 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2413 | 0f8a249a | blueswir1 | } |
2414 | 3475187d | bellard | #else
|
2415 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2416 | 3475187d | bellard | #endif
|
2417 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2418 | e8af50a3 | bellard | break;
|
2419 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2420 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2421 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2422 | a7812ae4 | pbrook | gen_helper_flushw(); |
2423 | 3475187d | bellard | #else
|
2424 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2425 | 0f8a249a | blueswir1 | goto priv_insn;
|
2426 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tbr); |
2427 | 3475187d | bellard | #endif
|
2428 | e8af50a3 | bellard | break;
|
2429 | e8af50a3 | bellard | #endif
|
2430 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2431 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2432 | a80dde08 | bellard | goto jmp_insn;
|
2433 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2434 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2435 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2436 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2437 | 0f8a249a | blueswir1 | switch (xop) {
|
2438 | dc1a6971 | Blue Swirl | case 0x1: /* fmovs */ |
2439 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2440 | dc1a6971 | Blue Swirl | break;
|
2441 | dc1a6971 | Blue Swirl | case 0x5: /* fnegs */ |
2442 | dc1a6971 | Blue Swirl | gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
2443 | dc1a6971 | Blue Swirl | break;
|
2444 | dc1a6971 | Blue Swirl | case 0x9: /* fabss */ |
2445 | dc1a6971 | Blue Swirl | gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
2446 | dc1a6971 | Blue Swirl | break;
|
2447 | dc1a6971 | Blue Swirl | case 0x29: /* fsqrts */ |
2448 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2449 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2450 | dc1a6971 | Blue Swirl | gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
2451 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2452 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2453 | dc1a6971 | Blue Swirl | break;
|
2454 | dc1a6971 | Blue Swirl | case 0x2a: /* fsqrtd */ |
2455 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2456 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2457 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2458 | dc1a6971 | Blue Swirl | gen_helper_fsqrtd(); |
2459 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2460 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2461 | dc1a6971 | Blue Swirl | break;
|
2462 | dc1a6971 | Blue Swirl | case 0x2b: /* fsqrtq */ |
2463 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2464 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2465 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2466 | dc1a6971 | Blue Swirl | gen_helper_fsqrtq(); |
2467 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2468 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2469 | dc1a6971 | Blue Swirl | break;
|
2470 | dc1a6971 | Blue Swirl | case 0x41: /* fadds */ |
2471 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2472 | dc1a6971 | Blue Swirl | gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2473 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2474 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2475 | dc1a6971 | Blue Swirl | break;
|
2476 | dc1a6971 | Blue Swirl | case 0x42: /* faddd */ |
2477 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2478 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2479 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2480 | dc1a6971 | Blue Swirl | gen_helper_faddd(); |
2481 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2482 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2483 | dc1a6971 | Blue Swirl | break;
|
2484 | dc1a6971 | Blue Swirl | case 0x43: /* faddq */ |
2485 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2486 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2487 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2488 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2489 | dc1a6971 | Blue Swirl | gen_helper_faddq(); |
2490 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2491 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2492 | dc1a6971 | Blue Swirl | break;
|
2493 | dc1a6971 | Blue Swirl | case 0x45: /* fsubs */ |
2494 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2495 | dc1a6971 | Blue Swirl | gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2496 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2497 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2498 | dc1a6971 | Blue Swirl | break;
|
2499 | dc1a6971 | Blue Swirl | case 0x46: /* fsubd */ |
2500 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2501 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2502 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2503 | dc1a6971 | Blue Swirl | gen_helper_fsubd(); |
2504 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2505 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2506 | dc1a6971 | Blue Swirl | break;
|
2507 | dc1a6971 | Blue Swirl | case 0x47: /* fsubq */ |
2508 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2509 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2510 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2511 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2512 | dc1a6971 | Blue Swirl | gen_helper_fsubq(); |
2513 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2514 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2515 | dc1a6971 | Blue Swirl | break;
|
2516 | dc1a6971 | Blue Swirl | case 0x49: /* fmuls */ |
2517 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2518 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2519 | dc1a6971 | Blue Swirl | gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2520 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2521 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2522 | dc1a6971 | Blue Swirl | break;
|
2523 | dc1a6971 | Blue Swirl | case 0x4a: /* fmuld */ |
2524 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2525 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2526 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2527 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2528 | dc1a6971 | Blue Swirl | gen_helper_fmuld(); |
2529 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2530 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2531 | dc1a6971 | Blue Swirl | break;
|
2532 | dc1a6971 | Blue Swirl | case 0x4b: /* fmulq */ |
2533 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2534 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2535 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2536 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2537 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2538 | dc1a6971 | Blue Swirl | gen_helper_fmulq(); |
2539 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2540 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2541 | dc1a6971 | Blue Swirl | break;
|
2542 | dc1a6971 | Blue Swirl | case 0x4d: /* fdivs */ |
2543 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2544 | dc1a6971 | Blue Swirl | gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2545 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2546 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2547 | dc1a6971 | Blue Swirl | break;
|
2548 | dc1a6971 | Blue Swirl | case 0x4e: /* fdivd */ |
2549 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2550 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2551 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2552 | dc1a6971 | Blue Swirl | gen_helper_fdivd(); |
2553 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2554 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2555 | dc1a6971 | Blue Swirl | break;
|
2556 | dc1a6971 | Blue Swirl | case 0x4f: /* fdivq */ |
2557 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2558 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2559 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2560 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2561 | dc1a6971 | Blue Swirl | gen_helper_fdivq(); |
2562 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2563 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2564 | dc1a6971 | Blue Swirl | break;
|
2565 | dc1a6971 | Blue Swirl | case 0x69: /* fsmuld */ |
2566 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSMULD); |
2567 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2568 | dc1a6971 | Blue Swirl | gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
2569 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2570 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2571 | dc1a6971 | Blue Swirl | break;
|
2572 | dc1a6971 | Blue Swirl | case 0x6e: /* fdmulq */ |
2573 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2574 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2575 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2576 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2577 | dc1a6971 | Blue Swirl | gen_helper_fdmulq(); |
2578 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2579 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2580 | dc1a6971 | Blue Swirl | break;
|
2581 | dc1a6971 | Blue Swirl | case 0xc4: /* fitos */ |
2582 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2583 | dc1a6971 | Blue Swirl | gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
2584 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2585 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2586 | dc1a6971 | Blue Swirl | break;
|
2587 | dc1a6971 | Blue Swirl | case 0xc6: /* fdtos */ |
2588 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2589 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2590 | dc1a6971 | Blue Swirl | gen_helper_fdtos(cpu_tmp32); |
2591 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2592 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2593 | dc1a6971 | Blue Swirl | break;
|
2594 | dc1a6971 | Blue Swirl | case 0xc7: /* fqtos */ |
2595 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2596 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2597 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2598 | dc1a6971 | Blue Swirl | gen_helper_fqtos(cpu_tmp32); |
2599 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2600 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2601 | dc1a6971 | Blue Swirl | break;
|
2602 | dc1a6971 | Blue Swirl | case 0xc8: /* fitod */ |
2603 | dc1a6971 | Blue Swirl | gen_helper_fitod(cpu_fpr[rs2]); |
2604 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2605 | dc1a6971 | Blue Swirl | break;
|
2606 | dc1a6971 | Blue Swirl | case 0xc9: /* fstod */ |
2607 | dc1a6971 | Blue Swirl | gen_helper_fstod(cpu_fpr[rs2]); |
2608 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2609 | dc1a6971 | Blue Swirl | break;
|
2610 | dc1a6971 | Blue Swirl | case 0xcb: /* fqtod */ |
2611 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2612 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2613 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2614 | dc1a6971 | Blue Swirl | gen_helper_fqtod(); |
2615 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2616 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2617 | dc1a6971 | Blue Swirl | break;
|
2618 | dc1a6971 | Blue Swirl | case 0xcc: /* fitoq */ |
2619 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2620 | dc1a6971 | Blue Swirl | gen_helper_fitoq(cpu_fpr[rs2]); |
2621 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2622 | dc1a6971 | Blue Swirl | break;
|
2623 | dc1a6971 | Blue Swirl | case 0xcd: /* fstoq */ |
2624 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2625 | dc1a6971 | Blue Swirl | gen_helper_fstoq(cpu_fpr[rs2]); |
2626 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2627 | dc1a6971 | Blue Swirl | break;
|
2628 | dc1a6971 | Blue Swirl | case 0xce: /* fdtoq */ |
2629 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2630 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2631 | dc1a6971 | Blue Swirl | gen_helper_fdtoq(); |
2632 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2633 | dc1a6971 | Blue Swirl | break;
|
2634 | dc1a6971 | Blue Swirl | case 0xd1: /* fstoi */ |
2635 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2636 | dc1a6971 | Blue Swirl | gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
2637 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2638 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2639 | dc1a6971 | Blue Swirl | break;
|
2640 | dc1a6971 | Blue Swirl | case 0xd2: /* fdtoi */ |
2641 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2642 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2643 | dc1a6971 | Blue Swirl | gen_helper_fdtoi(cpu_tmp32); |
2644 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2645 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2646 | dc1a6971 | Blue Swirl | break;
|
2647 | dc1a6971 | Blue Swirl | case 0xd3: /* fqtoi */ |
2648 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2649 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2650 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2651 | dc1a6971 | Blue Swirl | gen_helper_fqtoi(cpu_tmp32); |
2652 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2653 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2654 | dc1a6971 | Blue Swirl | break;
|
2655 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2656 | dc1a6971 | Blue Swirl | case 0x2: /* V9 fmovd */ |
2657 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2658 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
2659 | dc1a6971 | Blue Swirl | cpu_fpr[DFPREG(rs2) + 1]);
|
2660 | dc1a6971 | Blue Swirl | break;
|
2661 | dc1a6971 | Blue Swirl | case 0x3: /* V9 fmovq */ |
2662 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2663 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2664 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
|
2665 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 1]);
|
2666 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
|
2667 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 2]);
|
2668 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
|
2669 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 3]);
|
2670 | dc1a6971 | Blue Swirl | break;
|
2671 | dc1a6971 | Blue Swirl | case 0x6: /* V9 fnegd */ |
2672 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2673 | dc1a6971 | Blue Swirl | gen_helper_fnegd(); |
2674 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2675 | dc1a6971 | Blue Swirl | break;
|
2676 | dc1a6971 | Blue Swirl | case 0x7: /* V9 fnegq */ |
2677 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2678 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2679 | dc1a6971 | Blue Swirl | gen_helper_fnegq(); |
2680 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2681 | dc1a6971 | Blue Swirl | break;
|
2682 | dc1a6971 | Blue Swirl | case 0xa: /* V9 fabsd */ |
2683 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2684 | dc1a6971 | Blue Swirl | gen_helper_fabsd(); |
2685 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2686 | dc1a6971 | Blue Swirl | break;
|
2687 | dc1a6971 | Blue Swirl | case 0xb: /* V9 fabsq */ |
2688 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2689 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2690 | dc1a6971 | Blue Swirl | gen_helper_fabsq(); |
2691 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2692 | dc1a6971 | Blue Swirl | break;
|
2693 | dc1a6971 | Blue Swirl | case 0x81: /* V9 fstox */ |
2694 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2695 | dc1a6971 | Blue Swirl | gen_helper_fstox(cpu_fpr[rs2]); |
2696 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2697 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2698 | dc1a6971 | Blue Swirl | break;
|
2699 | dc1a6971 | Blue Swirl | case 0x82: /* V9 fdtox */ |
2700 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2701 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2702 | dc1a6971 | Blue Swirl | gen_helper_fdtox(); |
2703 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2704 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2705 | dc1a6971 | Blue Swirl | break;
|
2706 | dc1a6971 | Blue Swirl | case 0x83: /* V9 fqtox */ |
2707 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2708 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2709 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2710 | dc1a6971 | Blue Swirl | gen_helper_fqtox(); |
2711 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2712 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2713 | dc1a6971 | Blue Swirl | break;
|
2714 | dc1a6971 | Blue Swirl | case 0x84: /* V9 fxtos */ |
2715 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2716 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2717 | dc1a6971 | Blue Swirl | gen_helper_fxtos(cpu_tmp32); |
2718 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2719 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2720 | dc1a6971 | Blue Swirl | break;
|
2721 | dc1a6971 | Blue Swirl | case 0x88: /* V9 fxtod */ |
2722 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2723 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2724 | dc1a6971 | Blue Swirl | gen_helper_fxtod(); |
2725 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2726 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2727 | dc1a6971 | Blue Swirl | break;
|
2728 | dc1a6971 | Blue Swirl | case 0x8c: /* V9 fxtoq */ |
2729 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2730 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2731 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2732 | dc1a6971 | Blue Swirl | gen_helper_fxtoq(); |
2733 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2734 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2735 | dc1a6971 | Blue Swirl | break;
|
2736 | 1f587329 | blueswir1 | #endif
|
2737 | dc1a6971 | Blue Swirl | default:
|
2738 | dc1a6971 | Blue Swirl | goto illegal_insn;
|
2739 | 0f8a249a | blueswir1 | } |
2740 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2741 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2742 | 0f8a249a | blueswir1 | int cond;
|
2743 | 3475187d | bellard | #endif
|
2744 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2745 | a80dde08 | bellard | goto jmp_insn;
|
2746 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2747 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2748 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2749 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2750 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2751 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2752 | dcf24905 | blueswir1 | int l1;
|
2753 | dcf24905 | blueswir1 | |
2754 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2755 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2756 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2757 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2758 | cb63669a | pbrook | 0, l1);
|
2759 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2760 | dcf24905 | blueswir1 | gen_set_label(l1); |
2761 | 0f8a249a | blueswir1 | break;
|
2762 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2763 | dcf24905 | blueswir1 | int l1;
|
2764 | dcf24905 | blueswir1 | |
2765 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2766 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2767 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2768 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2769 | cb63669a | pbrook | 0, l1);
|
2770 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2771 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
2772 | dcf24905 | blueswir1 | gen_set_label(l1); |
2773 | 0f8a249a | blueswir1 | break;
|
2774 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2775 | dcf24905 | blueswir1 | int l1;
|
2776 | dcf24905 | blueswir1 | |
2777 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2778 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2779 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2780 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2781 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2782 | cb63669a | pbrook | 0, l1);
|
2783 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2784 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
2785 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
2786 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
2787 | dcf24905 | blueswir1 | gen_set_label(l1); |
2788 | 1f587329 | blueswir1 | break;
|
2789 | 0f8a249a | blueswir1 | } |
2790 | 0f8a249a | blueswir1 | #endif
|
2791 | 0f8a249a | blueswir1 | switch (xop) {
|
2792 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2793 | 714547bb | blueswir1 | #define FMOVSCC(fcc) \
|
2794 | 19f329ad | blueswir1 | { \ |
2795 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2796 | 19f329ad | blueswir1 | int l1; \
|
2797 | 19f329ad | blueswir1 | \ |
2798 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2799 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2800 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2801 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2802 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2803 | cb63669a | pbrook | 0, l1); \
|
2804 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2805 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2806 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2807 | 714547bb | blueswir1 | } |
2808 | 714547bb | blueswir1 | #define FMOVDCC(fcc) \
|
2809 | 714547bb | blueswir1 | { \ |
2810 | 714547bb | blueswir1 | TCGv r_cond; \ |
2811 | 714547bb | blueswir1 | int l1; \
|
2812 | 714547bb | blueswir1 | \ |
2813 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2814 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2815 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2816 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2817 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2818 | 714547bb | blueswir1 | 0, l1); \
|
2819 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2820 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2821 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2822 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2823 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2824 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2825 | 714547bb | blueswir1 | } |
2826 | 714547bb | blueswir1 | #define FMOVQCC(fcc) \
|
2827 | 714547bb | blueswir1 | { \ |
2828 | 714547bb | blueswir1 | TCGv r_cond; \ |
2829 | 714547bb | blueswir1 | int l1; \
|
2830 | 714547bb | blueswir1 | \ |
2831 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2832 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2833 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2834 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2835 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2836 | 714547bb | blueswir1 | 0, l1); \
|
2837 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2838 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2839 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2840 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2841 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2842 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2843 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2844 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2845 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2846 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2847 | 19f329ad | blueswir1 | } |
2848 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2849 | 714547bb | blueswir1 | FMOVSCC(0);
|
2850 | 0f8a249a | blueswir1 | break;
|
2851 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2852 | 714547bb | blueswir1 | FMOVDCC(0);
|
2853 | 0f8a249a | blueswir1 | break;
|
2854 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2855 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2856 | 714547bb | blueswir1 | FMOVQCC(0);
|
2857 | 1f587329 | blueswir1 | break;
|
2858 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2859 | 714547bb | blueswir1 | FMOVSCC(1);
|
2860 | 0f8a249a | blueswir1 | break;
|
2861 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2862 | 714547bb | blueswir1 | FMOVDCC(1);
|
2863 | 0f8a249a | blueswir1 | break;
|
2864 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2865 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2866 | 714547bb | blueswir1 | FMOVQCC(1);
|
2867 | 1f587329 | blueswir1 | break;
|
2868 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2869 | 714547bb | blueswir1 | FMOVSCC(2);
|
2870 | 0f8a249a | blueswir1 | break;
|
2871 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2872 | 714547bb | blueswir1 | FMOVDCC(2);
|
2873 | 0f8a249a | blueswir1 | break;
|
2874 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2875 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2876 | 714547bb | blueswir1 | FMOVQCC(2);
|
2877 | 1f587329 | blueswir1 | break;
|
2878 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2879 | 714547bb | blueswir1 | FMOVSCC(3);
|
2880 | 0f8a249a | blueswir1 | break;
|
2881 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2882 | 714547bb | blueswir1 | FMOVDCC(3);
|
2883 | 0f8a249a | blueswir1 | break;
|
2884 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2885 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2886 | 714547bb | blueswir1 | FMOVQCC(3);
|
2887 | 1f587329 | blueswir1 | break;
|
2888 | 714547bb | blueswir1 | #undef FMOVSCC
|
2889 | 714547bb | blueswir1 | #undef FMOVDCC
|
2890 | 714547bb | blueswir1 | #undef FMOVQCC
|
2891 | 714547bb | blueswir1 | #define FMOVSCC(icc) \
|
2892 | 714547bb | blueswir1 | { \ |
2893 | 714547bb | blueswir1 | TCGv r_cond; \ |
2894 | 714547bb | blueswir1 | int l1; \
|
2895 | 714547bb | blueswir1 | \ |
2896 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2897 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2898 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2899 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2900 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2901 | 714547bb | blueswir1 | 0, l1); \
|
2902 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2903 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2904 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2905 | 714547bb | blueswir1 | } |
2906 | 714547bb | blueswir1 | #define FMOVDCC(icc) \
|
2907 | 714547bb | blueswir1 | { \ |
2908 | 714547bb | blueswir1 | TCGv r_cond; \ |
2909 | 714547bb | blueswir1 | int l1; \
|
2910 | 714547bb | blueswir1 | \ |
2911 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2912 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2913 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2914 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2915 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2916 | 714547bb | blueswir1 | 0, l1); \
|
2917 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2918 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2919 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2920 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2921 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2922 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2923 | 714547bb | blueswir1 | } |
2924 | 714547bb | blueswir1 | #define FMOVQCC(icc) \
|
2925 | 714547bb | blueswir1 | { \ |
2926 | 714547bb | blueswir1 | TCGv r_cond; \ |
2927 | 714547bb | blueswir1 | int l1; \
|
2928 | 714547bb | blueswir1 | \ |
2929 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2930 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2931 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2932 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2933 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2934 | 714547bb | blueswir1 | 0, l1); \
|
2935 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2936 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2937 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2938 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2939 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2940 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2941 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2942 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2943 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2944 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2945 | 714547bb | blueswir1 | } |
2946 | 19f329ad | blueswir1 | |
2947 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2948 | 714547bb | blueswir1 | FMOVSCC(0);
|
2949 | 0f8a249a | blueswir1 | break;
|
2950 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2951 | 714547bb | blueswir1 | FMOVDCC(0);
|
2952 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2953 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2954 | 714547bb | blueswir1 | FMOVQCC(0);
|
2955 | 1f587329 | blueswir1 | break;
|
2956 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2957 | 714547bb | blueswir1 | FMOVSCC(1);
|
2958 | 0f8a249a | blueswir1 | break;
|
2959 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2960 | 714547bb | blueswir1 | FMOVDCC(1);
|
2961 | 0f8a249a | blueswir1 | break;
|
2962 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2963 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2964 | 714547bb | blueswir1 | FMOVQCC(1);
|
2965 | 1f587329 | blueswir1 | break;
|
2966 | 714547bb | blueswir1 | #undef FMOVSCC
|
2967 | 714547bb | blueswir1 | #undef FMOVDCC
|
2968 | 714547bb | blueswir1 | #undef FMOVQCC
|
2969 | 1f587329 | blueswir1 | #endif
|
2970 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2971 | 714547bb | blueswir1 | gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2972 | 0f8a249a | blueswir1 | break;
|
2973 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2974 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2975 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2976 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2977 | 0f8a249a | blueswir1 | break;
|
2978 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2979 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2980 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2981 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2982 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2983 | 1f587329 | blueswir1 | break;
|
2984 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2985 | 714547bb | blueswir1 | gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2986 | 0f8a249a | blueswir1 | break;
|
2987 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2988 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2989 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2990 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2991 | 0f8a249a | blueswir1 | break;
|
2992 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2993 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2994 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2995 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2996 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2997 | 1f587329 | blueswir1 | break;
|
2998 | 0f8a249a | blueswir1 | default:
|
2999 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3000 | 0f8a249a | blueswir1 | } |
3001 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
3002 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
3003 | e80cfcfc | bellard | |
3004 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3005 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
3006 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
3007 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3008 | 2ea815ca | blueswir1 | TCGv r_const; |
3009 | 2ea815ca | blueswir1 | |
3010 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3011 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3012 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3013 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3014 | 0f8a249a | blueswir1 | } else { /* register */ |
3015 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3016 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
3017 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3018 | 0f8a249a | blueswir1 | } |
3019 | 0f8a249a | blueswir1 | } else {
|
3020 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3021 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3022 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3023 | 67526b20 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
3024 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3025 | 0f8a249a | blueswir1 | } else { /* register */ |
3026 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
3027 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3028 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
3029 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3030 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3031 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3032 | 6f551262 | blueswir1 | } else
|
3033 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
3034 | 0f8a249a | blueswir1 | } |
3035 | 0f8a249a | blueswir1 | } |
3036 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
3037 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
3038 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3039 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3040 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3041 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3042 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
3043 | 1a2fb1c0 | blueswir1 | } else {
|
3044 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
|
3045 | 1a2fb1c0 | blueswir1 | } |
3046 | 0f8a249a | blueswir1 | } else { /* register */ |
3047 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3048 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3049 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3050 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3051 | 1a2fb1c0 | blueswir1 | } else {
|
3052 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3053 | 1a2fb1c0 | blueswir1 | } |
3054 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3055 | 83469015 | bellard | } |
3056 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3057 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
3058 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3059 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3060 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3061 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3062 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
3063 | 1a2fb1c0 | blueswir1 | } else {
|
3064 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3065 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
3066 | 1a2fb1c0 | blueswir1 | } |
3067 | 0f8a249a | blueswir1 | } else { /* register */ |
3068 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3069 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3070 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3071 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3072 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3073 | 1a2fb1c0 | blueswir1 | } else {
|
3074 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3075 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3076 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
3077 | 1a2fb1c0 | blueswir1 | } |
3078 | 83469015 | bellard | } |
3079 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3080 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
3081 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3082 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3083 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3084 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3085 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
3086 | 1a2fb1c0 | blueswir1 | } else {
|
3087 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3088 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
3089 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
3090 | 1a2fb1c0 | blueswir1 | } |
3091 | 0f8a249a | blueswir1 | } else { /* register */ |
3092 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3093 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3094 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3095 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3096 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3097 | 1a2fb1c0 | blueswir1 | } else {
|
3098 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3099 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3100 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
3101 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
3102 | 1a2fb1c0 | blueswir1 | } |
3103 | 83469015 | bellard | } |
3104 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3105 | 83469015 | bellard | #endif
|
3106 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
3107 | cf495bcf | bellard | if (xop < 0x20) { |
3108 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
3109 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
3110 | cf495bcf | bellard | switch (xop & ~0x10) { |
3111 | b89e94af | Blue Swirl | case 0x0: /* add */ |
3112 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3113 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3114 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3115 | 41d72852 | Blue Swirl | gen_op_addi_cc(cpu_dst, cpu_src1, simm); |
3116 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3117 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3118 | 41d72852 | Blue Swirl | } else {
|
3119 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
3120 | 41d72852 | Blue Swirl | } |
3121 | 41d72852 | Blue Swirl | } else {
|
3122 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3123 | 41d72852 | Blue Swirl | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
3124 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3125 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3126 | 41d72852 | Blue Swirl | } else {
|
3127 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3128 | 41d72852 | Blue Swirl | } |
3129 | 41d72852 | Blue Swirl | } |
3130 | cf495bcf | bellard | break;
|
3131 | b89e94af | Blue Swirl | case 0x1: /* and */ |
3132 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3133 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3134 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); |
3135 | 41d72852 | Blue Swirl | } else {
|
3136 | 41d72852 | Blue Swirl | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
3137 | 41d72852 | Blue Swirl | } |
3138 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3139 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3140 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3141 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3142 | 41d72852 | Blue Swirl | } |
3143 | cf495bcf | bellard | break;
|
3144 | b89e94af | Blue Swirl | case 0x2: /* or */ |
3145 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3146 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3147 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
3148 | 41d72852 | Blue Swirl | } else {
|
3149 | 41d72852 | Blue Swirl | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3150 | 41d72852 | Blue Swirl | } |
3151 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3152 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3153 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3154 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3155 | 8393617c | Blue Swirl | } |
3156 | 0f8a249a | blueswir1 | break;
|
3157 | b89e94af | Blue Swirl | case 0x3: /* xor */ |
3158 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3159 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3160 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); |
3161 | 41d72852 | Blue Swirl | } else {
|
3162 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3163 | 41d72852 | Blue Swirl | } |
3164 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3165 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3166 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3167 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3168 | 8393617c | Blue Swirl | } |
3169 | cf495bcf | bellard | break;
|
3170 | b89e94af | Blue Swirl | case 0x4: /* sub */ |
3171 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3172 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3173 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3174 | 41d72852 | Blue Swirl | gen_op_subi_cc(cpu_dst, cpu_src1, simm); |
3175 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3176 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3177 | 41d72852 | Blue Swirl | } else {
|
3178 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_dst, cpu_src1, simm); |
3179 | 41d72852 | Blue Swirl | } |
3180 | 41d72852 | Blue Swirl | } else {
|
3181 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3182 | 41d72852 | Blue Swirl | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
3183 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3184 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3185 | 41d72852 | Blue Swirl | } else {
|
3186 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
3187 | 41d72852 | Blue Swirl | } |
3188 | 41d72852 | Blue Swirl | } |
3189 | cf495bcf | bellard | break;
|
3190 | b89e94af | Blue Swirl | case 0x5: /* andn */ |
3191 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3192 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3193 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); |
3194 | 41d72852 | Blue Swirl | } else {
|
3195 | 41d72852 | Blue Swirl | tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
3196 | 41d72852 | Blue Swirl | } |
3197 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3198 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3199 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3200 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3201 | 8393617c | Blue Swirl | } |
3202 | cf495bcf | bellard | break;
|
3203 | b89e94af | Blue Swirl | case 0x6: /* orn */ |
3204 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3205 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3206 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); |
3207 | 41d72852 | Blue Swirl | } else {
|
3208 | 41d72852 | Blue Swirl | tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
3209 | 41d72852 | Blue Swirl | } |
3210 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3211 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3212 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3213 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3214 | 8393617c | Blue Swirl | } |
3215 | cf495bcf | bellard | break;
|
3216 | b89e94af | Blue Swirl | case 0x7: /* xorn */ |
3217 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3218 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3219 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); |
3220 | 41d72852 | Blue Swirl | } else {
|
3221 | 41d72852 | Blue Swirl | tcg_gen_not_tl(cpu_tmp0, cpu_src2); |
3222 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3223 | 41d72852 | Blue Swirl | } |
3224 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3225 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3226 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3227 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3228 | 8393617c | Blue Swirl | } |
3229 | cf495bcf | bellard | break;
|
3230 | b89e94af | Blue Swirl | case 0x8: /* addx, V9 addc */ |
3231 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3232 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3233 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3234 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3235 | 41d72852 | Blue Swirl | gen_op_addxi_cc(cpu_dst, cpu_src1, simm); |
3236 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
3237 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
3238 | 8393617c | Blue Swirl | } else {
|
3239 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3240 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3241 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
3242 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3243 | 41d72852 | Blue Swirl | } |
3244 | 41d72852 | Blue Swirl | } else {
|
3245 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3246 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3247 | 41d72852 | Blue Swirl | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
3248 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
3249 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
3250 | 8393617c | Blue Swirl | } else {
|
3251 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3252 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3253 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3254 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3255 | 41d72852 | Blue Swirl | } |
3256 | 38bc628b | blueswir1 | } |
3257 | cf495bcf | bellard | break;
|
3258 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3259 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3260 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3261 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3262 | 41d72852 | Blue Swirl | tcg_gen_muli_i64(cpu_dst, cpu_src1, simm); |
3263 | 41d72852 | Blue Swirl | } else {
|
3264 | 41d72852 | Blue Swirl | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
3265 | 41d72852 | Blue Swirl | } |
3266 | ded3ab80 | pbrook | break;
|
3267 | ded3ab80 | pbrook | #endif
|
3268 | b89e94af | Blue Swirl | case 0xa: /* umul */ |
3269 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3270 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
3271 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3272 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3273 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3274 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3275 | 8393617c | Blue Swirl | } |
3276 | cf495bcf | bellard | break;
|
3277 | b89e94af | Blue Swirl | case 0xb: /* smul */ |
3278 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3279 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
3280 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3281 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3282 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3283 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3284 | 8393617c | Blue Swirl | } |
3285 | cf495bcf | bellard | break;
|
3286 | b89e94af | Blue Swirl | case 0xc: /* subx, V9 subc */ |
3287 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3288 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3289 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3290 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3291 | 41d72852 | Blue Swirl | gen_op_subxi_cc(cpu_dst, cpu_src1, simm); |
3292 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3293 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3294 | 41d72852 | Blue Swirl | } else {
|
3295 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3296 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3297 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
3298 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3299 | 41d72852 | Blue Swirl | } |
3300 | 41d72852 | Blue Swirl | } else {
|
3301 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3302 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3303 | 41d72852 | Blue Swirl | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
3304 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3305 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3306 | 41d72852 | Blue Swirl | } else {
|
3307 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3308 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3309 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3310 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3311 | 41d72852 | Blue Swirl | } |
3312 | 38bc628b | blueswir1 | } |
3313 | cf495bcf | bellard | break;
|
3314 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3315 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3316 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3317 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3318 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3319 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3320 | ded3ab80 | pbrook | break;
|
3321 | ded3ab80 | pbrook | #endif
|
3322 | b89e94af | Blue Swirl | case 0xe: /* udiv */ |
3323 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3324 | a7812ae4 | pbrook | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
3325 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3326 | 6ae20372 | blueswir1 | gen_op_div_cc(cpu_dst); |
3327 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3328 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3329 | 8393617c | Blue Swirl | } |
3330 | cf495bcf | bellard | break;
|
3331 | b89e94af | Blue Swirl | case 0xf: /* sdiv */ |
3332 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3333 | a7812ae4 | pbrook | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
3334 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3335 | 6ae20372 | blueswir1 | gen_op_div_cc(cpu_dst); |
3336 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3337 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3338 | 8393617c | Blue Swirl | } |
3339 | cf495bcf | bellard | break;
|
3340 | cf495bcf | bellard | default:
|
3341 | cf495bcf | bellard | goto illegal_insn;
|
3342 | cf495bcf | bellard | } |
3343 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3344 | cf495bcf | bellard | } else {
|
3345 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
3346 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
3347 | cf495bcf | bellard | switch (xop) {
|
3348 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3349 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3350 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3351 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3352 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3353 | 0f8a249a | blueswir1 | break;
|
3354 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3355 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3356 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3357 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3358 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3359 | 0f8a249a | blueswir1 | break;
|
3360 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3361 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3362 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3363 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3364 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3365 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3366 | 0f8a249a | blueswir1 | break;
|
3367 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3368 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3369 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3370 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3371 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3372 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3373 | 0f8a249a | blueswir1 | break;
|
3374 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3375 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3376 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3377 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3378 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3379 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3380 | cf495bcf | bellard | break;
|
3381 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3382 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3383 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3384 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3385 | 67526b20 | Blue Swirl | tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3386 | e35298cd | blueswir1 | } else { /* register */ |
3387 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3388 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3389 | e35298cd | blueswir1 | } |
3390 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3391 | cf495bcf | bellard | break;
|
3392 | 83469015 | bellard | case 0x26: /* srl */ |
3393 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3394 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3395 | 67526b20 | Blue Swirl | tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3396 | e35298cd | blueswir1 | } else { /* register */ |
3397 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3398 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3399 | e35298cd | blueswir1 | } |
3400 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3401 | cf495bcf | bellard | break;
|
3402 | 83469015 | bellard | case 0x27: /* sra */ |
3403 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3404 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3405 | 67526b20 | Blue Swirl | tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3406 | e35298cd | blueswir1 | } else { /* register */ |
3407 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3408 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3409 | e35298cd | blueswir1 | } |
3410 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3411 | cf495bcf | bellard | break;
|
3412 | 83469015 | bellard | #endif
|
3413 | cf495bcf | bellard | case 0x30: |
3414 | cf495bcf | bellard | { |
3415 | cf495bcf | bellard | switch(rd) {
|
3416 | 3475187d | bellard | case 0: /* wry */ |
3417 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3418 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3419 | cf495bcf | bellard | break;
|
3420 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3421 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3422 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3423 | 65fe7b09 | blueswir1 | on the microSPARC
|
3424 | 65fe7b09 | blueswir1 | II */
|
3425 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3426 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3427 | 65fe7b09 | blueswir1 | manual, nop on the
|
3428 | 65fe7b09 | blueswir1 | microSPARC II */
|
3429 | 65fe7b09 | blueswir1 | break;
|
3430 | 65fe7b09 | blueswir1 | #else
|
3431 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3432 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3433 | a7812ae4 | pbrook | gen_helper_wrccr(cpu_dst); |
3434 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3435 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3436 | 0f8a249a | blueswir1 | break;
|
3437 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3438 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3439 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
3440 | 0f8a249a | blueswir1 | break;
|
3441 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3442 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3443 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
3444 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3445 | 3299908c | blueswir1 | gen_op_next_insn(); |
3446 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3447 | 3299908c | blueswir1 | dc->is_br = 1;
|
3448 | 0f8a249a | blueswir1 | break;
|
3449 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3450 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3451 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3452 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3453 | 3475187d | bellard | #endif
|
3454 | 0f8a249a | blueswir1 | break;
|
3455 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3456 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3457 | 725cb90b | bellard | goto jmp_insn;
|
3458 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3459 | 0f8a249a | blueswir1 | break;
|
3460 | 9d926598 | blueswir1 | case 0x14: /* Softint set */ |
3461 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3462 | 9d926598 | blueswir1 | goto illegal_insn;
|
3463 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3464 | a7812ae4 | pbrook | gen_helper_set_softint(cpu_tmp64); |
3465 | 9d926598 | blueswir1 | break;
|
3466 | 9d926598 | blueswir1 | case 0x15: /* Softint clear */ |
3467 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3468 | 9d926598 | blueswir1 | goto illegal_insn;
|
3469 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3470 | a7812ae4 | pbrook | gen_helper_clear_softint(cpu_tmp64); |
3471 | 9d926598 | blueswir1 | break;
|
3472 | 9d926598 | blueswir1 | case 0x16: /* Softint write */ |
3473 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3474 | 9d926598 | blueswir1 | goto illegal_insn;
|
3475 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3476 | a7812ae4 | pbrook | gen_helper_write_softint(cpu_tmp64); |
3477 | 9d926598 | blueswir1 | break;
|
3478 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3479 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3480 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3481 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3482 | 83469015 | bellard | #endif
|
3483 | ccd4a219 | blueswir1 | { |
3484 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3485 | ccd4a219 | blueswir1 | |
3486 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3487 | 6ae20372 | blueswir1 | cpu_src2); |
3488 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3489 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3490 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3491 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3492 | a7812ae4 | pbrook | cpu_tick_cmpr); |
3493 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3494 | ccd4a219 | blueswir1 | } |
3495 | 0f8a249a | blueswir1 | break;
|
3496 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3497 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3498 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3499 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3500 | 83469015 | bellard | #endif
|
3501 | ccd4a219 | blueswir1 | { |
3502 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3503 | ccd4a219 | blueswir1 | |
3504 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3505 | 6ae20372 | blueswir1 | cpu_src2); |
3506 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3507 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3508 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3509 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3510 | a7812ae4 | pbrook | cpu_dst); |
3511 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3512 | ccd4a219 | blueswir1 | } |
3513 | 0f8a249a | blueswir1 | break;
|
3514 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3515 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3516 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3517 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3518 | 3475187d | bellard | #endif
|
3519 | ccd4a219 | blueswir1 | { |
3520 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3521 | ccd4a219 | blueswir1 | |
3522 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3523 | 6ae20372 | blueswir1 | cpu_src2); |
3524 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3525 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3526 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3527 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3528 | a7812ae4 | pbrook | cpu_stick_cmpr); |
3529 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3530 | ccd4a219 | blueswir1 | } |
3531 | 0f8a249a | blueswir1 | break;
|
3532 | 83469015 | bellard | |
3533 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3534 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3535 | 77f193da | blueswir1 | Counter */
|
3536 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3537 | 83469015 | bellard | #endif
|
3538 | 3475187d | bellard | default:
|
3539 | cf495bcf | bellard | goto illegal_insn;
|
3540 | cf495bcf | bellard | } |
3541 | cf495bcf | bellard | } |
3542 | cf495bcf | bellard | break;
|
3543 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3544 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3545 | e8af50a3 | bellard | { |
3546 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3547 | 0f8a249a | blueswir1 | goto priv_insn;
|
3548 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3549 | 0f8a249a | blueswir1 | switch (rd) {
|
3550 | 0f8a249a | blueswir1 | case 0: |
3551 | a7812ae4 | pbrook | gen_helper_saved(); |
3552 | 0f8a249a | blueswir1 | break;
|
3553 | 0f8a249a | blueswir1 | case 1: |
3554 | a7812ae4 | pbrook | gen_helper_restored(); |
3555 | 0f8a249a | blueswir1 | break;
|
3556 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3557 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3558 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3559 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3560 | e9ebed4d | blueswir1 | // XXX
|
3561 | 0f8a249a | blueswir1 | default:
|
3562 | 3475187d | bellard | goto illegal_insn;
|
3563 | 3475187d | bellard | } |
3564 | 3475187d | bellard | #else
|
3565 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3566 | a7812ae4 | pbrook | gen_helper_wrpsr(cpu_dst); |
3567 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3568 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3569 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3570 | 9e61bde5 | bellard | gen_op_next_insn(); |
3571 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3572 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3573 | 3475187d | bellard | #endif
|
3574 | e8af50a3 | bellard | } |
3575 | e8af50a3 | bellard | break;
|
3576 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3577 | e8af50a3 | bellard | { |
3578 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3579 | 0f8a249a | blueswir1 | goto priv_insn;
|
3580 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3581 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3582 | 0f8a249a | blueswir1 | switch (rd) {
|
3583 | 0f8a249a | blueswir1 | case 0: // tpc |
3584 | 375ee38b | blueswir1 | { |
3585 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3586 | 375ee38b | blueswir1 | |
3587 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3588 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3589 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3590 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3591 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3592 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3593 | 375ee38b | blueswir1 | } |
3594 | 0f8a249a | blueswir1 | break;
|
3595 | 0f8a249a | blueswir1 | case 1: // tnpc |
3596 | 375ee38b | blueswir1 | { |
3597 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3598 | 375ee38b | blueswir1 | |
3599 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3600 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3601 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3602 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3603 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3604 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3605 | 375ee38b | blueswir1 | } |
3606 | 0f8a249a | blueswir1 | break;
|
3607 | 0f8a249a | blueswir1 | case 2: // tstate |
3608 | 375ee38b | blueswir1 | { |
3609 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3610 | 375ee38b | blueswir1 | |
3611 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3612 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3613 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3614 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3615 | 77f193da | blueswir1 | offsetof(trap_state, |
3616 | 77f193da | blueswir1 | tstate)); |
3617 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3618 | 375ee38b | blueswir1 | } |
3619 | 0f8a249a | blueswir1 | break;
|
3620 | 0f8a249a | blueswir1 | case 3: // tt |
3621 | 375ee38b | blueswir1 | { |
3622 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3623 | 375ee38b | blueswir1 | |
3624 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3625 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3626 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3627 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3628 | 527067d8 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, r_tsptr, |
3629 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3630 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3631 | 375ee38b | blueswir1 | } |
3632 | 0f8a249a | blueswir1 | break;
|
3633 | 0f8a249a | blueswir1 | case 4: // tick |
3634 | ccd4a219 | blueswir1 | { |
3635 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3636 | ccd4a219 | blueswir1 | |
3637 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3638 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3639 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3640 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3641 | a7812ae4 | pbrook | cpu_tmp0); |
3642 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3643 | ccd4a219 | blueswir1 | } |
3644 | 0f8a249a | blueswir1 | break;
|
3645 | 0f8a249a | blueswir1 | case 5: // tba |
3646 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3647 | 0f8a249a | blueswir1 | break;
|
3648 | 0f8a249a | blueswir1 | case 6: // pstate |
3649 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3650 | a7812ae4 | pbrook | gen_helper_wrpstate(cpu_tmp0); |
3651 | ded3ab80 | pbrook | gen_op_next_insn(); |
3652 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3653 | ded3ab80 | pbrook | dc->is_br = 1;
|
3654 | 0f8a249a | blueswir1 | break;
|
3655 | 0f8a249a | blueswir1 | case 7: // tl |
3656 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3657 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3658 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3659 | 0f8a249a | blueswir1 | break;
|
3660 | 0f8a249a | blueswir1 | case 8: // pil |
3661 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3662 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3663 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3664 | 77f193da | blueswir1 | psrpil)); |
3665 | 0f8a249a | blueswir1 | break;
|
3666 | 0f8a249a | blueswir1 | case 9: // cwp |
3667 | a7812ae4 | pbrook | gen_helper_wrcwp(cpu_tmp0); |
3668 | 0f8a249a | blueswir1 | break;
|
3669 | 0f8a249a | blueswir1 | case 10: // cansave |
3670 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3671 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3672 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3673 | 77f193da | blueswir1 | cansave)); |
3674 | 0f8a249a | blueswir1 | break;
|
3675 | 0f8a249a | blueswir1 | case 11: // canrestore |
3676 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3677 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3678 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3679 | 77f193da | blueswir1 | canrestore)); |
3680 | 0f8a249a | blueswir1 | break;
|
3681 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3682 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3683 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3684 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3685 | 77f193da | blueswir1 | cleanwin)); |
3686 | 0f8a249a | blueswir1 | break;
|
3687 | 0f8a249a | blueswir1 | case 13: // otherwin |
3688 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3689 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3690 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3691 | 77f193da | blueswir1 | otherwin)); |
3692 | 0f8a249a | blueswir1 | break;
|
3693 | 0f8a249a | blueswir1 | case 14: // wstate |
3694 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3695 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3696 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3697 | 77f193da | blueswir1 | wstate)); |
3698 | 0f8a249a | blueswir1 | break;
|
3699 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3700 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3701 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3702 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3703 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3704 | e9ebed4d | blueswir1 | break;
|
3705 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3706 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3707 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3708 | e9ebed4d | blueswir1 | goto priv_insn;
|
3709 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); |
3710 | e9ebed4d | blueswir1 | break;
|
3711 | 0f8a249a | blueswir1 | default:
|
3712 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3713 | 0f8a249a | blueswir1 | } |
3714 | 3475187d | bellard | #else
|
3715 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3716 | c93e7817 | blueswir1 | if (dc->def->nwindows != 32) |
3717 | c93e7817 | blueswir1 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
3718 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3719 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3720 | 3475187d | bellard | #endif
|
3721 | e8af50a3 | bellard | } |
3722 | e8af50a3 | bellard | break;
|
3723 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3724 | e8af50a3 | bellard | { |
3725 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3726 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3727 | 0f8a249a | blueswir1 | goto priv_insn;
|
3728 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3729 | e9ebed4d | blueswir1 | #else
|
3730 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3731 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3732 | e9ebed4d | blueswir1 | goto priv_insn;
|
3733 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3734 | e9ebed4d | blueswir1 | switch (rd) {
|
3735 | e9ebed4d | blueswir1 | case 0: // hpstate |
3736 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3737 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3738 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3739 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3740 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3741 | e9ebed4d | blueswir1 | break;
|
3742 | e9ebed4d | blueswir1 | case 1: // htstate |
3743 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3744 | e9ebed4d | blueswir1 | break;
|
3745 | e9ebed4d | blueswir1 | case 3: // hintp |
3746 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3747 | e9ebed4d | blueswir1 | break;
|
3748 | e9ebed4d | blueswir1 | case 5: // htba |
3749 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3750 | e9ebed4d | blueswir1 | break;
|
3751 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3752 | ccd4a219 | blueswir1 | { |
3753 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3754 | ccd4a219 | blueswir1 | |
3755 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3756 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3757 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3758 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3759 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3760 | a7812ae4 | pbrook | cpu_hstick_cmpr); |
3761 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3762 | ccd4a219 | blueswir1 | } |
3763 | e9ebed4d | blueswir1 | break;
|
3764 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3765 | e9ebed4d | blueswir1 | default:
|
3766 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3767 | e9ebed4d | blueswir1 | } |
3768 | e9ebed4d | blueswir1 | #endif
|
3769 | e8af50a3 | bellard | } |
3770 | e8af50a3 | bellard | break;
|
3771 | e8af50a3 | bellard | #endif
|
3772 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3773 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3774 | 0f8a249a | blueswir1 | { |
3775 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3776 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3777 | 748b9d8e | blueswir1 | TCGv r_cond; |
3778 | 00f219bf | blueswir1 | int l1;
|
3779 | 00f219bf | blueswir1 | |
3780 | a7812ae4 | pbrook | r_cond = tcg_temp_new(); |
3781 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3782 | 0f8a249a | blueswir1 | if (cc == 0) |
3783 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
3784 | 0f8a249a | blueswir1 | else if (cc == 2) |
3785 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
3786 | 0f8a249a | blueswir1 | else
|
3787 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3788 | 0f8a249a | blueswir1 | } else {
|
3789 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3790 | 0f8a249a | blueswir1 | } |
3791 | 00f219bf | blueswir1 | |
3792 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3793 | 00f219bf | blueswir1 | |
3794 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3795 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3796 | 2ea815ca | blueswir1 | TCGv r_const; |
3797 | 2ea815ca | blueswir1 | |
3798 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 10); |
3799 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3800 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3801 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3802 | 00f219bf | blueswir1 | } else {
|
3803 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3804 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3805 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3806 | 00f219bf | blueswir1 | } |
3807 | 00f219bf | blueswir1 | gen_set_label(l1); |
3808 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3809 | 0f8a249a | blueswir1 | break;
|
3810 | 0f8a249a | blueswir1 | } |
3811 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3812 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3813 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3814 | 0f8a249a | blueswir1 | break;
|
3815 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3816 | 0f8a249a | blueswir1 | { |
3817 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3818 | a7812ae4 | pbrook | gen_helper_popc(cpu_dst, cpu_src2); |
3819 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3820 | 0f8a249a | blueswir1 | } |
3821 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3822 | 0f8a249a | blueswir1 | { |
3823 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3824 | 00f219bf | blueswir1 | int l1;
|
3825 | 00f219bf | blueswir1 | |
3826 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3827 | 00f219bf | blueswir1 | |
3828 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3829 | 00f219bf | blueswir1 | |
3830 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3831 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3832 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3833 | 2ea815ca | blueswir1 | TCGv r_const; |
3834 | 2ea815ca | blueswir1 | |
3835 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 9); |
3836 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3837 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3838 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3839 | 00f219bf | blueswir1 | } else {
|
3840 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3841 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3842 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3843 | 0f8a249a | blueswir1 | } |
3844 | 00f219bf | blueswir1 | gen_set_label(l1); |
3845 | 0f8a249a | blueswir1 | break;
|
3846 | 0f8a249a | blueswir1 | } |
3847 | 0f8a249a | blueswir1 | #endif
|
3848 | 0f8a249a | blueswir1 | default:
|
3849 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3850 | 0f8a249a | blueswir1 | } |
3851 | 0f8a249a | blueswir1 | } |
3852 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3853 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3854 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3855 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3856 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3857 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3858 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3859 | 3299908c | blueswir1 | |
3860 | 3299908c | blueswir1 | switch (opf) {
|
3861 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3862 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3863 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3864 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3865 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3866 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3867 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3868 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3869 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3870 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3871 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3872 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3873 | e9ebed4d | blueswir1 | // XXX
|
3874 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3875 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3876 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3877 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3878 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3879 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3880 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3881 | e9ebed4d | blueswir1 | break;
|
3882 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3883 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3884 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3885 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3886 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3887 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3888 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3889 | e9ebed4d | blueswir1 | break;
|
3890 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3891 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3892 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3893 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3894 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3895 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3896 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3897 | e9ebed4d | blueswir1 | break;
|
3898 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3899 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3900 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3901 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3902 | a7812ae4 | pbrook | gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); |
3903 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3904 | 3299908c | blueswir1 | break;
|
3905 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3906 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3907 | 3299908c | blueswir1 | // XXX
|
3908 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3909 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3910 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3911 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3912 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3913 | a7812ae4 | pbrook | gen_helper_fcmple16(); |
3914 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3915 | e9ebed4d | blueswir1 | break;
|
3916 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3917 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3918 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3919 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3920 | a7812ae4 | pbrook | gen_helper_fcmpne16(); |
3921 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3922 | 3299908c | blueswir1 | break;
|
3923 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3924 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3925 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3926 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3927 | a7812ae4 | pbrook | gen_helper_fcmple32(); |
3928 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3929 | e9ebed4d | blueswir1 | break;
|
3930 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3931 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3932 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3933 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3934 | a7812ae4 | pbrook | gen_helper_fcmpne32(); |
3935 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3936 | e9ebed4d | blueswir1 | break;
|
3937 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3938 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3939 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3940 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3941 | a7812ae4 | pbrook | gen_helper_fcmpgt16(); |
3942 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3943 | e9ebed4d | blueswir1 | break;
|
3944 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3945 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3946 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3947 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3948 | a7812ae4 | pbrook | gen_helper_fcmpeq16(); |
3949 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3950 | e9ebed4d | blueswir1 | break;
|
3951 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3952 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3953 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3954 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3955 | a7812ae4 | pbrook | gen_helper_fcmpgt32(); |
3956 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3957 | e9ebed4d | blueswir1 | break;
|
3958 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3959 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3960 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3961 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3962 | a7812ae4 | pbrook | gen_helper_fcmpeq32(); |
3963 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3964 | e9ebed4d | blueswir1 | break;
|
3965 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3966 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3967 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3968 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3969 | a7812ae4 | pbrook | gen_helper_fmul8x16(); |
3970 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3971 | e9ebed4d | blueswir1 | break;
|
3972 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3973 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3974 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3975 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3976 | a7812ae4 | pbrook | gen_helper_fmul8x16au(); |
3977 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3978 | e9ebed4d | blueswir1 | break;
|
3979 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3980 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3981 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3982 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3983 | a7812ae4 | pbrook | gen_helper_fmul8x16al(); |
3984 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3985 | e9ebed4d | blueswir1 | break;
|
3986 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3987 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3988 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3989 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3990 | a7812ae4 | pbrook | gen_helper_fmul8sux16(); |
3991 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3992 | e9ebed4d | blueswir1 | break;
|
3993 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3994 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3995 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3996 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3997 | a7812ae4 | pbrook | gen_helper_fmul8ulx16(); |
3998 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3999 | e9ebed4d | blueswir1 | break;
|
4000 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
4001 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4002 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4003 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4004 | a7812ae4 | pbrook | gen_helper_fmuld8sux16(); |
4005 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4006 | e9ebed4d | blueswir1 | break;
|
4007 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
4008 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4009 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4010 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4011 | a7812ae4 | pbrook | gen_helper_fmuld8ulx16(); |
4012 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4013 | e9ebed4d | blueswir1 | break;
|
4014 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
4015 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
4016 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
4017 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
4018 | e9ebed4d | blueswir1 | // XXX
|
4019 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4020 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
4021 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4022 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4023 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4024 | a7812ae4 | pbrook | gen_helper_faligndata(); |
4025 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4026 | 3299908c | blueswir1 | break;
|
4027 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
4028 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4029 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4030 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4031 | a7812ae4 | pbrook | gen_helper_fpmerge(); |
4032 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4033 | e9ebed4d | blueswir1 | break;
|
4034 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
4035 | e9ebed4d | blueswir1 | // XXX
|
4036 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4037 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
4038 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4039 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4040 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4041 | a7812ae4 | pbrook | gen_helper_fexpand(); |
4042 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4043 | e9ebed4d | blueswir1 | break;
|
4044 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
4045 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4046 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4047 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4048 | a7812ae4 | pbrook | gen_helper_fpadd16(); |
4049 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4050 | e9ebed4d | blueswir1 | break;
|
4051 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
4052 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4053 | a7812ae4 | pbrook | gen_helper_fpadd16s(cpu_fpr[rd], |
4054 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
4055 | e9ebed4d | blueswir1 | break;
|
4056 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
4057 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4058 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4059 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4060 | a7812ae4 | pbrook | gen_helper_fpadd32(); |
4061 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4062 | e9ebed4d | blueswir1 | break;
|
4063 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
4064 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4065 | a7812ae4 | pbrook | gen_helper_fpadd32s(cpu_fpr[rd], |
4066 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
4067 | e9ebed4d | blueswir1 | break;
|
4068 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
4069 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4070 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4071 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4072 | a7812ae4 | pbrook | gen_helper_fpsub16(); |
4073 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4074 | e9ebed4d | blueswir1 | break;
|
4075 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
4076 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4077 | a7812ae4 | pbrook | gen_helper_fpsub16s(cpu_fpr[rd], |
4078 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
4079 | e9ebed4d | blueswir1 | break;
|
4080 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
4081 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4082 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4083 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4084 | a7812ae4 | pbrook | gen_helper_fpsub32(); |
4085 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4086 | e9ebed4d | blueswir1 | break;
|
4087 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
4088 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4089 | a7812ae4 | pbrook | gen_helper_fpsub32s(cpu_fpr[rd], |
4090 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
4091 | e9ebed4d | blueswir1 | break;
|
4092 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
4093 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4094 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
4095 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
4096 | 3299908c | blueswir1 | break;
|
4097 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
4098 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4099 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], 0);
|
4100 | 3299908c | blueswir1 | break;
|
4101 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
4102 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4103 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
4104 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4105 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
4106 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4107 | e9ebed4d | blueswir1 | break;
|
4108 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
4109 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4110 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
4111 | e9ebed4d | blueswir1 | break;
|
4112 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
4113 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4114 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4115 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4116 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
4117 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4118 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4119 | e9ebed4d | blueswir1 | break;
|
4120 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
4121 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4122 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4123 | e9ebed4d | blueswir1 | break;
|
4124 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
4125 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4126 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
4127 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
4128 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4129 | e9ebed4d | blueswir1 | break;
|
4130 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
4131 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4132 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
4133 | e9ebed4d | blueswir1 | break;
|
4134 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
4135 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4136 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
4137 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
4138 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
4139 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
4140 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4141 | e9ebed4d | blueswir1 | break;
|
4142 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
4143 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4144 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
4145 | e9ebed4d | blueswir1 | break;
|
4146 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
4147 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4148 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
4149 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
4150 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4151 | e9ebed4d | blueswir1 | break;
|
4152 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
4153 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4154 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
4155 | e9ebed4d | blueswir1 | break;
|
4156 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
4157 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4158 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4159 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4160 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
|
4161 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4162 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4163 | e9ebed4d | blueswir1 | break;
|
4164 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
4165 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4166 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4167 | e9ebed4d | blueswir1 | break;
|
4168 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
4169 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4170 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
4171 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4172 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
4173 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4174 | e9ebed4d | blueswir1 | break;
|
4175 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
4176 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4177 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
4178 | e9ebed4d | blueswir1 | break;
|
4179 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
4180 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4181 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4182 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4183 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
|
4184 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4185 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4186 | e9ebed4d | blueswir1 | break;
|
4187 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
4188 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4189 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4190 | e9ebed4d | blueswir1 | break;
|
4191 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
4192 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4193 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
4194 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
4195 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
4196 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
4197 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
4198 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4199 | e9ebed4d | blueswir1 | break;
|
4200 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
4201 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4202 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
4203 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
4204 | e9ebed4d | blueswir1 | break;
|
4205 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
4206 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4207 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
4208 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
4209 | 1d01299d | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4210 | 3299908c | blueswir1 | break;
|
4211 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
4212 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4213 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
4214 | 3299908c | blueswir1 | break;
|
4215 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
4216 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4217 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4218 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4219 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
4220 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4221 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4222 | e9ebed4d | blueswir1 | break;
|
4223 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
4224 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4225 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4226 | e9ebed4d | blueswir1 | break;
|
4227 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
4228 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4229 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
4230 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4231 | 3299908c | blueswir1 | break;
|
4232 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
4233 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4234 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
4235 | 3299908c | blueswir1 | break;
|
4236 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
4237 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4238 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
4239 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
4240 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
4241 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
4242 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4243 | e9ebed4d | blueswir1 | break;
|
4244 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
4245 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4246 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
4247 | e9ebed4d | blueswir1 | break;
|
4248 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
4249 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4250 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4251 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4252 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
|
4253 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4254 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4255 | e9ebed4d | blueswir1 | break;
|
4256 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
4257 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4258 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4259 | e9ebed4d | blueswir1 | break;
|
4260 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
4261 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4262 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
4263 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
4264 | 3299908c | blueswir1 | break;
|
4265 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
4266 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4267 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], -1);
|
4268 | 3299908c | blueswir1 | break;
|
4269 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
4270 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
4271 | e9ebed4d | blueswir1 | // XXX
|
4272 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4273 | 3299908c | blueswir1 | default:
|
4274 | 3299908c | blueswir1 | goto illegal_insn;
|
4275 | 3299908c | blueswir1 | } |
4276 | 3299908c | blueswir1 | #else
|
4277 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4278 | 3299908c | blueswir1 | #endif
|
4279 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
4280 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
4281 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4282 | fcc72045 | blueswir1 | #else
|
4283 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4284 | fcc72045 | blueswir1 | #endif
|
4285 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4286 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
4287 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4288 | 2ea815ca | blueswir1 | |
4289 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4290 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4291 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4292 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4293 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4294 | 0f8a249a | blueswir1 | } else { /* register */ |
4295 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4296 | 0f8a249a | blueswir1 | if (rs2) {
|
4297 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4298 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4299 | 6f551262 | blueswir1 | } else
|
4300 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4301 | 3475187d | bellard | } |
4302 | a7812ae4 | pbrook | gen_helper_restore(); |
4303 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4304 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4305 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4306 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4307 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4308 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4309 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4310 | 3475187d | bellard | #endif
|
4311 | 0f8a249a | blueswir1 | } else {
|
4312 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4313 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4314 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4315 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4316 | 0f8a249a | blueswir1 | } else { /* register */ |
4317 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4318 | 0f8a249a | blueswir1 | if (rs2) {
|
4319 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4320 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4321 | 6f551262 | blueswir1 | } else
|
4322 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4323 | cf495bcf | bellard | } |
4324 | 0f8a249a | blueswir1 | switch (xop) {
|
4325 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4326 | 0f8a249a | blueswir1 | { |
4327 | a7812ae4 | pbrook | TCGv r_pc; |
4328 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4329 | 2ea815ca | blueswir1 | |
4330 | a7812ae4 | pbrook | r_pc = tcg_const_tl(dc->pc); |
4331 | a7812ae4 | pbrook | gen_movl_TN_reg(rd, r_pc); |
4332 | a7812ae4 | pbrook | tcg_temp_free(r_pc); |
4333 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4334 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4335 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4336 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4337 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4338 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4339 | 0f8a249a | blueswir1 | } |
4340 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4341 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4342 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4343 | 0f8a249a | blueswir1 | { |
4344 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4345 | 2ea815ca | blueswir1 | |
4346 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4347 | 0f8a249a | blueswir1 | goto priv_insn;
|
4348 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4349 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4350 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4351 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4352 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4353 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4354 | a7812ae4 | pbrook | gen_helper_rett(); |
4355 | 0f8a249a | blueswir1 | } |
4356 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4357 | 0f8a249a | blueswir1 | #endif
|
4358 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4359 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4360 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4361 | a7812ae4 | pbrook | gen_helper_flush(cpu_dst); |
4362 | 0f8a249a | blueswir1 | break;
|
4363 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4364 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4365 | a7812ae4 | pbrook | gen_helper_save(); |
4366 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4367 | 0f8a249a | blueswir1 | break;
|
4368 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4369 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4370 | a7812ae4 | pbrook | gen_helper_restore(); |
4371 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4372 | 0f8a249a | blueswir1 | break;
|
4373 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4374 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4375 | 0f8a249a | blueswir1 | { |
4376 | 0f8a249a | blueswir1 | switch (rd) {
|
4377 | 0f8a249a | blueswir1 | case 0: |
4378 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4379 | 0f8a249a | blueswir1 | goto priv_insn;
|
4380 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4381 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4382 | a7812ae4 | pbrook | gen_helper_done(); |
4383 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4384 | 0f8a249a | blueswir1 | case 1: |
4385 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4386 | 0f8a249a | blueswir1 | goto priv_insn;
|
4387 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4388 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4389 | a7812ae4 | pbrook | gen_helper_retry(); |
4390 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4391 | 0f8a249a | blueswir1 | default:
|
4392 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4393 | 0f8a249a | blueswir1 | } |
4394 | 0f8a249a | blueswir1 | } |
4395 | 0f8a249a | blueswir1 | break;
|
4396 | 0f8a249a | blueswir1 | #endif
|
4397 | 0f8a249a | blueswir1 | default:
|
4398 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4399 | 0f8a249a | blueswir1 | } |
4400 | cf495bcf | bellard | } |
4401 | 0f8a249a | blueswir1 | break;
|
4402 | 0f8a249a | blueswir1 | } |
4403 | 0f8a249a | blueswir1 | break;
|
4404 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4405 | 0f8a249a | blueswir1 | { |
4406 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4407 | 9322a4bf | blueswir1 | |
4408 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4409 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4410 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4411 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4412 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4413 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4414 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4415 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_addr, cpu_src1, simm); |
4416 | 0f8a249a | blueswir1 | } else { /* register */ |
4417 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4418 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4419 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4420 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4421 | 6f551262 | blueswir1 | } else
|
4422 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4423 | 0f8a249a | blueswir1 | } |
4424 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4425 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4426 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4427 | 0f8a249a | blueswir1 | switch (xop) {
|
4428 | b89e94af | Blue Swirl | case 0x0: /* ld, V9 lduw, load unsigned word */ |
4429 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4430 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4431 | 0f8a249a | blueswir1 | break;
|
4432 | b89e94af | Blue Swirl | case 0x1: /* ldub, load unsigned byte */ |
4433 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4434 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4435 | 0f8a249a | blueswir1 | break;
|
4436 | b89e94af | Blue Swirl | case 0x2: /* lduh, load unsigned halfword */ |
4437 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4438 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4439 | 0f8a249a | blueswir1 | break;
|
4440 | b89e94af | Blue Swirl | case 0x3: /* ldd, load double word */ |
4441 | 0f8a249a | blueswir1 | if (rd & 1) |
4442 | d4218d99 | blueswir1 | goto illegal_insn;
|
4443 | 1a2fb1c0 | blueswir1 | else {
|
4444 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4445 | 2ea815ca | blueswir1 | |
4446 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4447 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4448 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4449 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4450 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4451 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4452 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4453 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4454 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4455 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4456 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4457 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4458 | 1a2fb1c0 | blueswir1 | } |
4459 | 0f8a249a | blueswir1 | break;
|
4460 | b89e94af | Blue Swirl | case 0x9: /* ldsb, load signed byte */ |
4461 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4462 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4463 | 0f8a249a | blueswir1 | break;
|
4464 | b89e94af | Blue Swirl | case 0xa: /* ldsh, load signed halfword */ |
4465 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4466 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4467 | 0f8a249a | blueswir1 | break;
|
4468 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4469 | 2ea815ca | blueswir1 | { |
4470 | 2ea815ca | blueswir1 | TCGv r_const; |
4471 | 2ea815ca | blueswir1 | |
4472 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4473 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4474 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4475 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4476 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4477 | 2ea815ca | blueswir1 | } |
4478 | 0f8a249a | blueswir1 | break;
|
4479 | b89e94af | Blue Swirl | case 0x0f: /* swap, swap register with memory. Also |
4480 | 77f193da | blueswir1 | atomically */
|
4481 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4482 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4483 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4484 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4485 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4486 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_val, cpu_tmp0); |
4487 | 0f8a249a | blueswir1 | break;
|
4488 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4489 | b89e94af | Blue Swirl | case 0x10: /* lda, V9 lduwa, load word alternate */ |
4490 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4491 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4492 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4493 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4494 | 0f8a249a | blueswir1 | goto priv_insn;
|
4495 | 6ea4a6c8 | blueswir1 | #endif
|
4496 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4497 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4498 | 0f8a249a | blueswir1 | break;
|
4499 | b89e94af | Blue Swirl | case 0x11: /* lduba, load unsigned byte alternate */ |
4500 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4501 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4502 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4503 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4504 | 0f8a249a | blueswir1 | goto priv_insn;
|
4505 | 0f8a249a | blueswir1 | #endif
|
4506 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4507 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4508 | 0f8a249a | blueswir1 | break;
|
4509 | b89e94af | Blue Swirl | case 0x12: /* lduha, load unsigned halfword alternate */ |
4510 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4511 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4512 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4513 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4514 | 0f8a249a | blueswir1 | goto priv_insn;
|
4515 | 6ea4a6c8 | blueswir1 | #endif
|
4516 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4517 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4518 | 0f8a249a | blueswir1 | break;
|
4519 | b89e94af | Blue Swirl | case 0x13: /* ldda, load double word alternate */ |
4520 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4521 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4522 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4523 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4524 | 0f8a249a | blueswir1 | goto priv_insn;
|
4525 | 3475187d | bellard | #endif
|
4526 | 0f8a249a | blueswir1 | if (rd & 1) |
4527 | d4218d99 | blueswir1 | goto illegal_insn;
|
4528 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4529 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4530 | db166940 | blueswir1 | goto skip_move;
|
4531 | b89e94af | Blue Swirl | case 0x19: /* ldsba, load signed byte alternate */ |
4532 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4533 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4534 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4535 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4536 | 0f8a249a | blueswir1 | goto priv_insn;
|
4537 | 0f8a249a | blueswir1 | #endif
|
4538 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4539 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4540 | 0f8a249a | blueswir1 | break;
|
4541 | b89e94af | Blue Swirl | case 0x1a: /* ldsha, load signed halfword alternate */ |
4542 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4543 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4544 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4545 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4546 | 0f8a249a | blueswir1 | goto priv_insn;
|
4547 | 6ea4a6c8 | blueswir1 | #endif
|
4548 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4549 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4550 | 0f8a249a | blueswir1 | break;
|
4551 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4552 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4553 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4554 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4555 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4556 | 0f8a249a | blueswir1 | goto priv_insn;
|
4557 | 0f8a249a | blueswir1 | #endif
|
4558 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4559 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4560 | 0f8a249a | blueswir1 | break;
|
4561 | b89e94af | Blue Swirl | case 0x1f: /* swapa, swap reg with alt. memory. Also |
4562 | 77f193da | blueswir1 | atomically */
|
4563 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4564 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4565 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4566 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4567 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4568 | 0f8a249a | blueswir1 | goto priv_insn;
|
4569 | 6ea4a6c8 | blueswir1 | #endif
|
4570 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4571 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4572 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4573 | 0f8a249a | blueswir1 | break;
|
4574 | 3475187d | bellard | |
4575 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4576 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4577 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4578 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4579 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4580 | 3475187d | bellard | #endif
|
4581 | 3475187d | bellard | #endif
|
4582 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4583 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4584 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4585 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4586 | 0f8a249a | blueswir1 | break;
|
4587 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4588 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4589 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4590 | 0f8a249a | blueswir1 | break;
|
4591 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4592 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4593 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4594 | 0f8a249a | blueswir1 | break;
|
4595 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4596 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4597 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4598 | 0f8a249a | blueswir1 | break;
|
4599 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4600 | 0f8a249a | blueswir1 | goto skip_move;
|
4601 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4602 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4603 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4604 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4605 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4606 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4607 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4608 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4609 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4610 | 0f8a249a | blueswir1 | goto skip_move;
|
4611 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4612 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4613 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4614 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4615 | 1f587329 | blueswir1 | goto skip_move;
|
4616 | 1f587329 | blueswir1 | #endif
|
4617 | 0f8a249a | blueswir1 | default:
|
4618 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4619 | 0f8a249a | blueswir1 | } |
4620 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4621 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4622 | 0f8a249a | blueswir1 | skip_move: ;
|
4623 | 3475187d | bellard | #endif
|
4624 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4625 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4626 | a80dde08 | bellard | goto jmp_insn;
|
4627 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4628 | 0f8a249a | blueswir1 | switch (xop) {
|
4629 | b89e94af | Blue Swirl | case 0x20: /* ldf, load fpreg */ |
4630 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4631 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4632 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
4633 | 0f8a249a | blueswir1 | break;
|
4634 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4635 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4636 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4637 | 3a3b925d | blueswir1 | if (rd == 1) { |
4638 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4639 | a7812ae4 | pbrook | gen_helper_ldxfsr(cpu_tmp64); |
4640 | 3a3b925d | blueswir1 | } else
|
4641 | 3a3b925d | blueswir1 | #else
|
4642 | 3a3b925d | blueswir1 | { |
4643 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4644 | a7812ae4 | pbrook | gen_helper_ldfsr(cpu_tmp32); |
4645 | 3a3b925d | blueswir1 | } |
4646 | 3a3b925d | blueswir1 | #endif
|
4647 | 0f8a249a | blueswir1 | break;
|
4648 | b89e94af | Blue Swirl | case 0x22: /* ldqf, load quad fpreg */ |
4649 | 2ea815ca | blueswir1 | { |
4650 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4651 | 2ea815ca | blueswir1 | |
4652 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4653 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4654 | a7812ae4 | pbrook | gen_helper_ldqf(cpu_addr, r_const); |
4655 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4656 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4657 | 2ea815ca | blueswir1 | } |
4658 | 1f587329 | blueswir1 | break;
|
4659 | b89e94af | Blue Swirl | case 0x23: /* lddf, load double fpreg */ |
4660 | 2ea815ca | blueswir1 | { |
4661 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4662 | 2ea815ca | blueswir1 | |
4663 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4664 | a7812ae4 | pbrook | gen_helper_lddf(cpu_addr, r_const); |
4665 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4666 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4667 | 2ea815ca | blueswir1 | } |
4668 | 0f8a249a | blueswir1 | break;
|
4669 | 0f8a249a | blueswir1 | default:
|
4670 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4671 | 0f8a249a | blueswir1 | } |
4672 | dc1a6971 | Blue Swirl | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || |
4673 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4674 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4675 | 0f8a249a | blueswir1 | switch (xop) {
|
4676 | b89e94af | Blue Swirl | case 0x4: /* st, store word */ |
4677 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4678 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4679 | 0f8a249a | blueswir1 | break;
|
4680 | b89e94af | Blue Swirl | case 0x5: /* stb, store byte */ |
4681 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4682 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4683 | 0f8a249a | blueswir1 | break;
|
4684 | b89e94af | Blue Swirl | case 0x6: /* sth, store halfword */ |
4685 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4686 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4687 | 0f8a249a | blueswir1 | break;
|
4688 | b89e94af | Blue Swirl | case 0x7: /* std, store double word */ |
4689 | 0f8a249a | blueswir1 | if (rd & 1) |
4690 | d4218d99 | blueswir1 | goto illegal_insn;
|
4691 | 1a2fb1c0 | blueswir1 | else {
|
4692 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4693 | 1a2fb1c0 | blueswir1 | |
4694 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4695 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4696 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4697 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4698 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4699 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
4700 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); |
4701 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4702 | 7fa76c0b | blueswir1 | } |
4703 | 0f8a249a | blueswir1 | break;
|
4704 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4705 | b89e94af | Blue Swirl | case 0x14: /* sta, V9 stwa, store word alternate */ |
4706 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4707 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4708 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4709 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4710 | 0f8a249a | blueswir1 | goto priv_insn;
|
4711 | 3475187d | bellard | #endif
|
4712 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4713 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4714 | d39c0b99 | bellard | break;
|
4715 | b89e94af | Blue Swirl | case 0x15: /* stba, store byte alternate */ |
4716 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4717 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4718 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4719 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4720 | 0f8a249a | blueswir1 | goto priv_insn;
|
4721 | 3475187d | bellard | #endif
|
4722 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4723 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4724 | d39c0b99 | bellard | break;
|
4725 | b89e94af | Blue Swirl | case 0x16: /* stha, store halfword alternate */ |
4726 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4727 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4728 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4729 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4730 | 0f8a249a | blueswir1 | goto priv_insn;
|
4731 | 3475187d | bellard | #endif
|
4732 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4733 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4734 | d39c0b99 | bellard | break;
|
4735 | b89e94af | Blue Swirl | case 0x17: /* stda, store double word alternate */ |
4736 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4737 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4738 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4739 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4740 | 0f8a249a | blueswir1 | goto priv_insn;
|
4741 | 3475187d | bellard | #endif
|
4742 | 0f8a249a | blueswir1 | if (rd & 1) |
4743 | d4218d99 | blueswir1 | goto illegal_insn;
|
4744 | 1a2fb1c0 | blueswir1 | else {
|
4745 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4746 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4747 | 1a2fb1c0 | blueswir1 | } |
4748 | d39c0b99 | bellard | break;
|
4749 | e80cfcfc | bellard | #endif
|
4750 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4751 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4752 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4753 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4754 | 0f8a249a | blueswir1 | break;
|
4755 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4756 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4757 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4758 | 0f8a249a | blueswir1 | break;
|
4759 | 3475187d | bellard | #endif
|
4760 | 0f8a249a | blueswir1 | default:
|
4761 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4762 | 0f8a249a | blueswir1 | } |
4763 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4764 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4765 | a80dde08 | bellard | goto jmp_insn;
|
4766 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4767 | 0f8a249a | blueswir1 | switch (xop) {
|
4768 | b89e94af | Blue Swirl | case 0x24: /* stf, store fpreg */ |
4769 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4770 | 527067d8 | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); |
4771 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); |
4772 | 0f8a249a | blueswir1 | break;
|
4773 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4774 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4775 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4776 | 3a3b925d | blueswir1 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4777 | 3a3b925d | blueswir1 | if (rd == 1) |
4778 | 3a3b925d | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4779 | 527067d8 | blueswir1 | else
|
4780 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx); |
4781 | 3a3b925d | blueswir1 | #else
|
4782 | 3a3b925d | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); |
4783 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4784 | 3a3b925d | blueswir1 | #endif
|
4785 | 0f8a249a | blueswir1 | break;
|
4786 | 1f587329 | blueswir1 | case 0x26: |
4787 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4788 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4789 | 2ea815ca | blueswir1 | { |
4790 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4791 | 2ea815ca | blueswir1 | |
4792 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4793 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4794 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4795 | a7812ae4 | pbrook | gen_helper_stqf(cpu_addr, r_const); |
4796 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4797 | 2ea815ca | blueswir1 | } |
4798 | 1f587329 | blueswir1 | break;
|
4799 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4800 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4801 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4802 | 1f587329 | blueswir1 | goto illegal_insn;
|
4803 | 1f587329 | blueswir1 | #else
|
4804 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4805 | 0f8a249a | blueswir1 | goto priv_insn;
|
4806 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4807 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4808 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4809 | 0f8a249a | blueswir1 | #endif
|
4810 | 1f587329 | blueswir1 | #endif
|
4811 | b89e94af | Blue Swirl | case 0x27: /* stdf, store double fpreg */ |
4812 | 2ea815ca | blueswir1 | { |
4813 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4814 | 2ea815ca | blueswir1 | |
4815 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4816 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4817 | a7812ae4 | pbrook | gen_helper_stdf(cpu_addr, r_const); |
4818 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4819 | 2ea815ca | blueswir1 | } |
4820 | 0f8a249a | blueswir1 | break;
|
4821 | 0f8a249a | blueswir1 | default:
|
4822 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4823 | 0f8a249a | blueswir1 | } |
4824 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4825 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4826 | 0f8a249a | blueswir1 | switch (xop) {
|
4827 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4828 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4829 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4830 | 0f8a249a | blueswir1 | break;
|
4831 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4832 | 2ea815ca | blueswir1 | { |
4833 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4834 | 2ea815ca | blueswir1 | |
4835 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4836 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4837 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); |
4838 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4839 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4840 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4841 | 2ea815ca | blueswir1 | } |
4842 | 1f587329 | blueswir1 | break;
|
4843 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4844 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4845 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4846 | 0f8a249a | blueswir1 | break;
|
4847 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4848 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4849 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4850 | 0f8a249a | blueswir1 | break;
|
4851 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4852 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4853 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4854 | 0f8a249a | blueswir1 | break;
|
4855 | a4d17f19 | blueswir1 | #else
|
4856 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4857 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4858 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4859 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4860 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4861 | 0f8a249a | blueswir1 | #endif
|
4862 | 0f8a249a | blueswir1 | default:
|
4863 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4864 | 0f8a249a | blueswir1 | } |
4865 | dc1a6971 | Blue Swirl | } else
|
4866 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4867 | 0f8a249a | blueswir1 | } |
4868 | 0f8a249a | blueswir1 | break;
|
4869 | cf495bcf | bellard | } |
4870 | cf495bcf | bellard | /* default case for non jump instructions */
|
4871 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4872 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4873 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4874 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4875 | 72cbca10 | bellard | /* we can do a static jump */
|
4876 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4877 | 72cbca10 | bellard | dc->is_br = 1;
|
4878 | 72cbca10 | bellard | } else {
|
4879 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4880 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4881 | cf495bcf | bellard | } |
4882 | e80cfcfc | bellard | jmp_insn:
|
4883 | cf495bcf | bellard | return;
|
4884 | cf495bcf | bellard | illegal_insn:
|
4885 | 2ea815ca | blueswir1 | { |
4886 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4887 | 2ea815ca | blueswir1 | |
4888 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4889 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4890 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4891 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4892 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4893 | 2ea815ca | blueswir1 | } |
4894 | e8af50a3 | bellard | return;
|
4895 | 64a88d5d | blueswir1 | unimp_flush:
|
4896 | 2ea815ca | blueswir1 | { |
4897 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4898 | 2ea815ca | blueswir1 | |
4899 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4900 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4901 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4902 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4903 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4904 | 2ea815ca | blueswir1 | } |
4905 | 64a88d5d | blueswir1 | return;
|
4906 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4907 | e8af50a3 | bellard | priv_insn:
|
4908 | 2ea815ca | blueswir1 | { |
4909 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4910 | 2ea815ca | blueswir1 | |
4911 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4912 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4913 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4914 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4915 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4916 | 2ea815ca | blueswir1 | } |
4917 | e80cfcfc | bellard | return;
|
4918 | 64a88d5d | blueswir1 | #endif
|
4919 | e80cfcfc | bellard | nfpu_insn:
|
4920 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4921 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4922 | e80cfcfc | bellard | dc->is_br = 1;
|
4923 | fcc72045 | blueswir1 | return;
|
4924 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4925 | 9143e598 | blueswir1 | nfq_insn:
|
4926 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4927 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4928 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4929 | 9143e598 | blueswir1 | return;
|
4930 | 9143e598 | blueswir1 | #endif
|
4931 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4932 | fcc72045 | blueswir1 | ncp_insn:
|
4933 | 2ea815ca | blueswir1 | { |
4934 | 2ea815ca | blueswir1 | TCGv r_const; |
4935 | 2ea815ca | blueswir1 | |
4936 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4937 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4938 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4939 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4940 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4941 | 2ea815ca | blueswir1 | } |
4942 | fcc72045 | blueswir1 | return;
|
4943 | fcc72045 | blueswir1 | #endif
|
4944 | 7a3f1944 | bellard | } |
4945 | 7a3f1944 | bellard | |
4946 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4947 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4948 | 7a3f1944 | bellard | { |
4949 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4950 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4951 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4952 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
4953 | e8af50a3 | bellard | int j, lj = -1; |
4954 | 2e70f6ef | pbrook | int num_insns;
|
4955 | 2e70f6ef | pbrook | int max_insns;
|
4956 | cf495bcf | bellard | |
4957 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4958 | cf495bcf | bellard | dc->tb = tb; |
4959 | 72cbca10 | bellard | pc_start = tb->pc; |
4960 | cf495bcf | bellard | dc->pc = pc_start; |
4961 | e80cfcfc | bellard | last_pc = dc->pc; |
4962 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4963 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_DYNAMIC; |
4964 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4965 | 5578ceab | blueswir1 | dc->def = env->def; |
4966 | 5578ceab | blueswir1 | if ((dc->def->features & CPU_FEATURE_FLOAT))
|
4967 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4968 | 5578ceab | blueswir1 | else
|
4969 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4970 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4971 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4972 | 2cade6a3 | blueswir1 | #endif
|
4973 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4974 | cf495bcf | bellard | |
4975 | a7812ae4 | pbrook | cpu_tmp0 = tcg_temp_new(); |
4976 | a7812ae4 | pbrook | cpu_tmp32 = tcg_temp_new_i32(); |
4977 | a7812ae4 | pbrook | cpu_tmp64 = tcg_temp_new_i64(); |
4978 | d987963a | blueswir1 | |
4979 | a7812ae4 | pbrook | cpu_dst = tcg_temp_local_new(); |
4980 | d987963a | blueswir1 | |
4981 | d987963a | blueswir1 | // loads and stores
|
4982 | a7812ae4 | pbrook | cpu_val = tcg_temp_local_new(); |
4983 | a7812ae4 | pbrook | cpu_addr = tcg_temp_local_new(); |
4984 | 1a2fb1c0 | blueswir1 | |
4985 | 2e70f6ef | pbrook | num_insns = 0;
|
4986 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4987 | 2e70f6ef | pbrook | if (max_insns == 0) |
4988 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4989 | 2e70f6ef | pbrook | gen_icount_start(); |
4990 | cf495bcf | bellard | do {
|
4991 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
4992 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
4993 | a1d1bb31 | aliguori | if (bp->pc == dc->pc) {
|
4994 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4995 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4996 | a7812ae4 | pbrook | gen_helper_debug(); |
4997 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4998 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4999 | e80cfcfc | bellard | goto exit_gen_loop;
|
5000 | e8af50a3 | bellard | } |
5001 | e8af50a3 | bellard | } |
5002 | e8af50a3 | bellard | } |
5003 | e8af50a3 | bellard | if (spc) {
|
5004 | 93fcfe39 | aliguori | qemu_log("Search PC...\n");
|
5005 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
5006 | e8af50a3 | bellard | if (lj < j) {
|
5007 | e8af50a3 | bellard | lj++; |
5008 | e8af50a3 | bellard | while (lj < j)
|
5009 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
5010 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
5011 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
5012 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
5013 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
5014 | e8af50a3 | bellard | } |
5015 | e8af50a3 | bellard | } |
5016 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
5017 | 2e70f6ef | pbrook | gen_io_start(); |
5018 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
5019 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
5020 | 2e70f6ef | pbrook | num_insns++; |
5021 | 0f8a249a | blueswir1 | |
5022 | 0f8a249a | blueswir1 | if (dc->is_br)
|
5023 | 0f8a249a | blueswir1 | break;
|
5024 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
5025 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
5026 | 0f8a249a | blueswir1 | break;
|
5027 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
5028 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
5029 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
5030 | d39c0b99 | bellard | break;
|
5031 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
5032 | e80cfcfc | bellard | generate an exception */
|
5033 | 1b530a6d | aurel32 | if (env->singlestep_enabled || singlestep) {
|
5034 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
5035 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
5036 | e80cfcfc | bellard | break;
|
5037 | e80cfcfc | bellard | } |
5038 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
5039 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
5040 | 2e70f6ef | pbrook | num_insns < max_insns); |
5041 | e80cfcfc | bellard | |
5042 | e80cfcfc | bellard | exit_gen_loop:
|
5043 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
5044 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
5045 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
5046 | a7812ae4 | pbrook | tcg_temp_free_i64(cpu_tmp64); |
5047 | a7812ae4 | pbrook | tcg_temp_free_i32(cpu_tmp32); |
5048 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
5049 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
5050 | 2e70f6ef | pbrook | gen_io_end(); |
5051 | 72cbca10 | bellard | if (!dc->is_br) {
|
5052 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
5053 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
5054 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
5055 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
5056 | 72cbca10 | bellard | } else {
|
5057 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
5058 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
5059 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
5060 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
5061 | 72cbca10 | bellard | } |
5062 | 72cbca10 | bellard | } |
5063 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
5064 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
5065 | e8af50a3 | bellard | if (spc) {
|
5066 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
5067 | e8af50a3 | bellard | lj++; |
5068 | e8af50a3 | bellard | while (lj <= j)
|
5069 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
5070 | e8af50a3 | bellard | #if 0
|
5071 | 93fcfe39 | aliguori | log_page_dump();
|
5072 | e8af50a3 | bellard | #endif
|
5073 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
5074 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
5075 | e8af50a3 | bellard | } else {
|
5076 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
5077 | 2e70f6ef | pbrook | tb->icount = num_insns; |
5078 | e8af50a3 | bellard | } |
5079 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
5080 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
5081 | 93fcfe39 | aliguori | qemu_log("--------------\n");
|
5082 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
5083 | 93fcfe39 | aliguori | log_target_disas(pc_start, last_pc + 4 - pc_start, 0); |
5084 | 93fcfe39 | aliguori | qemu_log("\n");
|
5085 | cf495bcf | bellard | } |
5086 | 7a3f1944 | bellard | #endif
|
5087 | 7a3f1944 | bellard | } |
5088 | 7a3f1944 | bellard | |
5089 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
5090 | 7a3f1944 | bellard | { |
5091 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
5092 | 7a3f1944 | bellard | } |
5093 | 7a3f1944 | bellard | |
5094 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
5095 | 7a3f1944 | bellard | { |
5096 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
5097 | 7a3f1944 | bellard | } |
5098 | 7a3f1944 | bellard | |
5099 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
5100 | e80cfcfc | bellard | { |
5101 | f5069b26 | blueswir1 | unsigned int i; |
5102 | c48fcb47 | blueswir1 | static int inited; |
5103 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
5104 | f5069b26 | blueswir1 | NULL, // g0 not used |
5105 | f5069b26 | blueswir1 | "g1",
|
5106 | f5069b26 | blueswir1 | "g2",
|
5107 | f5069b26 | blueswir1 | "g3",
|
5108 | f5069b26 | blueswir1 | "g4",
|
5109 | f5069b26 | blueswir1 | "g5",
|
5110 | f5069b26 | blueswir1 | "g6",
|
5111 | f5069b26 | blueswir1 | "g7",
|
5112 | f5069b26 | blueswir1 | }; |
5113 | 714547bb | blueswir1 | static const char * const fregnames[64] = { |
5114 | 714547bb | blueswir1 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
5115 | 714547bb | blueswir1 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
5116 | 714547bb | blueswir1 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
5117 | 714547bb | blueswir1 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
5118 | 714547bb | blueswir1 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
5119 | 714547bb | blueswir1 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
5120 | 714547bb | blueswir1 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
5121 | 714547bb | blueswir1 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
5122 | 714547bb | blueswir1 | }; |
5123 | aaed909a | bellard | |
5124 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
5125 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
5126 | 1a2fb1c0 | blueswir1 | inited = 1;
|
5127 | 1a2fb1c0 | blueswir1 | |
5128 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
5129 | a7812ae4 | pbrook | cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, |
5130 | a7812ae4 | pbrook | offsetof(CPUState, regwptr), |
5131 | a7812ae4 | pbrook | "regwptr");
|
5132 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
5133 | a7812ae4 | pbrook | cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc), |
5134 | a7812ae4 | pbrook | "xcc");
|
5135 | a7812ae4 | pbrook | cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi), |
5136 | a7812ae4 | pbrook | "asi");
|
5137 | a7812ae4 | pbrook | cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs), |
5138 | a7812ae4 | pbrook | "fprs");
|
5139 | a7812ae4 | pbrook | cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr), |
5140 | 255e1fcb | blueswir1 | "gsr");
|
5141 | a7812ae4 | pbrook | cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, |
5142 | 255e1fcb | blueswir1 | offsetof(CPUState, tick_cmpr), |
5143 | 255e1fcb | blueswir1 | "tick_cmpr");
|
5144 | a7812ae4 | pbrook | cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, |
5145 | 255e1fcb | blueswir1 | offsetof(CPUState, stick_cmpr), |
5146 | 255e1fcb | blueswir1 | "stick_cmpr");
|
5147 | a7812ae4 | pbrook | cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, |
5148 | 255e1fcb | blueswir1 | offsetof(CPUState, hstick_cmpr), |
5149 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
5150 | a7812ae4 | pbrook | cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp), |
5151 | 255e1fcb | blueswir1 | "hintp");
|
5152 | a7812ae4 | pbrook | cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba), |
5153 | a7812ae4 | pbrook | "htba");
|
5154 | a7812ae4 | pbrook | cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver), |
5155 | a7812ae4 | pbrook | "hver");
|
5156 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new(TCG_AREG0, |
5157 | 255e1fcb | blueswir1 | offsetof(CPUState, ssr), "ssr");
|
5158 | a7812ae4 | pbrook | cpu_ver = tcg_global_mem_new(TCG_AREG0, |
5159 | 255e1fcb | blueswir1 | offsetof(CPUState, version), "ver");
|
5160 | a7812ae4 | pbrook | cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, |
5161 | a7812ae4 | pbrook | offsetof(CPUState, softint), |
5162 | a7812ae4 | pbrook | "softint");
|
5163 | 255e1fcb | blueswir1 | #else
|
5164 | a7812ae4 | pbrook | cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), |
5165 | 255e1fcb | blueswir1 | "wim");
|
5166 | 1a2fb1c0 | blueswir1 | #endif
|
5167 | a7812ae4 | pbrook | cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), |
5168 | 77f193da | blueswir1 | "cond");
|
5169 | a7812ae4 | pbrook | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), |
5170 | dc99a3f2 | blueswir1 | "cc_src");
|
5171 | a7812ae4 | pbrook | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, |
5172 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
5173 | d9bdab86 | blueswir1 | "cc_src2");
|
5174 | a7812ae4 | pbrook | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), |
5175 | dc99a3f2 | blueswir1 | "cc_dst");
|
5176 | 8393617c | Blue Swirl | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), |
5177 | 8393617c | Blue Swirl | "cc_op");
|
5178 | a7812ae4 | pbrook | cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr), |
5179 | a7812ae4 | pbrook | "psr");
|
5180 | a7812ae4 | pbrook | cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr), |
5181 | 87e92502 | blueswir1 | "fsr");
|
5182 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc), |
5183 | 48d5c82b | blueswir1 | "pc");
|
5184 | a7812ae4 | pbrook | cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc), |
5185 | a7812ae4 | pbrook | "npc");
|
5186 | a7812ae4 | pbrook | cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
|
5187 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
5188 | a7812ae4 | pbrook | cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr), |
5189 | 255e1fcb | blueswir1 | "tbr");
|
5190 | 255e1fcb | blueswir1 | #endif
|
5191 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
5192 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, |
5193 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
5194 | f5069b26 | blueswir1 | gregnames[i]); |
5195 | 714547bb | blueswir1 | for (i = 0; i < TARGET_FPREGS; i++) |
5196 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, |
5197 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), |
5198 | a7812ae4 | pbrook | fregnames[i]); |
5199 | 714547bb | blueswir1 | |
5200 | c9e03d8f | blueswir1 | /* register helpers */
|
5201 | c9e03d8f | blueswir1 | |
5202 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
5203 | c9e03d8f | blueswir1 | #include "helper.h" |
5204 | 1a2fb1c0 | blueswir1 | } |
5205 | 658138bc | bellard | } |
5206 | d2856f1a | aurel32 | |
5207 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
5208 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
5209 | d2856f1a | aurel32 | { |
5210 | d2856f1a | aurel32 | target_ulong npc; |
5211 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
5212 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
5213 | d2856f1a | aurel32 | if (npc == 1) { |
5214 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
5215 | d2856f1a | aurel32 | } else if (npc == 2) { |
5216 | d2856f1a | aurel32 | target_ulong t2 = (target_ulong)(unsigned long)puc; |
5217 | d2856f1a | aurel32 | /* jump PC: use T2 and the jump targets of the translation */
|
5218 | d2856f1a | aurel32 | if (t2)
|
5219 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
5220 | d2856f1a | aurel32 | else
|
5221 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
5222 | d2856f1a | aurel32 | } else {
|
5223 | d2856f1a | aurel32 | env->npc = npc; |
5224 | d2856f1a | aurel32 | } |
5225 | d2856f1a | aurel32 | } |