Revision 38482a77 target-sparc/translate.c
b/target-sparc/translate.c | ||
---|---|---|
3136 | 3136 |
tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
3137 | 3137 |
} |
3138 | 3138 |
if (xop & 0x10) { |
3139 |
gen_op_logic_cc(cpu_dst);
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|
3140 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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3141 |
dc->cc_op = CC_OP_FLAGS;
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|
3139 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
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3140 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
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3141 |
dc->cc_op = CC_OP_LOGIC;
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|
3142 | 3142 |
} |
3143 | 3143 |
break; |
3144 | 3144 |
case 0x2: /* or */ |
... | ... | |
3149 | 3149 |
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3150 | 3150 |
} |
3151 | 3151 |
if (xop & 0x10) { |
3152 |
gen_op_logic_cc(cpu_dst);
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|
3153 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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3154 |
dc->cc_op = CC_OP_FLAGS;
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3152 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
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3153 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
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3154 |
dc->cc_op = CC_OP_LOGIC;
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|
3155 | 3155 |
} |
3156 | 3156 |
break; |
3157 | 3157 |
case 0x3: /* xor */ |
... | ... | |
3162 | 3162 |
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3163 | 3163 |
} |
3164 | 3164 |
if (xop & 0x10) { |
3165 |
gen_op_logic_cc(cpu_dst);
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|
3166 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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3167 |
dc->cc_op = CC_OP_FLAGS;
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3165 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
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3166 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
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|
3167 |
dc->cc_op = CC_OP_LOGIC;
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3168 | 3168 |
} |
3169 | 3169 |
break; |
3170 | 3170 |
case 0x4: /* sub */ |
... | ... | |
3195 | 3195 |
tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
3196 | 3196 |
} |
3197 | 3197 |
if (xop & 0x10) { |
3198 |
gen_op_logic_cc(cpu_dst);
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|
3199 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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|
3200 |
dc->cc_op = CC_OP_FLAGS;
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|
3198 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
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|
3199 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
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3200 |
dc->cc_op = CC_OP_LOGIC;
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|
3201 | 3201 |
} |
3202 | 3202 |
break; |
3203 | 3203 |
case 0x6: /* orn */ |
... | ... | |
3208 | 3208 |
tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
3209 | 3209 |
} |
3210 | 3210 |
if (xop & 0x10) { |
3211 |
gen_op_logic_cc(cpu_dst);
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|
3212 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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|
3213 |
dc->cc_op = CC_OP_FLAGS;
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|
3211 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
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3212 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
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|
3213 |
dc->cc_op = CC_OP_LOGIC;
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|
3214 | 3214 |
} |
3215 | 3215 |
break; |
3216 | 3216 |
case 0x7: /* xorn */ |
... | ... | |
3222 | 3222 |
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3223 | 3223 |
} |
3224 | 3224 |
if (xop & 0x10) { |
3225 |
gen_op_logic_cc(cpu_dst);
|
|
3226 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
|
|
3227 |
dc->cc_op = CC_OP_FLAGS;
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|
3225 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
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|
3226 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
|
|
3227 |
dc->cc_op = CC_OP_LOGIC;
|
|
3228 | 3228 |
} |
3229 | 3229 |
break; |
3230 | 3230 |
case 0x8: /* addx, V9 addc */ |
... | ... | |
3269 | 3269 |
CHECK_IU_FEATURE(dc, MUL); |
3270 | 3270 |
gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
3271 | 3271 |
if (xop & 0x10) { |
3272 |
gen_op_logic_cc(cpu_dst);
|
|
3273 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
|
|
3274 |
dc->cc_op = CC_OP_FLAGS;
|
|
3272 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
|
|
3273 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
|
|
3274 |
dc->cc_op = CC_OP_LOGIC;
|
|
3275 | 3275 |
} |
3276 | 3276 |
break; |
3277 | 3277 |
case 0xb: /* smul */ |
3278 | 3278 |
CHECK_IU_FEATURE(dc, MUL); |
3279 | 3279 |
gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
3280 | 3280 |
if (xop & 0x10) { |
3281 |
gen_op_logic_cc(cpu_dst);
|
|
3282 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
|
|
3283 |
dc->cc_op = CC_OP_FLAGS;
|
|
3281 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
|
|
3282 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
|
|
3283 |
dc->cc_op = CC_OP_LOGIC;
|
|
3284 | 3284 |
} |
3285 | 3285 |
break; |
3286 | 3286 |
case 0xc: /* subx, V9 subc */ |
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