Revision 38898d7e hw/openpic.c
| b/hw/openpic.c | ||
|---|---|---|
| 46 | 46 |
#define DPRINTF(fmt, ...) do { } while (0)
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| 47 | 47 |
#endif |
| 48 | 48 |
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| 49 |
#define USE_MPCxxx /* Intel model is broken, for now */ |
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#if defined (USE_INTEL_GW80314) |
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/* Intel GW80314 I/O Companion chip */ |
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#define MAX_CPU 4 |
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#define MAX_IRQ 32 |
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#define MAX_DBL 4 |
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#define MAX_MBX 4 |
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#define MAX_TMR 4 |
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#define VECTOR_BITS 8 |
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#define MAX_IPI 4 |
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#define VID (0x00000000) |
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#elif defined(USE_MPCxxx) |
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| 66 | 49 |
#define MAX_CPU 15 |
| 67 | 50 |
#define MAX_IRQ 128 |
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#define MAX_DBL 0 |
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#define MAX_MBX 0 |
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| 70 | 51 |
#define MAX_TMR 4 |
| 71 | 52 |
#define VECTOR_BITS 8 |
| 72 | 53 |
#define MAX_IPI 4 |
| ... | ... | |
| 149 | 130 |
IDR_P0 = 0, |
| 150 | 131 |
}; |
| 151 | 132 |
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#else |
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#error "Please select which OpenPic implementation is to be emulated" |
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#endif |
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#define OPENPIC_PAGE_SIZE 4096 |
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| 158 | 133 |
#define BF_WIDTH(_bits_) \ |
| 159 | 134 |
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
| 160 | 135 |
|
| ... | ... | |
| 250 | 225 |
uint32_t ticc; /* Global timer current count register */ |
| 251 | 226 |
uint32_t tibc; /* Global timer base count register */ |
| 252 | 227 |
} timers[MAX_TMR]; |
| 253 |
#if MAX_DBL > 0 |
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/* Doorbell registers */ |
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uint32_t dar; /* Doorbell activate register */ |
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struct {
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uint32_t dmr; /* Doorbell messaging register */ |
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} doorbells[MAX_DBL]; |
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#endif |
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#if MAX_MBX > 0 |
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/* Mailbox registers */ |
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struct {
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uint32_t mbr; /* Mailbox register */ |
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} mailboxes[MAX_MAILBOXES]; |
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#endif |
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| 266 | 228 |
/* IRQ out is used when in bypass mode (not implemented) */ |
| 267 | 229 |
qemu_irq irq_out; |
| 268 | 230 |
int max_irq; |
| ... | ... | |
| 470 | 432 |
opp->timers[i].ticc = 0x00000000; |
| 471 | 433 |
opp->timers[i].tibc = 0x80000000; |
| 472 | 434 |
} |
| 473 |
/* Initialise doorbells */ |
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#if MAX_DBL > 0 |
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opp->dar = 0x00000000; |
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for (i = 0; i < MAX_DBL; i++) {
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opp->doorbells[i].dmr = 0x00000000; |
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} |
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#endif |
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/* Initialise mailboxes */ |
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#if MAX_MBX > 0 |
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for (i = 0; i < MAX_MBX; i++) { /* ? */
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opp->mailboxes[i].mbr = 0x00000000; |
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} |
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#endif |
|
| 486 | 435 |
/* Go out of RESET state */ |
| 487 | 436 |
opp->glbc = 0x00000000; |
| 488 | 437 |
} |
| ... | ... | |
| 518 | 467 |
opp->src[n_IRQ].ipvp); |
| 519 | 468 |
} |
| 520 | 469 |
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#if 0 // Code provision for Intel model |
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#if MAX_DBL > 0 |
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static uint32_t read_doorbell_register (openpic_t *opp, |
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int n_dbl, uint32_t offset) |
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{
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uint32_t retval; |
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switch (offset) {
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case DBL_IPVP_OFFSET: |
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retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl); |
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break; |
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case DBL_IDE_OFFSET: |
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retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl); |
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break; |
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case DBL_DMR_OFFSET: |
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retval = opp->doorbells[n_dbl].dmr; |
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break; |
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} |
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return retval; |
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} |
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static void write_doorbell_register (penpic_t *opp, int n_dbl, |
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uint32_t offset, uint32_t value) |
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{
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switch (offset) {
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case DBL_IVPR_OFFSET: |
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write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value); |
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break; |
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case DBL_IDE_OFFSET: |
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write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value); |
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break; |
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case DBL_DMR_OFFSET: |
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opp->doorbells[n_dbl].dmr = value; |
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break; |
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} |
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} |
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#endif |
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#if MAX_MBX > 0 |
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static uint32_t read_mailbox_register (openpic_t *opp, |
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int n_mbx, uint32_t offset) |
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{
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uint32_t retval; |
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switch (offset) {
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case MBX_MBR_OFFSET: |
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retval = opp->mailboxes[n_mbx].mbr; |
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break; |
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case MBX_IVPR_OFFSET: |
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retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx); |
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break; |
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case MBX_DMR_OFFSET: |
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retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx); |
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break; |
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} |
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return retval; |
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} |
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static void write_mailbox_register (openpic_t *opp, int n_mbx, |
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uint32_t address, uint32_t value) |
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{
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switch (offset) {
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case MBX_MBR_OFFSET: |
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opp->mailboxes[n_mbx].mbr = value; |
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break; |
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case MBX_IVPR_OFFSET: |
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write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value); |
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break; |
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case MBX_DMR_OFFSET: |
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write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value); |
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break; |
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} |
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} |
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#endif |
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#endif /* 0 : Code provision for Intel model */ |
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| 599 | 470 |
static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val) |
| 600 | 471 |
{
|
| 601 | 472 |
openpic_t *opp = opaque; |
| ... | ... | |
| 841 | 712 |
dst = &opp->dst[idx]; |
| 842 | 713 |
addr &= 0xFF0; |
| 843 | 714 |
switch (addr) {
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#if MAX_IPI > 0 |
|
| 845 | 715 |
case 0x40: /* IPIDR */ |
| 846 | 716 |
case 0x50: |
| 847 | 717 |
case 0x60: |
| ... | ... | |
| 853 | 723 |
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); |
| 854 | 724 |
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); |
| 855 | 725 |
break; |
| 856 |
#endif |
|
| 857 | 726 |
case 0x80: /* PCTP */ |
| 858 | 727 |
dst->pctp = val & 0x0000000F; |
| 859 | 728 |
break; |
| ... | ... | |
| 1109 | 978 |
qemu_put_be32s(f, &opp->timers[i].tibc); |
| 1110 | 979 |
} |
| 1111 | 980 |
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#if MAX_DBL > 0 |
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qemu_put_be32s(f, &opp->dar); |
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for (i = 0; i < MAX_DBL; i++) {
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qemu_put_be32s(f, &opp->doorbells[i].dmr); |
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} |
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#endif |
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#if MAX_MBX > 0 |
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for (i = 0; i < MAX_MAILBOXES; i++) {
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qemu_put_be32s(f, &opp->mailboxes[i].mbr); |
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} |
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#endif |
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| 1125 |
|
|
| 1126 | 981 |
pci_device_save(&opp->pci_dev, f); |
| 1127 | 982 |
} |
| 1128 | 983 |
|
| ... | ... | |
| 1176 | 1031 |
qemu_get_be32s(f, &opp->timers[i].tibc); |
| 1177 | 1032 |
} |
| 1178 | 1033 |
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#if MAX_DBL > 0 |
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qemu_get_be32s(f, &opp->dar); |
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for (i = 0; i < MAX_DBL; i++) {
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qemu_get_be32s(f, &opp->doorbells[i].dmr); |
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} |
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#endif |
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#if MAX_MBX > 0 |
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for (i = 0; i < MAX_MAILBOXES; i++) {
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qemu_get_be32s(f, &opp->mailboxes[i].mbr); |
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} |
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| 1191 |
#endif |
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| 1192 |
|
|
| 1193 | 1034 |
return pci_device_load(&opp->pci_dev, f); |
| 1194 | 1035 |
} |
| 1195 | 1036 |
|
| ... | ... | |
| 1222 | 1063 |
for (; i < OPENPIC_IRQ_TIM0; i++) {
|
| 1223 | 1064 |
opp->src[i].type = IRQ_SPECIAL; |
| 1224 | 1065 |
} |
| 1225 |
#if MAX_IPI > 0 |
|
| 1226 | 1066 |
m = OPENPIC_IRQ_IPI0; |
| 1227 |
#else |
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| 1228 |
m = OPENPIC_IRQ_DBL0; |
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| 1229 |
#endif |
|
| 1230 | 1067 |
for (; i < m; i++) {
|
| 1231 | 1068 |
opp->src[i].type = IRQ_TIMER; |
| 1232 | 1069 |
} |
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