target-i386: Pass X86CPU object to cpu_x86_find_by_name()
This will help us change the initialization code to not require carryingsome intermediate values in a x86_def_t struct (and eventually kill thex86_def_t struct entirely).
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>...
target-i386: Disable PMU CPUID leaf by default
Bug description: QEMU currently gets all bits from GET_SUPPORTED_CPUIDfor CPUID leaf 0xA and passes them directly to the guest. This makesthe guest ABI depend on host kernel and host CPU capabilities, andbreaks live migration if we migrate between hosts with different...
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".
The reason for the failure is that CPUClass::kvm_fd is not yet...
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro andmakes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g., sed i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target*/gdbstub.c...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Move cpu_gdb_{read,write}_register()
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
kvm: Change prototype of kvm_update_guest_debug()
Passing a CPUState pointer instead of a CPUArchState pointer eliminatesthe last target dependent data type in sysemu/kvm.h.
It also simplifies the code.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
Merge remote-tracking branch 'quintela/migration.next' into staging
Fix real mode guest migration
Older KVM versions save CS dpl value to an invalid value for real mode guests(0x3). This patch detect this situation when loading CPU state and set all thesegments dpl to zero.This will allow migration from older KVM on host without unrestricted guest...
Fix real mode guest segments dpl value in savevm
Older KVM version put invalid value in the segments registers dpl field forreal mode guests (0x3).This breaks migration from those hosts to hosts with unrestricted guest support.We detect it by checking CS dpl value for real mode guest and fix the dpl values...
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
exec: Change cpu_memory_rw_debug() argument to CPUState
Propagate X86CPU in kvmvapic for simplicity.
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
target-i386: Change do_interrupt_all() argument to X86CPU
Prepares for log_cpu_state() changing argument to CPUState.
target-i386: Change do_smm_enter() argument to X86CPU
Prepares for log_cpu_state_mask() changing argument to CPUState.
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
target-i386: Change LOG_PCALL_STATE() argument to CPUState
Since log_cpu_state_mask() argument was changed to CPUState,CPUArchState is no longer needed.
Choose CPUState rather than X86CPU to not hide type mismatches with CPU.
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Don't overuse CPUArchState
Use CPUX86State instead in dump support code.
cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.Move first_cpu variable to qom/cpu.h.
gdbstub needs to use CPUState::env_ptr for now.cpu_copy() no longer needs to save and restore cpu_next.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPUrelated -- they are specific to the TLS ABI for a a particular OS.Move them into the linux-user/ tree where they belong....
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
A transition from CPUFooState to FooCPU can be considered safe,just like FooCPU::env access in the opposite direction.The only benefit of the FOO_CPU() casts would be protection againstbogus CPUFooState pointers, but then surrounding code would likely...
Fix -machine options accel, kernel_irqchip, kvm_shadow_mem
Multiple -machine options with the same ID are merged. All but theone without an ID are to be silently ignored.
In most places, we query these options with a null ID. This iscorrect.
In some places, we instead query whatever options come first in the...
memory: return MemoryRegion from qemu_ram_addr_from_host
It will be needed in the next patch.
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
kvm: Change kvm_cpu_synchronize_state() argument to CPUState
It no longer relies on CPUArchState since 20d695a.
Reviewed-by: liguang <lig.fnst@cn.fujitsu.com>Acked-by: Paolo Bonzini <pbonzini@redhat.com>Reviewed-by: Richard Henderson <rth@twiddle.net>...
kvm: Change cpu_synchronize_state() argument to CPUState
Change Monitor::mon_cpu to CPUState as well.
Reviewed-by: liguang <lig.fnst@cn.fujitsu.com>Acked-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-i386: fix over 80 chars warnings
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-i386/helper: remove redundant env->eip assignment
target-i386/helper: remove DF macro
target-i386/helper: remove EIP macro
target-i386/helper: remove EDI macro
target-i386/helper: remove ESI macro
target-i386/helper: remove ESP macro
target-i386/helper: remove EBP macro
target-i386/helper: remove EDX macro
target-i386/helper: remove ECX macro
target-i386/helper: remove EBX macro
target-i386/helper: remove EAX macro
cpu: Turn cpu_get_memory_mapping() into a CPUState hook
Change error reporting from return value to Error argument.
Reviewed-by: Jens Freimann <jfrei@linux.vnet.ibm.com>Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>[AF: Fixed cpu_get_memory_mapping() documentation]...
cpu: Turn cpu_paging_enabled() into a CPUState hook
Relocate assignment of x86 get_arch_id to have all hooks in one place.
Reviewed-by: Jens Freimann <jfrei@linux.vnet.ibm.com>Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: cpu: Fix potential buffer overrun in get_register_name_32()
Spotted by Coverity,x86_reg_info_32[] is CPU_NB_REGS32 elements long, so accessingx86_reg_info_32[CPU_NB_REGS32] will be one element off array.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>...
target-i386: Update model values on Conroe/Penryn/Nehalem CPU models
The CPUID model values on Conroe, Penryn, and Nehalem are tooconservative and don't reflect the values found on real Conroe, Penryn,and Nehalem CPUs.
This causes at least one known problems: Windows XP disables sysenter...
target-i386: Set level=4 on Conroe/Penryn/Nehalem
The CPUID level value on Conroe, Penryn, and Nehalem are too low. Thiscauses at least one known problem: the -smp "threads" option doesn'twork as expect if level is < 4, because thread count information is...
target-i386: Fix aflag logic for CODE64 and the 0x67 prefix
The code reorganization in commit 4a6fd938 broke handling of PREFIX_ADR.While fixing this, tidy and comment the code so that it's more obviouswhat's going on in setting both aflag and dflag.
The TARGET_X86_64 ifdef can be eliminated because CODE64 expands to the...
target-i386: Fix mask of pte index in memory mapping
Function walk_pte() needs pte index to calculate virtual address.However, pte index of PAE paging or IA-32e paging is 9 bit, so the maskshould be 0x1ff.
Signed-off-by: Qiao Nuohan <qiaonuohan@cn.fujitsu.com>...
target-i386: fix abort on bad PML4E/PDPTE/PDE/PTE addresses
The code used to walk IA-32e page-tables, and possibly PAE page-tables,uses the bit mask ~0xfff to get the next PML4E/PDPTE/PDE/PTE address.
However, as we use a uint64_t to store the resulting address, that mask...
target-i386: ROR r8/r16 imm instruction fix
Fix EFLAGS corruption by ROR r8/r16 imm instruction located at the endof the TB, similarly to commit 089305ac for the non-immediate case.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-i386: n270 can MOVBE
The Atom core (cpu name "n270" in QEMU speak) supports MOVBE. This isneeded when booting 3.8 and later linux kernels built with the MATOMtarget because we require MOVBE in order to boot properly now.
Signed-off-by: Borislav Petkov <bp@suse.de>...
target-i386: Introduce generic CPUID feature compat function
Introduce x86_cpu_compat_set_features(), that can be used to set/unsetfeature bits on specific CPU models for machine-type compatibility.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Change CPUID model of 486 to 8
This changes the model number of 486 to 8 (DX4) which matches thefeature set presented, and actually has the CPUID instruction.
This adds a compatibility property, to keep model=0 on pc-*-1.4 and older.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>...
target-i386: Emulate X86CPU subclasses for global properties
After initializing the object from its x86_def_t and before setting anyadditional cpu arguments, set any global properties for the designatedsubclass <name>{i386,x86_64}-cpu.
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>...
target-i386: Introduce X86CPU::filtered_features field
This field will contain the feature bits that were filtered out becauseof missing host support.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Reviewed-by: Eric Blake <eblake@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Add "filtered-features" property to X86CPU
This property will contain all the features that were removed from theCPU because they are not supported by the host.
This way, libvirt or other management tools can emulate thecheck/enforce behavior by checking if filtered-properties is all zeroes,...
target-i386: Add "feature-words" property to X86CPU
This property will be useful for libvirt, as libvirt already has logicbased on low-level feature bits (not feature names), so it will bereally easy to convert the current libvirt logic to something using the...
target-i386: Use FeatureWord loop on filter_features_for_kvm()
Instead of open-coding the filtering code for each feature word, changethe existing code to use the feature_word_info array, that has exactlythe same CPUID eax/ecx/register values for each feature word....
target-i386: Add ECX information to FeatureWordInfo
FEAT_7_0_EBX uses ECX as input, so we have to take that into accountwhen reporting feature word values.
target-i386: Replace cpuid_*features fields with a feature word array
This replaces the feature-bit fields on both X86CPU and x86_def_tstructs with an array.
With this, we will be able to simplify code that simply does the sameoperation on all feature words (e.g. kvm_check_features_against_host(),...
target-i386: Break CPUID feature definition lines
Break lines on kvm_check_features_against_host(), kvm_cpu_fill_host(),and builtin_x86_defs, so they don't get too long once the *_featuresfields are replaced by an array.
target-i386/kvm.c: Code formatting changes
Add appropriate spaces around operators, and break line where it needsto be broken to allow feature-words array to be introduced withouthaving too-long lines.
target-i386: Group together level, xlevel, xlevel2 fields
Consolidate level, xlevel, xlevel2 fields in x86_def_t and CPUX86State.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Reviewed-by: Igor Mammedov <imammedo@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Move APIC to ICC bus
It allows APIC to be hotplugged.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Attach ICC bus to CPU on its creation
X86CPU should have parent bus so it could provide bus for child APIC.
target-i386: Replace MSI_SPACE_SIZE with APIC_SPACE_SIZE
Put APIC_SPACE_SIZE in a public header so that it can bereused elsewhere later.
cpu: Move cpu_write_elfXX_note() functions to CPUState
Convert cpu_write_elfXX_note() functions to CPUClass methods and passCPUState as argument. Update target-i386 accordingly.
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>[AF: Retain stubs as CPUClass' default method implementation; style changes]...
cpu: Introduce get_arch_id() method and override it for X86CPU
get_arch_id() adds possibility for generic code to get a guest-visibleCPU ID without accessing CPUArchState.If derived classes don't override it, it will return cpu_index.
Override it on target-i386 in X86CPU to return the APIC ID....
target-i386: Introduce feat2prop() for CPU properties
This helper replaces '_' with '-' in a uniform way.As a side effect, even custom mappings must use '-' now.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>[AF: Split off; operate on NUL-terminated string rather than '=' delimiter]...
target-i386: Introduce apic-id CPU property
The property is used from board level to set APIC ID for CPUs itcreates. Do so in a new pc_new_cpu() helper, to be reused for hot-plug.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>...
target-i386: Do not allow to set apic-id once CPU is realized
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
i386 ROR r8/r16 instruction fix
Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the TB.
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: kvm: save/restore steal time MSR
Read and write steal time MSR, so that reporting is functional acrossmigration.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Gleb Natapov <gleb@redhat.com>
target-i386: Fix including "host" in -cpu ? output
kvm_enabled() cannot be true at this point because accelerators areinitialized much later during init. Also, hiding this makes it very hardto discover for users. Simply dump unconditionally if CONFIG_KVM is set....
target-i386: Improve -cpu ? features output
We were missing a bunch of feature lists. Fix this by simply dumpingthe meta list feature_word_info.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Reviewed-by: Igor Mammedov <imammedo@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Consolidate error propagation in x86_cpu_realizefn()
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Split APIC creation from initialization in x86_cpu_realizefn()
When APIC is hotplugged during CPU hotplug, device_set_realized()calls device_reset() on it. And if QEMU runs in KVM mode, followingcall chain will fail: apic_reset_common()...
target-i386/cpu.c: Coding style fixes
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>[AF: Changed whitespace]Reviewed-by: Igor Mammedov <imammedo@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Split out CPU creation and features parsing
Move CPU creation and features parsing into a separate cpu_x86_create()function, so that board would be able to set board-specific CPUproperties before CPU is realized.
Keep cpu_x86_init() for compatibility with the code that uses cpu_init()...
target-i386: add AES-NI instructions
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: add pclmulqdq instruction
Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: enable PCLMULQDQ on Westmere CPU
The PCLMULQDQ instruction has been introduced on the Westmere CPU.
hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
extract/unify the constant 0xfee00000 as APIC_DEFAULT_ADDRESS
A common dependency of the constant's current users:- hw/apic_common.c- hw/i386/kvmvapic.c- target-i386/cpu.cis "target-i386/cpu.h".
Signed-off-by: Laszlo Ersek <lersek@redhat.com>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>...
strip some whitespace
Signed-off-by: Laszlo Ersek <lersek@redhat.com>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Message-id: 1363821803-3380-2-git-send-email-lersek@redhat.comSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-i386: Check for host features before filter_features_for_kvm()
commit 5ec01c2e96910e1588d1a0de8609b9dda7618c7f broke "-cpu ..,enforce",as it has moved kvm_check_features_against_host() after thefilter_features_for_kvm() call. filter_features_for_kvm() removes all...
target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode
Fix the order of the of the comparisons to match the "Intel 64 andIA-32 Architectures Software Developer's Manual".
target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" mode
pcmpXstrX instructions in "Equal each" mode force both invalid elementpair to true. It means (upper - MAX) bits should be setto 1, not (upper - MAX + 1)....
target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" mode
The inner loop should only change the current bit of the result, insteadof the whole result.
target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarity
valids can equals to -1 if the reg/mem string is empty. Change theexpression to have an empty xor mask in that case.
target-i386: enable SSE4.1 and SSE4.2 in TCG mode
target-i386: SSE4.1: fix pinsrb instruction
gen_op_mov_TN_reg() loads the value in cpu_T0, so this temporary shouldbe used instead of cpu_tmp0.
target-i386: SSE4.2: fix pcmpgtq instruction
The "Intel 64 and IA-32 Architectures Software Developer's Manual" (atleast recent versions) clearly says that the comparison is signed.
target-i386: SSE4.2: fix pcmpXstri instructions
ffs1 returns the first bit set to one starting counting from the mostsignificant bit.
pcmpXstri returns the most significant bit set to one, starting countingfrom the least significant bit.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-i386: SSE4.2: fix pcmpXstrm instructions
pcmpXstrm instructions returns their result in the XMM0 register andnot in the first operand.