root / hw / ppc.h @ 38f5b2b8
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1 | 87ecb68b | pbrook | /* PowerPC hardware exceptions management helpers */
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2 | 87ecb68b | pbrook | typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
3 | c227f099 | Anthony Liguori | typedef struct clk_setup_t clk_setup_t; |
4 | c227f099 | Anthony Liguori | struct clk_setup_t {
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5 | 87ecb68b | pbrook | clk_setup_cb cb; |
6 | 87ecb68b | pbrook | void *opaque;
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7 | 87ecb68b | pbrook | }; |
8 | c227f099 | Anthony Liguori | static inline void clk_setup (clk_setup_t *clk, uint32_t freq) |
9 | 87ecb68b | pbrook | { |
10 | 87ecb68b | pbrook | if (clk->cb != NULL) |
11 | 87ecb68b | pbrook | (*clk->cb)(clk->opaque, freq); |
12 | 87ecb68b | pbrook | } |
13 | 87ecb68b | pbrook | |
14 | 87ecb68b | pbrook | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
15 | 87ecb68b | pbrook | /* Embedded PowerPC DCR management */
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16 | 87ecb68b | pbrook | typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); |
17 | 87ecb68b | pbrook | typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); |
18 | 87ecb68b | pbrook | int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), |
19 | 87ecb68b | pbrook | int (*dcr_write_error)(int dcrn)); |
20 | 87ecb68b | pbrook | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
21 | 87ecb68b | pbrook | dcr_read_cb drc_read, dcr_write_cb dcr_write); |
22 | 87ecb68b | pbrook | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
23 | 87ecb68b | pbrook | /* Embedded PowerPC reset */
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24 | 87ecb68b | pbrook | void ppc40x_core_reset (CPUState *env);
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25 | 87ecb68b | pbrook | void ppc40x_chip_reset (CPUState *env);
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26 | 87ecb68b | pbrook | void ppc40x_system_reset (CPUState *env);
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27 | 87ecb68b | pbrook | void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
28 | 87ecb68b | pbrook | |
29 | d60efc6b | Blue Swirl | extern CPUWriteMemoryFunc * const PPC_io_write[]; |
30 | d60efc6b | Blue Swirl | extern CPUReadMemoryFunc * const PPC_io_read[]; |
31 | 87ecb68b | pbrook | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
32 | b1d8e52e | blueswir1 | |
33 | b1d8e52e | blueswir1 | void ppc40x_irq_init (CPUState *env);
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34 | 9fdc60bf | aurel32 | void ppce500_irq_init (CPUState *env);
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35 | b1d8e52e | blueswir1 | void ppc6xx_irq_init (CPUState *env);
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36 | b1d8e52e | blueswir1 | void ppc970_irq_init (CPUState *env);
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37 | 5ce4aafd | aurel32 | |
38 | 5ce4aafd | aurel32 | /* PPC machines for OpenBIOS */
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39 | 5ce4aafd | aurel32 | enum {
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40 | 5ce4aafd | aurel32 | ARCH_PREP = 0,
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41 | 5ce4aafd | aurel32 | ARCH_MAC99, |
42 | 5ce4aafd | aurel32 | ARCH_HEATHROW, |
43 | 5ce4aafd | aurel32 | }; |
44 | 5ce4aafd | aurel32 | |
45 | 7f1aec5f | Laurent Vivier | #define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
46 | 7f1aec5f | Laurent Vivier | #define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
47 | 7f1aec5f | Laurent Vivier | #define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
48 | 802670e6 | Blue Swirl | |
49 | 802670e6 | Blue Swirl | #define PPC_SERIAL_MM_BAUDBASE 399193 |