Archipelago » qemu

/*

 * Tiny Code Generator for QEMU

 *

 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>

 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

/*

 * Register definitions

 */

#ifndef NDEBUG

static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {

     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",

     "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",

    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",

    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",

    "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",

    "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",

    "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",

    "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",

};

#endif

#ifdef CONFIG_USE_GUEST_BASE

#define TCG_GUEST_BASE_REG TCG_REG_R55

#else

#define TCG_GUEST_BASE_REG TCG_REG_R0

#endif

#ifndef GUEST_BASE

#define GUEST_BASE 0

#endif

/* Branch registers */

enum {

    TCG_REG_B0 = 0,

    TCG_REG_B1,

    TCG_REG_B2,

    TCG_REG_B3,

    TCG_REG_B4,

    TCG_REG_B5,

    TCG_REG_B6,

    TCG_REG_B7,

};

/* Floating point registers */

enum {

    TCG_REG_F0 = 0,

    TCG_REG_F1,

    TCG_REG_F2,

    TCG_REG_F3,

    TCG_REG_F4,

    TCG_REG_F5,

    TCG_REG_F6,

    TCG_REG_F7,

    TCG_REG_F8,

    TCG_REG_F9,

    TCG_REG_F10,

    TCG_REG_F11,

    TCG_REG_F12,

    TCG_REG_F13,

    TCG_REG_F14,

    TCG_REG_F15,

};

/* Predicate registers */

enum {

    TCG_REG_P0 = 0,

    TCG_REG_P1,

    TCG_REG_P2,

    TCG_REG_P3,

    TCG_REG_P4,

    TCG_REG_P5,

    TCG_REG_P6,

    TCG_REG_P7,

    TCG_REG_P8,

    TCG_REG_P9,

    TCG_REG_P10,

    TCG_REG_P11,

    TCG_REG_P12,

    TCG_REG_P13,

    TCG_REG_P14,

    TCG_REG_P15,

};

/* Application registers */

enum {

    TCG_REG_PFS = 64,

};

static const int tcg_target_reg_alloc_order[] = {

    TCG_REG_R34,

    TCG_REG_R35,

    TCG_REG_R36,

    TCG_REG_R37,

    TCG_REG_R38,

    TCG_REG_R39,

    TCG_REG_R40,

    TCG_REG_R41,

    TCG_REG_R42,

    TCG_REG_R43,

    TCG_REG_R44,

    TCG_REG_R45,

    TCG_REG_R46,

    TCG_REG_R47,

    TCG_REG_R48,

    TCG_REG_R49,

    TCG_REG_R50,

    TCG_REG_R51,

    TCG_REG_R52,

    TCG_REG_R53,

    TCG_REG_R54,

    TCG_REG_R55,

    TCG_REG_R14,

    TCG_REG_R15,

    TCG_REG_R16,

    TCG_REG_R17,

    TCG_REG_R18,

    TCG_REG_R19,

    TCG_REG_R20,

    TCG_REG_R21,

    TCG_REG_R22,

    TCG_REG_R23,

    TCG_REG_R24,

    TCG_REG_R25,

    TCG_REG_R26,

    TCG_REG_R27,

    TCG_REG_R28,

    TCG_REG_R29,

    TCG_REG_R30,

    TCG_REG_R31,

    TCG_REG_R56,

    TCG_REG_R57,

    TCG_REG_R58,

    TCG_REG_R59,

    TCG_REG_R60,

    TCG_REG_R61,

    TCG_REG_R62,

    TCG_REG_R63,

    TCG_REG_R8,

    TCG_REG_R9,

    TCG_REG_R10,

    TCG_REG_R11

};

static const int tcg_target_call_iarg_regs[8] = {

    TCG_REG_R56,

    TCG_REG_R57,

    TCG_REG_R58,

    TCG_REG_R59,

    TCG_REG_R60,

    TCG_REG_R61,

    TCG_REG_R62,

    TCG_REG_R63,

};

static const int tcg_target_call_oarg_regs[2] = {

    TCG_REG_R8,

    TCG_REG_R9

};

/* maximum number of register used for input function arguments */

static inline int tcg_target_get_call_iarg_regs_count(int flags)

{

    return 8;

}

/*

 * opcode formation

 */

/* bundle templates: stops (double bar in the IA64 manual) are marked with

   an uppercase letter. */

enum {

    mii = 0x00,

    miI = 0x01,

    mIi = 0x02,

    mII = 0x03,

    mlx = 0x04,

    mLX = 0x05,

    mmi = 0x08,

    mmI = 0x09,

    Mmi = 0x0a,

    MmI = 0x0b,

    mfi = 0x0c,

    mfI = 0x0d,

    mmf = 0x0e,

    mmF = 0x0f,

    mib = 0x10,

    miB = 0x11,

    mbb = 0x12,

    mbB = 0x13,

    bbb = 0x16,

    bbB = 0x17,

    mmb = 0x18,

    mmB = 0x19,

    mfb = 0x1c,

    mfB = 0x1d,

};

enum {

    OPC_ADD_A1                = 0x10000000000ull,

    OPC_AND_A1                = 0x10060000000ull,

    OPC_AND_A3                = 0x10160000000ull,

    OPC_ANDCM_A1              = 0x10068000000ull,

    OPC_ANDCM_A3              = 0x10168000000ull,

    OPC_ADDS_A4               = 0x10800000000ull,

    OPC_ADDL_A5               = 0x12000000000ull,

    OPC_ALLOC_M34             = 0x02c00000000ull,

    OPC_BR_DPTK_FEW_B1        = 0x08400000000ull,

    OPC_BR_SPTK_MANY_B1       = 0x08000001000ull,

    OPC_BR_SPTK_MANY_B4       = 0x00100001000ull,

    OPC_BR_CALL_SPTK_MANY_B5  = 0x02100001000ull,

    OPC_BR_RET_SPTK_MANY_B4   = 0x00108001100ull,

    OPC_BRL_SPTK_MANY_X3      = 0x18000001000ull,

    OPC_CMP_LT_A6             = 0x18000000000ull,

    OPC_CMP_LTU_A6            = 0x1a000000000ull,

    OPC_CMP_EQ_A6             = 0x1c000000000ull,

    OPC_CMP4_LT_A6            = 0x18400000000ull,

    OPC_CMP4_LTU_A6           = 0x1a400000000ull,

    OPC_CMP4_EQ_A6            = 0x1c400000000ull,

    OPC_DEP_Z_I12             = 0x0a600000000ull,

    OPC_EXTR_I11              = 0x0a400002000ull,

    OPC_EXTR_U_I11            = 0x0a400000000ull,

    OPC_FCVT_FX_TRUNC_S1_F10  = 0x004d0000000ull,

    OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,

    OPC_FCVT_XF_F11           = 0x000e0000000ull,

    OPC_FMA_S1_F1             = 0x10400000000ull,

    OPC_FNMA_S1_F1            = 0x18400000000ull,

    OPC_FRCPA_S1_F6           = 0x00600000000ull,

    OPC_GETF_SIG_M19          = 0x08708000000ull,

    OPC_LD1_M1                = 0x08000000000ull,

    OPC_LD1_M3                = 0x0a000000000ull,

    OPC_LD2_M1                = 0x08040000000ull,

    OPC_LD2_M3                = 0x0a040000000ull,

    OPC_LD4_M1                = 0x08080000000ull,

    OPC_LD4_M3                = 0x0a080000000ull,

    OPC_LD8_M1                = 0x080c0000000ull,

    OPC_LD8_M3                = 0x0a0c0000000ull,

    OPC_MUX1_I3               = 0x0eca0000000ull,

    OPC_NOP_B9                = 0x04008000000ull,

    OPC_NOP_F16               = 0x00008000000ull,

    OPC_NOP_I18               = 0x00008000000ull,

    OPC_NOP_M48               = 0x00008000000ull,

    OPC_MOV_I21               = 0x00e00100000ull,

    OPC_MOV_RET_I21           = 0x00e00500000ull,

    OPC_MOV_I22               = 0x00188000000ull,

    OPC_MOV_I_I26             = 0x00150000000ull,

    OPC_MOVL_X2               = 0x0c000000000ull,

    OPC_OR_A1                 = 0x10070000000ull,

    OPC_SETF_EXP_M18          = 0x0c748000000ull,

    OPC_SETF_SIG_M18          = 0x0c708000000ull,

    OPC_SHL_I7                = 0x0f240000000ull,

    OPC_SHR_I5                = 0x0f220000000ull,

    OPC_SHR_U_I5              = 0x0f200000000ull,

    OPC_SHRP_I10              = 0x0ac00000000ull,

    OPC_SXT1_I29              = 0x000a0000000ull,

    OPC_SXT2_I29              = 0x000a8000000ull,

    OPC_SXT4_I29              = 0x000b0000000ull,

    OPC_ST1_M4                = 0x08c00000000ull,

    OPC_ST2_M4                = 0x08c40000000ull,

    OPC_ST4_M4                = 0x08c80000000ull,

    OPC_ST8_M4                = 0x08cc0000000ull,

    OPC_SUB_A1                = 0x10028000000ull,

    OPC_SUB_A3                = 0x10128000000ull,

    OPC_UNPACK4_L_I2          = 0x0f860000000ull,

    OPC_XMA_L_F2              = 0x1d000000000ull,

    OPC_XOR_A1                = 0x10078000000ull,

    OPC_ZXT1_I29              = 0x00080000000ull,

    OPC_ZXT2_I29              = 0x00088000000ull,

    OPC_ZXT4_I29              = 0x00090000000ull,

};

static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,

                                  int r2, int r3)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,

                                  uint64_t imm, int r3)

{

    return opc

           | ((imm & 0x80) << 29) /* s */

           | ((imm & 0x7f) << 13) /* imm7b */

           | ((r3 & 0x7f) << 20)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,

                                  uint64_t imm, int r3)

{

    return opc

           | ((imm & 0x2000) << 23) /* s */

           | ((imm & 0x1f80) << 20) /* imm6d */

           | ((imm & 0x007f) << 13) /* imm7b */

           | ((r3 & 0x7f) << 20)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,

                                  uint64_t imm, int r3)

{

    return opc

           | ((imm & 0x200000) << 15) /* s */

           | ((imm & 0x1f0000) <<  6) /* imm5c */

           | ((imm & 0x00ff80) << 20) /* imm9d */

           | ((imm & 0x00007f) << 13) /* imm7b */

           | ((r3 & 0x03) << 20)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,

                                  int p2, int r2, int r3)

{

    return opc

           | ((p2 & 0x3f) << 27)

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((p1 & 0x3f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)

{

    return opc

           | ((imm & 0x100000) << 16) /* s */

           | ((imm & 0x0fffff) << 13) /* imm20b */

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)

{

    return opc

           | ((b2 & 0x7) << 13)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)

{

    return opc

           | ((b2 & 0x7) << 13)

           | ((b1 & 0x7) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)

{

    return opc

           | ((imm & 0x100000) << 16) /* i */

           | ((imm & 0x0fffff) << 6)  /* imm20a */

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,

                                  int f3, int f4, int f2)

{

    return opc

           | ((f4 & 0x7f) << 27)

           | ((f3 & 0x7f) << 20)

           | ((f2 & 0x7f) << 13)

           | ((f1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,

                                  int f3, int f4, int f2)

{

    return opc

           | ((f4 & 0x7f) << 27)

           | ((f3 & 0x7f) << 20)

           | ((f2 & 0x7f) << 13)

           | ((f1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,

                                  int p2, int f2, int f3)

{

    return opc

           | ((p2 & 0x3f) << 27)

           | ((f3 & 0x7f) << 20)

           | ((f2 & 0x7f) << 13)

           | ((f1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)

{

    return opc

           | ((f2 & 0x7f) << 13)

           | ((f1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)

{

    return opc

           | ((f2 & 0x7f) << 13)

           | ((f1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)

{

    return opc

           | ((imm & 0x100000) << 16) /* i */

           | ((imm & 0x0fffff) << 6)  /* imm20a */

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,

                                  int r2, int r3)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,

                                  int r2, int mbtype)

{

    return opc

           | ((mbtype & 0x0f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,

                                  int r3, int r2)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,

                                  int r2, int r3)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,

                                   int r2, int r3, uint64_t count)

{

    return opc

           | ((count & 0x3f) << 27)

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,

                                   int r3, uint64_t pos, uint64_t len)

{

    return opc

           | ((len & 0x3f) << 27)

           | ((r3 & 0x7f) << 20)

           | ((pos & 0x3f) << 14)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,

                                   int r2, uint64_t pos, uint64_t len)

{

    return opc

           | ((len & 0x3f) << 27)

           | ((pos & 0x3f) << 20)

           | ((r2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)

{

    return opc

           | ((imm & 0x100000) << 16) /* i */

           | ((imm & 0x0fffff) << 6)  /* imm20a */

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,

                                   int r2, uint64_t imm)

{

    return opc

           | ((imm & 0x1ff) << 24)

           | ((r2 & 0x7f) << 13)

           | ((b1 & 0x7) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)

{

    return opc

           | ((b2 & 0x7) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)

{

    return opc

           | ((ar3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_l2(uint64_t imm)

{

    return (imm & 0x7fffffffffc00000ull) >> 22;

}

static inline uint64_t tcg_opc_l3(uint64_t imm)

{

    return (imm & 0x07fffffffff00000ull) >> 18;

}

static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,

                                  int r3, uint64_t imm)

{

    return opc

           | ((imm & 0x100) << 28) /* s */

           | ((imm & 0x080) << 20) /* i */

           | ((imm & 0x07f) << 13) /* imm7b */

           | ((r3 & 0x7f) << 20)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)

{

    return opc

           | ((r3 & 0x7f) << 20)

           | ((r2 & 0x7f) << 13)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)

{

    return opc

           | ((r2 & 0x7f) << 13)

           | ((f1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)

{

    return opc

           | ((f2 & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,

                                   int sof, int sol, int sor)

{

    return opc

           | ((sor & 0x0f) << 27)

           | ((sol & 0x7f) << 20)

           | ((sof & 0x7f) << 13)

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)

{

    return opc

           | ((imm & 0x100000) << 16) /* i */

           | ((imm & 0x0fffff) << 6)  /* imm20a */

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,

                                  int r1, uint64_t imm)

{

    return opc

           | ((imm & 0x8000000000000000ull) >> 27) /* i */

           |  (imm & 0x0000000000200000ull)        /* ic */

           | ((imm & 0x00000000001f0000ull) << 6)  /* imm5c */

           | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */

           | ((imm & 0x000000000000007full) << 13) /* imm7b */

           | ((r1 & 0x7f) << 6)

           | (qp & 0x3f);

}

static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)

{

    return opc

           | ((imm & 0x0800000000000000ull) >> 23) /* i */

           | ((imm & 0x00000000000fffffull) << 13) /* imm20b */

           | (qp & 0x3f);

}

/*

 * Relocations

 */

static inline void reloc_pcrel21b (void *pc, tcg_target_long target)

{

    uint64_t imm;

    int64_t disp;

    int slot;

    slot = (tcg_target_long) pc & 3;

    pc = (void *)((tcg_target_long) pc & ~3);

    disp = target - (tcg_target_long) pc;

    imm = (uint64_t) disp >> 4;

    switch(slot) {

    case 0:

        *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)

                                | ((imm & 0x100000) << 21)  /* s */

                                | ((imm & 0x0fffff) << 18); /* imm20b */

        break;

    case 1:

        *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)

                                | ((imm & 0x100000) >> 2)   /* s */

                                | ((imm & 0x0fffe0) >> 5);  /* imm20b */

        *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)

                                | ((imm & 0x00001f) << 59); /* imm20b */

        break;

    case 2:

        *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)

                                | ((imm & 0x100000) << 39)  /* s */

                                | ((imm & 0x0fffff) << 36); /* imm20b */

        break;

    }

}

static inline uint64_t get_reloc_pcrel21b (void *pc)

{

    int64_t low, high;

    int slot;

    slot = (tcg_target_long) pc & 3;

    pc = (void *)((tcg_target_long) pc & ~3);

    low  = (*(uint64_t *)(pc + 0));

    high = (*(uint64_t *)(pc + 8));

    switch(slot) {

    case 0:

        return ((low >> 21) & 0x100000) + /* s */

               ((low >> 18) & 0x0fffff);  /* imm20b */

    case 1:

        return ((high << 2) & 0x100000) + /* s */

               ((high << 5) & 0x0fffe0) + /* imm20b */

               ((low >> 59) & 0x00001f);  /* imm20b */

    case 2:

        return ((high >> 39) & 0x100000) + /* s */

               ((high >> 36) & 0x0fffff);  /* imm20b */

    default:

        tcg_abort();

    }

}

static inline void reloc_pcrel60b (void *pc, tcg_target_long target)

{

    int64_t disp;

    uint64_t imm;

    disp = target - (tcg_target_long) pc;

    imm = (uint64_t) disp >> 4;

    *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)

                             |  (imm & 0x0800000000000000ull)         /* s */

                             | ((imm & 0x07fffff000000000ull) >> 36)  /* imm39 */

                             | ((imm & 0x00000000000fffffull) << 36); /* imm20b */

    *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)

                             | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */

}

static inline uint64_t get_reloc_pcrel60b (void *pc)

{

    int64_t low, high;

    low  = (*(uint64_t *)(pc + 0));

    high = (*(uint64_t *)(pc + 8));

    return ((high)       & 0x0800000000000000ull) + /* s */

           ((high >> 36) & 0x00000000000fffffull) + /* imm20b */

           ((high << 36) & 0x07fffff000000000ull) + /* imm39 */

           ((low >> 28)  & 0x0000000ffff00000ull);  /* imm39 */

}

static void patch_reloc(uint8_t *code_ptr, int type,

                        tcg_target_long value, tcg_target_long addend)

{

    value += addend;

    switch (type) {

    case R_IA64_PCREL21B:

        reloc_pcrel21b(code_ptr, value);

        break;

    case R_IA64_PCREL60B:

        reloc_pcrel60b(code_ptr, value);

    default:

        tcg_abort();

    }

}

/*

 * Constraints

 */

/* parse target specific constraints */

static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)

{

    const char *ct_str;

    ct_str = *pct_str;

    switch(ct_str[0]) {

    case 'r':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);

        break;

    case 'I':

        ct->ct |= TCG_CT_CONST_S22;

        break;

    case 'S':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);

#if defined(CONFIG_SOFTMMU)

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);

#endif

        break;

    case 'Z':

        /* We are cheating a bit here, using the fact that the register

           r0 is also the register number 0. Hence there is no need

           to check for const_args in each instruction. */

        ct->ct |= TCG_CT_CONST_ZERO;

        break;

    default:

        return -1;

    }

    ct_str++;

    *pct_str = ct_str;

    return 0;

}

/* test if a constant matches the constraint */

static inline int tcg_target_const_match(tcg_target_long val,

                                         const TCGArgConstraint *arg_ct)

{

    int ct;

    ct = arg_ct->ct;

    if (ct & TCG_CT_CONST)

        return 1;

    else if ((ct & TCG_CT_CONST_ZERO) && val == 0)

        return 1;

    else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)

        return 1;

    else

        return 0;

}

/*

 * Code generation

 */

static uint8_t *tb_ret_addr;

static inline void tcg_out_bundle(TCGContext *s, int template,

                                  uint64_t slot0, uint64_t slot1,

                                  uint64_t slot2)

{

    template &= 0x1f;          /* 5 bits */

    slot0 &= 0x1ffffffffffull; /* 41 bits */

    slot1 &= 0x1ffffffffffull; /* 41 bits */

    slot2 &= 0x1ffffffffffull; /* 41 bits */

    *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;

    *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);

    s->code_ptr += 16;

}

static inline void tcg_out_mov(TCGContext *s, TCGType type,

                               TCGArg ret, TCGArg arg)

{

    tcg_out_bundle(s, mmI,

                   tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),

                   tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),

                   tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));

}

static inline void tcg_out_movi(TCGContext *s, TCGType type,

                                TCGArg reg, tcg_target_long arg)

{