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1 | bb36d470 | bellard | /*
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2 | bb36d470 | bellard | * USB UHCI controller emulation
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3 | 5fafdf24 | ths | *
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4 | bb36d470 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 54f254f9 | aliguori | * Copyright (c) 2008 Max Krasnyansky
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7 | 54f254f9 | aliguori | * Magor rewrite of the UHCI data structures parser and frame processor
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8 | 54f254f9 | aliguori | * Support for fully async operation and multiple outstanding transactions
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9 | 54f254f9 | aliguori | *
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10 | bb36d470 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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11 | bb36d470 | bellard | * of this software and associated documentation files (the "Software"), to deal
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12 | bb36d470 | bellard | * in the Software without restriction, including without limitation the rights
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13 | bb36d470 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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14 | bb36d470 | bellard | * copies of the Software, and to permit persons to whom the Software is
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15 | bb36d470 | bellard | * furnished to do so, subject to the following conditions:
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16 | bb36d470 | bellard | *
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17 | bb36d470 | bellard | * The above copyright notice and this permission notice shall be included in
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18 | bb36d470 | bellard | * all copies or substantial portions of the Software.
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19 | bb36d470 | bellard | *
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20 | bb36d470 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 | bb36d470 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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22 | bb36d470 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 | bb36d470 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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24 | bb36d470 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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25 | bb36d470 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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26 | bb36d470 | bellard | * THE SOFTWARE.
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27 | bb36d470 | bellard | */
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28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "usb.h" |
30 | 87ecb68b | pbrook | #include "pci.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 18e08a55 | Michael S. Tsirkin | #include "usb-uhci.h" |
33 | bb36d470 | bellard | |
34 | bb36d470 | bellard | //#define DEBUG
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35 | 54f254f9 | aliguori | //#define DEBUG_DUMP_DATA
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36 | bb36d470 | bellard | |
37 | 96217e31 | ths | #define UHCI_CMD_FGR (1 << 4) |
38 | 96217e31 | ths | #define UHCI_CMD_EGSM (1 << 3) |
39 | bb36d470 | bellard | #define UHCI_CMD_GRESET (1 << 2) |
40 | bb36d470 | bellard | #define UHCI_CMD_HCRESET (1 << 1) |
41 | bb36d470 | bellard | #define UHCI_CMD_RS (1 << 0) |
42 | bb36d470 | bellard | |
43 | bb36d470 | bellard | #define UHCI_STS_HCHALTED (1 << 5) |
44 | bb36d470 | bellard | #define UHCI_STS_HCPERR (1 << 4) |
45 | bb36d470 | bellard | #define UHCI_STS_HSERR (1 << 3) |
46 | bb36d470 | bellard | #define UHCI_STS_RD (1 << 2) |
47 | bb36d470 | bellard | #define UHCI_STS_USBERR (1 << 1) |
48 | bb36d470 | bellard | #define UHCI_STS_USBINT (1 << 0) |
49 | bb36d470 | bellard | |
50 | bb36d470 | bellard | #define TD_CTRL_SPD (1 << 29) |
51 | bb36d470 | bellard | #define TD_CTRL_ERROR_SHIFT 27 |
52 | bb36d470 | bellard | #define TD_CTRL_IOS (1 << 25) |
53 | bb36d470 | bellard | #define TD_CTRL_IOC (1 << 24) |
54 | bb36d470 | bellard | #define TD_CTRL_ACTIVE (1 << 23) |
55 | bb36d470 | bellard | #define TD_CTRL_STALL (1 << 22) |
56 | bb36d470 | bellard | #define TD_CTRL_BABBLE (1 << 20) |
57 | bb36d470 | bellard | #define TD_CTRL_NAK (1 << 19) |
58 | bb36d470 | bellard | #define TD_CTRL_TIMEOUT (1 << 18) |
59 | bb36d470 | bellard | |
60 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_SUSPEND (1 << 12) |
61 | bb36d470 | bellard | #define UHCI_PORT_RESET (1 << 9) |
62 | bb36d470 | bellard | #define UHCI_PORT_LSDA (1 << 8) |
63 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_RD (1 << 6) |
64 | bb36d470 | bellard | #define UHCI_PORT_ENC (1 << 3) |
65 | bb36d470 | bellard | #define UHCI_PORT_EN (1 << 2) |
66 | bb36d470 | bellard | #define UHCI_PORT_CSC (1 << 1) |
67 | bb36d470 | bellard | #define UHCI_PORT_CCS (1 << 0) |
68 | bb36d470 | bellard | |
69 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_READ_ONLY (0x1bb) |
70 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
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71 | 9159f679 | Gerd Hoffmann | |
72 | bb36d470 | bellard | #define FRAME_TIMER_FREQ 1000 |
73 | bb36d470 | bellard | |
74 | bb36d470 | bellard | #define FRAME_MAX_LOOPS 100 |
75 | bb36d470 | bellard | |
76 | bb36d470 | bellard | #define NB_PORTS 2 |
77 | bb36d470 | bellard | |
78 | 54f254f9 | aliguori | #ifdef DEBUG
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79 | d0f2c4c6 | malc | #define DPRINTF printf
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80 | 54f254f9 | aliguori | |
81 | 0bf9e31a | Blue Swirl | static const char *pid2str(int pid) |
82 | 54f254f9 | aliguori | { |
83 | 54f254f9 | aliguori | switch (pid) {
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84 | 54f254f9 | aliguori | case USB_TOKEN_SETUP: return "SETUP"; |
85 | 54f254f9 | aliguori | case USB_TOKEN_IN: return "IN"; |
86 | 54f254f9 | aliguori | case USB_TOKEN_OUT: return "OUT"; |
87 | 54f254f9 | aliguori | } |
88 | 54f254f9 | aliguori | return "?"; |
89 | 54f254f9 | aliguori | } |
90 | 54f254f9 | aliguori | |
91 | 54f254f9 | aliguori | #else
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92 | d0f2c4c6 | malc | #define DPRINTF(...)
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93 | 54f254f9 | aliguori | #endif
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94 | 54f254f9 | aliguori | |
95 | 54f254f9 | aliguori | #ifdef DEBUG_DUMP_DATA
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96 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) |
97 | 54f254f9 | aliguori | { |
98 | 54f254f9 | aliguori | int i;
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99 | 54f254f9 | aliguori | |
100 | 54f254f9 | aliguori | printf("uhci: data: ");
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101 | 54f254f9 | aliguori | for(i = 0; i < len; i++) |
102 | 54f254f9 | aliguori | printf(" %02x", data[i]);
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103 | 54f254f9 | aliguori | printf("\n");
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104 | 54f254f9 | aliguori | } |
105 | 54f254f9 | aliguori | #else
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106 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) {} |
107 | 54f254f9 | aliguori | #endif
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108 | 54f254f9 | aliguori | |
109 | 7b5a44c5 | Gerd Hoffmann | typedef struct UHCIState UHCIState; |
110 | 7b5a44c5 | Gerd Hoffmann | |
111 | 54f254f9 | aliguori | /*
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112 | 54f254f9 | aliguori | * Pending async transaction.
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113 | 54f254f9 | aliguori | * 'packet' must be the first field because completion
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114 | 54f254f9 | aliguori | * handler does "(UHCIAsync *) pkt" cast.
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115 | 54f254f9 | aliguori | */
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116 | 54f254f9 | aliguori | typedef struct UHCIAsync { |
117 | 54f254f9 | aliguori | USBPacket packet; |
118 | 7b5a44c5 | Gerd Hoffmann | UHCIState *uhci; |
119 | ddf6583f | Gerd Hoffmann | QTAILQ_ENTRY(UHCIAsync) next; |
120 | 54f254f9 | aliguori | uint32_t td; |
121 | 54f254f9 | aliguori | uint32_t token; |
122 | 54f254f9 | aliguori | int8_t valid; |
123 | 8e65b7c0 | David S. Ahern | uint8_t isoc; |
124 | 54f254f9 | aliguori | uint8_t done; |
125 | 54f254f9 | aliguori | uint8_t buffer[2048];
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126 | 54f254f9 | aliguori | } UHCIAsync; |
127 | 54f254f9 | aliguori | |
128 | bb36d470 | bellard | typedef struct UHCIPort { |
129 | bb36d470 | bellard | USBPort port; |
130 | bb36d470 | bellard | uint16_t ctrl; |
131 | bb36d470 | bellard | } UHCIPort; |
132 | bb36d470 | bellard | |
133 | 7b5a44c5 | Gerd Hoffmann | struct UHCIState {
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134 | bb36d470 | bellard | PCIDevice dev; |
135 | b2317837 | Gerd Hoffmann | USBBus bus; |
136 | bb36d470 | bellard | uint16_t cmd; /* cmd register */
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137 | bb36d470 | bellard | uint16_t status; |
138 | bb36d470 | bellard | uint16_t intr; /* interrupt enable register */
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139 | bb36d470 | bellard | uint16_t frnum; /* frame number */
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140 | bb36d470 | bellard | uint32_t fl_base_addr; /* frame list base address */
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141 | bb36d470 | bellard | uint8_t sof_timing; |
142 | bb36d470 | bellard | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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143 | 8e65b7c0 | David S. Ahern | int64_t expire_time; |
144 | bb36d470 | bellard | QEMUTimer *frame_timer; |
145 | bb36d470 | bellard | UHCIPort ports[NB_PORTS]; |
146 | 4d611c9a | pbrook | |
147 | 4d611c9a | pbrook | /* Interrupts that should be raised at the end of the current frame. */
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148 | 4d611c9a | pbrook | uint32_t pending_int_mask; |
149 | 54f254f9 | aliguori | |
150 | 54f254f9 | aliguori | /* Active packets */
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151 | ddf6583f | Gerd Hoffmann | QTAILQ_HEAD(,UHCIAsync) async_pending; |
152 | 64e58fe5 | Juan Quintela | uint8_t num_ports_vmstate; |
153 | 7b5a44c5 | Gerd Hoffmann | }; |
154 | bb36d470 | bellard | |
155 | bb36d470 | bellard | typedef struct UHCI_TD { |
156 | bb36d470 | bellard | uint32_t link; |
157 | bb36d470 | bellard | uint32_t ctrl; /* see TD_CTRL_xxx */
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158 | bb36d470 | bellard | uint32_t token; |
159 | bb36d470 | bellard | uint32_t buffer; |
160 | bb36d470 | bellard | } UHCI_TD; |
161 | bb36d470 | bellard | |
162 | bb36d470 | bellard | typedef struct UHCI_QH { |
163 | bb36d470 | bellard | uint32_t link; |
164 | bb36d470 | bellard | uint32_t el_link; |
165 | bb36d470 | bellard | } UHCI_QH; |
166 | bb36d470 | bellard | |
167 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_alloc(UHCIState *s)
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168 | 54f254f9 | aliguori | { |
169 | 54f254f9 | aliguori | UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
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170 | 487414f1 | aliguori | |
171 | 487414f1 | aliguori | memset(&async->packet, 0, sizeof(async->packet)); |
172 | 7b5a44c5 | Gerd Hoffmann | async->uhci = s; |
173 | 487414f1 | aliguori | async->valid = 0;
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174 | 487414f1 | aliguori | async->td = 0;
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175 | 487414f1 | aliguori | async->token = 0;
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176 | 487414f1 | aliguori | async->done = 0;
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177 | 8e65b7c0 | David S. Ahern | async->isoc = 0;
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178 | 54f254f9 | aliguori | |
179 | 54f254f9 | aliguori | return async;
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180 | 54f254f9 | aliguori | } |
181 | 54f254f9 | aliguori | |
182 | 54f254f9 | aliguori | static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
183 | 54f254f9 | aliguori | { |
184 | 54f254f9 | aliguori | qemu_free(async); |
185 | 54f254f9 | aliguori | } |
186 | 54f254f9 | aliguori | |
187 | 54f254f9 | aliguori | static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
188 | 54f254f9 | aliguori | { |
189 | ddf6583f | Gerd Hoffmann | QTAILQ_INSERT_HEAD(&s->async_pending, async, next); |
190 | 54f254f9 | aliguori | } |
191 | 54f254f9 | aliguori | |
192 | 54f254f9 | aliguori | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
193 | 54f254f9 | aliguori | { |
194 | ddf6583f | Gerd Hoffmann | QTAILQ_REMOVE(&s->async_pending, async, next); |
195 | 54f254f9 | aliguori | } |
196 | 54f254f9 | aliguori | |
197 | 54f254f9 | aliguori | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
198 | 54f254f9 | aliguori | { |
199 | d0f2c4c6 | malc | DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
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200 | 54f254f9 | aliguori | async->td, async->token, async->done); |
201 | 54f254f9 | aliguori | |
202 | 54f254f9 | aliguori | if (!async->done)
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203 | 54f254f9 | aliguori | usb_cancel_packet(&async->packet); |
204 | 54f254f9 | aliguori | uhci_async_free(s, async); |
205 | 54f254f9 | aliguori | } |
206 | 54f254f9 | aliguori | |
207 | 54f254f9 | aliguori | /*
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208 | 54f254f9 | aliguori | * Mark all outstanding async packets as invalid.
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209 | 54f254f9 | aliguori | * This is used for canceling them when TDs are removed by the HCD.
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210 | 54f254f9 | aliguori | */
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211 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
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212 | 54f254f9 | aliguori | { |
213 | ddf6583f | Gerd Hoffmann | UHCIAsync *async; |
214 | 54f254f9 | aliguori | |
215 | ddf6583f | Gerd Hoffmann | QTAILQ_FOREACH(async, &s->async_pending, next) { |
216 | 54f254f9 | aliguori | async->valid--; |
217 | 54f254f9 | aliguori | } |
218 | 54f254f9 | aliguori | return NULL; |
219 | 54f254f9 | aliguori | } |
220 | 54f254f9 | aliguori | |
221 | 54f254f9 | aliguori | /*
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222 | 54f254f9 | aliguori | * Cancel async packets that are no longer valid
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223 | 54f254f9 | aliguori | */
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224 | 54f254f9 | aliguori | static void uhci_async_validate_end(UHCIState *s) |
225 | 54f254f9 | aliguori | { |
226 | ddf6583f | Gerd Hoffmann | UHCIAsync *curr, *n; |
227 | 54f254f9 | aliguori | |
228 | ddf6583f | Gerd Hoffmann | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
229 | 54f254f9 | aliguori | if (curr->valid > 0) { |
230 | 54f254f9 | aliguori | continue;
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231 | 54f254f9 | aliguori | } |
232 | ddf6583f | Gerd Hoffmann | uhci_async_unlink(s, curr); |
233 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
234 | 54f254f9 | aliguori | } |
235 | 54f254f9 | aliguori | } |
236 | 54f254f9 | aliguori | |
237 | 54f254f9 | aliguori | static void uhci_async_cancel_all(UHCIState *s) |
238 | 54f254f9 | aliguori | { |
239 | ddf6583f | Gerd Hoffmann | UHCIAsync *curr, *n; |
240 | 54f254f9 | aliguori | |
241 | ddf6583f | Gerd Hoffmann | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
242 | ddf6583f | Gerd Hoffmann | uhci_async_unlink(s, curr); |
243 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
244 | 54f254f9 | aliguori | } |
245 | 54f254f9 | aliguori | } |
246 | 54f254f9 | aliguori | |
247 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
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248 | 54f254f9 | aliguori | { |
249 | ddf6583f | Gerd Hoffmann | UHCIAsync *async; |
250 | e8ee3c72 | aurel32 | UHCIAsync *match = NULL;
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251 | e8ee3c72 | aurel32 | int count = 0; |
252 | e8ee3c72 | aurel32 | |
253 | e8ee3c72 | aurel32 | /*
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254 | e8ee3c72 | aurel32 | * We're looking for the best match here. ie both td addr and token.
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255 | e8ee3c72 | aurel32 | * Otherwise we return last good match. ie just token.
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256 | e8ee3c72 | aurel32 | * It's ok to match just token because it identifies the transaction
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257 | e8ee3c72 | aurel32 | * rather well, token includes: device addr, endpoint, size, etc.
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258 | e8ee3c72 | aurel32 | *
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259 | e8ee3c72 | aurel32 | * Also since we queue async transactions in reverse order by returning
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260 | e8ee3c72 | aurel32 | * last good match we restores the order.
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261 | e8ee3c72 | aurel32 | *
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262 | e8ee3c72 | aurel32 | * It's expected that we wont have a ton of outstanding transactions.
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263 | e8ee3c72 | aurel32 | * If we ever do we'd want to optimize this algorithm.
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264 | e8ee3c72 | aurel32 | */
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265 | 54f254f9 | aliguori | |
266 | ddf6583f | Gerd Hoffmann | QTAILQ_FOREACH(async, &s->async_pending, next) { |
267 | e8ee3c72 | aurel32 | if (async->token == token) {
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268 | e8ee3c72 | aurel32 | /* Good match */
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269 | e8ee3c72 | aurel32 | match = async; |
270 | e8ee3c72 | aurel32 | |
271 | e8ee3c72 | aurel32 | if (async->td == addr) {
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272 | e8ee3c72 | aurel32 | /* Best match */
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273 | e8ee3c72 | aurel32 | break;
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274 | 54f254f9 | aliguori | } |
275 | 54f254f9 | aliguori | } |
276 | e8ee3c72 | aurel32 | count++; |
277 | 54f254f9 | aliguori | } |
278 | e8ee3c72 | aurel32 | |
279 | e8ee3c72 | aurel32 | if (count > 64) |
280 | e8ee3c72 | aurel32 | fprintf(stderr, "uhci: warning lots of async transactions\n");
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281 | e8ee3c72 | aurel32 | |
282 | e8ee3c72 | aurel32 | return match;
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283 | 54f254f9 | aliguori | } |
284 | 54f254f9 | aliguori | |
285 | bb36d470 | bellard | static void uhci_update_irq(UHCIState *s) |
286 | bb36d470 | bellard | { |
287 | bb36d470 | bellard | int level;
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288 | bb36d470 | bellard | if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
289 | bb36d470 | bellard | ((s->status2 & 2) && (s->intr & (1 << 3))) || |
290 | bb36d470 | bellard | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
291 | bb36d470 | bellard | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
292 | bb36d470 | bellard | (s->status & UHCI_STS_HSERR) || |
293 | bb36d470 | bellard | (s->status & UHCI_STS_HCPERR)) { |
294 | bb36d470 | bellard | level = 1;
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295 | bb36d470 | bellard | } else {
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296 | bb36d470 | bellard | level = 0;
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297 | bb36d470 | bellard | } |
298 | d537cf6c | pbrook | qemu_set_irq(s->dev.irq[3], level);
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299 | bb36d470 | bellard | } |
300 | bb36d470 | bellard | |
301 | c8075ac3 | Gleb Natapov | static void uhci_reset(void *opaque) |
302 | bb36d470 | bellard | { |
303 | c8075ac3 | Gleb Natapov | UHCIState *s = opaque; |
304 | bb36d470 | bellard | uint8_t *pci_conf; |
305 | bb36d470 | bellard | int i;
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306 | bb36d470 | bellard | UHCIPort *port; |
307 | bb36d470 | bellard | |
308 | d0f2c4c6 | malc | DPRINTF("uhci: full reset\n");
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309 | 6f382b5e | aliguori | |
310 | bb36d470 | bellard | pci_conf = s->dev.config; |
311 | bb36d470 | bellard | |
312 | bb36d470 | bellard | pci_conf[0x6a] = 0x01; /* usb clock */ |
313 | bb36d470 | bellard | pci_conf[0x6b] = 0x00; |
314 | bb36d470 | bellard | s->cmd = 0;
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315 | bb36d470 | bellard | s->status = 0;
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316 | bb36d470 | bellard | s->status2 = 0;
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317 | bb36d470 | bellard | s->intr = 0;
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318 | bb36d470 | bellard | s->fl_base_addr = 0;
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319 | bb36d470 | bellard | s->sof_timing = 64;
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320 | 54f254f9 | aliguori | |
321 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
322 | bb36d470 | bellard | port = &s->ports[i]; |
323 | bb36d470 | bellard | port->ctrl = 0x0080;
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324 | 618c169b | Gerd Hoffmann | if (port->port.dev) {
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325 | 618c169b | Gerd Hoffmann | usb_attach(&port->port, port->port.dev); |
326 | 618c169b | Gerd Hoffmann | } |
327 | bb36d470 | bellard | } |
328 | 54f254f9 | aliguori | |
329 | 54f254f9 | aliguori | uhci_async_cancel_all(s); |
330 | bb36d470 | bellard | } |
331 | bb36d470 | bellard | |
332 | 817afc61 | Juan Quintela | static void uhci_pre_save(void *opaque) |
333 | b9dc033c | balrog | { |
334 | b9dc033c | balrog | UHCIState *s = opaque; |
335 | b9dc033c | balrog | |
336 | 6f382b5e | aliguori | uhci_async_cancel_all(s); |
337 | b9dc033c | balrog | } |
338 | b9dc033c | balrog | |
339 | 817afc61 | Juan Quintela | static const VMStateDescription vmstate_uhci_port = { |
340 | 817afc61 | Juan Quintela | .name = "uhci port",
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341 | 817afc61 | Juan Quintela | .version_id = 1,
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342 | 817afc61 | Juan Quintela | .minimum_version_id = 1,
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343 | 817afc61 | Juan Quintela | .minimum_version_id_old = 1,
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344 | 817afc61 | Juan Quintela | .fields = (VMStateField []) { |
345 | 817afc61 | Juan Quintela | VMSTATE_UINT16(ctrl, UHCIPort), |
346 | 817afc61 | Juan Quintela | VMSTATE_END_OF_LIST() |
347 | 817afc61 | Juan Quintela | } |
348 | 817afc61 | Juan Quintela | }; |
349 | 817afc61 | Juan Quintela | |
350 | 817afc61 | Juan Quintela | static const VMStateDescription vmstate_uhci = { |
351 | 817afc61 | Juan Quintela | .name = "uhci",
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352 | 6881dd5f | TeLeMan | .version_id = 2,
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353 | 817afc61 | Juan Quintela | .minimum_version_id = 1,
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354 | 817afc61 | Juan Quintela | .minimum_version_id_old = 1,
|
355 | 817afc61 | Juan Quintela | .pre_save = uhci_pre_save, |
356 | 817afc61 | Juan Quintela | .fields = (VMStateField []) { |
357 | 817afc61 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, UHCIState), |
358 | 817afc61 | Juan Quintela | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), |
359 | 817afc61 | Juan Quintela | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
|
360 | 817afc61 | Juan Quintela | vmstate_uhci_port, UHCIPort), |
361 | 817afc61 | Juan Quintela | VMSTATE_UINT16(cmd, UHCIState), |
362 | 817afc61 | Juan Quintela | VMSTATE_UINT16(status, UHCIState), |
363 | 817afc61 | Juan Quintela | VMSTATE_UINT16(intr, UHCIState), |
364 | 817afc61 | Juan Quintela | VMSTATE_UINT16(frnum, UHCIState), |
365 | 817afc61 | Juan Quintela | VMSTATE_UINT32(fl_base_addr, UHCIState), |
366 | 817afc61 | Juan Quintela | VMSTATE_UINT8(sof_timing, UHCIState), |
367 | 817afc61 | Juan Quintela | VMSTATE_UINT8(status2, UHCIState), |
368 | 817afc61 | Juan Quintela | VMSTATE_TIMER(frame_timer, UHCIState), |
369 | 6881dd5f | TeLeMan | VMSTATE_INT64_V(expire_time, UHCIState, 2),
|
370 | 817afc61 | Juan Quintela | VMSTATE_END_OF_LIST() |
371 | 817afc61 | Juan Quintela | } |
372 | 817afc61 | Juan Quintela | }; |
373 | b9dc033c | balrog | |
374 | bb36d470 | bellard | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
375 | bb36d470 | bellard | { |
376 | bb36d470 | bellard | UHCIState *s = opaque; |
377 | 3b46e624 | ths | |
378 | bb36d470 | bellard | addr &= 0x1f;
|
379 | bb36d470 | bellard | switch(addr) {
|
380 | bb36d470 | bellard | case 0x0c: |
381 | bb36d470 | bellard | s->sof_timing = val; |
382 | bb36d470 | bellard | break;
|
383 | bb36d470 | bellard | } |
384 | bb36d470 | bellard | } |
385 | bb36d470 | bellard | |
386 | bb36d470 | bellard | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
387 | bb36d470 | bellard | { |
388 | bb36d470 | bellard | UHCIState *s = opaque; |
389 | bb36d470 | bellard | uint32_t val; |
390 | bb36d470 | bellard | |
391 | bb36d470 | bellard | addr &= 0x1f;
|
392 | bb36d470 | bellard | switch(addr) {
|
393 | bb36d470 | bellard | case 0x0c: |
394 | bb36d470 | bellard | val = s->sof_timing; |
395 | d80cfb3f | pbrook | break;
|
396 | bb36d470 | bellard | default:
|
397 | bb36d470 | bellard | val = 0xff;
|
398 | bb36d470 | bellard | break;
|
399 | bb36d470 | bellard | } |
400 | bb36d470 | bellard | return val;
|
401 | bb36d470 | bellard | } |
402 | bb36d470 | bellard | |
403 | bb36d470 | bellard | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
404 | bb36d470 | bellard | { |
405 | bb36d470 | bellard | UHCIState *s = opaque; |
406 | 3b46e624 | ths | |
407 | bb36d470 | bellard | addr &= 0x1f;
|
408 | d0f2c4c6 | malc | DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
409 | 54f254f9 | aliguori | |
410 | bb36d470 | bellard | switch(addr) {
|
411 | bb36d470 | bellard | case 0x00: |
412 | bb36d470 | bellard | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
413 | bb36d470 | bellard | /* start frame processing */
|
414 | 74475455 | Paolo Bonzini | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
415 | 52328140 | bellard | s->status &= ~UHCI_STS_HCHALTED; |
416 | 467d409f | bellard | } else if (!(val & UHCI_CMD_RS)) { |
417 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
418 | bb36d470 | bellard | } |
419 | bb36d470 | bellard | if (val & UHCI_CMD_GRESET) {
|
420 | bb36d470 | bellard | UHCIPort *port; |
421 | bb36d470 | bellard | USBDevice *dev; |
422 | bb36d470 | bellard | int i;
|
423 | bb36d470 | bellard | |
424 | bb36d470 | bellard | /* send reset on the USB bus */
|
425 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
426 | bb36d470 | bellard | port = &s->ports[i]; |
427 | a594cfbf | bellard | dev = port->port.dev; |
428 | bb36d470 | bellard | if (dev) {
|
429 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
430 | bb36d470 | bellard | } |
431 | bb36d470 | bellard | } |
432 | bb36d470 | bellard | uhci_reset(s); |
433 | bb36d470 | bellard | return;
|
434 | bb36d470 | bellard | } |
435 | 5e9ab4c4 | bellard | if (val & UHCI_CMD_HCRESET) {
|
436 | bb36d470 | bellard | uhci_reset(s); |
437 | bb36d470 | bellard | return;
|
438 | bb36d470 | bellard | } |
439 | bb36d470 | bellard | s->cmd = val; |
440 | bb36d470 | bellard | break;
|
441 | bb36d470 | bellard | case 0x02: |
442 | bb36d470 | bellard | s->status &= ~val; |
443 | bb36d470 | bellard | /* XXX: the chip spec is not coherent, so we add a hidden
|
444 | bb36d470 | bellard | register to distinguish between IOC and SPD */
|
445 | bb36d470 | bellard | if (val & UHCI_STS_USBINT)
|
446 | bb36d470 | bellard | s->status2 = 0;
|
447 | bb36d470 | bellard | uhci_update_irq(s); |
448 | bb36d470 | bellard | break;
|
449 | bb36d470 | bellard | case 0x04: |
450 | bb36d470 | bellard | s->intr = val; |
451 | bb36d470 | bellard | uhci_update_irq(s); |
452 | bb36d470 | bellard | break;
|
453 | bb36d470 | bellard | case 0x06: |
454 | bb36d470 | bellard | if (s->status & UHCI_STS_HCHALTED)
|
455 | bb36d470 | bellard | s->frnum = val & 0x7ff;
|
456 | bb36d470 | bellard | break;
|
457 | bb36d470 | bellard | case 0x10 ... 0x1f: |
458 | bb36d470 | bellard | { |
459 | bb36d470 | bellard | UHCIPort *port; |
460 | bb36d470 | bellard | USBDevice *dev; |
461 | bb36d470 | bellard | int n;
|
462 | bb36d470 | bellard | |
463 | bb36d470 | bellard | n = (addr >> 1) & 7; |
464 | bb36d470 | bellard | if (n >= NB_PORTS)
|
465 | bb36d470 | bellard | return;
|
466 | bb36d470 | bellard | port = &s->ports[n]; |
467 | a594cfbf | bellard | dev = port->port.dev; |
468 | bb36d470 | bellard | if (dev) {
|
469 | bb36d470 | bellard | /* port reset */
|
470 | 5fafdf24 | ths | if ( (val & UHCI_PORT_RESET) &&
|
471 | bb36d470 | bellard | !(port->ctrl & UHCI_PORT_RESET) ) { |
472 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
473 | bb36d470 | bellard | } |
474 | bb36d470 | bellard | } |
475 | 9159f679 | Gerd Hoffmann | port->ctrl &= UHCI_PORT_READ_ONLY; |
476 | 9159f679 | Gerd Hoffmann | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
477 | bb36d470 | bellard | /* some bits are reset when a '1' is written to them */
|
478 | 9159f679 | Gerd Hoffmann | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
479 | bb36d470 | bellard | } |
480 | bb36d470 | bellard | break;
|
481 | bb36d470 | bellard | } |
482 | bb36d470 | bellard | } |
483 | bb36d470 | bellard | |
484 | bb36d470 | bellard | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
485 | bb36d470 | bellard | { |
486 | bb36d470 | bellard | UHCIState *s = opaque; |
487 | bb36d470 | bellard | uint32_t val; |
488 | bb36d470 | bellard | |
489 | bb36d470 | bellard | addr &= 0x1f;
|
490 | bb36d470 | bellard | switch(addr) {
|
491 | bb36d470 | bellard | case 0x00: |
492 | bb36d470 | bellard | val = s->cmd; |
493 | bb36d470 | bellard | break;
|
494 | bb36d470 | bellard | case 0x02: |
495 | bb36d470 | bellard | val = s->status; |
496 | bb36d470 | bellard | break;
|
497 | bb36d470 | bellard | case 0x04: |
498 | bb36d470 | bellard | val = s->intr; |
499 | bb36d470 | bellard | break;
|
500 | bb36d470 | bellard | case 0x06: |
501 | bb36d470 | bellard | val = s->frnum; |
502 | bb36d470 | bellard | break;
|
503 | bb36d470 | bellard | case 0x10 ... 0x1f: |
504 | bb36d470 | bellard | { |
505 | bb36d470 | bellard | UHCIPort *port; |
506 | bb36d470 | bellard | int n;
|
507 | bb36d470 | bellard | n = (addr >> 1) & 7; |
508 | 5fafdf24 | ths | if (n >= NB_PORTS)
|
509 | bb36d470 | bellard | goto read_default;
|
510 | bb36d470 | bellard | port = &s->ports[n]; |
511 | bb36d470 | bellard | val = port->ctrl; |
512 | bb36d470 | bellard | } |
513 | bb36d470 | bellard | break;
|
514 | bb36d470 | bellard | default:
|
515 | bb36d470 | bellard | read_default:
|
516 | bb36d470 | bellard | val = 0xff7f; /* disabled port */ |
517 | bb36d470 | bellard | break;
|
518 | bb36d470 | bellard | } |
519 | 54f254f9 | aliguori | |
520 | d0f2c4c6 | malc | DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
521 | 54f254f9 | aliguori | |
522 | bb36d470 | bellard | return val;
|
523 | bb36d470 | bellard | } |
524 | bb36d470 | bellard | |
525 | bb36d470 | bellard | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
526 | bb36d470 | bellard | { |
527 | bb36d470 | bellard | UHCIState *s = opaque; |
528 | bb36d470 | bellard | |
529 | bb36d470 | bellard | addr &= 0x1f;
|
530 | d0f2c4c6 | malc | DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
531 | 54f254f9 | aliguori | |
532 | bb36d470 | bellard | switch(addr) {
|
533 | bb36d470 | bellard | case 0x08: |
534 | bb36d470 | bellard | s->fl_base_addr = val & ~0xfff;
|
535 | bb36d470 | bellard | break;
|
536 | bb36d470 | bellard | } |
537 | bb36d470 | bellard | } |
538 | bb36d470 | bellard | |
539 | bb36d470 | bellard | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
540 | bb36d470 | bellard | { |
541 | bb36d470 | bellard | UHCIState *s = opaque; |
542 | bb36d470 | bellard | uint32_t val; |
543 | bb36d470 | bellard | |
544 | bb36d470 | bellard | addr &= 0x1f;
|
545 | bb36d470 | bellard | switch(addr) {
|
546 | bb36d470 | bellard | case 0x08: |
547 | bb36d470 | bellard | val = s->fl_base_addr; |
548 | bb36d470 | bellard | break;
|
549 | bb36d470 | bellard | default:
|
550 | bb36d470 | bellard | val = 0xffffffff;
|
551 | bb36d470 | bellard | break;
|
552 | bb36d470 | bellard | } |
553 | bb36d470 | bellard | return val;
|
554 | bb36d470 | bellard | } |
555 | bb36d470 | bellard | |
556 | 96217e31 | ths | /* signal resume if controller suspended */
|
557 | 96217e31 | ths | static void uhci_resume (void *opaque) |
558 | 96217e31 | ths | { |
559 | 96217e31 | ths | UHCIState *s = (UHCIState *)opaque; |
560 | 96217e31 | ths | |
561 | 96217e31 | ths | if (!s)
|
562 | 96217e31 | ths | return;
|
563 | 96217e31 | ths | |
564 | 96217e31 | ths | if (s->cmd & UHCI_CMD_EGSM) {
|
565 | 96217e31 | ths | s->cmd |= UHCI_CMD_FGR; |
566 | 96217e31 | ths | s->status |= UHCI_STS_RD; |
567 | 96217e31 | ths | uhci_update_irq(s); |
568 | 96217e31 | ths | } |
569 | 96217e31 | ths | } |
570 | 96217e31 | ths | |
571 | 618c169b | Gerd Hoffmann | static void uhci_attach(USBPort *port1) |
572 | bb36d470 | bellard | { |
573 | bb36d470 | bellard | UHCIState *s = port1->opaque; |
574 | bb36d470 | bellard | UHCIPort *port = &s->ports[port1->index]; |
575 | bb36d470 | bellard | |
576 | 618c169b | Gerd Hoffmann | /* set connect status */
|
577 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
578 | 61064870 | pbrook | |
579 | 618c169b | Gerd Hoffmann | /* update speed */
|
580 | 618c169b | Gerd Hoffmann | if (port->port.dev->speed == USB_SPEED_LOW) {
|
581 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_LSDA; |
582 | bb36d470 | bellard | } else {
|
583 | 618c169b | Gerd Hoffmann | port->ctrl &= ~UHCI_PORT_LSDA; |
584 | 618c169b | Gerd Hoffmann | } |
585 | 96217e31 | ths | |
586 | 618c169b | Gerd Hoffmann | uhci_resume(s); |
587 | 618c169b | Gerd Hoffmann | } |
588 | 96217e31 | ths | |
589 | 618c169b | Gerd Hoffmann | static void uhci_detach(USBPort *port1) |
590 | 618c169b | Gerd Hoffmann | { |
591 | 618c169b | Gerd Hoffmann | UHCIState *s = port1->opaque; |
592 | 618c169b | Gerd Hoffmann | UHCIPort *port = &s->ports[port1->index]; |
593 | 618c169b | Gerd Hoffmann | |
594 | 618c169b | Gerd Hoffmann | /* set connect status */
|
595 | 618c169b | Gerd Hoffmann | if (port->ctrl & UHCI_PORT_CCS) {
|
596 | 618c169b | Gerd Hoffmann | port->ctrl &= ~UHCI_PORT_CCS; |
597 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_CSC; |
598 | bb36d470 | bellard | } |
599 | 618c169b | Gerd Hoffmann | /* disable port */
|
600 | 618c169b | Gerd Hoffmann | if (port->ctrl & UHCI_PORT_EN) {
|
601 | 618c169b | Gerd Hoffmann | port->ctrl &= ~UHCI_PORT_EN; |
602 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_ENC; |
603 | 618c169b | Gerd Hoffmann | } |
604 | 618c169b | Gerd Hoffmann | |
605 | 618c169b | Gerd Hoffmann | uhci_resume(s); |
606 | bb36d470 | bellard | } |
607 | bb36d470 | bellard | |
608 | 9159f679 | Gerd Hoffmann | static void uhci_wakeup(USBDevice *dev) |
609 | 9159f679 | Gerd Hoffmann | { |
610 | 9159f679 | Gerd Hoffmann | USBBus *bus = usb_bus_from_device(dev); |
611 | 9159f679 | Gerd Hoffmann | UHCIState *s = container_of(bus, UHCIState, bus); |
612 | 9159f679 | Gerd Hoffmann | UHCIPort *port = s->ports + dev->port->index; |
613 | 9159f679 | Gerd Hoffmann | |
614 | 9159f679 | Gerd Hoffmann | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
|
615 | 9159f679 | Gerd Hoffmann | port->ctrl |= UHCI_PORT_RD; |
616 | 9159f679 | Gerd Hoffmann | uhci_resume(s); |
617 | 9159f679 | Gerd Hoffmann | } |
618 | 9159f679 | Gerd Hoffmann | } |
619 | 9159f679 | Gerd Hoffmann | |
620 | 4d611c9a | pbrook | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
621 | bb36d470 | bellard | { |
622 | bb36d470 | bellard | int i, ret;
|
623 | bb36d470 | bellard | |
624 | d0f2c4c6 | malc | DPRINTF("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
|
625 | 54f254f9 | aliguori | pid2str(p->pid), p->devaddr, p->devep, p->len); |
626 | 5d808245 | aurel32 | if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
|
627 | 54f254f9 | aliguori | dump_data(p->data, p->len); |
628 | 54f254f9 | aliguori | |
629 | 54f254f9 | aliguori | ret = USB_RET_NODEV; |
630 | 54f254f9 | aliguori | for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { |
631 | 54f254f9 | aliguori | UHCIPort *port = &s->ports[i]; |
632 | 54f254f9 | aliguori | USBDevice *dev = port->port.dev; |
633 | 54f254f9 | aliguori | |
634 | 54f254f9 | aliguori | if (dev && (port->ctrl & UHCI_PORT_EN))
|
635 | 806b6024 | Gerd Hoffmann | ret = dev->info->handle_packet(dev, p); |
636 | bb36d470 | bellard | } |
637 | 54f254f9 | aliguori | |
638 | d0f2c4c6 | malc | DPRINTF("uhci: packet exit. ret %d len %d\n", ret, p->len);
|
639 | 54f254f9 | aliguori | if (p->pid == USB_TOKEN_IN && ret > 0) |
640 | 54f254f9 | aliguori | dump_data(p->data, ret); |
641 | 54f254f9 | aliguori | |
642 | 54f254f9 | aliguori | return ret;
|
643 | bb36d470 | bellard | } |
644 | bb36d470 | bellard | |
645 | 13a9a0d3 | Gerd Hoffmann | static void uhci_async_complete(USBDevice *dev, USBPacket *packet); |
646 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s); |
647 | 4d611c9a | pbrook | |
648 | bb36d470 | bellard | /* return -1 if fatal error (frame must be stopped)
|
649 | bb36d470 | bellard | 0 if TD successful
|
650 | bb36d470 | bellard | 1 if TD unsuccessful or inactive
|
651 | bb36d470 | bellard | */
|
652 | 54f254f9 | aliguori | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
653 | bb36d470 | bellard | { |
654 | 54f254f9 | aliguori | int len = 0, max_len, err, ret; |
655 | bb36d470 | bellard | uint8_t pid; |
656 | bb36d470 | bellard | |
657 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
658 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
659 | 54f254f9 | aliguori | |
660 | 54f254f9 | aliguori | ret = async->packet.len; |
661 | 54f254f9 | aliguori | |
662 | 54f254f9 | aliguori | if (td->ctrl & TD_CTRL_IOS)
|
663 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
664 | bb36d470 | bellard | |
665 | 54f254f9 | aliguori | if (ret < 0) |
666 | 54f254f9 | aliguori | goto out;
|
667 | b9dc033c | balrog | |
668 | 54f254f9 | aliguori | len = async->packet.len; |
669 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
670 | 54f254f9 | aliguori | |
671 | 54f254f9 | aliguori | /* The NAK bit may have been set by a previous frame, so clear it
|
672 | 54f254f9 | aliguori | here. The docs are somewhat unclear, but win2k relies on this
|
673 | 54f254f9 | aliguori | behavior. */
|
674 | 54f254f9 | aliguori | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
675 | 5bd2c0d7 | Paul Brook | if (td->ctrl & TD_CTRL_IOC)
|
676 | 5bd2c0d7 | Paul Brook | *int_mask |= 0x01;
|
677 | 54f254f9 | aliguori | |
678 | 54f254f9 | aliguori | if (pid == USB_TOKEN_IN) {
|
679 | 54f254f9 | aliguori | if (len > max_len) {
|
680 | 54f254f9 | aliguori | ret = USB_RET_BABBLE; |
681 | 54f254f9 | aliguori | goto out;
|
682 | 4d611c9a | pbrook | } |
683 | b9dc033c | balrog | |
684 | 54f254f9 | aliguori | if (len > 0) { |
685 | 54f254f9 | aliguori | /* write the data back */
|
686 | 54f254f9 | aliguori | cpu_physical_memory_write(td->buffer, async->buffer, len); |
687 | 54f254f9 | aliguori | } |
688 | 54f254f9 | aliguori | |
689 | 54f254f9 | aliguori | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
690 | bb36d470 | bellard | *int_mask |= 0x02;
|
691 | bb36d470 | bellard | /* short packet: do not update QH */
|
692 | d0f2c4c6 | malc | DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
693 | bb36d470 | bellard | return 1; |
694 | bb36d470 | bellard | } |
695 | 54f254f9 | aliguori | } |
696 | 54f254f9 | aliguori | |
697 | 54f254f9 | aliguori | /* success */
|
698 | 54f254f9 | aliguori | return 0; |
699 | 54f254f9 | aliguori | |
700 | 54f254f9 | aliguori | out:
|
701 | 54f254f9 | aliguori | switch(ret) {
|
702 | 54f254f9 | aliguori | case USB_RET_STALL:
|
703 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_STALL; |
704 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
705 | 54f254f9 | aliguori | return 1; |
706 | 54f254f9 | aliguori | |
707 | 54f254f9 | aliguori | case USB_RET_BABBLE:
|
708 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
709 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
710 | 54f254f9 | aliguori | /* frame interrupted */
|
711 | 54f254f9 | aliguori | return -1; |
712 | 54f254f9 | aliguori | |
713 | 54f254f9 | aliguori | case USB_RET_NAK:
|
714 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_NAK; |
715 | 54f254f9 | aliguori | if (pid == USB_TOKEN_SETUP)
|
716 | 54f254f9 | aliguori | break;
|
717 | 54f254f9 | aliguori | return 1; |
718 | 54f254f9 | aliguori | |
719 | 54f254f9 | aliguori | case USB_RET_NODEV:
|
720 | 54f254f9 | aliguori | default:
|
721 | 54f254f9 | aliguori | break;
|
722 | 54f254f9 | aliguori | } |
723 | 54f254f9 | aliguori | |
724 | 54f254f9 | aliguori | /* Retry the TD if error count is not zero */
|
725 | 54f254f9 | aliguori | |
726 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_TIMEOUT; |
727 | 54f254f9 | aliguori | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
728 | 54f254f9 | aliguori | if (err != 0) { |
729 | 54f254f9 | aliguori | err--; |
730 | 54f254f9 | aliguori | if (err == 0) { |
731 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
732 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBERR; |
733 | 5bd2c0d7 | Paul Brook | if (td->ctrl & TD_CTRL_IOC)
|
734 | 5bd2c0d7 | Paul Brook | *int_mask |= 0x01;
|
735 | 54f254f9 | aliguori | uhci_update_irq(s); |
736 | bb36d470 | bellard | } |
737 | bb36d470 | bellard | } |
738 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
739 | 54f254f9 | aliguori | (err << TD_CTRL_ERROR_SHIFT); |
740 | 54f254f9 | aliguori | return 1; |
741 | bb36d470 | bellard | } |
742 | bb36d470 | bellard | |
743 | 54f254f9 | aliguori | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
744 | 54f254f9 | aliguori | { |
745 | 54f254f9 | aliguori | UHCIAsync *async; |
746 | 5d808245 | aurel32 | int len = 0, max_len; |
747 | 8e65b7c0 | David S. Ahern | uint8_t pid, isoc; |
748 | 8e65b7c0 | David S. Ahern | uint32_t token; |
749 | 54f254f9 | aliguori | |
750 | 54f254f9 | aliguori | /* Is active ? */
|
751 | 54f254f9 | aliguori | if (!(td->ctrl & TD_CTRL_ACTIVE))
|
752 | 54f254f9 | aliguori | return 1; |
753 | 54f254f9 | aliguori | |
754 | 8e65b7c0 | David S. Ahern | /* token field is not unique for isochronous requests,
|
755 | 8e65b7c0 | David S. Ahern | * so use the destination buffer
|
756 | 8e65b7c0 | David S. Ahern | */
|
757 | 8e65b7c0 | David S. Ahern | if (td->ctrl & TD_CTRL_IOS) {
|
758 | 8e65b7c0 | David S. Ahern | token = td->buffer; |
759 | 8e65b7c0 | David S. Ahern | isoc = 1;
|
760 | 8e65b7c0 | David S. Ahern | } else {
|
761 | 8e65b7c0 | David S. Ahern | token = td->token; |
762 | 8e65b7c0 | David S. Ahern | isoc = 0;
|
763 | 8e65b7c0 | David S. Ahern | } |
764 | 8e65b7c0 | David S. Ahern | |
765 | 8e65b7c0 | David S. Ahern | async = uhci_async_find_td(s, addr, token); |
766 | 54f254f9 | aliguori | if (async) {
|
767 | 54f254f9 | aliguori | /* Already submitted */
|
768 | a145ea51 | aliguori | async->valid = 32;
|
769 | 54f254f9 | aliguori | |
770 | 54f254f9 | aliguori | if (!async->done)
|
771 | 54f254f9 | aliguori | return 1; |
772 | 54f254f9 | aliguori | |
773 | 54f254f9 | aliguori | uhci_async_unlink(s, async); |
774 | 54f254f9 | aliguori | goto done;
|
775 | 54f254f9 | aliguori | } |
776 | 54f254f9 | aliguori | |
777 | 54f254f9 | aliguori | /* Allocate new packet */
|
778 | 54f254f9 | aliguori | async = uhci_async_alloc(s); |
779 | 54f254f9 | aliguori | if (!async)
|
780 | 54f254f9 | aliguori | return 1; |
781 | 54f254f9 | aliguori | |
782 | 8e65b7c0 | David S. Ahern | /* valid needs to be large enough to handle 10 frame delay
|
783 | 8e65b7c0 | David S. Ahern | * for initial isochronous requests
|
784 | 8e65b7c0 | David S. Ahern | */
|
785 | 8e65b7c0 | David S. Ahern | async->valid = 32;
|
786 | 54f254f9 | aliguori | async->td = addr; |
787 | 8e65b7c0 | David S. Ahern | async->token = token; |
788 | 8e65b7c0 | David S. Ahern | async->isoc = isoc; |
789 | 54f254f9 | aliguori | |
790 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
791 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
792 | 54f254f9 | aliguori | |
793 | 54f254f9 | aliguori | async->packet.pid = pid; |
794 | 54f254f9 | aliguori | async->packet.devaddr = (td->token >> 8) & 0x7f; |
795 | 54f254f9 | aliguori | async->packet.devep = (td->token >> 15) & 0xf; |
796 | 54f254f9 | aliguori | async->packet.data = async->buffer; |
797 | 54f254f9 | aliguori | async->packet.len = max_len; |
798 | 54f254f9 | aliguori | |
799 | 54f254f9 | aliguori | switch(pid) {
|
800 | 54f254f9 | aliguori | case USB_TOKEN_OUT:
|
801 | 54f254f9 | aliguori | case USB_TOKEN_SETUP:
|
802 | 54f254f9 | aliguori | cpu_physical_memory_read(td->buffer, async->buffer, max_len); |
803 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
804 | 5d808245 | aurel32 | if (len >= 0) |
805 | 5d808245 | aurel32 | len = max_len; |
806 | 54f254f9 | aliguori | break;
|
807 | 54f254f9 | aliguori | |
808 | 54f254f9 | aliguori | case USB_TOKEN_IN:
|
809 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
810 | 54f254f9 | aliguori | break;
|
811 | 54f254f9 | aliguori | |
812 | 54f254f9 | aliguori | default:
|
813 | 54f254f9 | aliguori | /* invalid pid : frame interrupted */
|
814 | 54f254f9 | aliguori | uhci_async_free(s, async); |
815 | 54f254f9 | aliguori | s->status |= UHCI_STS_HCPERR; |
816 | 54f254f9 | aliguori | uhci_update_irq(s); |
817 | 54f254f9 | aliguori | return -1; |
818 | 54f254f9 | aliguori | } |
819 | 54f254f9 | aliguori | |
820 | 5d808245 | aurel32 | if (len == USB_RET_ASYNC) {
|
821 | 54f254f9 | aliguori | uhci_async_link(s, async); |
822 | 54f254f9 | aliguori | return 2; |
823 | 54f254f9 | aliguori | } |
824 | 54f254f9 | aliguori | |
825 | 5d808245 | aurel32 | async->packet.len = len; |
826 | 54f254f9 | aliguori | |
827 | 54f254f9 | aliguori | done:
|
828 | 5d808245 | aurel32 | len = uhci_complete_td(s, td, async, int_mask); |
829 | 54f254f9 | aliguori | uhci_async_free(s, async); |
830 | 5d808245 | aurel32 | return len;
|
831 | 54f254f9 | aliguori | } |
832 | 54f254f9 | aliguori | |
833 | 13a9a0d3 | Gerd Hoffmann | static void uhci_async_complete(USBDevice *dev, USBPacket *packet) |
834 | 4d611c9a | pbrook | { |
835 | 7b5a44c5 | Gerd Hoffmann | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
836 | 7b5a44c5 | Gerd Hoffmann | UHCIState *s = async->uhci; |
837 | 54f254f9 | aliguori | |
838 | d0f2c4c6 | malc | DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
839 | 54f254f9 | aliguori | |
840 | 8e65b7c0 | David S. Ahern | if (async->isoc) {
|
841 | 8e65b7c0 | David S. Ahern | UHCI_TD td; |
842 | 8e65b7c0 | David S. Ahern | uint32_t link = async->td; |
843 | 8e65b7c0 | David S. Ahern | uint32_t int_mask = 0, val;
|
844 | d4c4e6fd | Blue Swirl | |
845 | 8e65b7c0 | David S. Ahern | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
846 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.link); |
847 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.ctrl); |
848 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.token); |
849 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.buffer); |
850 | 8e65b7c0 | David S. Ahern | |
851 | 8e65b7c0 | David S. Ahern | uhci_async_unlink(s, async); |
852 | d4c4e6fd | Blue Swirl | uhci_complete_td(s, &td, async, &int_mask); |
853 | 8e65b7c0 | David S. Ahern | s->pending_int_mask |= int_mask; |
854 | 54f254f9 | aliguori | |
855 | 8e65b7c0 | David S. Ahern | /* update the status bits of the TD */
|
856 | 8e65b7c0 | David S. Ahern | val = cpu_to_le32(td.ctrl); |
857 | 8e65b7c0 | David S. Ahern | cpu_physical_memory_write((link & ~0xf) + 4, |
858 | 8e65b7c0 | David S. Ahern | (const uint8_t *)&val, sizeof(val)); |
859 | 8e65b7c0 | David S. Ahern | uhci_async_free(s, async); |
860 | 8e65b7c0 | David S. Ahern | } else {
|
861 | 8e65b7c0 | David S. Ahern | async->done = 1;
|
862 | 8e65b7c0 | David S. Ahern | uhci_process_frame(s); |
863 | 8e65b7c0 | David S. Ahern | } |
864 | 54f254f9 | aliguori | } |
865 | 54f254f9 | aliguori | |
866 | 54f254f9 | aliguori | static int is_valid(uint32_t link) |
867 | 54f254f9 | aliguori | { |
868 | 54f254f9 | aliguori | return (link & 1) == 0; |
869 | 54f254f9 | aliguori | } |
870 | 54f254f9 | aliguori | |
871 | 54f254f9 | aliguori | static int is_qh(uint32_t link) |
872 | 54f254f9 | aliguori | { |
873 | 54f254f9 | aliguori | return (link & 2) != 0; |
874 | 54f254f9 | aliguori | } |
875 | 54f254f9 | aliguori | |
876 | 54f254f9 | aliguori | static int depth_first(uint32_t link) |
877 | 54f254f9 | aliguori | { |
878 | 54f254f9 | aliguori | return (link & 4) != 0; |
879 | 54f254f9 | aliguori | } |
880 | 54f254f9 | aliguori | |
881 | 54f254f9 | aliguori | /* QH DB used for detecting QH loops */
|
882 | 54f254f9 | aliguori | #define UHCI_MAX_QUEUES 128 |
883 | 54f254f9 | aliguori | typedef struct { |
884 | 54f254f9 | aliguori | uint32_t addr[UHCI_MAX_QUEUES]; |
885 | 54f254f9 | aliguori | int count;
|
886 | 54f254f9 | aliguori | } QhDb; |
887 | 54f254f9 | aliguori | |
888 | 54f254f9 | aliguori | static void qhdb_reset(QhDb *db) |
889 | 54f254f9 | aliguori | { |
890 | 54f254f9 | aliguori | db->count = 0;
|
891 | 54f254f9 | aliguori | } |
892 | 54f254f9 | aliguori | |
893 | 54f254f9 | aliguori | /* Add QH to DB. Returns 1 if already present or DB is full. */
|
894 | 54f254f9 | aliguori | static int qhdb_insert(QhDb *db, uint32_t addr) |
895 | 54f254f9 | aliguori | { |
896 | 54f254f9 | aliguori | int i;
|
897 | 54f254f9 | aliguori | for (i = 0; i < db->count; i++) |
898 | 54f254f9 | aliguori | if (db->addr[i] == addr)
|
899 | 54f254f9 | aliguori | return 1; |
900 | 54f254f9 | aliguori | |
901 | 54f254f9 | aliguori | if (db->count >= UHCI_MAX_QUEUES)
|
902 | 54f254f9 | aliguori | return 1; |
903 | 54f254f9 | aliguori | |
904 | 54f254f9 | aliguori | db->addr[db->count++] = addr; |
905 | 54f254f9 | aliguori | return 0; |
906 | 54f254f9 | aliguori | } |
907 | 54f254f9 | aliguori | |
908 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s) |
909 | 54f254f9 | aliguori | { |
910 | 54f254f9 | aliguori | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
911 | 54f254f9 | aliguori | uint32_t curr_qh; |
912 | 54f254f9 | aliguori | int cnt, ret;
|
913 | 4d611c9a | pbrook | UHCI_TD td; |
914 | 54f254f9 | aliguori | UHCI_QH qh; |
915 | 54f254f9 | aliguori | QhDb qhdb; |
916 | 4d611c9a | pbrook | |
917 | 54f254f9 | aliguori | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
918 | 54f254f9 | aliguori | |
919 | d0f2c4c6 | malc | DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
920 | 54f254f9 | aliguori | |
921 | 54f254f9 | aliguori | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
922 | 54f254f9 | aliguori | le32_to_cpus(&link); |
923 | b9dc033c | balrog | |
924 | 54f254f9 | aliguori | int_mask = 0;
|
925 | 54f254f9 | aliguori | curr_qh = 0;
|
926 | 54f254f9 | aliguori | |
927 | 54f254f9 | aliguori | qhdb_reset(&qhdb); |
928 | 54f254f9 | aliguori | |
929 | 54f254f9 | aliguori | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
930 | 54f254f9 | aliguori | if (is_qh(link)) {
|
931 | 54f254f9 | aliguori | /* QH */
|
932 | 54f254f9 | aliguori | |
933 | 54f254f9 | aliguori | if (qhdb_insert(&qhdb, link)) {
|
934 | 54f254f9 | aliguori | /*
|
935 | 54f254f9 | aliguori | * We're going in circles. Which is not a bug because
|
936 | 54f254f9 | aliguori | * HCD is allowed to do that as part of the BW management.
|
937 | 54f254f9 | aliguori | * In our case though it makes no sense to spin here. Sync transations
|
938 | 54f254f9 | aliguori | * are already done, and async completion handler will re-process
|
939 | 54f254f9 | aliguori | * the frame when something is ready.
|
940 | 54f254f9 | aliguori | */
|
941 | d0f2c4c6 | malc | DPRINTF("uhci: detected loop. qh 0x%x\n", link);
|
942 | 54f254f9 | aliguori | break;
|
943 | 54f254f9 | aliguori | } |
944 | 54f254f9 | aliguori | |
945 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); |
946 | 54f254f9 | aliguori | le32_to_cpus(&qh.link); |
947 | 54f254f9 | aliguori | le32_to_cpus(&qh.el_link); |
948 | 54f254f9 | aliguori | |
949 | d0f2c4c6 | malc | DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
950 | 54f254f9 | aliguori | link, qh.link, qh.el_link); |
951 | 54f254f9 | aliguori | |
952 | 54f254f9 | aliguori | if (!is_valid(qh.el_link)) {
|
953 | 54f254f9 | aliguori | /* QH w/o elements */
|
954 | 54f254f9 | aliguori | curr_qh = 0;
|
955 | 54f254f9 | aliguori | link = qh.link; |
956 | 54f254f9 | aliguori | } else {
|
957 | 54f254f9 | aliguori | /* QH with elements */
|
958 | 54f254f9 | aliguori | curr_qh = link; |
959 | 54f254f9 | aliguori | link = qh.el_link; |
960 | 54f254f9 | aliguori | } |
961 | 54f254f9 | aliguori | continue;
|
962 | 54f254f9 | aliguori | } |
963 | 54f254f9 | aliguori | |
964 | 54f254f9 | aliguori | /* TD */
|
965 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
966 | b9dc033c | balrog | le32_to_cpus(&td.link); |
967 | b9dc033c | balrog | le32_to_cpus(&td.ctrl); |
968 | b9dc033c | balrog | le32_to_cpus(&td.token); |
969 | b9dc033c | balrog | le32_to_cpus(&td.buffer); |
970 | b9dc033c | balrog | |
971 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
972 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
973 | 54f254f9 | aliguori | |
974 | 54f254f9 | aliguori | old_td_ctrl = td.ctrl; |
975 | 54f254f9 | aliguori | ret = uhci_handle_td(s, link, &td, &int_mask); |
976 | b9dc033c | balrog | if (old_td_ctrl != td.ctrl) {
|
977 | 54f254f9 | aliguori | /* update the status bits of the TD */
|
978 | b9dc033c | balrog | val = cpu_to_le32(td.ctrl); |
979 | b9dc033c | balrog | cpu_physical_memory_write((link & ~0xf) + 4, |
980 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
981 | b9dc033c | balrog | } |
982 | 54f254f9 | aliguori | |
983 | 54f254f9 | aliguori | if (ret < 0) { |
984 | 54f254f9 | aliguori | /* interrupted frame */
|
985 | 54f254f9 | aliguori | break;
|
986 | b9dc033c | balrog | } |
987 | b9dc033c | balrog | |
988 | 54f254f9 | aliguori | if (ret == 2 || ret == 1) { |
989 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
990 | 54f254f9 | aliguori | link, ret == 2 ? "pend" : "skip", |
991 | 54f254f9 | aliguori | td.link, td.ctrl, td.token, curr_qh); |
992 | b9dc033c | balrog | |
993 | 54f254f9 | aliguori | link = curr_qh ? qh.link : td.link; |
994 | 54f254f9 | aliguori | continue;
|
995 | 4d611c9a | pbrook | } |
996 | 54f254f9 | aliguori | |
997 | 54f254f9 | aliguori | /* completed TD */
|
998 | 54f254f9 | aliguori | |
999 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1000 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
1001 | 54f254f9 | aliguori | |
1002 | 54f254f9 | aliguori | link = td.link; |
1003 | 54f254f9 | aliguori | |
1004 | 54f254f9 | aliguori | if (curr_qh) {
|
1005 | 54f254f9 | aliguori | /* update QH element link */
|
1006 | 54f254f9 | aliguori | qh.el_link = link; |
1007 | 4d611c9a | pbrook | val = cpu_to_le32(qh.el_link); |
1008 | 54f254f9 | aliguori | cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1009 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
1010 | 54f254f9 | aliguori | |
1011 | 54f254f9 | aliguori | if (!depth_first(link)) {
|
1012 | 54f254f9 | aliguori | /* done with this QH */
|
1013 | 54f254f9 | aliguori | |
1014 | d0f2c4c6 | malc | DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
1015 | 54f254f9 | aliguori | curr_qh, qh.link, qh.el_link); |
1016 | 54f254f9 | aliguori | |
1017 | 54f254f9 | aliguori | curr_qh = 0;
|
1018 | 54f254f9 | aliguori | link = qh.link; |
1019 | 54f254f9 | aliguori | } |
1020 | 4d611c9a | pbrook | } |
1021 | 54f254f9 | aliguori | |
1022 | 54f254f9 | aliguori | /* go to the next entry */
|
1023 | 4d611c9a | pbrook | } |
1024 | 54f254f9 | aliguori | |
1025 | 8e65b7c0 | David S. Ahern | s->pending_int_mask |= int_mask; |
1026 | 4d611c9a | pbrook | } |
1027 | 4d611c9a | pbrook | |
1028 | bb36d470 | bellard | static void uhci_frame_timer(void *opaque) |
1029 | bb36d470 | bellard | { |
1030 | bb36d470 | bellard | UHCIState *s = opaque; |
1031 | 8e65b7c0 | David S. Ahern | |
1032 | 8e65b7c0 | David S. Ahern | /* prepare the timer for the next frame */
|
1033 | 8e65b7c0 | David S. Ahern | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1034 | bb36d470 | bellard | |
1035 | bb36d470 | bellard | if (!(s->cmd & UHCI_CMD_RS)) {
|
1036 | 54f254f9 | aliguori | /* Full stop */
|
1037 | bb36d470 | bellard | qemu_del_timer(s->frame_timer); |
1038 | 52328140 | bellard | /* set hchalted bit in status - UHCI11D 2.1.2 */
|
1039 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
1040 | 6f382b5e | aliguori | |
1041 | d0f2c4c6 | malc | DPRINTF("uhci: halted\n");
|
1042 | bb36d470 | bellard | return;
|
1043 | bb36d470 | bellard | } |
1044 | 54f254f9 | aliguori | |
1045 | 54f254f9 | aliguori | /* Complete the previous frame */
|
1046 | 4d611c9a | pbrook | if (s->pending_int_mask) {
|
1047 | 4d611c9a | pbrook | s->status2 |= s->pending_int_mask; |
1048 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBINT; |
1049 | 4d611c9a | pbrook | uhci_update_irq(s); |
1050 | 4d611c9a | pbrook | } |
1051 | 8e65b7c0 | David S. Ahern | s->pending_int_mask = 0;
|
1052 | b9dc033c | balrog | |
1053 | 54f254f9 | aliguori | /* Start new frame */
|
1054 | 54f254f9 | aliguori | s->frnum = (s->frnum + 1) & 0x7ff; |
1055 | 54f254f9 | aliguori | |
1056 | d0f2c4c6 | malc | DPRINTF("uhci: new frame #%u\n" , s->frnum);
|
1057 | 54f254f9 | aliguori | |
1058 | 54f254f9 | aliguori | uhci_async_validate_begin(s); |
1059 | 54f254f9 | aliguori | |
1060 | 54f254f9 | aliguori | uhci_process_frame(s); |
1061 | 54f254f9 | aliguori | |
1062 | 54f254f9 | aliguori | uhci_async_validate_end(s); |
1063 | b9dc033c | balrog | |
1064 | 8e65b7c0 | David S. Ahern | qemu_mod_timer(s->frame_timer, s->expire_time); |
1065 | bb36d470 | bellard | } |
1066 | bb36d470 | bellard | |
1067 | 5fafdf24 | ths | static void uhci_map(PCIDevice *pci_dev, int region_num, |
1068 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
1069 | bb36d470 | bellard | { |
1070 | bb36d470 | bellard | UHCIState *s = (UHCIState *)pci_dev; |
1071 | bb36d470 | bellard | |
1072 | bb36d470 | bellard | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
1073 | bb36d470 | bellard | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
1074 | bb36d470 | bellard | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
1075 | bb36d470 | bellard | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
1076 | bb36d470 | bellard | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
1077 | bb36d470 | bellard | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
1078 | bb36d470 | bellard | } |
1079 | bb36d470 | bellard | |
1080 | 0d86d2be | Gerd Hoffmann | static USBPortOps uhci_port_ops = {
|
1081 | 0d86d2be | Gerd Hoffmann | .attach = uhci_attach, |
1082 | 618c169b | Gerd Hoffmann | .detach = uhci_detach, |
1083 | 9159f679 | Gerd Hoffmann | .wakeup = uhci_wakeup, |
1084 | 13a9a0d3 | Gerd Hoffmann | .complete = uhci_async_complete, |
1085 | 0d86d2be | Gerd Hoffmann | }; |
1086 | 0d86d2be | Gerd Hoffmann | |
1087 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_common_initfn(UHCIState *s) |
1088 | bb36d470 | bellard | { |
1089 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1090 | bb36d470 | bellard | int i;
|
1091 | bb36d470 | bellard | |
1092 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_REVISION_ID] = 0x01; // revision number |
1093 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_CLASS_PROG] = 0x00;
|
1094 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); |
1095 | db579e9e | Michael S. Tsirkin | /* TODO: reset value should be 0. */
|
1096 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3 |
1097 | 38ca0f6d | pbrook | pci_conf[0x60] = 0x10; // release number |
1098 | 3b46e624 | ths | |
1099 | b2317837 | Gerd Hoffmann | usb_bus_new(&s->bus, &s->dev.qdev); |
1100 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
1101 | ace1318b | Gerd Hoffmann | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, |
1102 | 843d4e0c | Gerd Hoffmann | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1103 | c7a2196a | Gerd Hoffmann | usb_port_location(&s->ports[i].port, NULL, i+1); |
1104 | bb36d470 | bellard | } |
1105 | 74475455 | Paolo Bonzini | s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
1106 | 74475455 | Paolo Bonzini | s->expire_time = qemu_get_clock_ns(vm_clock) + |
1107 | 8e65b7c0 | David S. Ahern | (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1108 | 64e58fe5 | Juan Quintela | s->num_ports_vmstate = NB_PORTS; |
1109 | ddf6583f | Gerd Hoffmann | QTAILQ_INIT(&s->async_pending); |
1110 | bb36d470 | bellard | |
1111 | a08d4367 | Jan Kiszka | qemu_register_reset(uhci_reset, s); |
1112 | bb36d470 | bellard | |
1113 | 38ca0f6d | pbrook | /* Use region 4 for consistency with real hardware. BSD guests seem
|
1114 | 38ca0f6d | pbrook | to rely on this. */
|
1115 | 28c2c264 | Avi Kivity | pci_register_bar(&s->dev, 4, 0x20, |
1116 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, uhci_map); |
1117 | 6f382b5e | aliguori | |
1118 | 6cf9b6f1 | Gerd Hoffmann | return 0; |
1119 | bb36d470 | bellard | } |
1120 | afcc3cdf | ths | |
1121 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_piix3_initfn(PCIDevice *dev) |
1122 | afcc3cdf | ths | { |
1123 | 6cf9b6f1 | Gerd Hoffmann | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1124 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1125 | 6cf9b6f1 | Gerd Hoffmann | |
1126 | 6cf9b6f1 | Gerd Hoffmann | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1127 | 6cf9b6f1 | Gerd Hoffmann | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); |
1128 | 6cf9b6f1 | Gerd Hoffmann | return usb_uhci_common_initfn(s);
|
1129 | 6cf9b6f1 | Gerd Hoffmann | } |
1130 | 6cf9b6f1 | Gerd Hoffmann | |
1131 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_piix4_initfn(PCIDevice *dev) |
1132 | 6cf9b6f1 | Gerd Hoffmann | { |
1133 | 6cf9b6f1 | Gerd Hoffmann | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1134 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1135 | afcc3cdf | ths | |
1136 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1137 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); |
1138 | 6cf9b6f1 | Gerd Hoffmann | return usb_uhci_common_initfn(s);
|
1139 | 6cf9b6f1 | Gerd Hoffmann | } |
1140 | afcc3cdf | ths | |
1141 | 30235a54 | Huacai Chen | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1142 | 30235a54 | Huacai Chen | { |
1143 | 30235a54 | Huacai Chen | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1144 | 30235a54 | Huacai Chen | uint8_t *pci_conf = s->dev.config; |
1145 | 30235a54 | Huacai Chen | |
1146 | 30235a54 | Huacai Chen | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
1147 | 30235a54 | Huacai Chen | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI); |
1148 | 30235a54 | Huacai Chen | |
1149 | 30235a54 | Huacai Chen | /* USB misc control 1/2 */
|
1150 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0x40,0x00001000); |
1151 | 30235a54 | Huacai Chen | /* PM capability */
|
1152 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0x80,0x00020001); |
1153 | 30235a54 | Huacai Chen | /* USB legacy support */
|
1154 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0xc0,0x00002000); |
1155 | 30235a54 | Huacai Chen | |
1156 | 30235a54 | Huacai Chen | return usb_uhci_common_initfn(s);
|
1157 | 30235a54 | Huacai Chen | } |
1158 | 30235a54 | Huacai Chen | |
1159 | 6cf9b6f1 | Gerd Hoffmann | static PCIDeviceInfo uhci_info[] = {
|
1160 | 6cf9b6f1 | Gerd Hoffmann | { |
1161 | 556cd098 | Markus Armbruster | .qdev.name = "piix3-usb-uhci",
|
1162 | 6cf9b6f1 | Gerd Hoffmann | .qdev.size = sizeof(UHCIState),
|
1163 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_uhci, |
1164 | 6cf9b6f1 | Gerd Hoffmann | .init = usb_uhci_piix3_initfn, |
1165 | 6cf9b6f1 | Gerd Hoffmann | },{ |
1166 | 556cd098 | Markus Armbruster | .qdev.name = "piix4-usb-uhci",
|
1167 | 6cf9b6f1 | Gerd Hoffmann | .qdev.size = sizeof(UHCIState),
|
1168 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_uhci, |
1169 | 6cf9b6f1 | Gerd Hoffmann | .init = usb_uhci_piix4_initfn, |
1170 | 6cf9b6f1 | Gerd Hoffmann | },{ |
1171 | 30235a54 | Huacai Chen | .qdev.name = "vt82c686b-usb-uhci",
|
1172 | 30235a54 | Huacai Chen | .qdev.size = sizeof(UHCIState),
|
1173 | 30235a54 | Huacai Chen | .qdev.vmsd = &vmstate_uhci, |
1174 | 30235a54 | Huacai Chen | .init = usb_uhci_vt82c686b_initfn, |
1175 | 30235a54 | Huacai Chen | },{ |
1176 | 6cf9b6f1 | Gerd Hoffmann | /* end of list */
|
1177 | afcc3cdf | ths | } |
1178 | 6cf9b6f1 | Gerd Hoffmann | }; |
1179 | afcc3cdf | ths | |
1180 | 6cf9b6f1 | Gerd Hoffmann | static void uhci_register(void) |
1181 | 6cf9b6f1 | Gerd Hoffmann | { |
1182 | 6cf9b6f1 | Gerd Hoffmann | pci_qdev_register_many(uhci_info); |
1183 | 6cf9b6f1 | Gerd Hoffmann | } |
1184 | 6cf9b6f1 | Gerd Hoffmann | device_init(uhci_register); |
1185 | afcc3cdf | ths | |
1186 | 6cf9b6f1 | Gerd Hoffmann | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1187 | 6cf9b6f1 | Gerd Hoffmann | { |
1188 | 556cd098 | Markus Armbruster | pci_create_simple(bus, devfn, "piix3-usb-uhci");
|
1189 | 6cf9b6f1 | Gerd Hoffmann | } |
1190 | 54f254f9 | aliguori | |
1191 | 6cf9b6f1 | Gerd Hoffmann | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1192 | 6cf9b6f1 | Gerd Hoffmann | { |
1193 | 556cd098 | Markus Armbruster | pci_create_simple(bus, devfn, "piix4-usb-uhci");
|
1194 | afcc3cdf | ths | } |
1195 | 30235a54 | Huacai Chen | |
1196 | 30235a54 | Huacai Chen | void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) |
1197 | 30235a54 | Huacai Chen | { |
1198 | 30235a54 | Huacai Chen | pci_create_simple(bus, devfn, "vt82c686b-usb-uhci");
|
1199 | 30235a54 | Huacai Chen | } |