Statistics
| Branch: | Revision:

root / target-mips / op.c @ 3953d786

History | View | Annotate | Download (40.5 kB)

1 6af0bf9c bellard
/*
2 6af0bf9c bellard
 *  MIPS emulation micro-operations for qemu.
3 6af0bf9c bellard
 * 
4 6af0bf9c bellard
 *  Copyright (c) 2004-2005 Jocelyn Mayer
5 6ea83fed bellard
 *  Copyright (c) 2006 Marius Groeger (FPU operations)
6 6af0bf9c bellard
 *
7 6af0bf9c bellard
 * This library is free software; you can redistribute it and/or
8 6af0bf9c bellard
 * modify it under the terms of the GNU Lesser General Public
9 6af0bf9c bellard
 * License as published by the Free Software Foundation; either
10 6af0bf9c bellard
 * version 2 of the License, or (at your option) any later version.
11 6af0bf9c bellard
 *
12 6af0bf9c bellard
 * This library is distributed in the hope that it will be useful,
13 6af0bf9c bellard
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 6af0bf9c bellard
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 6af0bf9c bellard
 * Lesser General Public License for more details.
16 6af0bf9c bellard
 *
17 6af0bf9c bellard
 * You should have received a copy of the GNU Lesser General Public
18 6af0bf9c bellard
 * License along with this library; if not, write to the Free Software
19 6af0bf9c bellard
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20 6af0bf9c bellard
 */
21 6af0bf9c bellard
22 6af0bf9c bellard
#include "config.h"
23 6af0bf9c bellard
#include "exec.h"
24 6af0bf9c bellard
25 1b351e52 bellard
#ifndef CALL_FROM_TB0
26 1b351e52 bellard
#define CALL_FROM_TB0(func) func();
27 1b351e52 bellard
#endif
28 1b351e52 bellard
#ifndef CALL_FROM_TB1
29 1b351e52 bellard
#define CALL_FROM_TB1(func, arg0) func(arg0);
30 1b351e52 bellard
#endif
31 1b351e52 bellard
#ifndef CALL_FROM_TB1_CONST16
32 1b351e52 bellard
#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
33 1b351e52 bellard
#endif
34 1b351e52 bellard
#ifndef CALL_FROM_TB2
35 1b351e52 bellard
#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
36 1b351e52 bellard
#endif
37 1b351e52 bellard
#ifndef CALL_FROM_TB2_CONST16
38 1b351e52 bellard
#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
39 1b351e52 bellard
CALL_FROM_TB2(func, arg0, arg1);
40 1b351e52 bellard
#endif
41 1b351e52 bellard
#ifndef CALL_FROM_TB3
42 1b351e52 bellard
#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
43 1b351e52 bellard
#endif
44 1b351e52 bellard
#ifndef CALL_FROM_TB4
45 1b351e52 bellard
#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
46 1b351e52 bellard
        func(arg0, arg1, arg2, arg3);
47 1b351e52 bellard
#endif
48 1b351e52 bellard
49 6af0bf9c bellard
#define REG 1
50 6af0bf9c bellard
#include "op_template.c"
51 6af0bf9c bellard
#undef REG
52 6af0bf9c bellard
#define REG 2
53 6af0bf9c bellard
#include "op_template.c"
54 6af0bf9c bellard
#undef REG
55 6af0bf9c bellard
#define REG 3
56 6af0bf9c bellard
#include "op_template.c"
57 6af0bf9c bellard
#undef REG
58 6af0bf9c bellard
#define REG 4
59 6af0bf9c bellard
#include "op_template.c"
60 6af0bf9c bellard
#undef REG
61 6af0bf9c bellard
#define REG 5
62 6af0bf9c bellard
#include "op_template.c"
63 6af0bf9c bellard
#undef REG
64 6af0bf9c bellard
#define REG 6
65 6af0bf9c bellard
#include "op_template.c"
66 6af0bf9c bellard
#undef REG
67 6af0bf9c bellard
#define REG 7
68 6af0bf9c bellard
#include "op_template.c"
69 6af0bf9c bellard
#undef REG
70 6af0bf9c bellard
#define REG 8
71 6af0bf9c bellard
#include "op_template.c"
72 6af0bf9c bellard
#undef REG
73 6af0bf9c bellard
#define REG 9
74 6af0bf9c bellard
#include "op_template.c"
75 6af0bf9c bellard
#undef REG
76 6af0bf9c bellard
#define REG 10
77 6af0bf9c bellard
#include "op_template.c"
78 6af0bf9c bellard
#undef REG
79 6af0bf9c bellard
#define REG 11
80 6af0bf9c bellard
#include "op_template.c"
81 6af0bf9c bellard
#undef REG
82 6af0bf9c bellard
#define REG 12
83 6af0bf9c bellard
#include "op_template.c"
84 6af0bf9c bellard
#undef REG
85 6af0bf9c bellard
#define REG 13
86 6af0bf9c bellard
#include "op_template.c"
87 6af0bf9c bellard
#undef REG
88 6af0bf9c bellard
#define REG 14
89 6af0bf9c bellard
#include "op_template.c"
90 6af0bf9c bellard
#undef REG
91 6af0bf9c bellard
#define REG 15
92 6af0bf9c bellard
#include "op_template.c"
93 6af0bf9c bellard
#undef REG
94 6af0bf9c bellard
#define REG 16
95 6af0bf9c bellard
#include "op_template.c"
96 6af0bf9c bellard
#undef REG
97 6af0bf9c bellard
#define REG 17
98 6af0bf9c bellard
#include "op_template.c"
99 6af0bf9c bellard
#undef REG
100 6af0bf9c bellard
#define REG 18
101 6af0bf9c bellard
#include "op_template.c"
102 6af0bf9c bellard
#undef REG
103 6af0bf9c bellard
#define REG 19
104 6af0bf9c bellard
#include "op_template.c"
105 6af0bf9c bellard
#undef REG
106 6af0bf9c bellard
#define REG 20
107 6af0bf9c bellard
#include "op_template.c"
108 6af0bf9c bellard
#undef REG
109 6af0bf9c bellard
#define REG 21
110 6af0bf9c bellard
#include "op_template.c"
111 6af0bf9c bellard
#undef REG
112 6af0bf9c bellard
#define REG 22
113 6af0bf9c bellard
#include "op_template.c"
114 6af0bf9c bellard
#undef REG
115 6af0bf9c bellard
#define REG 23
116 6af0bf9c bellard
#include "op_template.c"
117 6af0bf9c bellard
#undef REG
118 6af0bf9c bellard
#define REG 24
119 6af0bf9c bellard
#include "op_template.c"
120 6af0bf9c bellard
#undef REG
121 6af0bf9c bellard
#define REG 25
122 6af0bf9c bellard
#include "op_template.c"
123 6af0bf9c bellard
#undef REG
124 6af0bf9c bellard
#define REG 26
125 6af0bf9c bellard
#include "op_template.c"
126 6af0bf9c bellard
#undef REG
127 6af0bf9c bellard
#define REG 27
128 6af0bf9c bellard
#include "op_template.c"
129 6af0bf9c bellard
#undef REG
130 6af0bf9c bellard
#define REG 28
131 6af0bf9c bellard
#include "op_template.c"
132 6af0bf9c bellard
#undef REG
133 6af0bf9c bellard
#define REG 29
134 6af0bf9c bellard
#include "op_template.c"
135 6af0bf9c bellard
#undef REG
136 6af0bf9c bellard
#define REG 30
137 6af0bf9c bellard
#include "op_template.c"
138 6af0bf9c bellard
#undef REG
139 6af0bf9c bellard
#define REG 31
140 6af0bf9c bellard
#include "op_template.c"
141 6af0bf9c bellard
#undef REG
142 6af0bf9c bellard
143 c570fd16 ths
#define TN
144 6af0bf9c bellard
#include "op_template.c"
145 6af0bf9c bellard
#undef TN
146 6af0bf9c bellard
147 6ea83fed bellard
#define SFREG 0
148 6ea83fed bellard
#define DFREG 0
149 6ea83fed bellard
#include "fop_template.c"
150 6ea83fed bellard
#undef SFREG
151 6ea83fed bellard
#undef DFREG
152 6ea83fed bellard
#define SFREG 1
153 6ea83fed bellard
#include "fop_template.c"
154 6ea83fed bellard
#undef SFREG
155 6ea83fed bellard
#define SFREG 2
156 6ea83fed bellard
#define DFREG 2
157 6ea83fed bellard
#include "fop_template.c"
158 6ea83fed bellard
#undef SFREG
159 6ea83fed bellard
#undef DFREG
160 6ea83fed bellard
#define SFREG 3
161 6ea83fed bellard
#include "fop_template.c"
162 6ea83fed bellard
#undef SFREG
163 6ea83fed bellard
#define SFREG 4
164 6ea83fed bellard
#define DFREG 4
165 6ea83fed bellard
#include "fop_template.c"
166 6ea83fed bellard
#undef SFREG
167 6ea83fed bellard
#undef DFREG
168 6ea83fed bellard
#define SFREG 5
169 6ea83fed bellard
#include "fop_template.c"
170 6ea83fed bellard
#undef SFREG
171 6ea83fed bellard
#define SFREG 6
172 6ea83fed bellard
#define DFREG 6
173 6ea83fed bellard
#include "fop_template.c"
174 6ea83fed bellard
#undef SFREG
175 6ea83fed bellard
#undef DFREG
176 6ea83fed bellard
#define SFREG 7
177 6ea83fed bellard
#include "fop_template.c"
178 6ea83fed bellard
#undef SFREG
179 6ea83fed bellard
#define SFREG 8
180 6ea83fed bellard
#define DFREG 8
181 6ea83fed bellard
#include "fop_template.c"
182 6ea83fed bellard
#undef SFREG
183 6ea83fed bellard
#undef DFREG
184 6ea83fed bellard
#define SFREG 9
185 6ea83fed bellard
#include "fop_template.c"
186 6ea83fed bellard
#undef SFREG
187 6ea83fed bellard
#define SFREG 10
188 6ea83fed bellard
#define DFREG 10
189 6ea83fed bellard
#include "fop_template.c"
190 6ea83fed bellard
#undef SFREG
191 6ea83fed bellard
#undef DFREG
192 6ea83fed bellard
#define SFREG 11
193 6ea83fed bellard
#include "fop_template.c"
194 6ea83fed bellard
#undef SFREG
195 6ea83fed bellard
#define SFREG 12
196 6ea83fed bellard
#define DFREG 12
197 6ea83fed bellard
#include "fop_template.c"
198 6ea83fed bellard
#undef SFREG
199 6ea83fed bellard
#undef DFREG
200 6ea83fed bellard
#define SFREG 13
201 6ea83fed bellard
#include "fop_template.c"
202 6ea83fed bellard
#undef SFREG
203 6ea83fed bellard
#define SFREG 14
204 6ea83fed bellard
#define DFREG 14
205 6ea83fed bellard
#include "fop_template.c"
206 6ea83fed bellard
#undef SFREG
207 6ea83fed bellard
#undef DFREG
208 6ea83fed bellard
#define SFREG 15
209 6ea83fed bellard
#include "fop_template.c"
210 6ea83fed bellard
#undef SFREG
211 6ea83fed bellard
#define SFREG 16
212 6ea83fed bellard
#define DFREG 16
213 6ea83fed bellard
#include "fop_template.c"
214 6ea83fed bellard
#undef SFREG
215 6ea83fed bellard
#undef DFREG
216 6ea83fed bellard
#define SFREG 17
217 6ea83fed bellard
#include "fop_template.c"
218 6ea83fed bellard
#undef SFREG
219 6ea83fed bellard
#define SFREG 18
220 6ea83fed bellard
#define DFREG 18
221 6ea83fed bellard
#include "fop_template.c"
222 6ea83fed bellard
#undef SFREG
223 6ea83fed bellard
#undef DFREG
224 6ea83fed bellard
#define SFREG 19
225 6ea83fed bellard
#include "fop_template.c"
226 6ea83fed bellard
#undef SFREG
227 6ea83fed bellard
#define SFREG 20
228 6ea83fed bellard
#define DFREG 20
229 6ea83fed bellard
#include "fop_template.c"
230 6ea83fed bellard
#undef SFREG
231 6ea83fed bellard
#undef DFREG
232 6ea83fed bellard
#define SFREG 21
233 6ea83fed bellard
#include "fop_template.c"
234 6ea83fed bellard
#undef SFREG
235 6ea83fed bellard
#define SFREG 22
236 6ea83fed bellard
#define DFREG 22
237 6ea83fed bellard
#include "fop_template.c"
238 6ea83fed bellard
#undef SFREG
239 6ea83fed bellard
#undef DFREG
240 6ea83fed bellard
#define SFREG 23
241 6ea83fed bellard
#include "fop_template.c"
242 6ea83fed bellard
#undef SFREG
243 6ea83fed bellard
#define SFREG 24
244 6ea83fed bellard
#define DFREG 24
245 6ea83fed bellard
#include "fop_template.c"
246 6ea83fed bellard
#undef SFREG
247 6ea83fed bellard
#undef DFREG
248 6ea83fed bellard
#define SFREG 25
249 6ea83fed bellard
#include "fop_template.c"
250 6ea83fed bellard
#undef SFREG
251 6ea83fed bellard
#define SFREG 26
252 6ea83fed bellard
#define DFREG 26
253 6ea83fed bellard
#include "fop_template.c"
254 6ea83fed bellard
#undef SFREG
255 6ea83fed bellard
#undef DFREG
256 6ea83fed bellard
#define SFREG 27
257 6ea83fed bellard
#include "fop_template.c"
258 6ea83fed bellard
#undef SFREG
259 6ea83fed bellard
#define SFREG 28
260 6ea83fed bellard
#define DFREG 28
261 6ea83fed bellard
#include "fop_template.c"
262 6ea83fed bellard
#undef SFREG
263 6ea83fed bellard
#undef DFREG
264 6ea83fed bellard
#define SFREG 29
265 6ea83fed bellard
#include "fop_template.c"
266 6ea83fed bellard
#undef SFREG
267 6ea83fed bellard
#define SFREG 30
268 6ea83fed bellard
#define DFREG 30
269 6ea83fed bellard
#include "fop_template.c"
270 6ea83fed bellard
#undef SFREG
271 6ea83fed bellard
#undef DFREG
272 6ea83fed bellard
#define SFREG 31
273 6ea83fed bellard
#include "fop_template.c"
274 6ea83fed bellard
#undef SFREG
275 6ea83fed bellard
276 6ea83fed bellard
#define FTN
277 6ea83fed bellard
#include "fop_template.c"
278 6ea83fed bellard
#undef FTN
279 6ea83fed bellard
280 6af0bf9c bellard
void op_dup_T0 (void)
281 6af0bf9c bellard
{
282 6af0bf9c bellard
    T2 = T0;
283 6af0bf9c bellard
    RETURN();
284 6af0bf9c bellard
}
285 6af0bf9c bellard
286 6af0bf9c bellard
void op_load_HI (void)
287 6af0bf9c bellard
{
288 6af0bf9c bellard
    T0 = env->HI;
289 6af0bf9c bellard
    RETURN();
290 6af0bf9c bellard
}
291 6af0bf9c bellard
292 6af0bf9c bellard
void op_store_HI (void)
293 6af0bf9c bellard
{
294 6af0bf9c bellard
    env->HI = T0;
295 6af0bf9c bellard
    RETURN();
296 6af0bf9c bellard
}
297 6af0bf9c bellard
298 6af0bf9c bellard
void op_load_LO (void)
299 6af0bf9c bellard
{
300 6af0bf9c bellard
    T0 = env->LO;
301 6af0bf9c bellard
    RETURN();
302 6af0bf9c bellard
}
303 6af0bf9c bellard
304 6af0bf9c bellard
void op_store_LO (void)
305 6af0bf9c bellard
{
306 6af0bf9c bellard
    env->LO = T0;
307 6af0bf9c bellard
    RETURN();
308 6af0bf9c bellard
}
309 6af0bf9c bellard
310 6af0bf9c bellard
/* Load and store */
311 6af0bf9c bellard
#define MEMSUFFIX _raw
312 6af0bf9c bellard
#include "op_mem.c"
313 6af0bf9c bellard
#undef MEMSUFFIX
314 6af0bf9c bellard
#if !defined(CONFIG_USER_ONLY)
315 6af0bf9c bellard
#define MEMSUFFIX _user
316 6af0bf9c bellard
#include "op_mem.c"
317 6af0bf9c bellard
#undef MEMSUFFIX
318 6af0bf9c bellard
319 6af0bf9c bellard
#define MEMSUFFIX _kernel
320 6af0bf9c bellard
#include "op_mem.c"
321 6af0bf9c bellard
#undef MEMSUFFIX
322 6af0bf9c bellard
#endif
323 6af0bf9c bellard
324 6af0bf9c bellard
/* Arithmetic */
325 6af0bf9c bellard
void op_add (void)
326 6af0bf9c bellard
{
327 5dc4b744 ths
    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
328 6af0bf9c bellard
    RETURN();
329 6af0bf9c bellard
}
330 6af0bf9c bellard
331 6af0bf9c bellard
void op_addo (void)
332 6af0bf9c bellard
{
333 6af0bf9c bellard
    target_ulong tmp;
334 6af0bf9c bellard
335 c570fd16 ths
    tmp = (int32_t)T0;
336 c570fd16 ths
    T0 = (int32_t)T0 + (int32_t)T1;
337 76e050c2 bellard
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
338 c570fd16 ths
        /* operands of same sign, result different sign */
339 4ad40f36 bellard
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
340 6af0bf9c bellard
    }
341 5dc4b744 ths
    T0 = (int32_t)T0;
342 6af0bf9c bellard
    RETURN();
343 6af0bf9c bellard
}
344 6af0bf9c bellard
345 6af0bf9c bellard
void op_sub (void)
346 6af0bf9c bellard
{
347 5dc4b744 ths
    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
348 6af0bf9c bellard
    RETURN();
349 6af0bf9c bellard
}
350 6af0bf9c bellard
351 6af0bf9c bellard
void op_subo (void)
352 6af0bf9c bellard
{
353 6af0bf9c bellard
    target_ulong tmp;
354 6af0bf9c bellard
355 c570fd16 ths
    tmp = (int32_t)T0;
356 6af0bf9c bellard
    T0 = (int32_t)T0 - (int32_t)T1;
357 76e050c2 bellard
    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
358 c570fd16 ths
        /* operands of different sign, first operand and result different sign */
359 4ad40f36 bellard
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
360 6af0bf9c bellard
    }
361 5dc4b744 ths
    T0 = (int32_t)T0;
362 6af0bf9c bellard
    RETURN();
363 6af0bf9c bellard
}
364 6af0bf9c bellard
365 6af0bf9c bellard
void op_mul (void)
366 6af0bf9c bellard
{
367 5dc4b744 ths
    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
368 6af0bf9c bellard
    RETURN();
369 6af0bf9c bellard
}
370 6af0bf9c bellard
371 6af0bf9c bellard
void op_div (void)
372 6af0bf9c bellard
{
373 6af0bf9c bellard
    if (T1 != 0) {
374 5dc4b744 ths
        env->LO = (int32_t)((int32_t)T0 / (int32_t)T1);
375 5dc4b744 ths
        env->HI = (int32_t)((int32_t)T0 % (int32_t)T1);
376 6af0bf9c bellard
    }
377 6af0bf9c bellard
    RETURN();
378 6af0bf9c bellard
}
379 6af0bf9c bellard
380 6af0bf9c bellard
void op_divu (void)
381 6af0bf9c bellard
{
382 6af0bf9c bellard
    if (T1 != 0) {
383 5dc4b744 ths
        env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
384 5dc4b744 ths
        env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
385 c570fd16 ths
    }
386 c570fd16 ths
    RETURN();
387 c570fd16 ths
}
388 c570fd16 ths
389 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
390 c570fd16 ths
/* Arithmetic */
391 c570fd16 ths
void op_dadd (void)
392 c570fd16 ths
{
393 c570fd16 ths
    T0 += T1;
394 c570fd16 ths
    RETURN();
395 c570fd16 ths
}
396 c570fd16 ths
397 c570fd16 ths
void op_daddo (void)
398 c570fd16 ths
{
399 c570fd16 ths
    target_long tmp;
400 c570fd16 ths
401 c570fd16 ths
    tmp = T0;
402 c570fd16 ths
    T0 += T1;
403 c570fd16 ths
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
404 c570fd16 ths
        /* operands of same sign, result different sign */
405 c570fd16 ths
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
406 c570fd16 ths
    }
407 c570fd16 ths
    RETURN();
408 c570fd16 ths
}
409 c570fd16 ths
410 c570fd16 ths
void op_dsub (void)
411 c570fd16 ths
{
412 c570fd16 ths
    T0 -= T1;
413 c570fd16 ths
    RETURN();
414 c570fd16 ths
}
415 c570fd16 ths
416 c570fd16 ths
void op_dsubo (void)
417 c570fd16 ths
{
418 c570fd16 ths
    target_long tmp;
419 c570fd16 ths
420 c570fd16 ths
    tmp = T0;
421 c570fd16 ths
    T0 = (int64_t)T0 - (int64_t)T1;
422 c570fd16 ths
    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
423 c570fd16 ths
        /* operands of different sign, first operand and result different sign */
424 c570fd16 ths
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
425 c570fd16 ths
    }
426 c570fd16 ths
    RETURN();
427 c570fd16 ths
}
428 c570fd16 ths
429 c570fd16 ths
void op_dmul (void)
430 c570fd16 ths
{
431 c570fd16 ths
    T0 = (int64_t)T0 * (int64_t)T1;
432 c570fd16 ths
    RETURN();
433 c570fd16 ths
}
434 c570fd16 ths
435 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
436 c570fd16 ths
/* Those might call libgcc functions.  */
437 c570fd16 ths
void op_ddiv (void)
438 c570fd16 ths
{
439 c570fd16 ths
    do_ddiv();
440 c570fd16 ths
    RETURN();
441 c570fd16 ths
}
442 c570fd16 ths
443 c570fd16 ths
void op_ddivu (void)
444 c570fd16 ths
{
445 c570fd16 ths
    do_ddivu();
446 c570fd16 ths
    RETURN();
447 c570fd16 ths
}
448 c570fd16 ths
#else
449 c570fd16 ths
void op_ddiv (void)
450 c570fd16 ths
{
451 c570fd16 ths
    if (T1 != 0) {
452 c570fd16 ths
        env->LO = (int64_t)T0 / (int64_t)T1;
453 c570fd16 ths
        env->HI = (int64_t)T0 % (int64_t)T1;
454 c570fd16 ths
    }
455 c570fd16 ths
    RETURN();
456 c570fd16 ths
}
457 c570fd16 ths
458 c570fd16 ths
void op_ddivu (void)
459 c570fd16 ths
{
460 c570fd16 ths
    if (T1 != 0) {
461 6af0bf9c bellard
        env->LO = T0 / T1;
462 6af0bf9c bellard
        env->HI = T0 % T1;
463 6af0bf9c bellard
    }
464 6af0bf9c bellard
    RETURN();
465 6af0bf9c bellard
}
466 c570fd16 ths
#endif
467 c570fd16 ths
#endif /* MIPS_HAS_MIPS64 */
468 6af0bf9c bellard
469 6af0bf9c bellard
/* Logical */
470 6af0bf9c bellard
void op_and (void)
471 6af0bf9c bellard
{
472 6af0bf9c bellard
    T0 &= T1;
473 6af0bf9c bellard
    RETURN();
474 6af0bf9c bellard
}
475 6af0bf9c bellard
476 6af0bf9c bellard
void op_nor (void)
477 6af0bf9c bellard
{
478 6af0bf9c bellard
    T0 = ~(T0 | T1);
479 6af0bf9c bellard
    RETURN();
480 6af0bf9c bellard
}
481 6af0bf9c bellard
482 6af0bf9c bellard
void op_or (void)
483 6af0bf9c bellard
{
484 6af0bf9c bellard
    T0 |= T1;
485 6af0bf9c bellard
    RETURN();
486 6af0bf9c bellard
}
487 6af0bf9c bellard
488 6af0bf9c bellard
void op_xor (void)
489 6af0bf9c bellard
{
490 6af0bf9c bellard
    T0 ^= T1;
491 6af0bf9c bellard
    RETURN();
492 6af0bf9c bellard
}
493 6af0bf9c bellard
494 6af0bf9c bellard
void op_sll (void)
495 6af0bf9c bellard
{
496 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T0 << (uint32_t)T1);
497 6af0bf9c bellard
    RETURN();
498 6af0bf9c bellard
}
499 6af0bf9c bellard
500 6af0bf9c bellard
void op_sra (void)
501 6af0bf9c bellard
{
502 5dc4b744 ths
    T0 = (int32_t)((int32_t)T0 >> (uint32_t)T1);
503 6af0bf9c bellard
    RETURN();
504 6af0bf9c bellard
}
505 6af0bf9c bellard
506 6af0bf9c bellard
void op_srl (void)
507 6af0bf9c bellard
{
508 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1);
509 6af0bf9c bellard
    RETURN();
510 6af0bf9c bellard
}
511 6af0bf9c bellard
512 7a387fff ths
void op_rotr (void)
513 7a387fff ths
{
514 7a387fff ths
    target_ulong tmp;
515 7a387fff ths
516 7a387fff ths
    if (T1) {
517 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T0 << (0x20 - (uint32_t)T1));
518 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1) | tmp;
519 7a387fff ths
    } else
520 7a387fff ths
       T0 = T1;
521 7a387fff ths
    RETURN();
522 7a387fff ths
}
523 7a387fff ths
524 6af0bf9c bellard
void op_sllv (void)
525 6af0bf9c bellard
{
526 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
527 6af0bf9c bellard
    RETURN();
528 6af0bf9c bellard
}
529 6af0bf9c bellard
530 6af0bf9c bellard
void op_srav (void)
531 6af0bf9c bellard
{
532 5dc4b744 ths
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
533 6af0bf9c bellard
    RETURN();
534 6af0bf9c bellard
}
535 6af0bf9c bellard
536 6af0bf9c bellard
void op_srlv (void)
537 6af0bf9c bellard
{
538 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
539 6af0bf9c bellard
    RETURN();
540 6af0bf9c bellard
}
541 6af0bf9c bellard
542 7a387fff ths
void op_rotrv (void)
543 7a387fff ths
{
544 7a387fff ths
    target_ulong tmp;
545 7a387fff ths
546 7a387fff ths
    T0 &= 0x1F;
547 7a387fff ths
    if (T0) {
548 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
549 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
550 7a387fff ths
    } else
551 7a387fff ths
       T0 = T1;
552 7a387fff ths
    RETURN();
553 7a387fff ths
}
554 7a387fff ths
555 6af0bf9c bellard
void op_clo (void)
556 6af0bf9c bellard
{
557 6af0bf9c bellard
    int n;
558 6af0bf9c bellard
559 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
560 6af0bf9c bellard
        T0 = 32;
561 6af0bf9c bellard
    } else {
562 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
563 6af0bf9c bellard
            if (!(T0 & (1 << 31)))
564 6af0bf9c bellard
                break;
565 6af0bf9c bellard
            T0 = T0 << 1;
566 6af0bf9c bellard
        }
567 6af0bf9c bellard
        T0 = n;
568 6af0bf9c bellard
    }
569 6af0bf9c bellard
    RETURN();
570 6af0bf9c bellard
}
571 6af0bf9c bellard
572 6af0bf9c bellard
void op_clz (void)
573 6af0bf9c bellard
{
574 6af0bf9c bellard
    int n;
575 6af0bf9c bellard
576 6af0bf9c bellard
    if (T0 == 0) {
577 6af0bf9c bellard
        T0 = 32;
578 6af0bf9c bellard
    } else {
579 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
580 6af0bf9c bellard
            if (T0 & (1 << 31))
581 6af0bf9c bellard
                break;
582 6af0bf9c bellard
            T0 = T0 << 1;
583 6af0bf9c bellard
        }
584 6af0bf9c bellard
        T0 = n;
585 6af0bf9c bellard
    }
586 6af0bf9c bellard
    RETURN();
587 6af0bf9c bellard
}
588 6af0bf9c bellard
589 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
590 c570fd16 ths
591 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
592 c570fd16 ths
/* Those might call libgcc functions.  */
593 c570fd16 ths
void op_dsll (void)
594 6af0bf9c bellard
{
595 c570fd16 ths
    CALL_FROM_TB0(do_dsll);
596 c570fd16 ths
    RETURN();
597 6af0bf9c bellard
}
598 6af0bf9c bellard
599 c570fd16 ths
void op_dsll32 (void)
600 6af0bf9c bellard
{
601 c570fd16 ths
    CALL_FROM_TB0(do_dsll32);
602 c570fd16 ths
    RETURN();
603 6af0bf9c bellard
}
604 6af0bf9c bellard
605 c570fd16 ths
void op_dsra (void)
606 6af0bf9c bellard
{
607 c570fd16 ths
    CALL_FROM_TB0(do_dsra);
608 6af0bf9c bellard
    RETURN();
609 6af0bf9c bellard
}
610 6af0bf9c bellard
611 c570fd16 ths
void op_dsra32 (void)
612 6af0bf9c bellard
{
613 c570fd16 ths
    CALL_FROM_TB0(do_dsra32);
614 6af0bf9c bellard
    RETURN();
615 6af0bf9c bellard
}
616 6af0bf9c bellard
617 c570fd16 ths
void op_dsrl (void)
618 6af0bf9c bellard
{
619 c570fd16 ths
    CALL_FROM_TB0(do_dsrl);
620 c570fd16 ths
    RETURN();
621 c570fd16 ths
}
622 6af0bf9c bellard
623 c570fd16 ths
void op_dsrl32 (void)
624 c570fd16 ths
{
625 c570fd16 ths
    CALL_FROM_TB0(do_dsrl32);
626 6af0bf9c bellard
    RETURN();
627 6af0bf9c bellard
}
628 6af0bf9c bellard
629 c570fd16 ths
void op_drotr (void)
630 6af0bf9c bellard
{
631 c570fd16 ths
    CALL_FROM_TB0(do_drotr);
632 c570fd16 ths
    RETURN();
633 c570fd16 ths
}
634 6af0bf9c bellard
635 c570fd16 ths
void op_drotr32 (void)
636 c570fd16 ths
{
637 c570fd16 ths
    CALL_FROM_TB0(do_drotr32);
638 6af0bf9c bellard
    RETURN();
639 6af0bf9c bellard
}
640 6af0bf9c bellard
641 c570fd16 ths
void op_dsllv (void)
642 6af0bf9c bellard
{
643 c570fd16 ths
    CALL_FROM_TB0(do_dsllv);
644 c570fd16 ths
    RETURN();
645 c570fd16 ths
}
646 6af0bf9c bellard
647 c570fd16 ths
void op_dsrav (void)
648 c570fd16 ths
{
649 c570fd16 ths
    CALL_FROM_TB0(do_dsrav);
650 6af0bf9c bellard
    RETURN();
651 6af0bf9c bellard
}
652 6af0bf9c bellard
653 c570fd16 ths
void op_dsrlv (void)
654 6af0bf9c bellard
{
655 c570fd16 ths
    CALL_FROM_TB0(do_dsrlv);
656 c570fd16 ths
    RETURN();
657 c570fd16 ths
}
658 6af0bf9c bellard
659 c570fd16 ths
void op_drotrv (void)
660 c570fd16 ths
{
661 c570fd16 ths
    CALL_FROM_TB0(do_drotrv);
662 6af0bf9c bellard
    RETURN();
663 6af0bf9c bellard
}
664 c570fd16 ths
665 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
666 c570fd16 ths
667 c570fd16 ths
void op_dsll (void)
668 c570fd16 ths
{
669 c570fd16 ths
    T0 = T0 << T1;
670 c570fd16 ths
    RETURN();
671 c570fd16 ths
}
672 c570fd16 ths
673 c570fd16 ths
void op_dsll32 (void)
674 c570fd16 ths
{
675 c570fd16 ths
    T0 = T0 << (T1 + 32);
676 c570fd16 ths
    RETURN();
677 c570fd16 ths
}
678 c570fd16 ths
679 c570fd16 ths
void op_dsra (void)
680 c570fd16 ths
{
681 c570fd16 ths
    T0 = (int64_t)T0 >> T1;
682 c570fd16 ths
    RETURN();
683 c570fd16 ths
}
684 c570fd16 ths
685 c570fd16 ths
void op_dsra32 (void)
686 c570fd16 ths
{
687 c570fd16 ths
    T0 = (int64_t)T0 >> (T1 + 32);
688 c570fd16 ths
    RETURN();
689 c570fd16 ths
}
690 c570fd16 ths
691 c570fd16 ths
void op_dsrl (void)
692 c570fd16 ths
{
693 c570fd16 ths
    T0 = T0 >> T1;
694 c570fd16 ths
    RETURN();
695 c570fd16 ths
}
696 c570fd16 ths
697 c570fd16 ths
void op_dsrl32 (void)
698 c570fd16 ths
{
699 c570fd16 ths
    T0 = T0 >> (T1 + 32);
700 c570fd16 ths
    RETURN();
701 c570fd16 ths
}
702 c570fd16 ths
703 c570fd16 ths
void op_drotr (void)
704 c570fd16 ths
{
705 c570fd16 ths
    target_ulong tmp;
706 c570fd16 ths
707 c570fd16 ths
    if (T1) {
708 c570fd16 ths
       tmp = T0 << (0x40 - T1);
709 c570fd16 ths
       T0 = (T0 >> T1) | tmp;
710 c570fd16 ths
    } else
711 c570fd16 ths
       T0 = T1;
712 c570fd16 ths
    RETURN();
713 c570fd16 ths
}
714 c570fd16 ths
715 c570fd16 ths
void op_drotr32 (void)
716 c570fd16 ths
{
717 c570fd16 ths
    target_ulong tmp;
718 c570fd16 ths
719 c570fd16 ths
    if (T1) {
720 c570fd16 ths
       tmp = T0 << (0x40 - (32 + T1));
721 c570fd16 ths
       T0 = (T0 >> (32 + T1)) | tmp;
722 c570fd16 ths
    } else
723 c570fd16 ths
       T0 = T1;
724 c570fd16 ths
    RETURN();
725 c570fd16 ths
}
726 c570fd16 ths
727 c570fd16 ths
void op_dsllv (void)
728 c570fd16 ths
{
729 c570fd16 ths
    T0 = T1 << (T0 & 0x3F);
730 c570fd16 ths
    RETURN();
731 c570fd16 ths
}
732 c570fd16 ths
733 c570fd16 ths
void op_dsrav (void)
734 c570fd16 ths
{
735 c570fd16 ths
    T0 = (int64_t)T1 >> (T0 & 0x3F);
736 c570fd16 ths
    RETURN();
737 c570fd16 ths
}
738 c570fd16 ths
739 c570fd16 ths
void op_dsrlv (void)
740 c570fd16 ths
{
741 c570fd16 ths
    T0 = T1 >> (T0 & 0x3F);
742 c570fd16 ths
    RETURN();
743 c570fd16 ths
}
744 c570fd16 ths
745 c570fd16 ths
void op_drotrv (void)
746 c570fd16 ths
{
747 c570fd16 ths
    target_ulong tmp;
748 c570fd16 ths
749 c570fd16 ths
    T0 &= 0x3F;
750 c570fd16 ths
    if (T0) {
751 c570fd16 ths
       tmp = T1 << (0x40 - T0);
752 c570fd16 ths
       T0 = (T1 >> T0) | tmp;
753 c570fd16 ths
    } else
754 c570fd16 ths
       T0 = T1;
755 c570fd16 ths
    RETURN();
756 c570fd16 ths
}
757 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
758 c570fd16 ths
759 c570fd16 ths
void op_dclo (void)
760 c570fd16 ths
{
761 c570fd16 ths
    int n;
762 c570fd16 ths
763 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
764 c570fd16 ths
        T0 = 64;
765 c570fd16 ths
    } else {
766 c570fd16 ths
        for (n = 0; n < 64; n++) {
767 c570fd16 ths
            if (!(T0 & (1ULL << 63)))
768 c570fd16 ths
                break;
769 c570fd16 ths
            T0 = T0 << 1;
770 c570fd16 ths
        }
771 c570fd16 ths
        T0 = n;
772 c570fd16 ths
    }
773 c570fd16 ths
    RETURN();
774 c570fd16 ths
}
775 c570fd16 ths
776 c570fd16 ths
void op_dclz (void)
777 c570fd16 ths
{
778 c570fd16 ths
    int n;
779 c570fd16 ths
780 c570fd16 ths
    if (T0 == 0) {
781 c570fd16 ths
        T0 = 64;
782 c570fd16 ths
    } else {
783 c570fd16 ths
        for (n = 0; n < 64; n++) {
784 c570fd16 ths
            if (T0 & (1ULL << 63))
785 c570fd16 ths
                break;
786 c570fd16 ths
            T0 = T0 << 1;
787 c570fd16 ths
        }
788 c570fd16 ths
        T0 = n;
789 c570fd16 ths
    }
790 c570fd16 ths
    RETURN();
791 c570fd16 ths
}
792 c570fd16 ths
#endif
793 c570fd16 ths
794 c570fd16 ths
/* 64 bits arithmetic */
795 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
796 6af0bf9c bellard
void op_mult (void)
797 6af0bf9c bellard
{
798 6af0bf9c bellard
    CALL_FROM_TB0(do_mult);
799 6af0bf9c bellard
    RETURN();
800 6af0bf9c bellard
}
801 6af0bf9c bellard
802 6af0bf9c bellard
void op_multu (void)
803 6af0bf9c bellard
{
804 6af0bf9c bellard
    CALL_FROM_TB0(do_multu);
805 6af0bf9c bellard
    RETURN();
806 6af0bf9c bellard
}
807 6af0bf9c bellard
808 6af0bf9c bellard
void op_madd (void)
809 6af0bf9c bellard
{
810 6af0bf9c bellard
    CALL_FROM_TB0(do_madd);
811 6af0bf9c bellard
    RETURN();
812 6af0bf9c bellard
}
813 6af0bf9c bellard
814 6af0bf9c bellard
void op_maddu (void)
815 6af0bf9c bellard
{
816 6af0bf9c bellard
    CALL_FROM_TB0(do_maddu);
817 6af0bf9c bellard
    RETURN();
818 6af0bf9c bellard
}
819 6af0bf9c bellard
820 6af0bf9c bellard
void op_msub (void)
821 6af0bf9c bellard
{
822 6af0bf9c bellard
    CALL_FROM_TB0(do_msub);
823 6af0bf9c bellard
    RETURN();
824 6af0bf9c bellard
}
825 6af0bf9c bellard
826 6af0bf9c bellard
void op_msubu (void)
827 6af0bf9c bellard
{
828 6af0bf9c bellard
    CALL_FROM_TB0(do_msubu);
829 6af0bf9c bellard
    RETURN();
830 6af0bf9c bellard
}
831 c570fd16 ths
832 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
833 c570fd16 ths
834 c570fd16 ths
static inline uint64_t get_HILO (void)
835 c570fd16 ths
{
836 c570fd16 ths
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
837 c570fd16 ths
}
838 c570fd16 ths
839 c570fd16 ths
static inline void set_HILO (uint64_t HILO)
840 c570fd16 ths
{
841 5dc4b744 ths
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
842 5dc4b744 ths
    env->HI = (int32_t)(HILO >> 32);
843 c570fd16 ths
}
844 c570fd16 ths
845 c570fd16 ths
void op_mult (void)
846 c570fd16 ths
{
847 c570fd16 ths
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
848 c570fd16 ths
    RETURN();
849 c570fd16 ths
}
850 c570fd16 ths
851 c570fd16 ths
void op_multu (void)
852 c570fd16 ths
{
853 c570fd16 ths
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
854 c570fd16 ths
    RETURN();
855 c570fd16 ths
}
856 c570fd16 ths
857 c570fd16 ths
void op_madd (void)
858 c570fd16 ths
{
859 c570fd16 ths
    int64_t tmp;
860 c570fd16 ths
861 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
862 c570fd16 ths
    set_HILO((int64_t)get_HILO() + tmp);
863 c570fd16 ths
    RETURN();
864 c570fd16 ths
}
865 c570fd16 ths
866 c570fd16 ths
void op_maddu (void)
867 c570fd16 ths
{
868 c570fd16 ths
    uint64_t tmp;
869 c570fd16 ths
870 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
871 c570fd16 ths
    set_HILO(get_HILO() + tmp);
872 c570fd16 ths
    RETURN();
873 c570fd16 ths
}
874 c570fd16 ths
875 c570fd16 ths
void op_msub (void)
876 c570fd16 ths
{
877 c570fd16 ths
    int64_t tmp;
878 c570fd16 ths
879 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
880 c570fd16 ths
    set_HILO((int64_t)get_HILO() - tmp);
881 c570fd16 ths
    RETURN();
882 c570fd16 ths
}
883 c570fd16 ths
884 c570fd16 ths
void op_msubu (void)
885 c570fd16 ths
{
886 c570fd16 ths
    uint64_t tmp;
887 c570fd16 ths
888 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
889 c570fd16 ths
    set_HILO(get_HILO() - tmp);
890 c570fd16 ths
    RETURN();
891 c570fd16 ths
}
892 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
893 c570fd16 ths
894 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
895 c570fd16 ths
void op_dmult (void)
896 c570fd16 ths
{
897 c570fd16 ths
    CALL_FROM_TB0(do_dmult);
898 c570fd16 ths
    RETURN();
899 c570fd16 ths
}
900 c570fd16 ths
901 c570fd16 ths
void op_dmultu (void)
902 c570fd16 ths
{
903 c570fd16 ths
    CALL_FROM_TB0(do_dmultu);
904 c570fd16 ths
    RETURN();
905 c570fd16 ths
}
906 6af0bf9c bellard
#endif
907 6af0bf9c bellard
908 6af0bf9c bellard
/* Conditional moves */
909 6af0bf9c bellard
void op_movn (void)
910 6af0bf9c bellard
{
911 6af0bf9c bellard
    if (T1 != 0)
912 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
913 6af0bf9c bellard
    RETURN();
914 6af0bf9c bellard
}
915 6af0bf9c bellard
916 6af0bf9c bellard
void op_movz (void)
917 6af0bf9c bellard
{
918 6af0bf9c bellard
    if (T1 == 0)
919 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
920 6af0bf9c bellard
    RETURN();
921 6af0bf9c bellard
}
922 6af0bf9c bellard
923 7a387fff ths
void op_movf (void)
924 7a387fff ths
{
925 7a387fff ths
    if (!(env->fcr31 & PARAM1))
926 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
927 7a387fff ths
    RETURN();
928 7a387fff ths
}
929 7a387fff ths
930 7a387fff ths
void op_movt (void)
931 7a387fff ths
{
932 7a387fff ths
    if (env->fcr31 & PARAM1)
933 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
934 7a387fff ths
    RETURN();
935 7a387fff ths
}
936 7a387fff ths
937 6af0bf9c bellard
/* Tests */
938 6af0bf9c bellard
#define OP_COND(name, cond) \
939 6af0bf9c bellard
void glue(op_, name) (void) \
940 6af0bf9c bellard
{                           \
941 6af0bf9c bellard
    if (cond) {             \
942 6af0bf9c bellard
        T0 = 1;             \
943 6af0bf9c bellard
    } else {                \
944 6af0bf9c bellard
        T0 = 0;             \
945 6af0bf9c bellard
    }                       \
946 6af0bf9c bellard
    RETURN();               \
947 6af0bf9c bellard
}
948 6af0bf9c bellard
949 6af0bf9c bellard
OP_COND(eq, T0 == T1);
950 6af0bf9c bellard
OP_COND(ne, T0 != T1);
951 6af0bf9c bellard
OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
952 6af0bf9c bellard
OP_COND(geu, T0 >= T1);
953 6af0bf9c bellard
OP_COND(lt, (int32_t)T0 < (int32_t)T1);
954 6af0bf9c bellard
OP_COND(ltu, T0 < T1);
955 6af0bf9c bellard
OP_COND(gez, (int32_t)T0 >= 0);
956 6af0bf9c bellard
OP_COND(gtz, (int32_t)T0 > 0);
957 6af0bf9c bellard
OP_COND(lez, (int32_t)T0 <= 0);
958 6af0bf9c bellard
OP_COND(ltz, (int32_t)T0 < 0);
959 6af0bf9c bellard
960 7a387fff ths
/* Branches */
961 6af0bf9c bellard
//#undef USE_DIRECT_JUMP
962 c53be334 bellard
963 c53be334 bellard
void OPPROTO op_goto_tb0(void)
964 c53be334 bellard
{
965 c53be334 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
966 7a387fff ths
    RETURN();
967 c53be334 bellard
}
968 c53be334 bellard
969 c53be334 bellard
void OPPROTO op_goto_tb1(void)
970 c53be334 bellard
{
971 c53be334 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
972 7a387fff ths
    RETURN();
973 c53be334 bellard
}
974 6af0bf9c bellard
975 6af0bf9c bellard
/* Branch to register */
976 6af0bf9c bellard
void op_save_breg_target (void)
977 6af0bf9c bellard
{
978 6af0bf9c bellard
    env->btarget = T2;
979 7a387fff ths
    RETURN();
980 6af0bf9c bellard
}
981 6af0bf9c bellard
982 6af0bf9c bellard
void op_restore_breg_target (void)
983 6af0bf9c bellard
{
984 6af0bf9c bellard
    T2 = env->btarget;
985 7a387fff ths
    RETURN();
986 6af0bf9c bellard
}
987 6af0bf9c bellard
988 6af0bf9c bellard
void op_breg (void)
989 6af0bf9c bellard
{
990 6af0bf9c bellard
    env->PC = T2;
991 6af0bf9c bellard
    RETURN();
992 6af0bf9c bellard
}
993 6af0bf9c bellard
994 6af0bf9c bellard
void op_save_btarget (void)
995 6af0bf9c bellard
{
996 6af0bf9c bellard
    env->btarget = PARAM1;
997 6af0bf9c bellard
    RETURN();
998 6af0bf9c bellard
}
999 6af0bf9c bellard
1000 6af0bf9c bellard
/* Conditional branch */
1001 6af0bf9c bellard
void op_set_bcond (void)
1002 6af0bf9c bellard
{
1003 6af0bf9c bellard
    T2 = T0;
1004 6af0bf9c bellard
    RETURN();
1005 6af0bf9c bellard
}
1006 6af0bf9c bellard
1007 6af0bf9c bellard
void op_save_bcond (void)
1008 6af0bf9c bellard
{
1009 6af0bf9c bellard
    env->bcond = T2;
1010 6af0bf9c bellard
    RETURN();
1011 6af0bf9c bellard
}
1012 6af0bf9c bellard
1013 6af0bf9c bellard
void op_restore_bcond (void)
1014 6af0bf9c bellard
{
1015 6af0bf9c bellard
    T2 = env->bcond;
1016 6af0bf9c bellard
    RETURN();
1017 6af0bf9c bellard
}
1018 6af0bf9c bellard
1019 c53be334 bellard
void op_jnz_T2 (void)
1020 6af0bf9c bellard
{
1021 c53be334 bellard
    if (T2)
1022 c53be334 bellard
        GOTO_LABEL_PARAM(1);
1023 6af0bf9c bellard
    RETURN();
1024 6af0bf9c bellard
}
1025 6af0bf9c bellard
1026 6af0bf9c bellard
/* CP0 functions */
1027 873eb012 ths
void op_mfc0_index (void)
1028 6af0bf9c bellard
{
1029 9c2149c8 ths
    T0 = env->CP0_Index;
1030 873eb012 ths
    RETURN();
1031 873eb012 ths
}
1032 873eb012 ths
1033 873eb012 ths
void op_mfc0_random (void)
1034 873eb012 ths
{
1035 873eb012 ths
    CALL_FROM_TB0(do_mfc0_random);
1036 873eb012 ths
    RETURN();
1037 873eb012 ths
}
1038 873eb012 ths
1039 873eb012 ths
void op_mfc0_entrylo0 (void)
1040 873eb012 ths
{
1041 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo0;
1042 873eb012 ths
    RETURN();
1043 873eb012 ths
}
1044 873eb012 ths
1045 873eb012 ths
void op_mfc0_entrylo1 (void)
1046 873eb012 ths
{
1047 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo1;
1048 873eb012 ths
    RETURN();
1049 873eb012 ths
}
1050 873eb012 ths
1051 873eb012 ths
void op_mfc0_context (void)
1052 873eb012 ths
{
1053 9c2149c8 ths
    T0 = (int32_t)env->CP0_Context;
1054 873eb012 ths
    RETURN();
1055 873eb012 ths
}
1056 873eb012 ths
1057 873eb012 ths
void op_mfc0_pagemask (void)
1058 873eb012 ths
{
1059 9c2149c8 ths
    T0 = env->CP0_PageMask;
1060 873eb012 ths
    RETURN();
1061 873eb012 ths
}
1062 873eb012 ths
1063 7a387fff ths
void op_mfc0_pagegrain (void)
1064 7a387fff ths
{
1065 9c2149c8 ths
    T0 = env->CP0_PageGrain;
1066 7a387fff ths
    RETURN();
1067 7a387fff ths
}
1068 7a387fff ths
1069 873eb012 ths
void op_mfc0_wired (void)
1070 873eb012 ths
{
1071 9c2149c8 ths
    T0 = env->CP0_Wired;
1072 873eb012 ths
    RETURN();
1073 873eb012 ths
}
1074 873eb012 ths
1075 7a387fff ths
void op_mfc0_hwrena (void)
1076 7a387fff ths
{
1077 9c2149c8 ths
    T0 = env->CP0_HWREna;
1078 7a387fff ths
    RETURN();
1079 7a387fff ths
}
1080 7a387fff ths
1081 873eb012 ths
void op_mfc0_badvaddr (void)
1082 873eb012 ths
{
1083 9c2149c8 ths
    T0 = (int32_t)env->CP0_BadVAddr;
1084 873eb012 ths
    RETURN();
1085 873eb012 ths
}
1086 873eb012 ths
1087 873eb012 ths
void op_mfc0_count (void)
1088 873eb012 ths
{
1089 873eb012 ths
    CALL_FROM_TB0(do_mfc0_count);
1090 873eb012 ths
    RETURN();
1091 873eb012 ths
}
1092 873eb012 ths
1093 873eb012 ths
void op_mfc0_entryhi (void)
1094 873eb012 ths
{
1095 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryHi;
1096 873eb012 ths
    RETURN();
1097 873eb012 ths
}
1098 873eb012 ths
1099 873eb012 ths
void op_mfc0_compare (void)
1100 873eb012 ths
{
1101 9c2149c8 ths
    T0 = env->CP0_Compare;
1102 873eb012 ths
    RETURN();
1103 873eb012 ths
}
1104 873eb012 ths
1105 873eb012 ths
void op_mfc0_status (void)
1106 873eb012 ths
{
1107 9c2149c8 ths
    T0 = env->CP0_Status;
1108 873eb012 ths
    if (env->hflags & MIPS_HFLAG_UM)
1109 873eb012 ths
        T0 |= (1 << CP0St_UM);
1110 873eb012 ths
    if (env->hflags & MIPS_HFLAG_ERL)
1111 873eb012 ths
        T0 |= (1 << CP0St_ERL);
1112 873eb012 ths
    if (env->hflags & MIPS_HFLAG_EXL)
1113 873eb012 ths
        T0 |= (1 << CP0St_EXL);
1114 873eb012 ths
    RETURN();
1115 873eb012 ths
}
1116 873eb012 ths
1117 7a387fff ths
void op_mfc0_intctl (void)
1118 7a387fff ths
{
1119 9c2149c8 ths
    T0 = env->CP0_IntCtl;
1120 7a387fff ths
    RETURN();
1121 7a387fff ths
}
1122 7a387fff ths
1123 7a387fff ths
void op_mfc0_srsctl (void)
1124 7a387fff ths
{
1125 9c2149c8 ths
    T0 = env->CP0_SRSCtl;
1126 9c2149c8 ths
    RETURN();
1127 9c2149c8 ths
}
1128 9c2149c8 ths
1129 9c2149c8 ths
void op_mfc0_srsmap (void)
1130 9c2149c8 ths
{
1131 9c2149c8 ths
    T0 = env->CP0_SRSMap;
1132 7a387fff ths
    RETURN();
1133 7a387fff ths
}
1134 7a387fff ths
1135 873eb012 ths
void op_mfc0_cause (void)
1136 873eb012 ths
{
1137 9c2149c8 ths
    T0 = env->CP0_Cause;
1138 873eb012 ths
    RETURN();
1139 873eb012 ths
}
1140 873eb012 ths
1141 873eb012 ths
void op_mfc0_epc (void)
1142 873eb012 ths
{
1143 9c2149c8 ths
    T0 = (int32_t)env->CP0_EPC;
1144 873eb012 ths
    RETURN();
1145 873eb012 ths
}
1146 873eb012 ths
1147 873eb012 ths
void op_mfc0_prid (void)
1148 873eb012 ths
{
1149 9c2149c8 ths
    T0 = env->CP0_PRid;
1150 873eb012 ths
    RETURN();
1151 873eb012 ths
}
1152 873eb012 ths
1153 7a387fff ths
void op_mfc0_ebase (void)
1154 7a387fff ths
{
1155 b29a0341 ths
    T0 = env->CP0_EBase;
1156 7a387fff ths
    RETURN();
1157 7a387fff ths
}
1158 7a387fff ths
1159 873eb012 ths
void op_mfc0_config0 (void)
1160 873eb012 ths
{
1161 9c2149c8 ths
    T0 = env->CP0_Config0;
1162 873eb012 ths
    RETURN();
1163 873eb012 ths
}
1164 873eb012 ths
1165 873eb012 ths
void op_mfc0_config1 (void)
1166 873eb012 ths
{
1167 9c2149c8 ths
    T0 = env->CP0_Config1;
1168 873eb012 ths
    RETURN();
1169 873eb012 ths
}
1170 873eb012 ths
1171 7a387fff ths
void op_mfc0_config2 (void)
1172 7a387fff ths
{
1173 9c2149c8 ths
    T0 = env->CP0_Config2;
1174 7a387fff ths
    RETURN();
1175 7a387fff ths
}
1176 7a387fff ths
1177 7a387fff ths
void op_mfc0_config3 (void)
1178 7a387fff ths
{
1179 9c2149c8 ths
    T0 = env->CP0_Config3;
1180 7a387fff ths
    RETURN();
1181 7a387fff ths
}
1182 7a387fff ths
1183 873eb012 ths
void op_mfc0_lladdr (void)
1184 873eb012 ths
{
1185 9c2149c8 ths
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1186 873eb012 ths
    RETURN();
1187 873eb012 ths
}
1188 873eb012 ths
1189 7a387fff ths
void op_mfc0_watchlo0 (void)
1190 873eb012 ths
{
1191 5dc4b744 ths
    T0 = (int32_t)env->CP0_WatchLo;
1192 873eb012 ths
    RETURN();
1193 873eb012 ths
}
1194 873eb012 ths
1195 7a387fff ths
void op_mfc0_watchhi0 (void)
1196 873eb012 ths
{
1197 9c2149c8 ths
    T0 = env->CP0_WatchHi;
1198 873eb012 ths
    RETURN();
1199 873eb012 ths
}
1200 873eb012 ths
1201 7a387fff ths
void op_mfc0_xcontext (void)
1202 7a387fff ths
{
1203 9c2149c8 ths
    T0 = (int32_t)env->CP0_XContext;
1204 7a387fff ths
    RETURN();
1205 7a387fff ths
}
1206 7a387fff ths
1207 7a387fff ths
void op_mfc0_framemask (void)
1208 7a387fff ths
{
1209 7a387fff ths
    T0 = env->CP0_Framemask;
1210 7a387fff ths
    RETURN();
1211 7a387fff ths
}
1212 7a387fff ths
1213 873eb012 ths
void op_mfc0_debug (void)
1214 873eb012 ths
{
1215 9c2149c8 ths
    T0 = env->CP0_Debug;
1216 873eb012 ths
    if (env->hflags & MIPS_HFLAG_DM)
1217 873eb012 ths
        T0 |= 1 << CP0DB_DM;
1218 873eb012 ths
    RETURN();
1219 873eb012 ths
}
1220 873eb012 ths
1221 873eb012 ths
void op_mfc0_depc (void)
1222 873eb012 ths
{
1223 9c2149c8 ths
    T0 = (int32_t)env->CP0_DEPC;
1224 873eb012 ths
    RETURN();
1225 873eb012 ths
}
1226 873eb012 ths
1227 7a387fff ths
void op_mfc0_performance0 (void)
1228 7a387fff ths
{
1229 9c2149c8 ths
    T0 = env->CP0_Performance0;
1230 7a387fff ths
    RETURN();
1231 7a387fff ths
}
1232 7a387fff ths
1233 873eb012 ths
void op_mfc0_taglo (void)
1234 873eb012 ths
{
1235 9c2149c8 ths
    T0 = env->CP0_TagLo;
1236 873eb012 ths
    RETURN();
1237 873eb012 ths
}
1238 873eb012 ths
1239 873eb012 ths
void op_mfc0_datalo (void)
1240 873eb012 ths
{
1241 9c2149c8 ths
    T0 = env->CP0_DataLo;
1242 873eb012 ths
    RETURN();
1243 873eb012 ths
}
1244 873eb012 ths
1245 7a387fff ths
void op_mfc0_taghi (void)
1246 7a387fff ths
{
1247 9c2149c8 ths
    T0 = env->CP0_TagHi;
1248 7a387fff ths
    RETURN();
1249 7a387fff ths
}
1250 7a387fff ths
1251 7a387fff ths
void op_mfc0_datahi (void)
1252 7a387fff ths
{
1253 9c2149c8 ths
    T0 = env->CP0_DataHi;
1254 7a387fff ths
    RETURN();
1255 7a387fff ths
}
1256 7a387fff ths
1257 873eb012 ths
void op_mfc0_errorepc (void)
1258 873eb012 ths
{
1259 9c2149c8 ths
    T0 = (int32_t)env->CP0_ErrorEPC;
1260 873eb012 ths
    RETURN();
1261 873eb012 ths
}
1262 873eb012 ths
1263 873eb012 ths
void op_mfc0_desave (void)
1264 873eb012 ths
{
1265 9c2149c8 ths
    T0 = env->CP0_DESAVE;
1266 6af0bf9c bellard
    RETURN();
1267 6af0bf9c bellard
}
1268 6af0bf9c bellard
1269 8c0fdd85 ths
void op_mtc0_index (void)
1270 6af0bf9c bellard
{
1271 9c2149c8 ths
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
1272 8c0fdd85 ths
    RETURN();
1273 8c0fdd85 ths
}
1274 8c0fdd85 ths
1275 8c0fdd85 ths
void op_mtc0_entrylo0 (void)
1276 8c0fdd85 ths
{
1277 7a387fff ths
    /* Large physaddr not implemented */
1278 7a387fff ths
    /* 1k pages not implemented */
1279 9c2149c8 ths
    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1280 8c0fdd85 ths
    RETURN();
1281 8c0fdd85 ths
}
1282 8c0fdd85 ths
1283 8c0fdd85 ths
void op_mtc0_entrylo1 (void)
1284 8c0fdd85 ths
{
1285 7a387fff ths
    /* Large physaddr not implemented */
1286 7a387fff ths
    /* 1k pages not implemented */
1287 9c2149c8 ths
    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1288 8c0fdd85 ths
    RETURN();
1289 8c0fdd85 ths
}
1290 8c0fdd85 ths
1291 8c0fdd85 ths
void op_mtc0_context (void)
1292 8c0fdd85 ths
{
1293 7a387fff ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1294 8c0fdd85 ths
    RETURN();
1295 8c0fdd85 ths
}
1296 8c0fdd85 ths
1297 8c0fdd85 ths
void op_mtc0_pagemask (void)
1298 8c0fdd85 ths
{
1299 7a387fff ths
    /* 1k pages not implemented */
1300 7a387fff ths
    env->CP0_PageMask = T0 & 0x1FFFE000;
1301 7a387fff ths
    RETURN();
1302 7a387fff ths
}
1303 7a387fff ths
1304 7a387fff ths
void op_mtc0_pagegrain (void)
1305 7a387fff ths
{
1306 7a387fff ths
    /* SmartMIPS not implemented */
1307 7a387fff ths
    /* Large physaddr not implemented */
1308 7a387fff ths
    /* 1k pages not implemented */
1309 7a387fff ths
    env->CP0_PageGrain = 0;
1310 8c0fdd85 ths
    RETURN();
1311 8c0fdd85 ths
}
1312 8c0fdd85 ths
1313 8c0fdd85 ths
void op_mtc0_wired (void)
1314 8c0fdd85 ths
{
1315 7a387fff ths
    env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1316 7a387fff ths
    RETURN();
1317 7a387fff ths
}
1318 7a387fff ths
1319 7a387fff ths
void op_mtc0_hwrena (void)
1320 7a387fff ths
{
1321 7a387fff ths
    env->CP0_HWREna = T0 & 0x0000000F;
1322 8c0fdd85 ths
    RETURN();
1323 8c0fdd85 ths
}
1324 8c0fdd85 ths
1325 8c0fdd85 ths
void op_mtc0_count (void)
1326 8c0fdd85 ths
{
1327 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1328 8c0fdd85 ths
    RETURN();
1329 8c0fdd85 ths
}
1330 8c0fdd85 ths
1331 8c0fdd85 ths
void op_mtc0_entryhi (void)
1332 8c0fdd85 ths
{
1333 0feef828 ths
    target_ulong old, val;
1334 8c0fdd85 ths
1335 7a387fff ths
    /* 1k pages not implemented */
1336 7a387fff ths
    /* Ignore MIPS64 TLB for now */
1337 925fd0f2 ths
    val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
1338 8c0fdd85 ths
    old = env->CP0_EntryHi;
1339 8c0fdd85 ths
    env->CP0_EntryHi = val;
1340 8c0fdd85 ths
    /* If the ASID changes, flush qemu's TLB.  */
1341 8c0fdd85 ths
    if ((old & 0xFF) != (val & 0xFF))
1342 8c0fdd85 ths
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1343 8c0fdd85 ths
    RETURN();
1344 8c0fdd85 ths
}
1345 8c0fdd85 ths
1346 8c0fdd85 ths
void op_mtc0_compare (void)
1347 8c0fdd85 ths
{
1348 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1349 8c0fdd85 ths
    RETURN();
1350 8c0fdd85 ths
}
1351 8c0fdd85 ths
1352 8c0fdd85 ths
void op_mtc0_status (void)
1353 8c0fdd85 ths
{
1354 4de9b249 ths
    uint32_t val, old;
1355 8c0fdd85 ths
1356 9c2149c8 ths
    val = (int32_t)T0 & 0xFA78FF01;
1357 8c0fdd85 ths
    old = env->CP0_Status;
1358 8c0fdd85 ths
    if (T0 & (1 << CP0St_UM))
1359 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_UM;
1360 8c0fdd85 ths
    else
1361 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_UM;
1362 8c0fdd85 ths
    if (T0 & (1 << CP0St_ERL))
1363 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_ERL;
1364 8c0fdd85 ths
    else
1365 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_ERL;
1366 8c0fdd85 ths
    if (T0 & (1 << CP0St_EXL))
1367 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_EXL;
1368 8c0fdd85 ths
    else
1369 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_EXL;
1370 8c0fdd85 ths
    env->CP0_Status = val;
1371 8c0fdd85 ths
    if (loglevel & CPU_LOG_TB_IN_ASM)
1372 8c0fdd85 ths
       CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1373 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1374 8c0fdd85 ths
    RETURN();
1375 8c0fdd85 ths
}
1376 8c0fdd85 ths
1377 7a387fff ths
void op_mtc0_intctl (void)
1378 7a387fff ths
{
1379 7a387fff ths
    /* vectored interrupts not implemented */
1380 7a387fff ths
    env->CP0_IntCtl = 0;
1381 7a387fff ths
    RETURN();
1382 7a387fff ths
}
1383 7a387fff ths
1384 7a387fff ths
void op_mtc0_srsctl (void)
1385 7a387fff ths
{
1386 7a387fff ths
    /* shadow registers not implemented */
1387 7a387fff ths
    env->CP0_SRSCtl = 0;
1388 7a387fff ths
    RETURN();
1389 7a387fff ths
}
1390 7a387fff ths
1391 9c2149c8 ths
void op_mtc0_srsmap (void)
1392 9c2149c8 ths
{
1393 9c2149c8 ths
    /* shadow registers not implemented */
1394 9c2149c8 ths
    env->CP0_SRSMap = 0;
1395 9c2149c8 ths
    RETURN();
1396 9c2149c8 ths
}
1397 9c2149c8 ths
1398 8c0fdd85 ths
void op_mtc0_cause (void)
1399 8c0fdd85 ths
{
1400 39d51eb8 ths
    uint32_t mask = 0x00C00300;
1401 39d51eb8 ths
1402 39d51eb8 ths
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1403 39d51eb8 ths
        mask |= 1 << CP0Ca_DC;
1404 39d51eb8 ths
1405 39d51eb8 ths
    env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
1406 8c0fdd85 ths
1407 4de9b249 ths
    /* Handle the software interrupt as an hardware one, as they
1408 4de9b249 ths
       are very similar */
1409 4de9b249 ths
    if (T0 & CP0Ca_IP_mask) {
1410 4de9b249 ths
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1411 8c0fdd85 ths
    }
1412 8c0fdd85 ths
    RETURN();
1413 8c0fdd85 ths
}
1414 8c0fdd85 ths
1415 8c0fdd85 ths
void op_mtc0_epc (void)
1416 8c0fdd85 ths
{
1417 9c2149c8 ths
    env->CP0_EPC = (int32_t)T0;
1418 8c0fdd85 ths
    RETURN();
1419 8c0fdd85 ths
}
1420 8c0fdd85 ths
1421 7a387fff ths
void op_mtc0_ebase (void)
1422 7a387fff ths
{
1423 7a387fff ths
    /* vectored interrupts not implemented */
1424 7a387fff ths
    /* Multi-CPU not implemented */
1425 b29a0341 ths
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1426 7a387fff ths
    RETURN();
1427 7a387fff ths
}
1428 7a387fff ths
1429 8c0fdd85 ths
void op_mtc0_config0 (void)
1430 8c0fdd85 ths
{
1431 8c0fdd85 ths
#if defined(MIPS_USES_R4K_TLB)
1432 7a387fff ths
     /* Fixed mapping MMU not implemented */
1433 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1434 8c0fdd85 ths
#else
1435 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1436 8c0fdd85 ths
#endif
1437 8c0fdd85 ths
    RETURN();
1438 8c0fdd85 ths
}
1439 8c0fdd85 ths
1440 7a387fff ths
void op_mtc0_config2 (void)
1441 7a387fff ths
{
1442 7a387fff ths
    /* tertiary/secondary caches not implemented */
1443 7a387fff ths
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1444 7a387fff ths
    RETURN();
1445 7a387fff ths
}
1446 7a387fff ths
1447 7a387fff ths
void op_mtc0_watchlo0 (void)
1448 8c0fdd85 ths
{
1449 9c2149c8 ths
    env->CP0_WatchLo = (int32_t)T0;
1450 8c0fdd85 ths
    RETURN();
1451 8c0fdd85 ths
}
1452 8c0fdd85 ths
1453 7a387fff ths
void op_mtc0_watchhi0 (void)
1454 8c0fdd85 ths
{
1455 8c0fdd85 ths
    env->CP0_WatchHi = T0 & 0x40FF0FF8;
1456 8c0fdd85 ths
    RETURN();
1457 8c0fdd85 ths
}
1458 8c0fdd85 ths
1459 7a387fff ths
void op_mtc0_xcontext (void)
1460 7a387fff ths
{
1461 9c2149c8 ths
    env->CP0_XContext = (int32_t)T0; /* XXX */
1462 7a387fff ths
    RETURN();
1463 7a387fff ths
}
1464 7a387fff ths
1465 7a387fff ths
void op_mtc0_framemask (void)
1466 7a387fff ths
{
1467 7a387fff ths
    env->CP0_Framemask = T0; /* XXX */
1468 7a387fff ths
    RETURN();
1469 7a387fff ths
}
1470 7a387fff ths
1471 8c0fdd85 ths
void op_mtc0_debug (void)
1472 8c0fdd85 ths
{
1473 8c0fdd85 ths
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1474 8c0fdd85 ths
    if (T0 & (1 << CP0DB_DM))
1475 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_DM;
1476 8c0fdd85 ths
    else
1477 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_DM;
1478 8c0fdd85 ths
    RETURN();
1479 8c0fdd85 ths
}
1480 8c0fdd85 ths
1481 8c0fdd85 ths
void op_mtc0_depc (void)
1482 8c0fdd85 ths
{
1483 9c2149c8 ths
    env->CP0_DEPC = (int32_t)T0;
1484 8c0fdd85 ths
    RETURN();
1485 8c0fdd85 ths
}
1486 8c0fdd85 ths
1487 7a387fff ths
void op_mtc0_performance0 (void)
1488 7a387fff ths
{
1489 7a387fff ths
    env->CP0_Performance0 = T0; /* XXX */
1490 7a387fff ths
    RETURN();
1491 7a387fff ths
}
1492 7a387fff ths
1493 8c0fdd85 ths
void op_mtc0_taglo (void)
1494 8c0fdd85 ths
{
1495 9c2149c8 ths
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1496 8c0fdd85 ths
    RETURN();
1497 8c0fdd85 ths
}
1498 8c0fdd85 ths
1499 7a387fff ths
void op_mtc0_datalo (void)
1500 7a387fff ths
{
1501 7a387fff ths
    env->CP0_DataLo = T0; /* XXX */
1502 7a387fff ths
    RETURN();
1503 7a387fff ths
}
1504 7a387fff ths
1505 7a387fff ths
void op_mtc0_taghi (void)
1506 7a387fff ths
{
1507 7a387fff ths
    env->CP0_TagHi = T0; /* XXX */
1508 7a387fff ths
    RETURN();
1509 7a387fff ths
}
1510 7a387fff ths
1511 7a387fff ths
void op_mtc0_datahi (void)
1512 7a387fff ths
{
1513 7a387fff ths
    env->CP0_DataHi = T0; /* XXX */
1514 7a387fff ths
    RETURN();
1515 7a387fff ths
}
1516 7a387fff ths
1517 8c0fdd85 ths
void op_mtc0_errorepc (void)
1518 8c0fdd85 ths
{
1519 9c2149c8 ths
    env->CP0_ErrorEPC = (int32_t)T0;
1520 8c0fdd85 ths
    RETURN();
1521 8c0fdd85 ths
}
1522 8c0fdd85 ths
1523 8c0fdd85 ths
void op_mtc0_desave (void)
1524 8c0fdd85 ths
{
1525 8c0fdd85 ths
    env->CP0_DESAVE = T0;
1526 6af0bf9c bellard
    RETURN();
1527 6af0bf9c bellard
}
1528 6af0bf9c bellard
1529 9c2149c8 ths
void op_dmfc0_entrylo0 (void)
1530 9c2149c8 ths
{
1531 9c2149c8 ths
    T0 = env->CP0_EntryLo0;
1532 9c2149c8 ths
    RETURN();
1533 9c2149c8 ths
}
1534 9c2149c8 ths
1535 9c2149c8 ths
void op_dmfc0_entrylo1 (void)
1536 9c2149c8 ths
{
1537 9c2149c8 ths
    T0 = env->CP0_EntryLo1;
1538 9c2149c8 ths
    RETURN();
1539 9c2149c8 ths
}
1540 9c2149c8 ths
1541 9c2149c8 ths
void op_dmfc0_context (void)
1542 9c2149c8 ths
{
1543 9c2149c8 ths
    T0 = env->CP0_Context;
1544 9c2149c8 ths
    RETURN();
1545 9c2149c8 ths
}
1546 9c2149c8 ths
1547 9c2149c8 ths
void op_dmfc0_badvaddr (void)
1548 9c2149c8 ths
{
1549 9c2149c8 ths
    T0 = env->CP0_BadVAddr;
1550 9c2149c8 ths
    RETURN();
1551 9c2149c8 ths
}
1552 9c2149c8 ths
1553 9c2149c8 ths
void op_dmfc0_entryhi (void)
1554 9c2149c8 ths
{
1555 9c2149c8 ths
    T0 = env->CP0_EntryHi;
1556 9c2149c8 ths
    RETURN();
1557 9c2149c8 ths
}
1558 9c2149c8 ths
1559 9c2149c8 ths
void op_dmfc0_epc (void)
1560 9c2149c8 ths
{
1561 9c2149c8 ths
    T0 = env->CP0_EPC;
1562 9c2149c8 ths
    RETURN();
1563 9c2149c8 ths
}
1564 9c2149c8 ths
1565 9c2149c8 ths
void op_dmfc0_lladdr (void)
1566 9c2149c8 ths
{
1567 9c2149c8 ths
    T0 = env->CP0_LLAddr >> 4;
1568 9c2149c8 ths
    RETURN();
1569 9c2149c8 ths
}
1570 9c2149c8 ths
1571 9c2149c8 ths
void op_dmfc0_watchlo0 (void)
1572 9c2149c8 ths
{
1573 9c2149c8 ths
    T0 = env->CP0_WatchLo;
1574 9c2149c8 ths
    RETURN();
1575 9c2149c8 ths
}
1576 9c2149c8 ths
1577 9c2149c8 ths
void op_dmfc0_xcontext (void)
1578 9c2149c8 ths
{
1579 9c2149c8 ths
    T0 = env->CP0_XContext;
1580 9c2149c8 ths
    RETURN();
1581 9c2149c8 ths
}
1582 9c2149c8 ths
1583 9c2149c8 ths
void op_dmfc0_depc (void)
1584 9c2149c8 ths
{
1585 9c2149c8 ths
    T0 = env->CP0_DEPC;
1586 9c2149c8 ths
    RETURN();
1587 9c2149c8 ths
}
1588 9c2149c8 ths
1589 9c2149c8 ths
void op_dmfc0_errorepc (void)
1590 9c2149c8 ths
{
1591 9c2149c8 ths
    T0 = env->CP0_ErrorEPC;
1592 9c2149c8 ths
    RETURN();
1593 9c2149c8 ths
}
1594 9c2149c8 ths
1595 9c2149c8 ths
void op_dmtc0_entrylo0 (void)
1596 9c2149c8 ths
{
1597 9c2149c8 ths
    /* Large physaddr not implemented */
1598 9c2149c8 ths
    /* 1k pages not implemented */
1599 9c2149c8 ths
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1600 9c2149c8 ths
    RETURN();
1601 9c2149c8 ths
}
1602 9c2149c8 ths
1603 9c2149c8 ths
void op_dmtc0_entrylo1 (void)
1604 9c2149c8 ths
{
1605 9c2149c8 ths
    /* Large physaddr not implemented */
1606 9c2149c8 ths
    /* 1k pages not implemented */
1607 9c2149c8 ths
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1608 9c2149c8 ths
    RETURN();
1609 9c2149c8 ths
}
1610 9c2149c8 ths
1611 9c2149c8 ths
void op_dmtc0_context (void)
1612 9c2149c8 ths
{
1613 9c2149c8 ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1614 9c2149c8 ths
    RETURN();
1615 9c2149c8 ths
}
1616 9c2149c8 ths
1617 9c2149c8 ths
void op_dmtc0_epc (void)
1618 9c2149c8 ths
{
1619 9c2149c8 ths
    env->CP0_EPC = T0;
1620 9c2149c8 ths
    RETURN();
1621 9c2149c8 ths
}
1622 9c2149c8 ths
1623 9c2149c8 ths
void op_dmtc0_watchlo0 (void)
1624 9c2149c8 ths
{
1625 9c2149c8 ths
    env->CP0_WatchLo = T0;
1626 9c2149c8 ths
    RETURN();
1627 9c2149c8 ths
}
1628 9c2149c8 ths
1629 9c2149c8 ths
void op_dmtc0_xcontext (void)
1630 9c2149c8 ths
{
1631 9c2149c8 ths
    env->CP0_XContext = T0; /* XXX */
1632 9c2149c8 ths
    RETURN();
1633 9c2149c8 ths
}
1634 9c2149c8 ths
1635 9c2149c8 ths
void op_dmtc0_depc (void)
1636 9c2149c8 ths
{
1637 9c2149c8 ths
    env->CP0_DEPC = T0;
1638 9c2149c8 ths
    RETURN();
1639 9c2149c8 ths
}
1640 9c2149c8 ths
1641 9c2149c8 ths
void op_dmtc0_errorepc (void)
1642 9c2149c8 ths
{
1643 9c2149c8 ths
    env->CP0_ErrorEPC = T0;
1644 9c2149c8 ths
    RETURN();
1645 9c2149c8 ths
}
1646 9c2149c8 ths
1647 6ea83fed bellard
#if 0
1648 6ea83fed bellard
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1649 6ea83fed bellard
#else
1650 6ea83fed bellard
# define DEBUG_FPU_STATE() do { } while(0)
1651 6ea83fed bellard
#endif
1652 6ea83fed bellard
1653 6ea83fed bellard
void op_cp1_enabled(void)
1654 6ea83fed bellard
{
1655 6ea83fed bellard
    if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1656 6ea83fed bellard
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1657 6ea83fed bellard
    }
1658 6ea83fed bellard
    RETURN();
1659 6ea83fed bellard
}
1660 6ea83fed bellard
1661 6ea83fed bellard
/* CP1 functions */
1662 6ea83fed bellard
void op_cfc1 (void)
1663 6ea83fed bellard
{
1664 6ea83fed bellard
    if (T1 == 0) {
1665 6ea83fed bellard
        T0 = env->fcr0;
1666 6ea83fed bellard
    }
1667 6ea83fed bellard
    else {
1668 6ea83fed bellard
        /* fetch fcr31, masking unused bits */
1669 6ea83fed bellard
        T0 = env->fcr31 & 0x0183FFFF;
1670 6ea83fed bellard
    }
1671 6ea83fed bellard
    DEBUG_FPU_STATE();
1672 6ea83fed bellard
    RETURN();
1673 6ea83fed bellard
}
1674 6ea83fed bellard
1675 6ea83fed bellard
/* convert MIPS rounding mode in FCR31 to IEEE library */
1676 6ea83fed bellard
unsigned int ieee_rm[] = { 
1677 6ea83fed bellard
    float_round_nearest_even,
1678 6ea83fed bellard
    float_round_to_zero,
1679 6ea83fed bellard
    float_round_up,
1680 6ea83fed bellard
    float_round_down
1681 6ea83fed bellard
};
1682 6ea83fed bellard
1683 6ea83fed bellard
#define RESTORE_ROUNDING_MODE \
1684 6ea83fed bellard
    set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1685 6ea83fed bellard
1686 6ea83fed bellard
void op_ctc1 (void)
1687 6ea83fed bellard
{
1688 6ea83fed bellard
    if (T1 == 0) {
1689 6ea83fed bellard
        /* XXX should this throw an exception?
1690 6ea83fed bellard
         * don't write to FCR0.
1691 6ea83fed bellard
         * env->fcr0 = T0; 
1692 6ea83fed bellard
         */
1693 6ea83fed bellard
    }
1694 6ea83fed bellard
    else {
1695 6ea83fed bellard
        /* store new fcr31, masking unused bits */  
1696 6ea83fed bellard
        env->fcr31 = T0 & 0x0183FFFF;
1697 6ea83fed bellard
1698 6ea83fed bellard
        /* set rounding mode */
1699 6ea83fed bellard
        RESTORE_ROUNDING_MODE;
1700 6ea83fed bellard
1701 6ea83fed bellard
#ifndef CONFIG_SOFTFLOAT
1702 6ea83fed bellard
        /* no floating point exception for native float */
1703 6ea83fed bellard
        SET_FP_ENABLE(env->fcr31, 0);
1704 6ea83fed bellard
#endif
1705 6ea83fed bellard
    }
1706 6ea83fed bellard
    DEBUG_FPU_STATE();
1707 6ea83fed bellard
    RETURN();
1708 6ea83fed bellard
}
1709 6ea83fed bellard
1710 6ea83fed bellard
void op_mfc1 (void)
1711 6ea83fed bellard
{
1712 6ea83fed bellard
    T0 = WT0;
1713 6ea83fed bellard
    DEBUG_FPU_STATE();
1714 6ea83fed bellard
    RETURN();
1715 6ea83fed bellard
}
1716 6ea83fed bellard
1717 6ea83fed bellard
void op_mtc1 (void)
1718 6ea83fed bellard
{
1719 6ea83fed bellard
    WT0 = T0;
1720 6ea83fed bellard
    DEBUG_FPU_STATE();
1721 6ea83fed bellard
    RETURN();
1722 6ea83fed bellard
}
1723 6ea83fed bellard
1724 6ea83fed bellard
/* Float support.
1725 6ea83fed bellard
   Single precition routines have a "s" suffix, double precision a
1726 6ea83fed bellard
   "d" suffix.  */
1727 6ea83fed bellard
1728 6ea83fed bellard
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1729 6ea83fed bellard
1730 dd016883 bellard
FLOAT_OP(cvtd, s)
1731 dd016883 bellard
{
1732 00a709c7 ths
    FDT2 = float32_to_float64(FST0, &env->fp_status);
1733 dd016883 bellard
    DEBUG_FPU_STATE();
1734 dd016883 bellard
    RETURN();
1735 dd016883 bellard
}
1736 6ea83fed bellard
FLOAT_OP(cvtd, w)
1737 6ea83fed bellard
{
1738 6ea83fed bellard
    FDT2 = int32_to_float64(WT0, &env->fp_status);
1739 6ea83fed bellard
    DEBUG_FPU_STATE();
1740 6ea83fed bellard
    RETURN();
1741 6ea83fed bellard
}
1742 dd016883 bellard
FLOAT_OP(cvts, d)
1743 dd016883 bellard
{
1744 417f38f0 pbrook
    FST2 = float64_to_float32(FDT0, &env->fp_status);
1745 dd016883 bellard
    DEBUG_FPU_STATE();
1746 dd016883 bellard
    RETURN();
1747 dd016883 bellard
}
1748 6ea83fed bellard
FLOAT_OP(cvts, w)
1749 6ea83fed bellard
{
1750 6ea83fed bellard
    FST2 = int32_to_float32(WT0, &env->fp_status);
1751 6ea83fed bellard
    DEBUG_FPU_STATE();
1752 6ea83fed bellard
    RETURN();
1753 6ea83fed bellard
}
1754 6ea83fed bellard
FLOAT_OP(cvtw, s)
1755 6ea83fed bellard
{
1756 6ea83fed bellard
    WT2 = float32_to_int32(FST0, &env->fp_status);
1757 6ea83fed bellard
    DEBUG_FPU_STATE();
1758 6ea83fed bellard
    RETURN();
1759 6ea83fed bellard
}
1760 6ea83fed bellard
FLOAT_OP(cvtw, d)
1761 6ea83fed bellard
{
1762 6ea83fed bellard
    WT2 = float64_to_int32(FDT0, &env->fp_status);
1763 6ea83fed bellard
    DEBUG_FPU_STATE();
1764 6ea83fed bellard
    RETURN();
1765 6ea83fed bellard
}
1766 6ea83fed bellard
1767 6ea83fed bellard
FLOAT_OP(roundw, d)
1768 6ea83fed bellard
{
1769 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1770 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1771 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1772 6ea83fed bellard
1773 6ea83fed bellard
    DEBUG_FPU_STATE();
1774 6ea83fed bellard
    RETURN();
1775 6ea83fed bellard
}
1776 6ea83fed bellard
FLOAT_OP(roundw, s)
1777 6ea83fed bellard
{
1778 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1779 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1780 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1781 6ea83fed bellard
    DEBUG_FPU_STATE();
1782 6ea83fed bellard
    RETURN();
1783 6ea83fed bellard
}
1784 6ea83fed bellard
1785 6ea83fed bellard
FLOAT_OP(truncw, d)
1786 6ea83fed bellard
{
1787 6ea83fed bellard
    WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1788 6ea83fed bellard
    DEBUG_FPU_STATE();
1789 6ea83fed bellard
    RETURN();
1790 6ea83fed bellard
}
1791 6ea83fed bellard
FLOAT_OP(truncw, s)
1792 6ea83fed bellard
{
1793 6ea83fed bellard
    WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1794 6ea83fed bellard
    DEBUG_FPU_STATE();
1795 6ea83fed bellard
    RETURN();
1796 6ea83fed bellard
}
1797 6ea83fed bellard
1798 6ea83fed bellard
FLOAT_OP(ceilw, d)
1799 6ea83fed bellard
{
1800 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1801 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1802 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1803 6ea83fed bellard
1804 6ea83fed bellard
    DEBUG_FPU_STATE();
1805 6ea83fed bellard
    RETURN();
1806 6ea83fed bellard
}
1807 6ea83fed bellard
FLOAT_OP(ceilw, s)
1808 6ea83fed bellard
{
1809 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1810 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1811 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1812 6ea83fed bellard
    DEBUG_FPU_STATE();
1813 6ea83fed bellard
    RETURN();
1814 6ea83fed bellard
}
1815 6ea83fed bellard
1816 6ea83fed bellard
FLOAT_OP(floorw, d)
1817 6ea83fed bellard
{
1818 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1819 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1820 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1821 6ea83fed bellard
1822 6ea83fed bellard
    DEBUG_FPU_STATE();
1823 6ea83fed bellard
    RETURN();
1824 6ea83fed bellard
}
1825 6ea83fed bellard
FLOAT_OP(floorw, s)
1826 6ea83fed bellard
{
1827 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1828 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1829 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1830 6ea83fed bellard
    DEBUG_FPU_STATE();
1831 6ea83fed bellard
    RETURN();
1832 6ea83fed bellard
}
1833 6ea83fed bellard
1834 6ea83fed bellard
/* binary operations */
1835 6ea83fed bellard
#define FLOAT_BINOP(name) \
1836 6ea83fed bellard
FLOAT_OP(name, d)         \
1837 6ea83fed bellard
{                         \
1838 6ea83fed bellard
    FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
1839 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1840 6ea83fed bellard
}                         \
1841 6ea83fed bellard
FLOAT_OP(name, s)         \
1842 6ea83fed bellard
{                         \
1843 6ea83fed bellard
    FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1844 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1845 6ea83fed bellard
}
1846 6ea83fed bellard
FLOAT_BINOP(add)
1847 6ea83fed bellard
FLOAT_BINOP(sub)
1848 6ea83fed bellard
FLOAT_BINOP(mul)
1849 6ea83fed bellard
FLOAT_BINOP(div)
1850 6ea83fed bellard
#undef FLOAT_BINOP
1851 6ea83fed bellard
1852 6ea83fed bellard
/* unary operations, modifying fp status  */
1853 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1854 6ea83fed bellard
FLOAT_OP(name, d)         \
1855 6ea83fed bellard
{                         \
1856 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
1857 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1858 6ea83fed bellard
}                         \
1859 6ea83fed bellard
FLOAT_OP(name, s)         \
1860 6ea83fed bellard
{                         \
1861 6ea83fed bellard
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
1862 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1863 6ea83fed bellard
}
1864 6ea83fed bellard
FLOAT_UNOP(sqrt)
1865 6ea83fed bellard
#undef FLOAT_UNOP
1866 6ea83fed bellard
1867 6ea83fed bellard
/* unary operations, not modifying fp status  */
1868 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1869 6ea83fed bellard
FLOAT_OP(name, d)         \
1870 6ea83fed bellard
{                         \
1871 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0);   \
1872 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1873 6ea83fed bellard
}                         \
1874 6ea83fed bellard
FLOAT_OP(name, s)         \
1875 6ea83fed bellard
{                         \
1876 6ea83fed bellard
    FST2 = float32_ ## name(FST0);   \
1877 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1878 6ea83fed bellard
}
1879 6ea83fed bellard
FLOAT_UNOP(abs)
1880 6ea83fed bellard
FLOAT_UNOP(chs)
1881 6ea83fed bellard
#undef FLOAT_UNOP
1882 6ea83fed bellard
1883 6ea83fed bellard
FLOAT_OP(mov, d)
1884 6ea83fed bellard
{
1885 6ea83fed bellard
    FDT2 = FDT0;
1886 6ea83fed bellard
    DEBUG_FPU_STATE();
1887 6ea83fed bellard
    RETURN();
1888 6ea83fed bellard
}
1889 6ea83fed bellard
FLOAT_OP(mov, s)
1890 6ea83fed bellard
{
1891 6ea83fed bellard
    FST2 = FST0;
1892 6ea83fed bellard
    DEBUG_FPU_STATE();
1893 6ea83fed bellard
    RETURN();
1894 6ea83fed bellard
}
1895 6ea83fed bellard
1896 6ea83fed bellard
#ifdef CONFIG_SOFTFLOAT
1897 6ea83fed bellard
#define clear_invalid() do {                                \
1898 6ea83fed bellard
    int flags = get_float_exception_flags(&env->fp_status); \
1899 6ea83fed bellard
    flags &= ~float_flag_invalid;                           \
1900 6ea83fed bellard
    set_float_exception_flags(flags, &env->fp_status);      \
1901 6ea83fed bellard
} while(0)
1902 6ea83fed bellard
#else
1903 6ea83fed bellard
#define clear_invalid() do { } while(0)
1904 6ea83fed bellard
#endif
1905 6ea83fed bellard
1906 6ea83fed bellard
extern void dump_fpu_s(CPUState *env);
1907 6ea83fed bellard
1908 6ea83fed bellard
#define FOP_COND(fmt, op, sig, cond)           \
1909 6ea83fed bellard
void op_cmp_ ## fmt ## _ ## op (void)          \
1910 6ea83fed bellard
{                                              \
1911 6ea83fed bellard
    if (cond)                                  \
1912 6ea83fed bellard
        SET_FP_COND(env->fcr31);               \
1913 6ea83fed bellard
    else                                       \
1914 6ea83fed bellard
        CLEAR_FP_COND(env->fcr31);             \
1915 6ea83fed bellard
    if (!sig)                                  \
1916 6ea83fed bellard
        clear_invalid();                       \
1917 6ea83fed bellard
    /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1918 6ea83fed bellard
    DEBUG_FPU_STATE();                         \
1919 6ea83fed bellard
    RETURN();                                  \
1920 6ea83fed bellard
}
1921 6ea83fed bellard
1922 569f5d66 bellard
int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1923 6ea83fed bellard
{
1924 6ea83fed bellard
    if (float64_is_nan(a) || float64_is_nan(b)) {
1925 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1926 6ea83fed bellard
        return 1;
1927 6ea83fed bellard
    }
1928 6ea83fed bellard
    else {
1929 6ea83fed bellard
        return 0;
1930 6ea83fed bellard
    }
1931 6ea83fed bellard
}
1932 6ea83fed bellard
1933 6ea83fed bellard
FOP_COND(d, f,   0,                                                      0) 
1934 6ea83fed bellard
FOP_COND(d, un,  0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1935 6ea83fed bellard
FOP_COND(d, eq,  0,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1936 6ea83fed bellard
FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1937 6ea83fed bellard
FOP_COND(d, olt, 0,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1938 6ea83fed bellard
FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1939 6ea83fed bellard
FOP_COND(d, ole, 0,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1940 6ea83fed bellard
FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1941 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1942 6ea83fed bellard
 * but float*_is_unordered() is still called
1943 6ea83fed bellard
 */
1944 6ea83fed bellard
FOP_COND(d, sf,  1,                                                      (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1945 6ea83fed bellard
FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1946 6ea83fed bellard
FOP_COND(d, seq, 1,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1947 6ea83fed bellard
FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1948 6ea83fed bellard
FOP_COND(d, lt,  1,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1949 6ea83fed bellard
FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1950 6ea83fed bellard
FOP_COND(d, le,  1,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1951 6ea83fed bellard
FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1952 6ea83fed bellard
1953 6ea83fed bellard
flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1954 6ea83fed bellard
{
1955 6ea83fed bellard
    extern flag float32_is_nan( float32 a );
1956 6ea83fed bellard
    if (float32_is_nan(a) || float32_is_nan(b)) {
1957 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1958 6ea83fed bellard
        return 1;
1959 6ea83fed bellard
    }
1960 6ea83fed bellard
    else {
1961 6ea83fed bellard
        return 0;
1962 6ea83fed bellard
    }
1963 6ea83fed bellard
}
1964 6ea83fed bellard
1965 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1966 6ea83fed bellard
 * but float*_is_unordered() is still called
1967 6ea83fed bellard
 */
1968 6ea83fed bellard
FOP_COND(s, f,   0,                                                      0) 
1969 6ea83fed bellard
FOP_COND(s, un,  0, float32_is_unordered(FST1, FST0, &env->fp_status))
1970 6ea83fed bellard
FOP_COND(s, eq,  0,                                                      float32_eq(FST0, FST1, &env->fp_status))
1971 6ea83fed bellard
FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1972 6ea83fed bellard
FOP_COND(s, olt, 0,                                                      float32_lt(FST0, FST1, &env->fp_status))
1973 6ea83fed bellard
FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1974 6ea83fed bellard
FOP_COND(s, ole, 0,                                                      float32_le(FST0, FST1, &env->fp_status))
1975 6ea83fed bellard
FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1976 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1977 6ea83fed bellard
 * but float*_is_unordered() is still called
1978 6ea83fed bellard
 */
1979 6ea83fed bellard
FOP_COND(s, sf,  1,                                                      (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1980 6ea83fed bellard
FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1981 6ea83fed bellard
FOP_COND(s, seq, 1,                                                      float32_eq(FST0, FST1, &env->fp_status))
1982 6ea83fed bellard
FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1983 6ea83fed bellard
FOP_COND(s, lt,  1,                                                      float32_lt(FST0, FST1, &env->fp_status))
1984 6ea83fed bellard
FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1985 6ea83fed bellard
FOP_COND(s, le,  1,                                                      float32_le(FST0, FST1, &env->fp_status))
1986 6ea83fed bellard
FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1987 6ea83fed bellard
1988 6ea83fed bellard
void op_bc1f (void)
1989 6ea83fed bellard
{
1990 6ea83fed bellard
    T0 = ! IS_FP_COND_SET(env->fcr31);
1991 6ea83fed bellard
    DEBUG_FPU_STATE();
1992 6ea83fed bellard
    RETURN();
1993 6ea83fed bellard
}
1994 6ea83fed bellard
1995 6ea83fed bellard
void op_bc1t (void)
1996 6ea83fed bellard
{
1997 6ea83fed bellard
    T0 = IS_FP_COND_SET(env->fcr31);
1998 6ea83fed bellard
    DEBUG_FPU_STATE();
1999 6ea83fed bellard
    RETURN();
2000 6ea83fed bellard
}
2001 6ea83fed bellard
2002 6af0bf9c bellard
#if defined(MIPS_USES_R4K_TLB)
2003 6af0bf9c bellard
void op_tlbwi (void)
2004 6af0bf9c bellard
{
2005 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwi);
2006 6af0bf9c bellard
    RETURN();
2007 6af0bf9c bellard
}
2008 6af0bf9c bellard
2009 6af0bf9c bellard
void op_tlbwr (void)
2010 6af0bf9c bellard
{
2011 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwr);
2012 6af0bf9c bellard
    RETURN();
2013 6af0bf9c bellard
}
2014 6af0bf9c bellard
2015 6af0bf9c bellard
void op_tlbp (void)
2016 6af0bf9c bellard
{
2017 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbp);
2018 6af0bf9c bellard
    RETURN();
2019 6af0bf9c bellard
}
2020 6af0bf9c bellard
2021 6af0bf9c bellard
void op_tlbr (void)
2022 6af0bf9c bellard
{
2023 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbr);
2024 6af0bf9c bellard
    RETURN();
2025 6af0bf9c bellard
}
2026 6af0bf9c bellard
#endif
2027 6af0bf9c bellard
2028 6af0bf9c bellard
/* Specials */
2029 6f5b89a0 ths
#if defined (CONFIG_USER_ONLY)
2030 6f5b89a0 ths
void op_tls_value (void)
2031 6f5b89a0 ths
{
2032 6f5b89a0 ths
  T0 = env->tls_value;
2033 6f5b89a0 ths
}
2034 6f5b89a0 ths
#endif
2035 6f5b89a0 ths
2036 6af0bf9c bellard
void op_pmon (void)
2037 6af0bf9c bellard
{
2038 6af0bf9c bellard
    CALL_FROM_TB1(do_pmon, PARAM1);
2039 7a387fff ths
    RETURN();
2040 7a387fff ths
}
2041 7a387fff ths
2042 7a387fff ths
void op_di (void)
2043 7a387fff ths
{
2044 7a387fff ths
    T0 = env->CP0_Status;
2045 4de9b249 ths
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2046 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2047 7a387fff ths
    RETURN();
2048 7a387fff ths
}
2049 7a387fff ths
2050 7a387fff ths
void op_ei (void)
2051 7a387fff ths
{
2052 7a387fff ths
    T0 = env->CP0_Status;
2053 4de9b249 ths
    env->CP0_Status = T0 | (1 << CP0St_IE);
2054 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2055 7a387fff ths
    RETURN();
2056 6af0bf9c bellard
}
2057 6af0bf9c bellard
2058 6af0bf9c bellard
void op_trap (void)
2059 6af0bf9c bellard
{
2060 6af0bf9c bellard
    if (T0) {
2061 4ad40f36 bellard
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
2062 6af0bf9c bellard
    }
2063 6af0bf9c bellard
    RETURN();
2064 6af0bf9c bellard
}
2065 6af0bf9c bellard
2066 4ad40f36 bellard
void op_debug (void)
2067 4ad40f36 bellard
{
2068 7a387fff ths
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2069 7a387fff ths
    RETURN();
2070 4ad40f36 bellard
}
2071 4ad40f36 bellard
2072 6af0bf9c bellard
void op_set_lladdr (void)
2073 6af0bf9c bellard
{
2074 6af0bf9c bellard
    env->CP0_LLAddr = T2;
2075 7a387fff ths
    RETURN();
2076 6af0bf9c bellard
}
2077 6af0bf9c bellard
2078 6af0bf9c bellard
void debug_eret (void);
2079 6af0bf9c bellard
void op_eret (void)
2080 6af0bf9c bellard
{
2081 6af0bf9c bellard
    CALL_FROM_TB0(debug_eret);
2082 51e11d9e bellard
    if (env->hflags & MIPS_HFLAG_ERL) {
2083 6af0bf9c bellard
        env->PC = env->CP0_ErrorEPC;
2084 51e11d9e bellard
        env->hflags &= ~MIPS_HFLAG_ERL;
2085 3e382bc8 bellard
        env->CP0_Status &= ~(1 << CP0St_ERL);
2086 51e11d9e bellard
    } else {
2087 6af0bf9c bellard
        env->PC = env->CP0_EPC;
2088 51e11d9e bellard
        env->hflags &= ~MIPS_HFLAG_EXL;
2089 3e382bc8 bellard
        env->CP0_Status &= ~(1 << CP0St_EXL);
2090 51e11d9e bellard
    }
2091 6af0bf9c bellard
    env->CP0_LLAddr = 1;
2092 7a387fff ths
    RETURN();
2093 6af0bf9c bellard
}
2094 6af0bf9c bellard
2095 6af0bf9c bellard
void op_deret (void)
2096 6af0bf9c bellard
{
2097 6af0bf9c bellard
    CALL_FROM_TB0(debug_eret);
2098 6af0bf9c bellard
    env->PC = env->CP0_DEPC;
2099 7a387fff ths
    RETURN();
2100 7a387fff ths
}
2101 7a387fff ths
2102 7a387fff ths
void op_rdhwr_cpunum(void)
2103 7a387fff ths
{
2104 7a387fff ths
    if (env->CP0_HWREna & (1 << 0))
2105 7a387fff ths
       T0 = env->CP0_EBase & 0x2ff;
2106 7a387fff ths
    else
2107 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2108 7a387fff ths
    RETURN();
2109 7a387fff ths
}
2110 7a387fff ths
2111 7a387fff ths
void op_rdhwr_synci_step(void)
2112 7a387fff ths
{
2113 7a387fff ths
    if (env->CP0_HWREna & (1 << 1))
2114 7a387fff ths
       T0 = env->SYNCI_Step;
2115 7a387fff ths
    else
2116 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2117 7a387fff ths
    RETURN();
2118 7a387fff ths
}
2119 7a387fff ths
2120 7a387fff ths
void op_rdhwr_cc(void)
2121 7a387fff ths
{
2122 7a387fff ths
    if (env->CP0_HWREna & (1 << 2))
2123 7a387fff ths
       T0 = env->CP0_Count;
2124 7a387fff ths
    else
2125 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2126 7a387fff ths
    RETURN();
2127 7a387fff ths
}
2128 7a387fff ths
2129 7a387fff ths
void op_rdhwr_ccres(void)
2130 7a387fff ths
{
2131 7a387fff ths
    if (env->CP0_HWREna & (1 << 3))
2132 7a387fff ths
       T0 = env->CCRes;
2133 7a387fff ths
    else
2134 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2135 7a387fff ths
    RETURN();
2136 6af0bf9c bellard
}
2137 6af0bf9c bellard
2138 6af0bf9c bellard
void op_save_state (void)
2139 6af0bf9c bellard
{
2140 6af0bf9c bellard
    env->hflags = PARAM1;
2141 6af0bf9c bellard
    RETURN();
2142 6af0bf9c bellard
}
2143 6af0bf9c bellard
2144 6af0bf9c bellard
void op_save_pc (void)
2145 6af0bf9c bellard
{
2146 6af0bf9c bellard
    env->PC = PARAM1;
2147 6af0bf9c bellard
    RETURN();
2148 6af0bf9c bellard
}
2149 6af0bf9c bellard
2150 6af0bf9c bellard
void op_raise_exception (void)
2151 6af0bf9c bellard
{
2152 6af0bf9c bellard
    CALL_FROM_TB1(do_raise_exception, PARAM1);
2153 6af0bf9c bellard
    RETURN();
2154 6af0bf9c bellard
}
2155 6af0bf9c bellard
2156 6af0bf9c bellard
void op_raise_exception_err (void)
2157 6af0bf9c bellard
{
2158 6af0bf9c bellard
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2159 6af0bf9c bellard
    RETURN();
2160 6af0bf9c bellard
}
2161 6af0bf9c bellard
2162 6af0bf9c bellard
void op_exit_tb (void)
2163 6af0bf9c bellard
{
2164 6af0bf9c bellard
    EXIT_TB();
2165 7a387fff ths
    RETURN();
2166 6af0bf9c bellard
}
2167 6af0bf9c bellard
2168 4ad40f36 bellard
void op_wait (void)
2169 4ad40f36 bellard
{
2170 4ad40f36 bellard
    env->halted = 1;
2171 4ad40f36 bellard
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2172 7a387fff ths
    RETURN();
2173 7a387fff ths
}
2174 7a387fff ths
2175 7a387fff ths
/* Bitfield operations. */
2176 7a387fff ths
void op_ext(void)
2177 7a387fff ths
{
2178 7a387fff ths
    unsigned int pos = PARAM1;
2179 7a387fff ths
    unsigned int size = PARAM2;
2180 7a387fff ths
2181 c570fd16 ths
    T0 = ((uint32_t)T1 >> pos) & ((1 << size) - 1);
2182 7a387fff ths
    RETURN();
2183 7a387fff ths
}
2184 7a387fff ths
2185 7a387fff ths
void op_ins(void)
2186 7a387fff ths
{
2187 7a387fff ths
    unsigned int pos = PARAM1;
2188 7a387fff ths
    unsigned int size = PARAM2;
2189 7a387fff ths
    target_ulong mask = ((1 << size) - 1) << pos;
2190 7a387fff ths
2191 c570fd16 ths
    T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask);
2192 7a387fff ths
    RETURN();
2193 7a387fff ths
}
2194 7a387fff ths
2195 7a387fff ths
void op_wsbh(void)
2196 7a387fff ths
{
2197 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2198 7a387fff ths
    RETURN();
2199 7a387fff ths
}
2200 7a387fff ths
2201 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
2202 c570fd16 ths
void op_dext(void)
2203 c570fd16 ths
{
2204 c570fd16 ths
    unsigned int pos = PARAM1;
2205 c570fd16 ths
    unsigned int size = PARAM2;
2206 c570fd16 ths
2207 c570fd16 ths
    T0 = (T1 >> pos) & ((1 << size) - 1);
2208 c570fd16 ths
    RETURN();
2209 c570fd16 ths
}
2210 c570fd16 ths
2211 c570fd16 ths
void op_dins(void)
2212 c570fd16 ths
{
2213 c570fd16 ths
    unsigned int pos = PARAM1;
2214 c570fd16 ths
    unsigned int size = PARAM2;
2215 c570fd16 ths
    target_ulong mask = ((1 << size) - 1) << pos;
2216 c570fd16 ths
2217 c570fd16 ths
    T0 = (T2 & ~mask) | ((T1 << pos) & mask);
2218 c570fd16 ths
    RETURN();
2219 c570fd16 ths
}
2220 c570fd16 ths
2221 7a387fff ths
void op_dsbh(void)
2222 7a387fff ths
{
2223 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2224 7a387fff ths
    RETURN();
2225 7a387fff ths
}
2226 7a387fff ths
2227 7a387fff ths
void op_dshd(void)
2228 7a387fff ths
{
2229 7a387fff ths
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2230 7a387fff ths
    RETURN();
2231 7a387fff ths
}
2232 c570fd16 ths
#endif
2233 7a387fff ths
2234 7a387fff ths
void op_seb(void)
2235 7a387fff ths
{
2236 7a387fff ths
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2237 7a387fff ths
    RETURN();
2238 7a387fff ths
}
2239 7a387fff ths
2240 7a387fff ths
void op_seh(void)
2241 7a387fff ths
{
2242 7a387fff ths
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2243 7a387fff ths
    RETURN();
2244 4ad40f36 bellard
}