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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 85571bc7 | bellard | *
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4 | 85571bc7 | bellard | * Copyright (c) 2003-2004 Vassili Karpov (malc)
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5 | 85571bc7 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 16d17fdb | bellard | #include "vl.h" |
25 | 27503323 | bellard | |
26 | 85571bc7 | bellard | /* #define DEBUG_DMA */
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27 | 7ebb5e41 | bellard | |
28 | 85571bc7 | bellard | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
29 | 27503323 | bellard | #ifdef DEBUG_DMA
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30 | 27503323 | bellard | #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
31 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #else
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34 | 27503323 | bellard | #define lwarn(...)
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35 | 27503323 | bellard | #define linfo(...)
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36 | 27503323 | bellard | #define ldebug(...)
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37 | 27503323 | bellard | #endif
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38 | 27503323 | bellard | |
39 | 27503323 | bellard | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
40 | 27503323 | bellard | |
41 | 27503323 | bellard | struct dma_regs {
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42 | 27503323 | bellard | int now[2]; |
43 | 27503323 | bellard | uint16_t base[2];
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44 | 27503323 | bellard | uint8_t mode; |
45 | 27503323 | bellard | uint8_t page; |
46 | b0bda528 | bellard | uint8_t pageh; |
47 | 27503323 | bellard | uint8_t dack; |
48 | 27503323 | bellard | uint8_t eop; |
49 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
50 | 16f62432 | bellard | void *opaque;
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51 | 27503323 | bellard | }; |
52 | 27503323 | bellard | |
53 | 27503323 | bellard | #define ADDR 0 |
54 | 27503323 | bellard | #define COUNT 1 |
55 | 27503323 | bellard | |
56 | 27503323 | bellard | static struct dma_cont { |
57 | 27503323 | bellard | uint8_t status; |
58 | 27503323 | bellard | uint8_t command; |
59 | 27503323 | bellard | uint8_t mask; |
60 | 27503323 | bellard | uint8_t flip_flop; |
61 | 9eb153f1 | bellard | int dshift;
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62 | 27503323 | bellard | struct dma_regs regs[4]; |
63 | 27503323 | bellard | } dma_controllers[2];
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64 | 27503323 | bellard | |
65 | 27503323 | bellard | enum {
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66 | e875c40a | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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67 | e875c40a | bellard | CMD_FIXED_ADDRESS = 0x02,
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68 | e875c40a | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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69 | e875c40a | bellard | CMD_COMPRESSED_TIME = 0x08,
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70 | e875c40a | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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71 | e875c40a | bellard | CMD_EXTENDED_WRITE = 0x20,
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72 | e875c40a | bellard | CMD_LOW_DREQ = 0x40,
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73 | e875c40a | bellard | CMD_LOW_DACK = 0x80,
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74 | e875c40a | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
75 | e875c40a | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
76 | e875c40a | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
77 | 27503323 | bellard | |
78 | 27503323 | bellard | }; |
79 | 27503323 | bellard | |
80 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
81 | 9eb153f1 | bellard | |
82 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
83 | 27503323 | bellard | { |
84 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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85 | 27503323 | bellard | int ichan;
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86 | 27503323 | bellard | |
87 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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88 | 27503323 | bellard | if (-1 == ichan) { |
89 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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90 | 27503323 | bellard | return;
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91 | 27503323 | bellard | } |
92 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
93 | 9eb153f1 | bellard | } |
94 | 9eb153f1 | bellard | |
95 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
96 | 9eb153f1 | bellard | { |
97 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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98 | 9eb153f1 | bellard | int ichan;
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99 | 27503323 | bellard | |
100 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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101 | b0bda528 | bellard | if (-1 == ichan) { |
102 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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103 | b0bda528 | bellard | return;
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104 | b0bda528 | bellard | } |
105 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
106 | b0bda528 | bellard | } |
107 | 9eb153f1 | bellard | |
108 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
109 | b0bda528 | bellard | { |
110 | b0bda528 | bellard | struct dma_cont *d = opaque;
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111 | b0bda528 | bellard | int ichan;
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112 | b0bda528 | bellard | |
113 | b0bda528 | bellard | ichan = channels[nport & 7];
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114 | 9eb153f1 | bellard | if (-1 == ichan) { |
115 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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116 | 9eb153f1 | bellard | return 0; |
117 | 9eb153f1 | bellard | } |
118 | 9eb153f1 | bellard | return d->regs[ichan].page;
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119 | 27503323 | bellard | } |
120 | 27503323 | bellard | |
121 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
122 | b0bda528 | bellard | { |
123 | b0bda528 | bellard | struct dma_cont *d = opaque;
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124 | b0bda528 | bellard | int ichan;
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125 | b0bda528 | bellard | |
126 | b0bda528 | bellard | ichan = channels[nport & 7];
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127 | b0bda528 | bellard | if (-1 == ichan) { |
128 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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129 | b0bda528 | bellard | return 0; |
130 | b0bda528 | bellard | } |
131 | b0bda528 | bellard | return d->regs[ichan].pageh;
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132 | b0bda528 | bellard | } |
133 | b0bda528 | bellard | |
134 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
135 | 27503323 | bellard | { |
136 | 27503323 | bellard | struct dma_regs *r;
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137 | 27503323 | bellard | |
138 | 9eb153f1 | bellard | r = d->regs + ichan; |
139 | 85571bc7 | bellard | r->now[ADDR] = r->base[ADDR] << d->dshift; |
140 | 27503323 | bellard | r->now[COUNT] = 0;
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141 | 27503323 | bellard | } |
142 | 27503323 | bellard | |
143 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
144 | 27503323 | bellard | { |
145 | 27503323 | bellard | int ff;
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146 | 27503323 | bellard | |
147 | 9eb153f1 | bellard | ff = d->flip_flop; |
148 | 9eb153f1 | bellard | d->flip_flop = !ff; |
149 | 27503323 | bellard | return ff;
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150 | 27503323 | bellard | } |
151 | 27503323 | bellard | |
152 | 7d977de7 | bellard | static uint32_t read_chan (void *opaque, uint32_t nport) |
153 | 27503323 | bellard | { |
154 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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155 | 85571bc7 | bellard | int ichan, nreg, iport, ff, val, dir;
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156 | 27503323 | bellard | struct dma_regs *r;
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157 | 27503323 | bellard | |
158 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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159 | 9eb153f1 | bellard | ichan = iport >> 1;
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160 | 9eb153f1 | bellard | nreg = iport & 1;
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161 | 9eb153f1 | bellard | r = d->regs + ichan; |
162 | 27503323 | bellard | |
163 | 85571bc7 | bellard | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
164 | 9eb153f1 | bellard | ff = getff (d); |
165 | 27503323 | bellard | if (nreg)
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166 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
167 | 27503323 | bellard | else
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168 | 85571bc7 | bellard | val = r->now[ADDR] + r->now[COUNT] * dir; |
169 | 27503323 | bellard | |
170 | 85571bc7 | bellard | ldebug ("read_chan %#x -> %d\n", iport, val);
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171 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
172 | 27503323 | bellard | } |
173 | 27503323 | bellard | |
174 | 7d977de7 | bellard | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
175 | 27503323 | bellard | { |
176 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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177 | 9eb153f1 | bellard | int iport, ichan, nreg;
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178 | 27503323 | bellard | struct dma_regs *r;
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179 | 27503323 | bellard | |
180 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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181 | 9eb153f1 | bellard | ichan = iport >> 1;
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182 | 9eb153f1 | bellard | nreg = iport & 1;
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183 | 9eb153f1 | bellard | r = d->regs + ichan; |
184 | 9eb153f1 | bellard | if (getff (d)) {
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185 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
186 | 9eb153f1 | bellard | init_chan (d, ichan); |
187 | 3504fe17 | bellard | } else {
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188 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
189 | 27503323 | bellard | } |
190 | 27503323 | bellard | } |
191 | 27503323 | bellard | |
192 | 7d977de7 | bellard | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
193 | 27503323 | bellard | { |
194 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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195 | 85571bc7 | bellard | int iport, ichan = 0; |
196 | 27503323 | bellard | |
197 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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198 | 27503323 | bellard | switch (iport) {
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199 | 85571bc7 | bellard | case 0x08: /* command */ |
200 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
201 | 85571bc7 | bellard | dolog ("command %#x not supported\n", data);
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202 | df475d18 | bellard | return;
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203 | 27503323 | bellard | } |
204 | 27503323 | bellard | d->command = data; |
205 | 27503323 | bellard | break;
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206 | 27503323 | bellard | |
207 | 85571bc7 | bellard | case 0x09: |
208 | 27503323 | bellard | ichan = data & 3;
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209 | 27503323 | bellard | if (data & 4) { |
210 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
211 | 27503323 | bellard | } |
212 | 27503323 | bellard | else {
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213 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
214 | 27503323 | bellard | } |
215 | 27503323 | bellard | d->status &= ~(1 << ichan);
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216 | 27503323 | bellard | break;
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217 | 27503323 | bellard | |
218 | 85571bc7 | bellard | case 0x0a: /* single mask */ |
219 | 27503323 | bellard | if (data & 4) |
220 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
221 | 27503323 | bellard | else
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222 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
223 | 27503323 | bellard | break;
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224 | 27503323 | bellard | |
225 | 85571bc7 | bellard | case 0x0b: /* mode */ |
226 | 27503323 | bellard | { |
227 | 16d17fdb | bellard | ichan = data & 3;
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228 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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229 | 85571bc7 | bellard | { |
230 | 85571bc7 | bellard | int op, ai, dir, opmode;
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231 | e875c40a | bellard | op = (data >> 2) & 3; |
232 | e875c40a | bellard | ai = (data >> 4) & 1; |
233 | e875c40a | bellard | dir = (data >> 5) & 1; |
234 | e875c40a | bellard | opmode = (data >> 6) & 3; |
235 | 27503323 | bellard | |
236 | e875c40a | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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237 | e875c40a | bellard | ichan, op, ai, dir, opmode); |
238 | 85571bc7 | bellard | } |
239 | 27503323 | bellard | #endif
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240 | 27503323 | bellard | d->regs[ichan].mode = data; |
241 | 27503323 | bellard | break;
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242 | 27503323 | bellard | } |
243 | 27503323 | bellard | |
244 | 85571bc7 | bellard | case 0x0c: /* clear flip flop */ |
245 | 27503323 | bellard | d->flip_flop = 0;
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246 | 27503323 | bellard | break;
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247 | 27503323 | bellard | |
248 | 85571bc7 | bellard | case 0x0d: /* reset */ |
249 | 27503323 | bellard | d->flip_flop = 0;
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250 | 27503323 | bellard | d->mask = ~0;
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251 | 27503323 | bellard | d->status = 0;
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252 | 27503323 | bellard | d->command = 0;
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253 | 27503323 | bellard | break;
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254 | 27503323 | bellard | |
255 | 85571bc7 | bellard | case 0x0e: /* clear mask for all channels */ |
256 | 27503323 | bellard | d->mask = 0;
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257 | 27503323 | bellard | break;
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258 | 27503323 | bellard | |
259 | 85571bc7 | bellard | case 0x0f: /* write mask for all channels */ |
260 | 27503323 | bellard | d->mask = data; |
261 | 27503323 | bellard | break;
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262 | 27503323 | bellard | |
263 | 27503323 | bellard | default:
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264 | 85571bc7 | bellard | dolog ("unknown iport %#x\n", iport);
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265 | df475d18 | bellard | break;
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266 | 27503323 | bellard | } |
267 | 27503323 | bellard | |
268 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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269 | 27503323 | bellard | if (0xc != iport) { |
270 | 85571bc7 | bellard | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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271 | 9eb153f1 | bellard | nport, ichan, data); |
272 | 27503323 | bellard | } |
273 | 27503323 | bellard | #endif
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274 | 27503323 | bellard | } |
275 | 27503323 | bellard | |
276 | 9eb153f1 | bellard | static uint32_t read_cont (void *opaque, uint32_t nport) |
277 | 9eb153f1 | bellard | { |
278 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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279 | 9eb153f1 | bellard | int iport, val;
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280 | 85571bc7 | bellard | |
281 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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282 | 9eb153f1 | bellard | switch (iport) {
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283 | 85571bc7 | bellard | case 0x08: /* status */ |
284 | 9eb153f1 | bellard | val = d->status; |
285 | 9eb153f1 | bellard | d->status &= 0xf0;
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286 | 9eb153f1 | bellard | break;
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287 | 85571bc7 | bellard | case 0x0f: /* mask */ |
288 | 9eb153f1 | bellard | val = d->mask; |
289 | 9eb153f1 | bellard | break;
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290 | 9eb153f1 | bellard | default:
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291 | 9eb153f1 | bellard | val = 0;
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292 | 9eb153f1 | bellard | break;
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293 | 9eb153f1 | bellard | } |
294 | 85571bc7 | bellard | |
295 | 85571bc7 | bellard | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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296 | 9eb153f1 | bellard | return val;
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297 | 9eb153f1 | bellard | } |
298 | 9eb153f1 | bellard | |
299 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
300 | 27503323 | bellard | { |
301 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
302 | 27503323 | bellard | } |
303 | 27503323 | bellard | |
304 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
305 | 27503323 | bellard | { |
306 | 27503323 | bellard | int ncont, ichan;
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307 | 27503323 | bellard | |
308 | 27503323 | bellard | ncont = nchan > 3;
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309 | 27503323 | bellard | ichan = nchan & 3;
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310 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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311 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
312 | 27503323 | bellard | } |
313 | 27503323 | bellard | |
314 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
315 | 27503323 | bellard | { |
316 | 27503323 | bellard | int ncont, ichan;
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317 | 27503323 | bellard | |
318 | 27503323 | bellard | ncont = nchan > 3;
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319 | 27503323 | bellard | ichan = nchan & 3;
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320 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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321 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
322 | 27503323 | bellard | } |
323 | 27503323 | bellard | |
324 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
325 | 27503323 | bellard | { |
326 | 27503323 | bellard | int n;
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327 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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328 | 85571bc7 | bellard | #ifdef DEBUG_DMA
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329 | 85571bc7 | bellard | int dir, opmode;
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330 | 27503323 | bellard | |
331 | 85571bc7 | bellard | dir = (r->mode >> 5) & 1; |
332 | 85571bc7 | bellard | opmode = (r->mode >> 6) & 3; |
333 | 27503323 | bellard | |
334 | 85571bc7 | bellard | if (dir) {
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335 | 85571bc7 | bellard | dolog ("DMA in address decrement mode\n");
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336 | 85571bc7 | bellard | } |
337 | 85571bc7 | bellard | if (opmode != 1) { |
338 | 85571bc7 | bellard | dolog ("DMA not in single mode select %#x\n", opmode);
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339 | 85571bc7 | bellard | } |
340 | 85571bc7 | bellard | #endif
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341 | 27503323 | bellard | |
342 | 85571bc7 | bellard | r = dma_controllers[ncont].regs + ichan; |
343 | 85571bc7 | bellard | n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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344 | 85571bc7 | bellard | r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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345 | 85571bc7 | bellard | r->now[COUNT] = n; |
346 | 85571bc7 | bellard | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
347 | 27503323 | bellard | } |
348 | 27503323 | bellard | |
349 | 27503323 | bellard | void DMA_run (void) |
350 | 27503323 | bellard | { |
351 | 27503323 | bellard | struct dma_cont *d;
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352 | 27503323 | bellard | int icont, ichan;
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353 | 27503323 | bellard | |
354 | 27503323 | bellard | d = dma_controllers; |
355 | 27503323 | bellard | |
356 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
357 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
358 | 27503323 | bellard | int mask;
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359 | 27503323 | bellard | |
360 | 27503323 | bellard | mask = 1 << ichan;
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361 | 27503323 | bellard | |
362 | 27503323 | bellard | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) |
363 | 27503323 | bellard | channel_run (icont, ichan); |
364 | 27503323 | bellard | } |
365 | 27503323 | bellard | } |
366 | 27503323 | bellard | } |
367 | 27503323 | bellard | |
368 | 27503323 | bellard | void DMA_register_channel (int nchan, |
369 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
370 | 16f62432 | bellard | void *opaque)
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371 | 27503323 | bellard | { |
372 | 27503323 | bellard | struct dma_regs *r;
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373 | 27503323 | bellard | int ichan, ncont;
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374 | 27503323 | bellard | |
375 | 27503323 | bellard | ncont = nchan > 3;
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376 | 27503323 | bellard | ichan = nchan & 3;
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377 | 27503323 | bellard | |
378 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
379 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
380 | 16f62432 | bellard | r->opaque = opaque; |
381 | 16f62432 | bellard | } |
382 | 16f62432 | bellard | |
383 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
384 | 85571bc7 | bellard | { |
385 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
386 | 85571bc7 | bellard | target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
387 | 85571bc7 | bellard | |
388 | 85571bc7 | bellard | if (r->mode & 0x20) { |
389 | 85571bc7 | bellard | int i;
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390 | 85571bc7 | bellard | uint8_t *p = buf; |
391 | 85571bc7 | bellard | |
392 | 85571bc7 | bellard | cpu_physical_memory_read (addr - pos - len, buf, len); |
393 | 85571bc7 | bellard | /* What about 16bit transfers? */
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394 | 85571bc7 | bellard | for (i = 0; i < len >> 1; i++) { |
395 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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396 | 85571bc7 | bellard | p[i] = b; |
397 | 85571bc7 | bellard | } |
398 | 85571bc7 | bellard | } |
399 | 85571bc7 | bellard | else
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400 | 85571bc7 | bellard | cpu_physical_memory_read (addr + pos, buf, len); |
401 | 85571bc7 | bellard | |
402 | 85571bc7 | bellard | return len;
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403 | 85571bc7 | bellard | } |
404 | 85571bc7 | bellard | |
405 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
406 | 85571bc7 | bellard | { |
407 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
408 | 85571bc7 | bellard | target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
409 | 85571bc7 | bellard | |
410 | 85571bc7 | bellard | if (r->mode & 0x20) { |
411 | 85571bc7 | bellard | int i;
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412 | 85571bc7 | bellard | uint8_t *p = buf; |
413 | 85571bc7 | bellard | |
414 | 85571bc7 | bellard | cpu_physical_memory_write (addr - pos - len, buf, len); |
415 | 85571bc7 | bellard | /* What about 16bit transfers? */
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416 | 85571bc7 | bellard | for (i = 0; i < len; i++) { |
417 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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418 | 85571bc7 | bellard | p[i] = b; |
419 | 85571bc7 | bellard | } |
420 | 85571bc7 | bellard | } |
421 | 85571bc7 | bellard | else
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422 | 85571bc7 | bellard | cpu_physical_memory_write (addr + pos, buf, len); |
423 | 85571bc7 | bellard | |
424 | 85571bc7 | bellard | return len;
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425 | 85571bc7 | bellard | } |
426 | 85571bc7 | bellard | |
427 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
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428 | 16f62432 | bellard | void DMA_schedule(int nchan) |
429 | 16f62432 | bellard | { |
430 | 16f62432 | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); |
431 | 27503323 | bellard | } |
432 | 27503323 | bellard | |
433 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
434 | d7d02e3c | bellard | { |
435 | d7d02e3c | bellard | struct dma_cont *d = opaque;
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436 | d7d02e3c | bellard | write_cont (d, (0x0d << d->dshift), 0); |
437 | d7d02e3c | bellard | } |
438 | d7d02e3c | bellard | |
439 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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440 | 85571bc7 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
441 | b0bda528 | bellard | int page_base, int pageh_base) |
442 | 27503323 | bellard | { |
443 | 9eb153f1 | bellard | const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
444 | 27503323 | bellard | int i;
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445 | 27503323 | bellard | |
446 | 9eb153f1 | bellard | d->dshift = dshift; |
447 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
448 | 9eb153f1 | bellard | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
449 | 9eb153f1 | bellard | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
450 | 27503323 | bellard | } |
451 | 27503323 | bellard | for (i = 0; i < LENOFA (page_port_list); i++) { |
452 | 85571bc7 | bellard | register_ioport_write (page_base + page_port_list[i], 1, 1, |
453 | 9eb153f1 | bellard | write_page, d); |
454 | 85571bc7 | bellard | register_ioport_read (page_base + page_port_list[i], 1, 1, |
455 | 9eb153f1 | bellard | read_page, d); |
456 | b0bda528 | bellard | if (pageh_base >= 0) { |
457 | 85571bc7 | bellard | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
458 | b0bda528 | bellard | write_pageh, d); |
459 | 85571bc7 | bellard | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
460 | b0bda528 | bellard | read_pageh, d); |
461 | b0bda528 | bellard | } |
462 | 27503323 | bellard | } |
463 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
464 | 85571bc7 | bellard | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
465 | 9eb153f1 | bellard | write_cont, d); |
466 | 85571bc7 | bellard | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
467 | 9eb153f1 | bellard | read_cont, d); |
468 | 27503323 | bellard | } |
469 | d7d02e3c | bellard | qemu_register_reset(dma_reset, d); |
470 | d7d02e3c | bellard | dma_reset(d); |
471 | 9eb153f1 | bellard | } |
472 | 27503323 | bellard | |
473 | 85571bc7 | bellard | static void dma_save (QEMUFile *f, void *opaque) |
474 | 85571bc7 | bellard | { |
475 | 85571bc7 | bellard | struct dma_cont *d = opaque;
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476 | 85571bc7 | bellard | int i;
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477 | 85571bc7 | bellard | |
478 | 85571bc7 | bellard | /* qemu_put_8s (f, &d->status); */
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479 | 85571bc7 | bellard | qemu_put_8s (f, &d->command); |
480 | 85571bc7 | bellard | qemu_put_8s (f, &d->mask); |
481 | 85571bc7 | bellard | qemu_put_8s (f, &d->flip_flop); |
482 | 85571bc7 | bellard | qemu_put_be32s (f, &d->dshift); |
483 | 85571bc7 | bellard | |
484 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
485 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
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486 | 85571bc7 | bellard | qemu_put_be32s (f, &r->now[0]);
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487 | 85571bc7 | bellard | qemu_put_be32s (f, &r->now[1]);
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488 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[0]);
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489 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[1]);
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490 | 85571bc7 | bellard | qemu_put_8s (f, &r->mode); |
491 | 85571bc7 | bellard | qemu_put_8s (f, &r->page); |
492 | 85571bc7 | bellard | qemu_put_8s (f, &r->pageh); |
493 | 85571bc7 | bellard | qemu_put_8s (f, &r->dack); |
494 | 85571bc7 | bellard | qemu_put_8s (f, &r->eop); |
495 | 85571bc7 | bellard | } |
496 | 85571bc7 | bellard | } |
497 | 85571bc7 | bellard | |
498 | 85571bc7 | bellard | static int dma_load (QEMUFile *f, void *opaque, int version_id) |
499 | 85571bc7 | bellard | { |
500 | 85571bc7 | bellard | struct dma_cont *d = opaque;
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501 | 85571bc7 | bellard | int i;
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502 | 85571bc7 | bellard | |
503 | 85571bc7 | bellard | if (version_id != 1) |
504 | 85571bc7 | bellard | return -EINVAL;
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505 | 85571bc7 | bellard | |
506 | 85571bc7 | bellard | /* qemu_get_8s (f, &d->status); */
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507 | 85571bc7 | bellard | qemu_get_8s (f, &d->command); |
508 | 85571bc7 | bellard | qemu_get_8s (f, &d->mask); |
509 | 85571bc7 | bellard | qemu_get_8s (f, &d->flip_flop); |
510 | 85571bc7 | bellard | qemu_get_be32s (f, &d->dshift); |
511 | 85571bc7 | bellard | |
512 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
513 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
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514 | 85571bc7 | bellard | qemu_get_be32s (f, &r->now[0]);
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515 | 85571bc7 | bellard | qemu_get_be32s (f, &r->now[1]);
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516 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[0]);
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517 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[1]);
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518 | 85571bc7 | bellard | qemu_get_8s (f, &r->mode); |
519 | 85571bc7 | bellard | qemu_get_8s (f, &r->page); |
520 | 85571bc7 | bellard | qemu_get_8s (f, &r->pageh); |
521 | 85571bc7 | bellard | qemu_get_8s (f, &r->dack); |
522 | 85571bc7 | bellard | qemu_get_8s (f, &r->eop); |
523 | 85571bc7 | bellard | } |
524 | 85571bc7 | bellard | return 0; |
525 | 85571bc7 | bellard | } |
526 | 85571bc7 | bellard | |
527 | b0bda528 | bellard | void DMA_init (int high_page_enable) |
528 | 9eb153f1 | bellard | { |
529 | 85571bc7 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
530 | b0bda528 | bellard | high_page_enable ? 0x480 : -1); |
531 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
532 | b0bda528 | bellard | high_page_enable ? 0x488 : -1); |
533 | 85571bc7 | bellard | register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); |
534 | 85571bc7 | bellard | register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); |
535 | 27503323 | bellard | } |