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/*
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* PowerPC emulation for qemu: main translation routines.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#include "helper.h" |
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#include "tcg-op.h" |
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#include "qemu-common.h" |
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#define CPU_SINGLE_STEP 0x1 |
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#define CPU_BRANCH_STEP 0x2 |
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#define GDBSTUB_SINGLE_STEP 0x4 |
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/* Include definitions for instructions classes and implementations flags */
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//#define DO_SINGLE_STEP
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//#define PPC_DEBUG_DISAS
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//#define DEBUG_MEMORY_ACCESSES
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//#define DO_PPC_STATISTICS
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//#define OPTIMIZE_FPRF_UPDATE
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/*****************************************************************************/
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/* Code translation helpers */
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/* global register indexes */
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static TCGv cpu_env;
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static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
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#if !defined(TARGET_PPC64)
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+ 10*4 + 22*5 /* SPE GPRh */ |
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#endif
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+ 10*4 + 22*5 /* FPR */ |
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+ 2*(10*6 + 22*7) /* AVRh, AVRl */ |
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+ 8*5 /* CRF */]; |
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static TCGv cpu_gpr[32]; |
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#if !defined(TARGET_PPC64)
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static TCGv cpu_gprh[32]; |
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#endif
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static TCGv cpu_fpr[32]; |
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static TCGv cpu_avrh[32], cpu_avrl[32]; |
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static TCGv cpu_crf[8]; |
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static TCGv cpu_nip;
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/* dyngen register indexes */
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static TCGv cpu_T[3]; |
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#if defined(TARGET_PPC64)
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#define cpu_T64 cpu_T
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#else
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static TCGv cpu_T64[3]; |
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#endif
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static TCGv cpu_FT[3]; |
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static TCGv cpu_AVRh[3], cpu_AVRl[3]; |
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#include "gen-icount.h" |
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void ppc_translate_init(void) |
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{ |
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int i;
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char* p;
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static int done_init = 0; |
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if (done_init)
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return;
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cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
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TCG_AREG0, offsetof(CPUState, t0), "T0");
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cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
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TCG_AREG0, offsetof(CPUState, t1), "T1");
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cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
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TCG_AREG0, offsetof(CPUState, t2), "T2");
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#else
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cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
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cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
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cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
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#endif
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#if !defined(TARGET_PPC64)
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cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
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TCG_AREG0, offsetof(CPUState, t0_64), |
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"T0_64");
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cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
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TCG_AREG0, offsetof(CPUState, t1_64), |
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"T1_64");
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cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
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TCG_AREG0, offsetof(CPUState, t2_64), |
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"T2_64");
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#endif
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cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, ft0), "FT0");
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cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, ft1), "FT1");
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cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, ft2), "FT2");
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cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, avr0.u64[0]), "AVR0H"); |
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cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, avr0.u64[1]), "AVR0L"); |
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cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, avr1.u64[0]), "AVR1H"); |
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cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, avr1.u64[1]), "AVR1L"); |
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cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, avr2.u64[0]), "AVR2H"); |
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cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, avr2.u64[1]), "AVR2L"); |
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p = cpu_reg_names; |
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for (i = 0; i < 8; i++) { |
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sprintf(p, "crf%d", i);
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cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
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offsetof(CPUState, crf[i]), p); |
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p += 5;
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} |
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for (i = 0; i < 32; i++) { |
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sprintf(p, "r%d", i);
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cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
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offsetof(CPUState, gpr[i]), p); |
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p += (i < 10) ? 3 : 4; |
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#if !defined(TARGET_PPC64)
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sprintf(p, "r%dH", i);
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cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
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offsetof(CPUState, gprh[i]), p); |
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p += (i < 10) ? 4 : 5; |
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#endif
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sprintf(p, "fp%d", i);
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cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, fpr[i]), p); |
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p += (i < 10) ? 4 : 5; |
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sprintf(p, "avr%dH", i);
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cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, avr[i].u64[0]), p);
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p += (i < 10) ? 6 : 7; |
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sprintf(p, "avr%dL", i);
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cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, avr[i].u64[1]), p);
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p += (i < 10) ? 6 : 7; |
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} |
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cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
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offsetof(CPUState, nip), "nip");
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/* register helpers */
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#undef DEF_HELPER
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#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
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#include "helper.h" |
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done_init = 1;
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} |
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#if defined(OPTIMIZE_FPRF_UPDATE)
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static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
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static uint16_t **gen_fprf_ptr;
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#endif
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/* internal defines */
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typedef struct DisasContext { |
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struct TranslationBlock *tb;
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target_ulong nip; |
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uint32_t opcode; |
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uint32_t exception; |
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/* Routine used to access memory */
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int mem_idx;
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/* Translation flags */
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#if !defined(CONFIG_USER_ONLY)
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int supervisor;
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#endif
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#if defined(TARGET_PPC64)
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int sf_mode;
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#endif
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int fpu_enabled;
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int altivec_enabled;
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int spe_enabled;
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ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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int singlestep_enabled;
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int dcache_line_size;
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} DisasContext; |
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struct opc_handler_t {
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/* invalid bits */
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uint32_t inval; |
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/* instruction type */
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uint64_t type; |
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/* handler */
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void (*handler)(DisasContext *ctx);
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#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
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const unsigned char *oname; |
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#endif
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#if defined(DO_PPC_STATISTICS)
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uint64_t count; |
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#endif
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}; |
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static always_inline void gen_set_Rc0 (DisasContext *ctx) |
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{ |
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#if defined(TARGET_PPC64)
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if (ctx->sf_mode)
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gen_op_cmpi_64(0);
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else
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#endif
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gen_op_cmpi(0);
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gen_op_set_Rc0(); |
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} |
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static always_inline void gen_reset_fpstatus (void) |
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{ |
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#ifdef CONFIG_SOFTFLOAT
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gen_op_reset_fpstatus(); |
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#endif
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} |
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static always_inline void gen_compute_fprf (int set_fprf, int set_rc) |
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{ |
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if (set_fprf != 0) { |
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/* This case might be optimized later */
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#if defined(OPTIMIZE_FPRF_UPDATE)
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*gen_fprf_ptr++ = gen_opc_ptr; |
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#endif
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gen_op_compute_fprf(1);
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if (unlikely(set_rc))
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tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf); |
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gen_op_float_check_status(); |
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} else if (unlikely(set_rc)) { |
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/* We always need to compute fpcc */
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gen_op_compute_fprf(0);
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tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf); |
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if (set_fprf)
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gen_op_float_check_status(); |
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} |
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} |
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static always_inline void gen_optimize_fprf (void) |
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{ |
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#if defined(OPTIMIZE_FPRF_UPDATE)
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uint16_t **ptr; |
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for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++) |
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*ptr = INDEX_op_nop1; |
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gen_fprf_ptr = gen_fprf_buf; |
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#endif
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} |
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static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) |
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{ |
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#if defined(TARGET_PPC64)
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if (ctx->sf_mode)
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tcg_gen_movi_tl(cpu_nip, nip); |
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else
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#endif
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tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
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} |
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#define GEN_EXCP(ctx, excp, error) \
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do { \
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if ((ctx)->exception == POWERPC_EXCP_NONE) { \
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gen_update_nip(ctx, (ctx)->nip); \ |
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} \ |
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gen_op_raise_exception_err((excp), (error)); \ |
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ctx->exception = (excp); \ |
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} while (0) |
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#define GEN_EXCP_INVAL(ctx) \
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GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
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POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL) |
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#define GEN_EXCP_PRIVOPC(ctx) \
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GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
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POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC) |
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#define GEN_EXCP_PRIVREG(ctx) \
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GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
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POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG) |
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#define GEN_EXCP_NO_FP(ctx) \
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GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
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#define GEN_EXCP_NO_AP(ctx) \
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GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
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#define GEN_EXCP_NO_VR(ctx) \
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GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
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/* Stop translation */
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static always_inline void GEN_STOP (DisasContext *ctx) |
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{ |
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gen_update_nip(ctx, ctx->nip); |
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ctx->exception = POWERPC_EXCP_STOP; |
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} |
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/* No need to update nip here, as execution flow will change */
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static always_inline void GEN_SYNC (DisasContext *ctx) |
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{ |
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ctx->exception = POWERPC_EXCP_SYNC; |
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} |
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#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
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static void gen_##name (DisasContext *ctx); \ |
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GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
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static void gen_##name (DisasContext *ctx) |
328 |
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#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
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static void gen_##name (DisasContext *ctx); \ |
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GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \ |
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static void gen_##name (DisasContext *ctx) |
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typedef struct opcode_t { |
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unsigned char opc1, opc2, opc3; |
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#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
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unsigned char pad[5]; |
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#else
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unsigned char pad[1]; |
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#endif
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opc_handler_t handler; |
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const unsigned char *oname; |
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} opcode_t; |
344 |
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/*****************************************************************************/
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/*** Instruction decoding ***/
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#define EXTRACT_HELPER(name, shift, nb) \
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static always_inline uint32_t name (uint32_t opcode) \
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{ \ |
350 |
return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
351 |
} |
352 |
|
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#define EXTRACT_SHELPER(name, shift, nb) \
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static always_inline int32_t name (uint32_t opcode) \
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{ \ |
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return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
357 |
} |
358 |
|
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/* Opcode part 1 */
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EXTRACT_HELPER(opc1, 26, 6); |
361 |
/* Opcode part 2 */
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EXTRACT_HELPER(opc2, 1, 5); |
363 |
/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5); |
365 |
/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1); |
367 |
/* Destination */
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368 |
EXTRACT_HELPER(rD, 21, 5); |
369 |
/* Source */
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EXTRACT_HELPER(rS, 21, 5); |
371 |
/* First operand */
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EXTRACT_HELPER(rA, 16, 5); |
373 |
/* Second operand */
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EXTRACT_HELPER(rB, 11, 5); |
375 |
/* Third operand */
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EXTRACT_HELPER(rC, 6, 5); |
377 |
/*** Get CRn ***/
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EXTRACT_HELPER(crfD, 23, 3); |
379 |
EXTRACT_HELPER(crfS, 18, 3); |
380 |
EXTRACT_HELPER(crbD, 21, 5); |
381 |
EXTRACT_HELPER(crbA, 16, 5); |
382 |
EXTRACT_HELPER(crbB, 11, 5); |
383 |
/* SPR / TBL */
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EXTRACT_HELPER(_SPR, 11, 10); |
385 |
static always_inline uint32_t SPR (uint32_t opcode)
|
386 |
{ |
387 |
uint32_t sprn = _SPR(opcode); |
388 |
|
389 |
return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
390 |
} |
391 |
/*** Get constants ***/
|
392 |
EXTRACT_HELPER(IMM, 12, 8); |
393 |
/* 16 bits signed immediate value */
|
394 |
EXTRACT_SHELPER(SIMM, 0, 16); |
395 |
/* 16 bits unsigned immediate value */
|
396 |
EXTRACT_HELPER(UIMM, 0, 16); |
397 |
/* Bit count */
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EXTRACT_HELPER(NB, 11, 5); |
399 |
/* Shift count */
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400 |
EXTRACT_HELPER(SH, 11, 5); |
401 |
/* Mask start */
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EXTRACT_HELPER(MB, 6, 5); |
403 |
/* Mask end */
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EXTRACT_HELPER(ME, 1, 5); |
405 |
/* Trap operand */
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406 |
EXTRACT_HELPER(TO, 21, 5); |
407 |
|
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EXTRACT_HELPER(CRM, 12, 8); |
409 |
EXTRACT_HELPER(FM, 17, 8); |
410 |
EXTRACT_HELPER(SR, 16, 4); |
411 |
EXTRACT_HELPER(FPIMM, 12, 4); |
412 |
|
413 |
/*** Jump target decoding ***/
|
414 |
/* Displacement */
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EXTRACT_SHELPER(d, 0, 16); |
416 |
/* Immediate address */
|
417 |
static always_inline target_ulong LI (uint32_t opcode)
|
418 |
{ |
419 |
return (opcode >> 0) & 0x03FFFFFC; |
420 |
} |
421 |
|
422 |
static always_inline uint32_t BD (uint32_t opcode)
|
423 |
{ |
424 |
return (opcode >> 0) & 0xFFFC; |
425 |
} |
426 |
|
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EXTRACT_HELPER(BO, 21, 5); |
428 |
EXTRACT_HELPER(BI, 16, 5); |
429 |
/* Absolute/relative address */
|
430 |
EXTRACT_HELPER(AA, 1, 1); |
431 |
/* Link */
|
432 |
EXTRACT_HELPER(LK, 0, 1); |
433 |
|
434 |
/* Create a mask between <start> and <end> bits */
|
435 |
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
|
436 |
{ |
437 |
target_ulong ret; |
438 |
|
439 |
#if defined(TARGET_PPC64)
|
440 |
if (likely(start == 0)) { |
441 |
ret = UINT64_MAX << (63 - end);
|
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} else if (likely(end == 63)) { |
443 |
ret = UINT64_MAX >> start; |
444 |
} |
445 |
#else
|
446 |
if (likely(start == 0)) { |
447 |
ret = UINT32_MAX << (31 - end);
|
448 |
} else if (likely(end == 31)) { |
449 |
ret = UINT32_MAX >> start; |
450 |
} |
451 |
#endif
|
452 |
else {
|
453 |
ret = (((target_ulong)(-1ULL)) >> (start)) ^
|
454 |
(((target_ulong)(-1ULL) >> (end)) >> 1); |
455 |
if (unlikely(start > end))
|
456 |
return ~ret;
|
457 |
} |
458 |
|
459 |
return ret;
|
460 |
} |
461 |
|
462 |
/*****************************************************************************/
|
463 |
/* PowerPC Instructions types definitions */
|
464 |
enum {
|
465 |
PPC_NONE = 0x0000000000000000ULL,
|
466 |
/* PowerPC base instructions set */
|
467 |
PPC_INSNS_BASE = 0x0000000000000001ULL,
|
468 |
/* integer operations instructions */
|
469 |
#define PPC_INTEGER PPC_INSNS_BASE
|
470 |
/* flow control instructions */
|
471 |
#define PPC_FLOW PPC_INSNS_BASE
|
472 |
/* virtual memory instructions */
|
473 |
#define PPC_MEM PPC_INSNS_BASE
|
474 |
/* ld/st with reservation instructions */
|
475 |
#define PPC_RES PPC_INSNS_BASE
|
476 |
/* spr/msr access instructions */
|
477 |
#define PPC_MISC PPC_INSNS_BASE
|
478 |
/* Deprecated instruction sets */
|
479 |
/* Original POWER instruction set */
|
480 |
PPC_POWER = 0x0000000000000002ULL,
|
481 |
/* POWER2 instruction set extension */
|
482 |
PPC_POWER2 = 0x0000000000000004ULL,
|
483 |
/* Power RTC support */
|
484 |
PPC_POWER_RTC = 0x0000000000000008ULL,
|
485 |
/* Power-to-PowerPC bridge (601) */
|
486 |
PPC_POWER_BR = 0x0000000000000010ULL,
|
487 |
/* 64 bits PowerPC instruction set */
|
488 |
PPC_64B = 0x0000000000000020ULL,
|
489 |
/* New 64 bits extensions (PowerPC 2.0x) */
|
490 |
PPC_64BX = 0x0000000000000040ULL,
|
491 |
/* 64 bits hypervisor extensions */
|
492 |
PPC_64H = 0x0000000000000080ULL,
|
493 |
/* New wait instruction (PowerPC 2.0x) */
|
494 |
PPC_WAIT = 0x0000000000000100ULL,
|
495 |
/* Time base mftb instruction */
|
496 |
PPC_MFTB = 0x0000000000000200ULL,
|
497 |
|
498 |
/* Fixed-point unit extensions */
|
499 |
/* PowerPC 602 specific */
|
500 |
PPC_602_SPEC = 0x0000000000000400ULL,
|
501 |
/* isel instruction */
|
502 |
PPC_ISEL = 0x0000000000000800ULL,
|
503 |
/* popcntb instruction */
|
504 |
PPC_POPCNTB = 0x0000000000001000ULL,
|
505 |
/* string load / store */
|
506 |
PPC_STRING = 0x0000000000002000ULL,
|
507 |
|
508 |
/* Floating-point unit extensions */
|
509 |
/* Optional floating point instructions */
|
510 |
PPC_FLOAT = 0x0000000000010000ULL,
|
511 |
/* New floating-point extensions (PowerPC 2.0x) */
|
512 |
PPC_FLOAT_EXT = 0x0000000000020000ULL,
|
513 |
PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
|
514 |
PPC_FLOAT_FRES = 0x0000000000080000ULL,
|
515 |
PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
|
516 |
PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
|
517 |
PPC_FLOAT_FSEL = 0x0000000000400000ULL,
|
518 |
PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
|
519 |
|
520 |
/* Vector/SIMD extensions */
|
521 |
/* Altivec support */
|
522 |
PPC_ALTIVEC = 0x0000000001000000ULL,
|
523 |
/* PowerPC 2.03 SPE extension */
|
524 |
PPC_SPE = 0x0000000002000000ULL,
|
525 |
/* PowerPC 2.03 SPE floating-point extension */
|
526 |
PPC_SPEFPU = 0x0000000004000000ULL,
|
527 |
|
528 |
/* Optional memory control instructions */
|
529 |
PPC_MEM_TLBIA = 0x0000000010000000ULL,
|
530 |
PPC_MEM_TLBIE = 0x0000000020000000ULL,
|
531 |
PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
|
532 |
/* sync instruction */
|
533 |
PPC_MEM_SYNC = 0x0000000080000000ULL,
|
534 |
/* eieio instruction */
|
535 |
PPC_MEM_EIEIO = 0x0000000100000000ULL,
|
536 |
|
537 |
/* Cache control instructions */
|
538 |
PPC_CACHE = 0x0000000200000000ULL,
|
539 |
/* icbi instruction */
|
540 |
PPC_CACHE_ICBI = 0x0000000400000000ULL,
|
541 |
/* dcbz instruction with fixed cache line size */
|
542 |
PPC_CACHE_DCBZ = 0x0000000800000000ULL,
|
543 |
/* dcbz instruction with tunable cache line size */
|
544 |
PPC_CACHE_DCBZT = 0x0000001000000000ULL,
|
545 |
/* dcba instruction */
|
546 |
PPC_CACHE_DCBA = 0x0000002000000000ULL,
|
547 |
/* Freescale cache locking instructions */
|
548 |
PPC_CACHE_LOCK = 0x0000004000000000ULL,
|
549 |
|
550 |
/* MMU related extensions */
|
551 |
/* external control instructions */
|
552 |
PPC_EXTERN = 0x0000010000000000ULL,
|
553 |
/* segment register access instructions */
|
554 |
PPC_SEGMENT = 0x0000020000000000ULL,
|
555 |
/* PowerPC 6xx TLB management instructions */
|
556 |
PPC_6xx_TLB = 0x0000040000000000ULL,
|
557 |
/* PowerPC 74xx TLB management instructions */
|
558 |
PPC_74xx_TLB = 0x0000080000000000ULL,
|
559 |
/* PowerPC 40x TLB management instructions */
|
560 |
PPC_40x_TLB = 0x0000100000000000ULL,
|
561 |
/* segment register access instructions for PowerPC 64 "bridge" */
|
562 |
PPC_SEGMENT_64B = 0x0000200000000000ULL,
|
563 |
/* SLB management */
|
564 |
PPC_SLBI = 0x0000400000000000ULL,
|
565 |
|
566 |
/* Embedded PowerPC dedicated instructions */
|
567 |
PPC_WRTEE = 0x0001000000000000ULL,
|
568 |
/* PowerPC 40x exception model */
|
569 |
PPC_40x_EXCP = 0x0002000000000000ULL,
|
570 |
/* PowerPC 405 Mac instructions */
|
571 |
PPC_405_MAC = 0x0004000000000000ULL,
|
572 |
/* PowerPC 440 specific instructions */
|
573 |
PPC_440_SPEC = 0x0008000000000000ULL,
|
574 |
/* BookE (embedded) PowerPC specification */
|
575 |
PPC_BOOKE = 0x0010000000000000ULL,
|
576 |
/* mfapidi instruction */
|
577 |
PPC_MFAPIDI = 0x0020000000000000ULL,
|
578 |
/* tlbiva instruction */
|
579 |
PPC_TLBIVA = 0x0040000000000000ULL,
|
580 |
/* tlbivax instruction */
|
581 |
PPC_TLBIVAX = 0x0080000000000000ULL,
|
582 |
/* PowerPC 4xx dedicated instructions */
|
583 |
PPC_4xx_COMMON = 0x0100000000000000ULL,
|
584 |
/* PowerPC 40x ibct instructions */
|
585 |
PPC_40x_ICBT = 0x0200000000000000ULL,
|
586 |
/* rfmci is not implemented in all BookE PowerPC */
|
587 |
PPC_RFMCI = 0x0400000000000000ULL,
|
588 |
/* rfdi instruction */
|
589 |
PPC_RFDI = 0x0800000000000000ULL,
|
590 |
/* DCR accesses */
|
591 |
PPC_DCR = 0x1000000000000000ULL,
|
592 |
/* DCR extended accesse */
|
593 |
PPC_DCRX = 0x2000000000000000ULL,
|
594 |
/* user-mode DCR access, implemented in PowerPC 460 */
|
595 |
PPC_DCRUX = 0x4000000000000000ULL,
|
596 |
}; |
597 |
|
598 |
/*****************************************************************************/
|
599 |
/* PowerPC instructions table */
|
600 |
#if HOST_LONG_BITS == 64 |
601 |
#define OPC_ALIGN 8 |
602 |
#else
|
603 |
#define OPC_ALIGN 4 |
604 |
#endif
|
605 |
#if defined(__APPLE__)
|
606 |
#define OPCODES_SECTION \
|
607 |
__attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
|
608 |
#else
|
609 |
#define OPCODES_SECTION \
|
610 |
__attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
|
611 |
#endif
|
612 |
|
613 |
#if defined(DO_PPC_STATISTICS)
|
614 |
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
615 |
OPCODES_SECTION opcode_t opc_##name = { \ |
616 |
.opc1 = op1, \ |
617 |
.opc2 = op2, \ |
618 |
.opc3 = op3, \ |
619 |
.pad = { 0, }, \
|
620 |
.handler = { \ |
621 |
.inval = invl, \ |
622 |
.type = _typ, \ |
623 |
.handler = &gen_##name, \ |
624 |
.oname = stringify(name), \ |
625 |
}, \ |
626 |
.oname = stringify(name), \ |
627 |
} |
628 |
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
629 |
OPCODES_SECTION opcode_t opc_##name = { \ |
630 |
.opc1 = op1, \ |
631 |
.opc2 = op2, \ |
632 |
.opc3 = op3, \ |
633 |
.pad = { 0, }, \
|
634 |
.handler = { \ |
635 |
.inval = invl, \ |
636 |
.type = _typ, \ |
637 |
.handler = &gen_##name, \ |
638 |
.oname = onam, \ |
639 |
}, \ |
640 |
.oname = onam, \ |
641 |
} |
642 |
#else
|
643 |
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
644 |
OPCODES_SECTION opcode_t opc_##name = { \ |
645 |
.opc1 = op1, \ |
646 |
.opc2 = op2, \ |
647 |
.opc3 = op3, \ |
648 |
.pad = { 0, }, \
|
649 |
.handler = { \ |
650 |
.inval = invl, \ |
651 |
.type = _typ, \ |
652 |
.handler = &gen_##name, \ |
653 |
}, \ |
654 |
.oname = stringify(name), \ |
655 |
} |
656 |
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
657 |
OPCODES_SECTION opcode_t opc_##name = { \ |
658 |
.opc1 = op1, \ |
659 |
.opc2 = op2, \ |
660 |
.opc3 = op3, \ |
661 |
.pad = { 0, }, \
|
662 |
.handler = { \ |
663 |
.inval = invl, \ |
664 |
.type = _typ, \ |
665 |
.handler = &gen_##name, \ |
666 |
}, \ |
667 |
.oname = onam, \ |
668 |
} |
669 |
#endif
|
670 |
|
671 |
#define GEN_OPCODE_MARK(name) \
|
672 |
OPCODES_SECTION opcode_t opc_##name = { \ |
673 |
.opc1 = 0xFF, \
|
674 |
.opc2 = 0xFF, \
|
675 |
.opc3 = 0xFF, \
|
676 |
.pad = { 0, }, \
|
677 |
.handler = { \ |
678 |
.inval = 0x00000000, \
|
679 |
.type = 0x00, \
|
680 |
.handler = NULL, \
|
681 |
}, \ |
682 |
.oname = stringify(name), \ |
683 |
} |
684 |
|
685 |
/* Start opcode list */
|
686 |
GEN_OPCODE_MARK(start); |
687 |
|
688 |
/* Invalid instruction */
|
689 |
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) |
690 |
{ |
691 |
GEN_EXCP_INVAL(ctx); |
692 |
} |
693 |
|
694 |
static opc_handler_t invalid_handler = {
|
695 |
.inval = 0xFFFFFFFF,
|
696 |
.type = PPC_NONE, |
697 |
.handler = gen_invalid, |
698 |
}; |
699 |
|
700 |
/*** Integer arithmetic ***/
|
701 |
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
|
702 |
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
703 |
{ \ |
704 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
705 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
706 |
gen_op_##name(); \ |
707 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
708 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
709 |
gen_set_Rc0(ctx); \ |
710 |
} |
711 |
|
712 |
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
|
713 |
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
714 |
{ \ |
715 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
716 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
717 |
gen_op_##name(); \ |
718 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
719 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
720 |
gen_set_Rc0(ctx); \ |
721 |
} |
722 |
|
723 |
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
|
724 |
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
725 |
{ \ |
726 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
727 |
gen_op_##name(); \ |
728 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
729 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
730 |
gen_set_Rc0(ctx); \ |
731 |
} |
732 |
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
|
733 |
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
734 |
{ \ |
735 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
736 |
gen_op_##name(); \ |
737 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
738 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
739 |
gen_set_Rc0(ctx); \ |
740 |
} |
741 |
|
742 |
/* Two operands arithmetic functions */
|
743 |
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
|
744 |
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
|
745 |
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type) |
746 |
|
747 |
/* Two operands arithmetic functions with no overflow allowed */
|
748 |
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
|
749 |
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
|
750 |
|
751 |
/* One operand arithmetic functions */
|
752 |
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
|
753 |
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ |
754 |
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type) |
755 |
|
756 |
#if defined(TARGET_PPC64)
|
757 |
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
|
758 |
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
759 |
{ \ |
760 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
761 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
762 |
if (ctx->sf_mode) \
|
763 |
gen_op_##name##_64(); \ |
764 |
else \
|
765 |
gen_op_##name(); \ |
766 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
767 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
768 |
gen_set_Rc0(ctx); \ |
769 |
} |
770 |
|
771 |
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
|
772 |
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
773 |
{ \ |
774 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
775 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
776 |
if (ctx->sf_mode) \
|
777 |
gen_op_##name##_64(); \ |
778 |
else \
|
779 |
gen_op_##name(); \ |
780 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
781 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
782 |
gen_set_Rc0(ctx); \ |
783 |
} |
784 |
|
785 |
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
|
786 |
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
787 |
{ \ |
788 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
789 |
if (ctx->sf_mode) \
|
790 |
gen_op_##name##_64(); \ |
791 |
else \
|
792 |
gen_op_##name(); \ |
793 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
794 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
795 |
gen_set_Rc0(ctx); \ |
796 |
} |
797 |
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
|
798 |
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
799 |
{ \ |
800 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
801 |
if (ctx->sf_mode) \
|
802 |
gen_op_##name##_64(); \ |
803 |
else \
|
804 |
gen_op_##name(); \ |
805 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
806 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
807 |
gen_set_Rc0(ctx); \ |
808 |
} |
809 |
|
810 |
/* Two operands arithmetic functions */
|
811 |
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
|
812 |
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
|
813 |
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type) |
814 |
|
815 |
/* Two operands arithmetic functions with no overflow allowed */
|
816 |
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
|
817 |
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
|
818 |
|
819 |
/* One operand arithmetic functions */
|
820 |
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
|
821 |
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ |
822 |
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) |
823 |
#else
|
824 |
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
|
825 |
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
|
826 |
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
|
827 |
#endif
|
828 |
|
829 |
/* add add. addo addo. */
|
830 |
static always_inline void gen_op_add (void) |
831 |
{ |
832 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
833 |
} |
834 |
static always_inline void gen_op_addo (void) |
835 |
{ |
836 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
837 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
838 |
gen_op_check_addo(); |
839 |
} |
840 |
#if defined(TARGET_PPC64)
|
841 |
#define gen_op_add_64 gen_op_add
|
842 |
static always_inline void gen_op_addo_64 (void) |
843 |
{ |
844 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
845 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
846 |
gen_op_check_addo_64(); |
847 |
} |
848 |
#endif
|
849 |
GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); |
850 |
/* addc addc. addco addco. */
|
851 |
static always_inline void gen_op_addc (void) |
852 |
{ |
853 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
854 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
855 |
gen_op_check_addc(); |
856 |
} |
857 |
static always_inline void gen_op_addco (void) |
858 |
{ |
859 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
860 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
861 |
gen_op_check_addc(); |
862 |
gen_op_check_addo(); |
863 |
} |
864 |
#if defined(TARGET_PPC64)
|
865 |
static always_inline void gen_op_addc_64 (void) |
866 |
{ |
867 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
868 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
869 |
gen_op_check_addc_64(); |
870 |
} |
871 |
static always_inline void gen_op_addco_64 (void) |
872 |
{ |
873 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
874 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
875 |
gen_op_check_addc_64(); |
876 |
gen_op_check_addo_64(); |
877 |
} |
878 |
#endif
|
879 |
GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER); |
880 |
/* adde adde. addeo addeo. */
|
881 |
static always_inline void gen_op_addeo (void) |
882 |
{ |
883 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
884 |
gen_op_adde(); |
885 |
gen_op_check_addo(); |
886 |
} |
887 |
#if defined(TARGET_PPC64)
|
888 |
static always_inline void gen_op_addeo_64 (void) |
889 |
{ |
890 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
891 |
gen_op_adde_64(); |
892 |
gen_op_check_addo_64(); |
893 |
} |
894 |
#endif
|
895 |
GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER); |
896 |
/* addme addme. addmeo addmeo. */
|
897 |
static always_inline void gen_op_addme (void) |
898 |
{ |
899 |
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
900 |
gen_op_add_me(); |
901 |
} |
902 |
#if defined(TARGET_PPC64)
|
903 |
static always_inline void gen_op_addme_64 (void) |
904 |
{ |
905 |
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
906 |
gen_op_add_me_64(); |
907 |
} |
908 |
#endif
|
909 |
GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER); |
910 |
/* addze addze. addzeo addzeo. */
|
911 |
static always_inline void gen_op_addze (void) |
912 |
{ |
913 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
914 |
gen_op_add_ze(); |
915 |
gen_op_check_addc(); |
916 |
} |
917 |
static always_inline void gen_op_addzeo (void) |
918 |
{ |
919 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
920 |
gen_op_add_ze(); |
921 |
gen_op_check_addc(); |
922 |
gen_op_check_addo(); |
923 |
} |
924 |
#if defined(TARGET_PPC64)
|
925 |
static always_inline void gen_op_addze_64 (void) |
926 |
{ |
927 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
928 |
gen_op_add_ze(); |
929 |
gen_op_check_addc_64(); |
930 |
} |
931 |
static always_inline void gen_op_addzeo_64 (void) |
932 |
{ |
933 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
934 |
gen_op_add_ze(); |
935 |
gen_op_check_addc_64(); |
936 |
gen_op_check_addo_64(); |
937 |
} |
938 |
#endif
|
939 |
GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER); |
940 |
/* divw divw. divwo divwo. */
|
941 |
GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER); |
942 |
/* divwu divwu. divwuo divwuo. */
|
943 |
GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER); |
944 |
/* mulhw mulhw. */
|
945 |
GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER); |
946 |
/* mulhwu mulhwu. */
|
947 |
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER); |
948 |
/* mullw mullw. mullwo mullwo. */
|
949 |
GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER); |
950 |
/* neg neg. nego nego. */
|
951 |
GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); |
952 |
/* subf subf. subfo subfo. */
|
953 |
static always_inline void gen_op_subfo (void) |
954 |
{ |
955 |
tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
956 |
gen_op_subf(); |
957 |
gen_op_check_addo(); |
958 |
} |
959 |
#if defined(TARGET_PPC64)
|
960 |
#define gen_op_subf_64 gen_op_subf
|
961 |
static always_inline void gen_op_subfo_64 (void) |
962 |
{ |
963 |
tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
964 |
gen_op_subf(); |
965 |
gen_op_check_addo_64(); |
966 |
} |
967 |
#endif
|
968 |
GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER); |
969 |
/* subfc subfc. subfco subfco. */
|
970 |
static always_inline void gen_op_subfc (void) |
971 |
{ |
972 |
gen_op_subf(); |
973 |
gen_op_check_subfc(); |
974 |
} |
975 |
static always_inline void gen_op_subfco (void) |
976 |
{ |
977 |
tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
978 |
gen_op_subf(); |
979 |
gen_op_check_subfc(); |
980 |
gen_op_check_addo(); |
981 |
} |
982 |
#if defined(TARGET_PPC64)
|
983 |
static always_inline void gen_op_subfc_64 (void) |
984 |
{ |
985 |
gen_op_subf(); |
986 |
gen_op_check_subfc_64(); |
987 |
} |
988 |
static always_inline void gen_op_subfco_64 (void) |
989 |
{ |
990 |
tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
991 |
gen_op_subf(); |
992 |
gen_op_check_subfc_64(); |
993 |
gen_op_check_addo_64(); |
994 |
} |
995 |
#endif
|
996 |
GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER); |
997 |
/* subfe subfe. subfeo subfeo. */
|
998 |
static always_inline void gen_op_subfeo (void) |
999 |
{ |
1000 |
tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
1001 |
gen_op_subfe(); |
1002 |
gen_op_check_addo(); |
1003 |
} |
1004 |
#if defined(TARGET_PPC64)
|
1005 |
#define gen_op_subfe_64 gen_op_subfe
|
1006 |
static always_inline void gen_op_subfeo_64 (void) |
1007 |
{ |
1008 |
tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
1009 |
gen_op_subfe_64(); |
1010 |
gen_op_check_addo_64(); |
1011 |
} |
1012 |
#endif
|
1013 |
GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER); |
1014 |
/* subfme subfme. subfmeo subfmeo. */
|
1015 |
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER); |
1016 |
/* subfze subfze. subfzeo subfzeo. */
|
1017 |
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER); |
1018 |
/* addi */
|
1019 |
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1020 |
{ |
1021 |
target_long simm = SIMM(ctx->opcode); |
1022 |
|
1023 |
if (rA(ctx->opcode) == 0) { |
1024 |
/* li case */
|
1025 |
tcg_gen_movi_tl(cpu_T[0], simm);
|
1026 |
} else {
|
1027 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1028 |
if (likely(simm != 0)) |
1029 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
1030 |
} |
1031 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1032 |
} |
1033 |
/* addic */
|
1034 |
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1035 |
{ |
1036 |
target_long simm = SIMM(ctx->opcode); |
1037 |
|
1038 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1039 |
if (likely(simm != 0)) { |
1040 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
1041 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
1042 |
#if defined(TARGET_PPC64)
|
1043 |
if (ctx->sf_mode)
|
1044 |
gen_op_check_addc_64(); |
1045 |
else
|
1046 |
#endif
|
1047 |
gen_op_check_addc(); |
1048 |
} else {
|
1049 |
gen_op_clear_xer_ca(); |
1050 |
} |
1051 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1052 |
} |
1053 |
/* addic. */
|
1054 |
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1055 |
{ |
1056 |
target_long simm = SIMM(ctx->opcode); |
1057 |
|
1058 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1059 |
if (likely(simm != 0)) { |
1060 |
tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
1061 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
1062 |
#if defined(TARGET_PPC64)
|
1063 |
if (ctx->sf_mode)
|
1064 |
gen_op_check_addc_64(); |
1065 |
else
|
1066 |
#endif
|
1067 |
gen_op_check_addc(); |
1068 |
} else {
|
1069 |
gen_op_clear_xer_ca(); |
1070 |
} |
1071 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1072 |
gen_set_Rc0(ctx); |
1073 |
} |
1074 |
/* addis */
|
1075 |
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1076 |
{ |
1077 |
target_long simm = SIMM(ctx->opcode); |
1078 |
|
1079 |
if (rA(ctx->opcode) == 0) { |
1080 |
/* lis case */
|
1081 |
tcg_gen_movi_tl(cpu_T[0], simm << 16); |
1082 |
} else {
|
1083 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1084 |
if (likely(simm != 0)) |
1085 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16); |
1086 |
} |
1087 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1088 |
} |
1089 |
/* mulli */
|
1090 |
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1091 |
{ |
1092 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1093 |
gen_op_mulli(SIMM(ctx->opcode)); |
1094 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1095 |
} |
1096 |
/* subfic */
|
1097 |
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1098 |
{ |
1099 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1100 |
#if defined(TARGET_PPC64)
|
1101 |
if (ctx->sf_mode)
|
1102 |
gen_op_subfic_64(SIMM(ctx->opcode)); |
1103 |
else
|
1104 |
#endif
|
1105 |
gen_op_subfic(SIMM(ctx->opcode)); |
1106 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1107 |
} |
1108 |
|
1109 |
#if defined(TARGET_PPC64)
|
1110 |
/* mulhd mulhd. */
|
1111 |
GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B); |
1112 |
/* mulhdu mulhdu. */
|
1113 |
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B); |
1114 |
/* mulld mulld. mulldo mulldo. */
|
1115 |
GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B); |
1116 |
/* divd divd. divdo divdo. */
|
1117 |
GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B); |
1118 |
/* divdu divdu. divduo divduo. */
|
1119 |
GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B); |
1120 |
#endif
|
1121 |
|
1122 |
/*** Integer comparison ***/
|
1123 |
#if defined(TARGET_PPC64)
|
1124 |
#define GEN_CMP(name, opc, type) \
|
1125 |
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ |
1126 |
{ \ |
1127 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
1128 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
1129 |
if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \ |
1130 |
gen_op_##name##_64(); \ |
1131 |
else \
|
1132 |
gen_op_##name(); \ |
1133 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \ |
1134 |
} |
1135 |
#else
|
1136 |
#define GEN_CMP(name, opc, type) \
|
1137 |
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ |
1138 |
{ \ |
1139 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
1140 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
1141 |
gen_op_##name(); \ |
1142 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \ |
1143 |
} |
1144 |
#endif
|
1145 |
|
1146 |
/* cmp */
|
1147 |
GEN_CMP(cmp, 0x00, PPC_INTEGER);
|
1148 |
/* cmpi */
|
1149 |
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
1150 |
{ |
1151 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1152 |
#if defined(TARGET_PPC64)
|
1153 |
if (ctx->sf_mode && (ctx->opcode & 0x00200000)) |
1154 |
gen_op_cmpi_64(SIMM(ctx->opcode)); |
1155 |
else
|
1156 |
#endif
|
1157 |
gen_op_cmpi(SIMM(ctx->opcode)); |
1158 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); |
1159 |
} |
1160 |
/* cmpl */
|
1161 |
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
|
1162 |
/* cmpli */
|
1163 |
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
1164 |
{ |
1165 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1166 |
#if defined(TARGET_PPC64)
|
1167 |
if (ctx->sf_mode && (ctx->opcode & 0x00200000)) |
1168 |
gen_op_cmpli_64(UIMM(ctx->opcode)); |
1169 |
else
|
1170 |
#endif
|
1171 |
gen_op_cmpli(UIMM(ctx->opcode)); |
1172 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); |
1173 |
} |
1174 |
|
1175 |
/* isel (PowerPC 2.03 specification) */
|
1176 |
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) |
1177 |
{ |
1178 |
uint32_t bi = rC(ctx->opcode); |
1179 |
uint32_t mask; |
1180 |
|
1181 |
if (rA(ctx->opcode) == 0) { |
1182 |
tcg_gen_movi_tl(cpu_T[0], 0); |
1183 |
} else {
|
1184 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1185 |
} |
1186 |
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
1187 |
mask = 1 << (3 - (bi & 0x03)); |
1188 |
tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]); |
1189 |
gen_op_test_true(mask); |
1190 |
gen_op_isel(); |
1191 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1192 |
} |
1193 |
|
1194 |
/*** Integer logical ***/
|
1195 |
#define __GEN_LOGICAL2(name, opc2, opc3, type) \
|
1196 |
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \ |
1197 |
{ \ |
1198 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
|
1199 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
1200 |
gen_op_##name(); \ |
1201 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
1202 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
1203 |
gen_set_Rc0(ctx); \ |
1204 |
} |
1205 |
#define GEN_LOGICAL2(name, opc, type) \
|
1206 |
__GEN_LOGICAL2(name, 0x1C, opc, type)
|
1207 |
|
1208 |
#define GEN_LOGICAL1(name, opc, type) \
|
1209 |
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ |
1210 |
{ \ |
1211 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
|
1212 |
gen_op_##name(); \ |
1213 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
1214 |
if (unlikely(Rc(ctx->opcode) != 0)) \ |
1215 |
gen_set_Rc0(ctx); \ |
1216 |
} |
1217 |
|
1218 |
/* and & and. */
|
1219 |
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
|
1220 |
/* andc & andc. */
|
1221 |
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
|
1222 |
/* andi. */
|
1223 |
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1224 |
{ |
1225 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1226 |
gen_op_andi_T0(UIMM(ctx->opcode)); |
1227 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1228 |
gen_set_Rc0(ctx); |
1229 |
} |
1230 |
/* andis. */
|
1231 |
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1232 |
{ |
1233 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1234 |
gen_op_andi_T0(UIMM(ctx->opcode) << 16);
|
1235 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1236 |
gen_set_Rc0(ctx); |
1237 |
} |
1238 |
|
1239 |
/* cntlzw */
|
1240 |
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
|
1241 |
/* eqv & eqv. */
|
1242 |
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
|
1243 |
/* extsb & extsb. */
|
1244 |
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
|
1245 |
/* extsh & extsh. */
|
1246 |
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
|
1247 |
/* nand & nand. */
|
1248 |
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
|
1249 |
/* nor & nor. */
|
1250 |
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
|
1251 |
|
1252 |
/* or & or. */
|
1253 |
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) |
1254 |
{ |
1255 |
int rs, ra, rb;
|
1256 |
|
1257 |
rs = rS(ctx->opcode); |
1258 |
ra = rA(ctx->opcode); |
1259 |
rb = rB(ctx->opcode); |
1260 |
/* Optimisation for mr. ri case */
|
1261 |
if (rs != ra || rs != rb) {
|
1262 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
|
1263 |
if (rs != rb) {
|
1264 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
|
1265 |
gen_op_or(); |
1266 |
} |
1267 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
1268 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1269 |
gen_set_Rc0(ctx); |
1270 |
} else if (unlikely(Rc(ctx->opcode) != 0)) { |
1271 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
|
1272 |
gen_set_Rc0(ctx); |
1273 |
#if defined(TARGET_PPC64)
|
1274 |
} else {
|
1275 |
switch (rs) {
|
1276 |
case 1: |
1277 |
/* Set process priority to low */
|
1278 |
gen_op_store_pri(2);
|
1279 |
break;
|
1280 |
case 6: |
1281 |
/* Set process priority to medium-low */
|
1282 |
gen_op_store_pri(3);
|
1283 |
break;
|
1284 |
case 2: |
1285 |
/* Set process priority to normal */
|
1286 |
gen_op_store_pri(4);
|
1287 |
break;
|
1288 |
#if !defined(CONFIG_USER_ONLY)
|
1289 |
case 31: |
1290 |
if (ctx->supervisor > 0) { |
1291 |
/* Set process priority to very low */
|
1292 |
gen_op_store_pri(1);
|
1293 |
} |
1294 |
break;
|
1295 |
case 5: |
1296 |
if (ctx->supervisor > 0) { |
1297 |
/* Set process priority to medium-hight */
|
1298 |
gen_op_store_pri(5);
|
1299 |
} |
1300 |
break;
|
1301 |
case 3: |
1302 |
if (ctx->supervisor > 0) { |
1303 |
/* Set process priority to high */
|
1304 |
gen_op_store_pri(6);
|
1305 |
} |
1306 |
break;
|
1307 |
case 7: |
1308 |
if (ctx->supervisor > 1) { |
1309 |
/* Set process priority to very high */
|
1310 |
gen_op_store_pri(7);
|
1311 |
} |
1312 |
break;
|
1313 |
#endif
|
1314 |
default:
|
1315 |
/* nop */
|
1316 |
break;
|
1317 |
} |
1318 |
#endif
|
1319 |
} |
1320 |
} |
1321 |
|
1322 |
/* orc & orc. */
|
1323 |
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
|
1324 |
/* xor & xor. */
|
1325 |
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) |
1326 |
{ |
1327 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1328 |
/* Optimisation for "set to zero" case */
|
1329 |
if (rS(ctx->opcode) != rB(ctx->opcode)) {
|
1330 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
1331 |
gen_op_xor(); |
1332 |
} else {
|
1333 |
tcg_gen_movi_tl(cpu_T[0], 0); |
1334 |
} |
1335 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1336 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1337 |
gen_set_Rc0(ctx); |
1338 |
} |
1339 |
/* ori */
|
1340 |
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1341 |
{ |
1342 |
target_ulong uimm = UIMM(ctx->opcode); |
1343 |
|
1344 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1345 |
/* NOP */
|
1346 |
/* XXX: should handle special NOPs for POWER series */
|
1347 |
return;
|
1348 |
} |
1349 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1350 |
if (likely(uimm != 0)) |
1351 |
gen_op_ori(uimm); |
1352 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1353 |
} |
1354 |
/* oris */
|
1355 |
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1356 |
{ |
1357 |
target_ulong uimm = UIMM(ctx->opcode); |
1358 |
|
1359 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1360 |
/* NOP */
|
1361 |
return;
|
1362 |
} |
1363 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1364 |
if (likely(uimm != 0)) |
1365 |
gen_op_ori(uimm << 16);
|
1366 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1367 |
} |
1368 |
/* xori */
|
1369 |
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1370 |
{ |
1371 |
target_ulong uimm = UIMM(ctx->opcode); |
1372 |
|
1373 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1374 |
/* NOP */
|
1375 |
return;
|
1376 |
} |
1377 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1378 |
if (likely(uimm != 0)) |
1379 |
gen_op_xori(uimm); |
1380 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1381 |
} |
1382 |
|
1383 |
/* xoris */
|
1384 |
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1385 |
{ |
1386 |
target_ulong uimm = UIMM(ctx->opcode); |
1387 |
|
1388 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1389 |
/* NOP */
|
1390 |
return;
|
1391 |
} |
1392 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1393 |
if (likely(uimm != 0)) |
1394 |
gen_op_xori(uimm << 16);
|
1395 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1396 |
} |
1397 |
|
1398 |
/* popcntb : PowerPC 2.03 specification */
|
1399 |
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) |
1400 |
{ |
1401 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1402 |
#if defined(TARGET_PPC64)
|
1403 |
if (ctx->sf_mode)
|
1404 |
gen_op_popcntb_64(); |
1405 |
else
|
1406 |
#endif
|
1407 |
gen_op_popcntb(); |
1408 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1409 |
} |
1410 |
|
1411 |
#if defined(TARGET_PPC64)
|
1412 |
/* extsw & extsw. */
|
1413 |
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
|
1414 |
/* cntlzd */
|
1415 |
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
|
1416 |
#endif
|
1417 |
|
1418 |
/*** Integer rotate ***/
|
1419 |
/* rlwimi & rlwimi. */
|
1420 |
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1421 |
{ |
1422 |
target_ulong mask; |
1423 |
uint32_t mb, me, sh; |
1424 |
|
1425 |
mb = MB(ctx->opcode); |
1426 |
me = ME(ctx->opcode); |
1427 |
sh = SH(ctx->opcode); |
1428 |
if (likely(sh == 0)) { |
1429 |
if (likely(mb == 0 && me == 31)) { |
1430 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1431 |
goto do_store;
|
1432 |
} else if (likely(mb == 31 && me == 0)) { |
1433 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1434 |
goto do_store;
|
1435 |
} |
1436 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1437 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1438 |
goto do_mask;
|
1439 |
} |
1440 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1441 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1442 |
gen_op_rotli32_T0(SH(ctx->opcode)); |
1443 |
do_mask:
|
1444 |
#if defined(TARGET_PPC64)
|
1445 |
mb += 32;
|
1446 |
me += 32;
|
1447 |
#endif
|
1448 |
mask = MASK(mb, me); |
1449 |
gen_op_andi_T0(mask); |
1450 |
gen_op_andi_T1(~mask); |
1451 |
gen_op_or(); |
1452 |
do_store:
|
1453 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1454 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1455 |
gen_set_Rc0(ctx); |
1456 |
} |
1457 |
/* rlwinm & rlwinm. */
|
1458 |
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1459 |
{ |
1460 |
uint32_t mb, me, sh; |
1461 |
|
1462 |
sh = SH(ctx->opcode); |
1463 |
mb = MB(ctx->opcode); |
1464 |
me = ME(ctx->opcode); |
1465 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1466 |
if (likely(sh == 0)) { |
1467 |
goto do_mask;
|
1468 |
} |
1469 |
if (likely(mb == 0)) { |
1470 |
if (likely(me == 31)) { |
1471 |
gen_op_rotli32_T0(sh); |
1472 |
goto do_store;
|
1473 |
} else if (likely(me == (31 - sh))) { |
1474 |
gen_op_sli_T0(sh); |
1475 |
goto do_store;
|
1476 |
} |
1477 |
} else if (likely(me == 31)) { |
1478 |
if (likely(sh == (32 - mb))) { |
1479 |
gen_op_srli_T0(mb); |
1480 |
goto do_store;
|
1481 |
} |
1482 |
} |
1483 |
gen_op_rotli32_T0(sh); |
1484 |
do_mask:
|
1485 |
#if defined(TARGET_PPC64)
|
1486 |
mb += 32;
|
1487 |
me += 32;
|
1488 |
#endif
|
1489 |
gen_op_andi_T0(MASK(mb, me)); |
1490 |
do_store:
|
1491 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1492 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1493 |
gen_set_Rc0(ctx); |
1494 |
} |
1495 |
/* rlwnm & rlwnm. */
|
1496 |
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1497 |
{ |
1498 |
uint32_t mb, me; |
1499 |
|
1500 |
mb = MB(ctx->opcode); |
1501 |
me = ME(ctx->opcode); |
1502 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1503 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
1504 |
gen_op_rotl32_T0_T1(); |
1505 |
if (unlikely(mb != 0 || me != 31)) { |
1506 |
#if defined(TARGET_PPC64)
|
1507 |
mb += 32;
|
1508 |
me += 32;
|
1509 |
#endif
|
1510 |
gen_op_andi_T0(MASK(mb, me)); |
1511 |
} |
1512 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1513 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1514 |
gen_set_Rc0(ctx); |
1515 |
} |
1516 |
|
1517 |
#if defined(TARGET_PPC64)
|
1518 |
#define GEN_PPC64_R2(name, opc1, opc2) \
|
1519 |
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ |
1520 |
{ \ |
1521 |
gen_##name(ctx, 0); \ |
1522 |
} \ |
1523 |
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
1524 |
PPC_64B) \ |
1525 |
{ \ |
1526 |
gen_##name(ctx, 1); \ |
1527 |
} |
1528 |
#define GEN_PPC64_R4(name, opc1, opc2) \
|
1529 |
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ |
1530 |
{ \ |
1531 |
gen_##name(ctx, 0, 0); \ |
1532 |
} \ |
1533 |
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
1534 |
PPC_64B) \ |
1535 |
{ \ |
1536 |
gen_##name(ctx, 0, 1); \ |
1537 |
} \ |
1538 |
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
1539 |
PPC_64B) \ |
1540 |
{ \ |
1541 |
gen_##name(ctx, 1, 0); \ |
1542 |
} \ |
1543 |
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
1544 |
PPC_64B) \ |
1545 |
{ \ |
1546 |
gen_##name(ctx, 1, 1); \ |
1547 |
} |
1548 |
|
1549 |
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask) |
1550 |
{ |
1551 |
if (mask >> 32) |
1552 |
gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF); |
1553 |
else
|
1554 |
gen_op_andi_T0(mask); |
1555 |
} |
1556 |
|
1557 |
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask) |
1558 |
{ |
1559 |
if (mask >> 32) |
1560 |
gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF); |
1561 |
else
|
1562 |
gen_op_andi_T1(mask); |
1563 |
} |
1564 |
|
1565 |
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, |
1566 |
uint32_t me, uint32_t sh) |
1567 |
{ |
1568 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1569 |
if (likely(sh == 0)) { |
1570 |
goto do_mask;
|
1571 |
} |
1572 |
if (likely(mb == 0)) { |
1573 |
if (likely(me == 63)) { |
1574 |
gen_op_rotli64_T0(sh); |
1575 |
goto do_store;
|
1576 |
} else if (likely(me == (63 - sh))) { |
1577 |
gen_op_sli_T0(sh); |
1578 |
goto do_store;
|
1579 |
} |
1580 |
} else if (likely(me == 63)) { |
1581 |
if (likely(sh == (64 - mb))) { |
1582 |
gen_op_srli_T0_64(mb); |
1583 |
goto do_store;
|
1584 |
} |
1585 |
} |
1586 |
gen_op_rotli64_T0(sh); |
1587 |
do_mask:
|
1588 |
gen_andi_T0_64(ctx, MASK(mb, me)); |
1589 |
do_store:
|
1590 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1591 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1592 |
gen_set_Rc0(ctx); |
1593 |
} |
1594 |
/* rldicl - rldicl. */
|
1595 |
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) |
1596 |
{ |
1597 |
uint32_t sh, mb; |
1598 |
|
1599 |
sh = SH(ctx->opcode) | (shn << 5);
|
1600 |
mb = MB(ctx->opcode) | (mbn << 5);
|
1601 |
gen_rldinm(ctx, mb, 63, sh);
|
1602 |
} |
1603 |
GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1604 |
/* rldicr - rldicr. */
|
1605 |
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) |
1606 |
{ |
1607 |
uint32_t sh, me; |
1608 |
|
1609 |
sh = SH(ctx->opcode) | (shn << 5);
|
1610 |
me = MB(ctx->opcode) | (men << 5);
|
1611 |
gen_rldinm(ctx, 0, me, sh);
|
1612 |
} |
1613 |
GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1614 |
/* rldic - rldic. */
|
1615 |
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) |
1616 |
{ |
1617 |
uint32_t sh, mb; |
1618 |
|
1619 |
sh = SH(ctx->opcode) | (shn << 5);
|
1620 |
mb = MB(ctx->opcode) | (mbn << 5);
|
1621 |
gen_rldinm(ctx, mb, 63 - sh, sh);
|
1622 |
} |
1623 |
GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1624 |
|
1625 |
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, |
1626 |
uint32_t me) |
1627 |
{ |
1628 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1629 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
1630 |
gen_op_rotl64_T0_T1(); |
1631 |
if (unlikely(mb != 0 || me != 63)) { |
1632 |
gen_andi_T0_64(ctx, MASK(mb, me)); |
1633 |
} |
1634 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1635 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1636 |
gen_set_Rc0(ctx); |
1637 |
} |
1638 |
|
1639 |
/* rldcl - rldcl. */
|
1640 |
static always_inline void gen_rldcl (DisasContext *ctx, int mbn) |
1641 |
{ |
1642 |
uint32_t mb; |
1643 |
|
1644 |
mb = MB(ctx->opcode) | (mbn << 5);
|
1645 |
gen_rldnm(ctx, mb, 63);
|
1646 |
} |
1647 |
GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1648 |
/* rldcr - rldcr. */
|
1649 |
static always_inline void gen_rldcr (DisasContext *ctx, int men) |
1650 |
{ |
1651 |
uint32_t me; |
1652 |
|
1653 |
me = MB(ctx->opcode) | (men << 5);
|
1654 |
gen_rldnm(ctx, 0, me);
|
1655 |
} |
1656 |
GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1657 |
/* rldimi - rldimi. */
|
1658 |
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) |
1659 |
{ |
1660 |
uint64_t mask; |
1661 |
uint32_t sh, mb, me; |
1662 |
|
1663 |
sh = SH(ctx->opcode) | (shn << 5);
|
1664 |
mb = MB(ctx->opcode) | (mbn << 5);
|
1665 |
me = 63 - sh;
|
1666 |
if (likely(sh == 0)) { |
1667 |
if (likely(mb == 0)) { |
1668 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1669 |
goto do_store;
|
1670 |
} |
1671 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1672 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1673 |
goto do_mask;
|
1674 |
} |
1675 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1676 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1677 |
gen_op_rotli64_T0(sh); |
1678 |
do_mask:
|
1679 |
mask = MASK(mb, me); |
1680 |
gen_andi_T0_64(ctx, mask); |
1681 |
gen_andi_T1_64(ctx, ~mask); |
1682 |
gen_op_or(); |
1683 |
do_store:
|
1684 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1685 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1686 |
gen_set_Rc0(ctx); |
1687 |
} |
1688 |
GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
1689 |
#endif
|
1690 |
|
1691 |
/*** Integer shift ***/
|
1692 |
/* slw & slw. */
|
1693 |
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER); |
1694 |
/* sraw & sraw. */
|
1695 |
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER); |
1696 |
/* srawi & srawi. */
|
1697 |
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
1698 |
{ |
1699 |
int mb, me;
|
1700 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1701 |
if (SH(ctx->opcode) != 0) { |
1702 |
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
1703 |
mb = 32 - SH(ctx->opcode);
|
1704 |
me = 31;
|
1705 |
#if defined(TARGET_PPC64)
|
1706 |
mb += 32;
|
1707 |
me += 32;
|
1708 |
#endif
|
1709 |
gen_op_srawi(SH(ctx->opcode), MASK(mb, me)); |
1710 |
} |
1711 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1712 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1713 |
gen_set_Rc0(ctx); |
1714 |
} |
1715 |
/* srw & srw. */
|
1716 |
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER); |
1717 |
|
1718 |
#if defined(TARGET_PPC64)
|
1719 |
/* sld & sld. */
|
1720 |
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B); |
1721 |
/* srad & srad. */
|
1722 |
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B); |
1723 |
/* sradi & sradi. */
|
1724 |
static always_inline void gen_sradi (DisasContext *ctx, int n) |
1725 |
{ |
1726 |
uint64_t mask; |
1727 |
int sh, mb, me;
|
1728 |
|
1729 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1730 |
sh = SH(ctx->opcode) + (n << 5);
|
1731 |
if (sh != 0) { |
1732 |
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
1733 |
mb = 64 - SH(ctx->opcode);
|
1734 |
me = 63;
|
1735 |
mask = MASK(mb, me); |
1736 |
gen_op_sradi(sh, mask >> 32, mask);
|
1737 |
} |
1738 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1739 |
if (unlikely(Rc(ctx->opcode) != 0)) |
1740 |
gen_set_Rc0(ctx); |
1741 |
} |
1742 |
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B) |
1743 |
{ |
1744 |
gen_sradi(ctx, 0);
|
1745 |
} |
1746 |
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B) |
1747 |
{ |
1748 |
gen_sradi(ctx, 1);
|
1749 |
} |
1750 |
/* srd & srd. */
|
1751 |
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B); |
1752 |
#endif
|
1753 |
|
1754 |
/*** Floating-Point arithmetic ***/
|
1755 |
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
1756 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ |
1757 |
{ \ |
1758 |
if (unlikely(!ctx->fpu_enabled)) { \
|
1759 |
GEN_EXCP_NO_FP(ctx); \ |
1760 |
return; \
|
1761 |
} \ |
1762 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
1763 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
|
1764 |
tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
|
1765 |
gen_reset_fpstatus(); \ |
1766 |
gen_op_f##op(); \ |
1767 |
if (isfloat) { \
|
1768 |
gen_op_frsp(); \ |
1769 |
} \ |
1770 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1771 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1772 |
} |
1773 |
|
1774 |
#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
1775 |
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
1776 |
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
1777 |
|
1778 |
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
1779 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ |
1780 |
{ \ |
1781 |
if (unlikely(!ctx->fpu_enabled)) { \
|
1782 |
GEN_EXCP_NO_FP(ctx); \ |
1783 |
return; \
|
1784 |
} \ |
1785 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
1786 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
|
1787 |
gen_reset_fpstatus(); \ |
1788 |
gen_op_f##op(); \ |
1789 |
if (isfloat) { \
|
1790 |
gen_op_frsp(); \ |
1791 |
} \ |
1792 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1793 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1794 |
} |
1795 |
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
1796 |
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
1797 |
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
1798 |
|
1799 |
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
1800 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ |
1801 |
{ \ |
1802 |
if (unlikely(!ctx->fpu_enabled)) { \
|
1803 |
GEN_EXCP_NO_FP(ctx); \ |
1804 |
return; \
|
1805 |
} \ |
1806 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
1807 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
|
1808 |
gen_reset_fpstatus(); \ |
1809 |
gen_op_f##op(); \ |
1810 |
if (isfloat) { \
|
1811 |
gen_op_frsp(); \ |
1812 |
} \ |
1813 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1814 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1815 |
} |
1816 |
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
1817 |
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
1818 |
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
1819 |
|
1820 |
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
1821 |
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ |
1822 |
{ \ |
1823 |
if (unlikely(!ctx->fpu_enabled)) { \
|
1824 |
GEN_EXCP_NO_FP(ctx); \ |
1825 |
return; \
|
1826 |
} \ |
1827 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
|
1828 |
gen_reset_fpstatus(); \ |
1829 |
gen_op_f##name(); \ |
1830 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1831 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1832 |
} |
1833 |
|
1834 |
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
1835 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ |
1836 |
{ \ |
1837 |
if (unlikely(!ctx->fpu_enabled)) { \
|
1838 |
GEN_EXCP_NO_FP(ctx); \ |
1839 |
return; \
|
1840 |
} \ |
1841 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
|
1842 |
gen_reset_fpstatus(); \ |
1843 |
gen_op_f##name(); \ |
1844 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1845 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1846 |
} |
1847 |
|
1848 |
/* fadd - fadds */
|
1849 |
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
1850 |
/* fdiv - fdivs */
|
1851 |
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
1852 |
/* fmul - fmuls */
|
1853 |
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
1854 |
|
1855 |
/* fre */
|
1856 |
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
1857 |
|
1858 |
/* fres */
|
1859 |
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
1860 |
|
1861 |
/* frsqrte */
|
1862 |
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
1863 |
|
1864 |
/* frsqrtes */
|
1865 |
static always_inline void gen_op_frsqrtes (void) |
1866 |
{ |
1867 |
gen_op_frsqrte(); |
1868 |
gen_op_frsp(); |
1869 |
} |
1870 |
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES); |
1871 |
|
1872 |
/* fsel */
|
1873 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
1874 |
/* fsub - fsubs */
|
1875 |
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
1876 |
/* Optional: */
|
1877 |
/* fsqrt */
|
1878 |
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
1879 |
{ |
1880 |
if (unlikely(!ctx->fpu_enabled)) {
|
1881 |
GEN_EXCP_NO_FP(ctx); |
1882 |
return;
|
1883 |
} |
1884 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
1885 |
gen_reset_fpstatus(); |
1886 |
gen_op_fsqrt(); |
1887 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
1888 |
gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
1889 |
} |
1890 |
|
1891 |
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
1892 |
{ |
1893 |
if (unlikely(!ctx->fpu_enabled)) {
|
1894 |
GEN_EXCP_NO_FP(ctx); |
1895 |
return;
|
1896 |
} |
1897 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
1898 |
gen_reset_fpstatus(); |
1899 |
gen_op_fsqrt(); |
1900 |
gen_op_frsp(); |
1901 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
1902 |
gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
1903 |
} |
1904 |
|
1905 |
/*** Floating-Point multiply-and-add ***/
|
1906 |
/* fmadd - fmadds */
|
1907 |
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
1908 |
/* fmsub - fmsubs */
|
1909 |
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
1910 |
/* fnmadd - fnmadds */
|
1911 |
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
1912 |
/* fnmsub - fnmsubs */
|
1913 |
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
1914 |
|
1915 |
/*** Floating-Point round & convert ***/
|
1916 |
/* fctiw */
|
1917 |
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
1918 |
/* fctiwz */
|
1919 |
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
1920 |
/* frsp */
|
1921 |
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
1922 |
#if defined(TARGET_PPC64)
|
1923 |
/* fcfid */
|
1924 |
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
1925 |
/* fctid */
|
1926 |
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
1927 |
/* fctidz */
|
1928 |
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
1929 |
#endif
|
1930 |
|
1931 |
/* frin */
|
1932 |
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
1933 |
/* friz */
|
1934 |
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
1935 |
/* frip */
|
1936 |
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
1937 |
/* frim */
|
1938 |
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
1939 |
|
1940 |
/*** Floating-Point compare ***/
|
1941 |
/* fcmpo */
|
1942 |
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) |
1943 |
{ |
1944 |
if (unlikely(!ctx->fpu_enabled)) {
|
1945 |
GEN_EXCP_NO_FP(ctx); |
1946 |
return;
|
1947 |
} |
1948 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
|
1949 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
|
1950 |
gen_reset_fpstatus(); |
1951 |
gen_op_fcmpo(); |
1952 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); |
1953 |
gen_op_float_check_status(); |
1954 |
} |
1955 |
|
1956 |
/* fcmpu */
|
1957 |
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) |
1958 |
{ |
1959 |
if (unlikely(!ctx->fpu_enabled)) {
|
1960 |
GEN_EXCP_NO_FP(ctx); |
1961 |
return;
|
1962 |
} |
1963 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
|
1964 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
|
1965 |
gen_reset_fpstatus(); |
1966 |
gen_op_fcmpu(); |
1967 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); |
1968 |
gen_op_float_check_status(); |
1969 |
} |
1970 |
|
1971 |
/*** Floating-point move ***/
|
1972 |
/* fabs */
|
1973 |
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
|
1974 |
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
1975 |
|
1976 |
/* fmr - fmr. */
|
1977 |
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
|
1978 |
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
1979 |
{ |
1980 |
if (unlikely(!ctx->fpu_enabled)) {
|
1981 |
GEN_EXCP_NO_FP(ctx); |
1982 |
return;
|
1983 |
} |
1984 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
1985 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
1986 |
gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
1987 |
} |
1988 |
|
1989 |
/* fnabs */
|
1990 |
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
|
1991 |
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
1992 |
/* fneg */
|
1993 |
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
|
1994 |
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
1995 |
|
1996 |
/*** Floating-Point status & ctrl register ***/
|
1997 |
/* mcrfs */
|
1998 |
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) |
1999 |
{ |
2000 |
int bfa;
|
2001 |
|
2002 |
if (unlikely(!ctx->fpu_enabled)) {
|
2003 |
GEN_EXCP_NO_FP(ctx); |
2004 |
return;
|
2005 |
} |
2006 |
gen_optimize_fprf(); |
2007 |
bfa = 4 * (7 - crfS(ctx->opcode)); |
2008 |
gen_op_load_fpscr_T0(bfa); |
2009 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); |
2010 |
gen_op_fpscr_resetbit(~(0xF << bfa));
|
2011 |
} |
2012 |
|
2013 |
/* mffs */
|
2014 |
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) |
2015 |
{ |
2016 |
if (unlikely(!ctx->fpu_enabled)) {
|
2017 |
GEN_EXCP_NO_FP(ctx); |
2018 |
return;
|
2019 |
} |
2020 |
gen_optimize_fprf(); |
2021 |
gen_reset_fpstatus(); |
2022 |
gen_op_load_fpscr_FT0(); |
2023 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
2024 |
gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
2025 |
} |
2026 |
|
2027 |
/* mtfsb0 */
|
2028 |
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) |
2029 |
{ |
2030 |
uint8_t crb; |
2031 |
|
2032 |
if (unlikely(!ctx->fpu_enabled)) {
|
2033 |
GEN_EXCP_NO_FP(ctx); |
2034 |
return;
|
2035 |
} |
2036 |
crb = 32 - (crbD(ctx->opcode) >> 2); |
2037 |
gen_optimize_fprf(); |
2038 |
gen_reset_fpstatus(); |
2039 |
if (likely(crb != 30 && crb != 29)) |
2040 |
gen_op_fpscr_resetbit(~(1 << crb));
|
2041 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2042 |
gen_op_load_fpcc(); |
2043 |
gen_op_set_Rc0(); |
2044 |
} |
2045 |
} |
2046 |
|
2047 |
/* mtfsb1 */
|
2048 |
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) |
2049 |
{ |
2050 |
uint8_t crb; |
2051 |
|
2052 |
if (unlikely(!ctx->fpu_enabled)) {
|
2053 |
GEN_EXCP_NO_FP(ctx); |
2054 |
return;
|
2055 |
} |
2056 |
crb = 32 - (crbD(ctx->opcode) >> 2); |
2057 |
gen_optimize_fprf(); |
2058 |
gen_reset_fpstatus(); |
2059 |
/* XXX: we pretend we can only do IEEE floating-point computations */
|
2060 |
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
|
2061 |
gen_op_fpscr_setbit(crb); |
2062 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2063 |
gen_op_load_fpcc(); |
2064 |
gen_op_set_Rc0(); |
2065 |
} |
2066 |
/* We can raise a differed exception */
|
2067 |
gen_op_float_check_status(); |
2068 |
} |
2069 |
|
2070 |
/* mtfsf */
|
2071 |
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
2072 |
{ |
2073 |
if (unlikely(!ctx->fpu_enabled)) {
|
2074 |
GEN_EXCP_NO_FP(ctx); |
2075 |
return;
|
2076 |
} |
2077 |
gen_optimize_fprf(); |
2078 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
2079 |
gen_reset_fpstatus(); |
2080 |
gen_op_store_fpscr(FM(ctx->opcode)); |
2081 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2082 |
gen_op_load_fpcc(); |
2083 |
gen_op_set_Rc0(); |
2084 |
} |
2085 |
/* We can raise a differed exception */
|
2086 |
gen_op_float_check_status(); |
2087 |
} |
2088 |
|
2089 |
/* mtfsfi */
|
2090 |
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
2091 |
{ |
2092 |
int bf, sh;
|
2093 |
|
2094 |
if (unlikely(!ctx->fpu_enabled)) {
|
2095 |
GEN_EXCP_NO_FP(ctx); |
2096 |
return;
|
2097 |
} |
2098 |
bf = crbD(ctx->opcode) >> 2;
|
2099 |
sh = 7 - bf;
|
2100 |
gen_optimize_fprf(); |
2101 |
tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh)); |
2102 |
gen_reset_fpstatus(); |
2103 |
gen_op_store_fpscr(1 << sh);
|
2104 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2105 |
gen_op_load_fpcc(); |
2106 |
gen_op_set_Rc0(); |
2107 |
} |
2108 |
/* We can raise a differed exception */
|
2109 |
gen_op_float_check_status(); |
2110 |
} |
2111 |
|
2112 |
/*** Addressing modes ***/
|
2113 |
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
|
2114 |
static always_inline void gen_addr_imm_index (DisasContext *ctx, |
2115 |
target_long maskl) |
2116 |
{ |
2117 |
target_long simm = SIMM(ctx->opcode); |
2118 |
|
2119 |
simm &= ~maskl; |
2120 |
if (rA(ctx->opcode) == 0) { |
2121 |
tcg_gen_movi_tl(cpu_T[0], simm);
|
2122 |
} else {
|
2123 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
2124 |
if (likely(simm != 0)) |
2125 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); |
2126 |
} |
2127 |
#ifdef DEBUG_MEMORY_ACCESSES
|
2128 |
gen_op_print_mem_EA(); |
2129 |
#endif
|
2130 |
} |
2131 |
|
2132 |
static always_inline void gen_addr_reg_index (DisasContext *ctx) |
2133 |
{ |
2134 |
if (rA(ctx->opcode) == 0) { |
2135 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
2136 |
} else {
|
2137 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
2138 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
2139 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
2140 |
} |
2141 |
#ifdef DEBUG_MEMORY_ACCESSES
|
2142 |
gen_op_print_mem_EA(); |
2143 |
#endif
|
2144 |
} |
2145 |
|
2146 |
static always_inline void gen_addr_register (DisasContext *ctx) |
2147 |
{ |
2148 |
if (rA(ctx->opcode) == 0) { |
2149 |
tcg_gen_movi_tl(cpu_T[0], 0); |
2150 |
} else {
|
2151 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
2152 |
} |
2153 |
#ifdef DEBUG_MEMORY_ACCESSES
|
2154 |
gen_op_print_mem_EA(); |
2155 |
#endif
|
2156 |
} |
2157 |
|
2158 |
#if defined(TARGET_PPC64)
|
2159 |
#define _GEN_MEM_FUNCS(name, mode) \
|
2160 |
&gen_op_##name##_##mode, \ |
2161 |
&gen_op_##name##_le_##mode, \ |
2162 |
&gen_op_##name##_64_##mode, \ |
2163 |
&gen_op_##name##_le_64_##mode |
2164 |
#else
|
2165 |
#define _GEN_MEM_FUNCS(name, mode) \
|
2166 |
&gen_op_##name##_##mode, \ |
2167 |
&gen_op_##name##_le_##mode |
2168 |
#endif
|
2169 |
#if defined(CONFIG_USER_ONLY)
|
2170 |
#if defined(TARGET_PPC64)
|
2171 |
#define NB_MEM_FUNCS 4 |
2172 |
#else
|
2173 |
#define NB_MEM_FUNCS 2 |
2174 |
#endif
|
2175 |
#define GEN_MEM_FUNCS(name) \
|
2176 |
_GEN_MEM_FUNCS(name, raw) |
2177 |
#else
|
2178 |
#if defined(TARGET_PPC64)
|
2179 |
#define NB_MEM_FUNCS 12 |
2180 |
#else
|
2181 |
#define NB_MEM_FUNCS 6 |
2182 |
#endif
|
2183 |
#define GEN_MEM_FUNCS(name) \
|
2184 |
_GEN_MEM_FUNCS(name, user), \ |
2185 |
_GEN_MEM_FUNCS(name, kernel), \ |
2186 |
_GEN_MEM_FUNCS(name, hypv) |
2187 |
#endif
|
2188 |
|
2189 |
/*** Integer load ***/
|
2190 |
#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
2191 |
/* Byte access routine are endian safe */
|
2192 |
#define gen_op_lbz_le_raw gen_op_lbz_raw
|
2193 |
#define gen_op_lbz_le_user gen_op_lbz_user
|
2194 |
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
|
2195 |
#define gen_op_lbz_le_hypv gen_op_lbz_hypv
|
2196 |
#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
|
2197 |
#define gen_op_lbz_le_64_user gen_op_lbz_64_user
|
2198 |
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
|
2199 |
#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
|
2200 |
#define gen_op_stb_le_raw gen_op_stb_raw
|
2201 |
#define gen_op_stb_le_user gen_op_stb_user
|
2202 |
#define gen_op_stb_le_kernel gen_op_stb_kernel
|
2203 |
#define gen_op_stb_le_hypv gen_op_stb_hypv
|
2204 |
#define gen_op_stb_le_64_raw gen_op_stb_64_raw
|
2205 |
#define gen_op_stb_le_64_user gen_op_stb_64_user
|
2206 |
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
|
2207 |
#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
|
2208 |
#define OP_LD_TABLE(width) \
|
2209 |
static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \ |
2210 |
GEN_MEM_FUNCS(l##width), \ |
2211 |
}; |
2212 |
#define OP_ST_TABLE(width) \
|
2213 |
static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \ |
2214 |
GEN_MEM_FUNCS(st##width), \ |
2215 |
}; |
2216 |
|
2217 |
#define GEN_LD(width, opc, type) \
|
2218 |
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2219 |
{ \ |
2220 |
gen_addr_imm_index(ctx, 0); \
|
2221 |
op_ldst(l##width); \ |
2222 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2223 |
} |
2224 |
|
2225 |
#define GEN_LDU(width, opc, type) \
|
2226 |
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2227 |
{ \ |
2228 |
if (unlikely(rA(ctx->opcode) == 0 || \ |
2229 |
rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2230 |
GEN_EXCP_INVAL(ctx); \ |
2231 |
return; \
|
2232 |
} \ |
2233 |
if (type == PPC_64B) \
|
2234 |
gen_addr_imm_index(ctx, 0x03); \
|
2235 |
else \
|
2236 |
gen_addr_imm_index(ctx, 0); \
|
2237 |
op_ldst(l##width); \ |
2238 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2239 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2240 |
} |
2241 |
|
2242 |
#define GEN_LDUX(width, opc2, opc3, type) \
|
2243 |
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ |
2244 |
{ \ |
2245 |
if (unlikely(rA(ctx->opcode) == 0 || \ |
2246 |
rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2247 |
GEN_EXCP_INVAL(ctx); \ |
2248 |
return; \
|
2249 |
} \ |
2250 |
gen_addr_reg_index(ctx); \ |
2251 |
op_ldst(l##width); \ |
2252 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2253 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2254 |
} |
2255 |
|
2256 |
#define GEN_LDX(width, opc2, opc3, type) \
|
2257 |
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2258 |
{ \ |
2259 |
gen_addr_reg_index(ctx); \ |
2260 |
op_ldst(l##width); \ |
2261 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2262 |
} |
2263 |
|
2264 |
#define GEN_LDS(width, op, type) \
|
2265 |
OP_LD_TABLE(width); \ |
2266 |
GEN_LD(width, op | 0x20, type); \
|
2267 |
GEN_LDU(width, op | 0x21, type); \
|
2268 |
GEN_LDUX(width, 0x17, op | 0x01, type); \ |
2269 |
GEN_LDX(width, 0x17, op | 0x00, type) |
2270 |
|
2271 |
/* lbz lbzu lbzux lbzx */
|
2272 |
GEN_LDS(bz, 0x02, PPC_INTEGER);
|
2273 |
/* lha lhau lhaux lhax */
|
2274 |
GEN_LDS(ha, 0x0A, PPC_INTEGER);
|
2275 |
/* lhz lhzu lhzux lhzx */
|
2276 |
GEN_LDS(hz, 0x08, PPC_INTEGER);
|
2277 |
/* lwz lwzu lwzux lwzx */
|
2278 |
GEN_LDS(wz, 0x00, PPC_INTEGER);
|
2279 |
#if defined(TARGET_PPC64)
|
2280 |
OP_LD_TABLE(wa); |
2281 |
OP_LD_TABLE(d); |
2282 |
/* lwaux */
|
2283 |
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B); |
2284 |
/* lwax */
|
2285 |
GEN_LDX(wa, 0x15, 0x0A, PPC_64B); |
2286 |
/* ldux */
|
2287 |
GEN_LDUX(d, 0x15, 0x01, PPC_64B); |
2288 |
/* ldx */
|
2289 |
GEN_LDX(d, 0x15, 0x00, PPC_64B); |
2290 |
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) |
2291 |
{ |
2292 |
if (Rc(ctx->opcode)) {
|
2293 |
if (unlikely(rA(ctx->opcode) == 0 || |
2294 |
rA(ctx->opcode) == rD(ctx->opcode))) { |
2295 |
GEN_EXCP_INVAL(ctx); |
2296 |
return;
|
2297 |
} |
2298 |
} |
2299 |
gen_addr_imm_index(ctx, 0x03);
|
2300 |
if (ctx->opcode & 0x02) { |
2301 |
/* lwa (lwau is undefined) */
|
2302 |
op_ldst(lwa); |
2303 |
} else {
|
2304 |
/* ld - ldu */
|
2305 |
op_ldst(ld); |
2306 |
} |
2307 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
|
2308 |
if (Rc(ctx->opcode))
|
2309 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
2310 |
} |
2311 |
/* lq */
|
2312 |
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) |
2313 |
{ |
2314 |
#if defined(CONFIG_USER_ONLY)
|
2315 |
GEN_EXCP_PRIVOPC(ctx); |
2316 |
#else
|
2317 |
int ra, rd;
|
2318 |
|
2319 |
/* Restore CPU state */
|
2320 |
if (unlikely(ctx->supervisor == 0)) { |
2321 |
GEN_EXCP_PRIVOPC(ctx); |
2322 |
return;
|
2323 |
} |
2324 |
ra = rA(ctx->opcode); |
2325 |
rd = rD(ctx->opcode); |
2326 |
if (unlikely((rd & 1) || rd == ra)) { |
2327 |
GEN_EXCP_INVAL(ctx); |
2328 |
return;
|
2329 |
} |
2330 |
if (unlikely(ctx->mem_idx & 1)) { |
2331 |
/* Little-endian mode is not handled */
|
2332 |
GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2333 |
return;
|
2334 |
} |
2335 |
gen_addr_imm_index(ctx, 0x0F);
|
2336 |
op_ldst(ld); |
2337 |
tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
|
2338 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); |
2339 |
op_ldst(ld); |
2340 |
tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]); |
2341 |
#endif
|
2342 |
} |
2343 |
#endif
|
2344 |
|
2345 |
/*** Integer store ***/
|
2346 |
#define GEN_ST(width, opc, type) \
|
2347 |
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2348 |
{ \ |
2349 |
gen_addr_imm_index(ctx, 0); \
|
2350 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2351 |
op_ldst(st##width); \ |
2352 |
} |
2353 |
|
2354 |
#define GEN_STU(width, opc, type) \
|
2355 |
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2356 |
{ \ |
2357 |
if (unlikely(rA(ctx->opcode) == 0)) { \ |
2358 |
GEN_EXCP_INVAL(ctx); \ |
2359 |
return; \
|
2360 |
} \ |
2361 |
if (type == PPC_64B) \
|
2362 |
gen_addr_imm_index(ctx, 0x03); \
|
2363 |
else \
|
2364 |
gen_addr_imm_index(ctx, 0); \
|
2365 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2366 |
op_ldst(st##width); \ |
2367 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2368 |
} |
2369 |
|
2370 |
#define GEN_STUX(width, opc2, opc3, type) \
|
2371 |
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ |
2372 |
{ \ |
2373 |
if (unlikely(rA(ctx->opcode) == 0)) { \ |
2374 |
GEN_EXCP_INVAL(ctx); \ |
2375 |
return; \
|
2376 |
} \ |
2377 |
gen_addr_reg_index(ctx); \ |
2378 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2379 |
op_ldst(st##width); \ |
2380 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2381 |
} |
2382 |
|
2383 |
#define GEN_STX(width, opc2, opc3, type) \
|
2384 |
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2385 |
{ \ |
2386 |
gen_addr_reg_index(ctx); \ |
2387 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2388 |
op_ldst(st##width); \ |
2389 |
} |
2390 |
|
2391 |
#define GEN_STS(width, op, type) \
|
2392 |
OP_ST_TABLE(width); \ |
2393 |
GEN_ST(width, op | 0x20, type); \
|
2394 |
GEN_STU(width, op | 0x21, type); \
|
2395 |
GEN_STUX(width, 0x17, op | 0x01, type); \ |
2396 |
GEN_STX(width, 0x17, op | 0x00, type) |
2397 |
|
2398 |
/* stb stbu stbux stbx */
|
2399 |
GEN_STS(b, 0x06, PPC_INTEGER);
|
2400 |
/* sth sthu sthux sthx */
|
2401 |
GEN_STS(h, 0x0C, PPC_INTEGER);
|
2402 |
/* stw stwu stwux stwx */
|
2403 |
GEN_STS(w, 0x04, PPC_INTEGER);
|
2404 |
#if defined(TARGET_PPC64)
|
2405 |
OP_ST_TABLE(d); |
2406 |
GEN_STUX(d, 0x15, 0x05, PPC_64B); |
2407 |
GEN_STX(d, 0x15, 0x04, PPC_64B); |
2408 |
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) |
2409 |
{ |
2410 |
int rs;
|
2411 |
|
2412 |
rs = rS(ctx->opcode); |
2413 |
if ((ctx->opcode & 0x3) == 0x2) { |
2414 |
#if defined(CONFIG_USER_ONLY)
|
2415 |
GEN_EXCP_PRIVOPC(ctx); |
2416 |
#else
|
2417 |
/* stq */
|
2418 |
if (unlikely(ctx->supervisor == 0)) { |
2419 |
GEN_EXCP_PRIVOPC(ctx); |
2420 |
return;
|
2421 |
} |
2422 |
if (unlikely(rs & 1)) { |
2423 |
GEN_EXCP_INVAL(ctx); |
2424 |
return;
|
2425 |
} |
2426 |
if (unlikely(ctx->mem_idx & 1)) { |
2427 |
/* Little-endian mode is not handled */
|
2428 |
GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2429 |
return;
|
2430 |
} |
2431 |
gen_addr_imm_index(ctx, 0x03);
|
2432 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
|
2433 |
op_ldst(std); |
2434 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); |
2435 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); |
2436 |
op_ldst(std); |
2437 |
#endif
|
2438 |
} else {
|
2439 |
/* std / stdu */
|
2440 |
if (Rc(ctx->opcode)) {
|
2441 |
if (unlikely(rA(ctx->opcode) == 0)) { |
2442 |
GEN_EXCP_INVAL(ctx); |
2443 |
return;
|
2444 |
} |
2445 |
} |
2446 |
gen_addr_imm_index(ctx, 0x03);
|
2447 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
|
2448 |
op_ldst(std); |
2449 |
if (Rc(ctx->opcode))
|
2450 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
2451 |
} |
2452 |
} |
2453 |
#endif
|
2454 |
/*** Integer load and store with byte reverse ***/
|
2455 |
/* lhbrx */
|
2456 |
OP_LD_TABLE(hbr); |
2457 |
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER); |
2458 |
/* lwbrx */
|
2459 |
OP_LD_TABLE(wbr); |
2460 |
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER); |
2461 |
/* sthbrx */
|
2462 |
OP_ST_TABLE(hbr); |
2463 |
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER); |
2464 |
/* stwbrx */
|
2465 |
OP_ST_TABLE(wbr); |
2466 |
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER); |
2467 |
|
2468 |
/*** Integer load and store multiple ***/
|
2469 |
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) |
2470 |
static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
|
2471 |
GEN_MEM_FUNCS(lmw), |
2472 |
}; |
2473 |
static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
|
2474 |
GEN_MEM_FUNCS(stmw), |
2475 |
}; |
2476 |
|
2477 |
/* lmw */
|
2478 |
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
2479 |
{ |
2480 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2481 |
gen_update_nip(ctx, ctx->nip - 4);
|
2482 |
gen_addr_imm_index(ctx, 0);
|
2483 |
op_ldstm(lmw, rD(ctx->opcode)); |
2484 |
} |
2485 |
|
2486 |
/* stmw */
|
2487 |
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
2488 |
{ |
2489 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2490 |
gen_update_nip(ctx, ctx->nip - 4);
|
2491 |
gen_addr_imm_index(ctx, 0);
|
2492 |
op_ldstm(stmw, rS(ctx->opcode)); |
2493 |
} |
2494 |
|
2495 |
/*** Integer load and store strings ***/
|
2496 |
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start) |
2497 |
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb) |
2498 |
/* string load & stores are by definition endian-safe */
|
2499 |
#define gen_op_lswi_le_raw gen_op_lswi_raw
|
2500 |
#define gen_op_lswi_le_user gen_op_lswi_user
|
2501 |
#define gen_op_lswi_le_kernel gen_op_lswi_kernel
|
2502 |
#define gen_op_lswi_le_hypv gen_op_lswi_hypv
|
2503 |
#define gen_op_lswi_le_64_raw gen_op_lswi_raw
|
2504 |
#define gen_op_lswi_le_64_user gen_op_lswi_user
|
2505 |
#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
|
2506 |
#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
|
2507 |
static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
|
2508 |
GEN_MEM_FUNCS(lswi), |
2509 |
}; |
2510 |
#define gen_op_lswx_le_raw gen_op_lswx_raw
|
2511 |
#define gen_op_lswx_le_user gen_op_lswx_user
|
2512 |
#define gen_op_lswx_le_kernel gen_op_lswx_kernel
|
2513 |
#define gen_op_lswx_le_hypv gen_op_lswx_hypv
|
2514 |
#define gen_op_lswx_le_64_raw gen_op_lswx_raw
|
2515 |
#define gen_op_lswx_le_64_user gen_op_lswx_user
|
2516 |
#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
|
2517 |
#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
|
2518 |
static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
|
2519 |
GEN_MEM_FUNCS(lswx), |
2520 |
}; |
2521 |
#define gen_op_stsw_le_raw gen_op_stsw_raw
|
2522 |
#define gen_op_stsw_le_user gen_op_stsw_user
|
2523 |
#define gen_op_stsw_le_kernel gen_op_stsw_kernel
|
2524 |
#define gen_op_stsw_le_hypv gen_op_stsw_hypv
|
2525 |
#define gen_op_stsw_le_64_raw gen_op_stsw_raw
|
2526 |
#define gen_op_stsw_le_64_user gen_op_stsw_user
|
2527 |
#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
|
2528 |
#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
|
2529 |
static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
|
2530 |
GEN_MEM_FUNCS(stsw), |
2531 |
}; |
2532 |
|
2533 |
/* lswi */
|
2534 |
/* PowerPC32 specification says we must generate an exception if
|
2535 |
* rA is in the range of registers to be loaded.
|
2536 |
* In an other hand, IBM says this is valid, but rA won't be loaded.
|
2537 |
* For now, I'll follow the spec...
|
2538 |
*/
|
2539 |
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) |
2540 |
{ |
2541 |
int nb = NB(ctx->opcode);
|
2542 |
int start = rD(ctx->opcode);
|
2543 |
int ra = rA(ctx->opcode);
|
2544 |
int nr;
|
2545 |
|
2546 |
if (nb == 0) |
2547 |
nb = 32;
|
2548 |
nr = nb / 4;
|
2549 |
if (unlikely(((start + nr) > 32 && |
2550 |
start <= ra && (start + nr - 32) > ra) ||
|
2551 |
((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
|
2552 |
GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
2553 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX); |
2554 |
return;
|
2555 |
} |
2556 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2557 |
gen_update_nip(ctx, ctx->nip - 4);
|
2558 |
gen_addr_register(ctx); |
2559 |
tcg_gen_movi_tl(cpu_T[1], nb);
|
2560 |
op_ldsts(lswi, start); |
2561 |
} |
2562 |
|
2563 |
/* lswx */
|
2564 |
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING) |
2565 |
{ |
2566 |
int ra = rA(ctx->opcode);
|
2567 |
int rb = rB(ctx->opcode);
|
2568 |
|
2569 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2570 |
gen_update_nip(ctx, ctx->nip - 4);
|
2571 |
gen_addr_reg_index(ctx); |
2572 |
if (ra == 0) { |
2573 |
ra = rb; |
2574 |
} |
2575 |
gen_op_load_xer_bc(); |
2576 |
op_ldstsx(lswx, rD(ctx->opcode), ra, rb); |
2577 |
} |
2578 |
|
2579 |
/* stswi */
|
2580 |
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) |
2581 |
{ |
2582 |
int nb = NB(ctx->opcode);
|
2583 |
|
2584 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2585 |
gen_update_nip(ctx, ctx->nip - 4);
|
2586 |
gen_addr_register(ctx); |
2587 |
if (nb == 0) |
2588 |
nb = 32;
|
2589 |
tcg_gen_movi_tl(cpu_T[1], nb);
|
2590 |
op_ldsts(stsw, rS(ctx->opcode)); |
2591 |
} |
2592 |
|
2593 |
/* stswx */
|
2594 |
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING) |
2595 |
{ |
2596 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2597 |
gen_update_nip(ctx, ctx->nip - 4);
|
2598 |
gen_addr_reg_index(ctx); |
2599 |
gen_op_load_xer_bc(); |
2600 |
op_ldsts(stsw, rS(ctx->opcode)); |
2601 |
} |
2602 |
|
2603 |
/*** Memory synchronisation ***/
|
2604 |
/* eieio */
|
2605 |
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO) |
2606 |
{ |
2607 |
} |
2608 |
|
2609 |
/* isync */
|
2610 |
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM) |
2611 |
{ |
2612 |
GEN_STOP(ctx); |
2613 |
} |
2614 |
|
2615 |
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
|
2616 |
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
|
2617 |
static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
|
2618 |
GEN_MEM_FUNCS(lwarx), |
2619 |
}; |
2620 |
static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
|
2621 |
GEN_MEM_FUNCS(stwcx), |
2622 |
}; |
2623 |
|
2624 |
/* lwarx */
|
2625 |
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) |
2626 |
{ |
2627 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2628 |
gen_update_nip(ctx, ctx->nip - 4);
|
2629 |
gen_addr_reg_index(ctx); |
2630 |
op_lwarx(); |
2631 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
|
2632 |
} |
2633 |
|
2634 |
/* stwcx. */
|
2635 |
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) |
2636 |
{ |
2637 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2638 |
gen_update_nip(ctx, ctx->nip - 4);
|
2639 |
gen_addr_reg_index(ctx); |
2640 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
2641 |
op_stwcx(); |
2642 |
} |
2643 |
|
2644 |
#if defined(TARGET_PPC64)
|
2645 |
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
|
2646 |
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
|
2647 |
static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
|
2648 |
GEN_MEM_FUNCS(ldarx), |
2649 |
}; |
2650 |
static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
|
2651 |
GEN_MEM_FUNCS(stdcx), |
2652 |
}; |
2653 |
|
2654 |
/* ldarx */
|
2655 |
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) |
2656 |
{ |
2657 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2658 |
gen_update_nip(ctx, ctx->nip - 4);
|
2659 |
gen_addr_reg_index(ctx); |
2660 |
op_ldarx(); |
2661 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
|
2662 |
} |
2663 |
|
2664 |
/* stdcx. */
|
2665 |
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) |
2666 |
{ |
2667 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
2668 |
gen_update_nip(ctx, ctx->nip - 4);
|
2669 |
gen_addr_reg_index(ctx); |
2670 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
2671 |
op_stdcx(); |
2672 |
} |
2673 |
#endif /* defined(TARGET_PPC64) */ |
2674 |
|
2675 |
/* sync */
|
2676 |
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC) |
2677 |
{ |
2678 |
} |
2679 |
|
2680 |
/* wait */
|
2681 |
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT) |
2682 |
{ |
2683 |
/* Stop translation, as the CPU is supposed to sleep from now */
|
2684 |
gen_op_wait(); |
2685 |
GEN_EXCP(ctx, EXCP_HLT, 1);
|
2686 |
} |
2687 |
|
2688 |
/*** Floating-point load ***/
|
2689 |
#define GEN_LDF(width, opc, type) \
|
2690 |
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2691 |
{ \ |
2692 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2693 |
GEN_EXCP_NO_FP(ctx); \ |
2694 |
return; \
|
2695 |
} \ |
2696 |
gen_addr_imm_index(ctx, 0); \
|
2697 |
op_ldst(l##width); \ |
2698 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2699 |
} |
2700 |
|
2701 |
#define GEN_LDUF(width, opc, type) \
|
2702 |
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2703 |
{ \ |
2704 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2705 |
GEN_EXCP_NO_FP(ctx); \ |
2706 |
return; \
|
2707 |
} \ |
2708 |
if (unlikely(rA(ctx->opcode) == 0)) { \ |
2709 |
GEN_EXCP_INVAL(ctx); \ |
2710 |
return; \
|
2711 |
} \ |
2712 |
gen_addr_imm_index(ctx, 0); \
|
2713 |
op_ldst(l##width); \ |
2714 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2715 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2716 |
} |
2717 |
|
2718 |
#define GEN_LDUXF(width, opc, type) \
|
2719 |
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ |
2720 |
{ \ |
2721 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2722 |
GEN_EXCP_NO_FP(ctx); \ |
2723 |
return; \
|
2724 |
} \ |
2725 |
if (unlikely(rA(ctx->opcode) == 0)) { \ |
2726 |
GEN_EXCP_INVAL(ctx); \ |
2727 |
return; \
|
2728 |
} \ |
2729 |
gen_addr_reg_index(ctx); \ |
2730 |
op_ldst(l##width); \ |
2731 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2732 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2733 |
} |
2734 |
|
2735 |
#define GEN_LDXF(width, opc2, opc3, type) \
|
2736 |
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2737 |
{ \ |
2738 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2739 |
GEN_EXCP_NO_FP(ctx); \ |
2740 |
return; \
|
2741 |
} \ |
2742 |
gen_addr_reg_index(ctx); \ |
2743 |
op_ldst(l##width); \ |
2744 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2745 |
} |
2746 |
|
2747 |
#define GEN_LDFS(width, op, type) \
|
2748 |
OP_LD_TABLE(width); \ |
2749 |
GEN_LDF(width, op | 0x20, type); \
|
2750 |
GEN_LDUF(width, op | 0x21, type); \
|
2751 |
GEN_LDUXF(width, op | 0x01, type); \
|
2752 |
GEN_LDXF(width, 0x17, op | 0x00, type) |
2753 |
|
2754 |
/* lfd lfdu lfdux lfdx */
|
2755 |
GEN_LDFS(fd, 0x12, PPC_FLOAT);
|
2756 |
/* lfs lfsu lfsux lfsx */
|
2757 |
GEN_LDFS(fs, 0x10, PPC_FLOAT);
|
2758 |
|
2759 |
/*** Floating-point store ***/
|
2760 |
#define GEN_STF(width, opc, type) \
|
2761 |
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2762 |
{ \ |
2763 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2764 |
GEN_EXCP_NO_FP(ctx); \ |
2765 |
return; \
|
2766 |
} \ |
2767 |
gen_addr_imm_index(ctx, 0); \
|
2768 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2769 |
op_ldst(st##width); \ |
2770 |
} |
2771 |
|
2772 |
#define GEN_STUF(width, opc, type) \
|
2773 |
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2774 |
{ \ |
2775 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2776 |
GEN_EXCP_NO_FP(ctx); \ |
2777 |
return; \
|
2778 |
} \ |
2779 |
if (unlikely(rA(ctx->opcode) == 0)) { \ |
2780 |
GEN_EXCP_INVAL(ctx); \ |
2781 |
return; \
|
2782 |
} \ |
2783 |
gen_addr_imm_index(ctx, 0); \
|
2784 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2785 |
op_ldst(st##width); \ |
2786 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2787 |
} |
2788 |
|
2789 |
#define GEN_STUXF(width, opc, type) \
|
2790 |
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ |
2791 |
{ \ |
2792 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2793 |
GEN_EXCP_NO_FP(ctx); \ |
2794 |
return; \
|
2795 |
} \ |
2796 |
if (unlikely(rA(ctx->opcode) == 0)) { \ |
2797 |
GEN_EXCP_INVAL(ctx); \ |
2798 |
return; \
|
2799 |
} \ |
2800 |
gen_addr_reg_index(ctx); \ |
2801 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2802 |
op_ldst(st##width); \ |
2803 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2804 |
} |
2805 |
|
2806 |
#define GEN_STXF(width, opc2, opc3, type) \
|
2807 |
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2808 |
{ \ |
2809 |
if (unlikely(!ctx->fpu_enabled)) { \
|
2810 |
GEN_EXCP_NO_FP(ctx); \ |
2811 |
return; \
|
2812 |
} \ |
2813 |
gen_addr_reg_index(ctx); \ |
2814 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2815 |
op_ldst(st##width); \ |
2816 |
} |
2817 |
|
2818 |
#define GEN_STFS(width, op, type) \
|
2819 |
OP_ST_TABLE(width); \ |
2820 |
GEN_STF(width, op | 0x20, type); \
|
2821 |
GEN_STUF(width, op | 0x21, type); \
|
2822 |
GEN_STUXF(width, op | 0x01, type); \
|
2823 |
GEN_STXF(width, 0x17, op | 0x00, type) |
2824 |
|
2825 |
/* stfd stfdu stfdux stfdx */
|
2826 |
GEN_STFS(fd, 0x16, PPC_FLOAT);
|
2827 |
/* stfs stfsu stfsux stfsx */
|
2828 |
GEN_STFS(fs, 0x14, PPC_FLOAT);
|
2829 |
|
2830 |
/* Optional: */
|
2831 |
/* stfiwx */
|
2832 |
OP_ST_TABLE(fiw); |
2833 |
GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
2834 |
|
2835 |
/*** Branch ***/
|
2836 |
static always_inline void gen_goto_tb (DisasContext *ctx, int n, |
2837 |
target_ulong dest) |
2838 |
{ |
2839 |
TranslationBlock *tb; |
2840 |
tb = ctx->tb; |
2841 |
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
2842 |
likely(!ctx->singlestep_enabled)) { |
2843 |
tcg_gen_goto_tb(n); |
2844 |
tcg_gen_movi_tl(cpu_T[1], dest);
|
2845 |
#if defined(TARGET_PPC64)
|
2846 |
if (ctx->sf_mode)
|
2847 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3); |
2848 |
else
|
2849 |
#endif
|
2850 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3); |
2851 |
tcg_gen_exit_tb((long)tb + n);
|
2852 |
} else {
|
2853 |
tcg_gen_movi_tl(cpu_T[1], dest);
|
2854 |
#if defined(TARGET_PPC64)
|
2855 |
if (ctx->sf_mode)
|
2856 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3); |
2857 |
else
|
2858 |
#endif
|
2859 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3); |
2860 |
if (unlikely(ctx->singlestep_enabled)) {
|
2861 |
if ((ctx->singlestep_enabled &
|
2862 |
(CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
2863 |
ctx->exception == POWERPC_EXCP_BRANCH) { |
2864 |
target_ulong tmp = ctx->nip; |
2865 |
ctx->nip = dest; |
2866 |
GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
|
2867 |
ctx->nip = tmp; |
2868 |
} |
2869 |
if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
2870 |
gen_update_nip(ctx, dest); |
2871 |
gen_op_debug(); |
2872 |
} |
2873 |
} |
2874 |
tcg_gen_exit_tb(0);
|
2875 |
} |
2876 |
} |
2877 |
|
2878 |
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) |
2879 |
{ |
2880 |
#if defined(TARGET_PPC64)
|
2881 |
if (ctx->sf_mode != 0 && (nip >> 32)) |
2882 |
gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
|
2883 |
else
|
2884 |
#endif
|
2885 |
gen_op_setlr(ctx->nip); |
2886 |
} |
2887 |
|
2888 |
/* b ba bl bla */
|
2889 |
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
2890 |
{ |
2891 |
target_ulong li, target; |
2892 |
|
2893 |
ctx->exception = POWERPC_EXCP_BRANCH; |
2894 |
/* sign extend LI */
|
2895 |
#if defined(TARGET_PPC64)
|
2896 |
if (ctx->sf_mode)
|
2897 |
li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
2898 |
else
|
2899 |
#endif
|
2900 |
li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
2901 |
if (likely(AA(ctx->opcode) == 0)) |
2902 |
target = ctx->nip + li - 4;
|
2903 |
else
|
2904 |
target = li; |
2905 |
#if defined(TARGET_PPC64)
|
2906 |
if (!ctx->sf_mode)
|
2907 |
target = (uint32_t)target; |
2908 |
#endif
|
2909 |
if (LK(ctx->opcode))
|
2910 |
gen_setlr(ctx, ctx->nip); |
2911 |
gen_goto_tb(ctx, 0, target);
|
2912 |
} |
2913 |
|
2914 |
#define BCOND_IM 0 |
2915 |
#define BCOND_LR 1 |
2916 |
#define BCOND_CTR 2 |
2917 |
|
2918 |
static always_inline void gen_bcond (DisasContext *ctx, int type) |
2919 |
{ |
2920 |
target_ulong target = 0;
|
2921 |
target_ulong li; |
2922 |
uint32_t bo = BO(ctx->opcode); |
2923 |
uint32_t bi = BI(ctx->opcode); |
2924 |
uint32_t mask; |
2925 |
|
2926 |
ctx->exception = POWERPC_EXCP_BRANCH; |
2927 |
if ((bo & 0x4) == 0) |
2928 |
gen_op_dec_ctr(); |
2929 |
switch(type) {
|
2930 |
case BCOND_IM:
|
2931 |
li = (target_long)((int16_t)(BD(ctx->opcode))); |
2932 |
if (likely(AA(ctx->opcode) == 0)) { |
2933 |
target = ctx->nip + li - 4;
|
2934 |
} else {
|
2935 |
target = li; |
2936 |
} |
2937 |
#if defined(TARGET_PPC64)
|
2938 |
if (!ctx->sf_mode)
|
2939 |
target = (uint32_t)target; |
2940 |
#endif
|
2941 |
break;
|
2942 |
case BCOND_CTR:
|
2943 |
gen_op_movl_T1_ctr(); |
2944 |
break;
|
2945 |
default:
|
2946 |
case BCOND_LR:
|
2947 |
gen_op_movl_T1_lr(); |
2948 |
break;
|
2949 |
} |
2950 |
if (LK(ctx->opcode))
|
2951 |
gen_setlr(ctx, ctx->nip); |
2952 |
if (bo & 0x10) { |
2953 |
/* No CR condition */
|
2954 |
switch (bo & 0x6) { |
2955 |
case 0: |
2956 |
#if defined(TARGET_PPC64)
|
2957 |
if (ctx->sf_mode)
|
2958 |
gen_op_test_ctr_64(); |
2959 |
else
|
2960 |
#endif
|
2961 |
gen_op_test_ctr(); |
2962 |
break;
|
2963 |
case 2: |
2964 |
#if defined(TARGET_PPC64)
|
2965 |
if (ctx->sf_mode)
|
2966 |
gen_op_test_ctrz_64(); |
2967 |
else
|
2968 |
#endif
|
2969 |
gen_op_test_ctrz(); |
2970 |
break;
|
2971 |
default:
|
2972 |
case 4: |
2973 |
case 6: |
2974 |
if (type == BCOND_IM) {
|
2975 |
gen_goto_tb(ctx, 0, target);
|
2976 |
return;
|
2977 |
} else {
|
2978 |
#if defined(TARGET_PPC64)
|
2979 |
if (ctx->sf_mode)
|
2980 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3); |
2981 |
else
|
2982 |
#endif
|
2983 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3); |
2984 |
goto no_test;
|
2985 |
} |
2986 |
break;
|
2987 |
} |
2988 |
} else {
|
2989 |
mask = 1 << (3 - (bi & 0x03)); |
2990 |
tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]); |
2991 |
if (bo & 0x8) { |
2992 |
switch (bo & 0x6) { |
2993 |
case 0: |
2994 |
#if defined(TARGET_PPC64)
|
2995 |
if (ctx->sf_mode)
|
2996 |
gen_op_test_ctr_true_64(mask); |
2997 |
else
|
2998 |
#endif
|
2999 |
gen_op_test_ctr_true(mask); |
3000 |
break;
|
3001 |
case 2: |
3002 |
#if defined(TARGET_PPC64)
|
3003 |
if (ctx->sf_mode)
|
3004 |
gen_op_test_ctrz_true_64(mask); |
3005 |
else
|
3006 |
#endif
|
3007 |
gen_op_test_ctrz_true(mask); |
3008 |
break;
|
3009 |
default:
|
3010 |
case 4: |
3011 |
case 6: |
3012 |
gen_op_test_true(mask); |
3013 |
break;
|
3014 |
} |
3015 |
} else {
|
3016 |
switch (bo & 0x6) { |
3017 |
case 0: |
3018 |
#if defined(TARGET_PPC64)
|
3019 |
if (ctx->sf_mode)
|
3020 |
gen_op_test_ctr_false_64(mask); |
3021 |
else
|
3022 |
#endif
|
3023 |
gen_op_test_ctr_false(mask); |
3024 |
break;
|
3025 |
case 2: |
3026 |
#if defined(TARGET_PPC64)
|
3027 |
if (ctx->sf_mode)
|
3028 |
gen_op_test_ctrz_false_64(mask); |
3029 |
else
|
3030 |
#endif
|
3031 |
gen_op_test_ctrz_false(mask); |
3032 |
break;
|
3033 |
default:
|
3034 |
case 4: |
3035 |
case 6: |
3036 |
gen_op_test_false(mask); |
3037 |
break;
|
3038 |
} |
3039 |
} |
3040 |
} |
3041 |
if (type == BCOND_IM) {
|
3042 |
int l1 = gen_new_label();
|
3043 |
gen_op_jz_T0(l1); |
3044 |
gen_goto_tb(ctx, 0, target);
|
3045 |
gen_set_label(l1); |
3046 |
gen_goto_tb(ctx, 1, ctx->nip);
|
3047 |
} else {
|
3048 |
#if defined(TARGET_PPC64)
|
3049 |
if (ctx->sf_mode)
|
3050 |
gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
|
3051 |
else
|
3052 |
#endif
|
3053 |
gen_op_btest_T1(ctx->nip); |
3054 |
no_test:
|
3055 |
if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
3056 |
gen_update_nip(ctx, ctx->nip); |
3057 |
gen_op_debug(); |
3058 |
} |
3059 |
tcg_gen_exit_tb(0);
|
3060 |
} |
3061 |
} |
3062 |
|
3063 |
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
3064 |
{ |
3065 |
gen_bcond(ctx, BCOND_IM); |
3066 |
} |
3067 |
|
3068 |
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) |
3069 |
{ |
3070 |
gen_bcond(ctx, BCOND_CTR); |
3071 |
} |
3072 |
|
3073 |
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) |
3074 |
{ |
3075 |
gen_bcond(ctx, BCOND_LR); |
3076 |
} |
3077 |
|
3078 |
/*** Condition register logical ***/
|
3079 |
#define GEN_CRLOGIC(op, opc) \
|
3080 |
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ |
3081 |
{ \ |
3082 |
uint8_t bitmask; \ |
3083 |
int sh; \
|
3084 |
tcg_gen_mov_i32(cpu_T[0], cpu_crf[crbA(ctx->opcode) >> 2]); \ |
3085 |
sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3086 |
if (sh > 0) \ |
3087 |
gen_op_srli_T0(sh); \ |
3088 |
else if (sh < 0) \ |
3089 |
gen_op_sli_T0(-sh); \ |
3090 |
tcg_gen_mov_i32(cpu_T[1], cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3091 |
sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3092 |
if (sh > 0) \ |
3093 |
gen_op_srli_T1(sh); \ |
3094 |
else if (sh < 0) \ |
3095 |
gen_op_sli_T1(-sh); \ |
3096 |
gen_op_##op(); \ |
3097 |
bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
3098 |
gen_op_andi_T0(bitmask); \ |
3099 |
tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ |
3100 |
gen_op_or(); \ |
3101 |
tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf); \ |
3102 |
} |
3103 |
|
3104 |
/* crand */
|
3105 |
GEN_CRLOGIC(and, 0x08);
|
3106 |
/* crandc */
|
3107 |
GEN_CRLOGIC(andc, 0x04);
|
3108 |
/* creqv */
|
3109 |
GEN_CRLOGIC(eqv, 0x09);
|
3110 |
/* crnand */
|
3111 |
GEN_CRLOGIC(nand, 0x07);
|
3112 |
/* crnor */
|
3113 |
GEN_CRLOGIC(nor, 0x01);
|
3114 |
/* cror */
|
3115 |
GEN_CRLOGIC(or, 0x0E);
|
3116 |
/* crorc */
|
3117 |
GEN_CRLOGIC(orc, 0x0D);
|
3118 |
/* crxor */
|
3119 |
GEN_CRLOGIC(xor, 0x06);
|
3120 |
/* mcrf */
|
3121 |
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) |
3122 |
{ |
3123 |
tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
3124 |
} |
3125 |
|
3126 |
/*** System linkage ***/
|
3127 |
/* rfi (supervisor only) */
|
3128 |
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) |
3129 |
{ |
3130 |
#if defined(CONFIG_USER_ONLY)
|
3131 |
GEN_EXCP_PRIVOPC(ctx); |
3132 |
#else
|
3133 |
/* Restore CPU state */
|
3134 |
if (unlikely(!ctx->supervisor)) {
|
3135 |
GEN_EXCP_PRIVOPC(ctx); |
3136 |
return;
|
3137 |
} |
3138 |
gen_op_rfi(); |
3139 |
GEN_SYNC(ctx); |
3140 |
#endif
|
3141 |
} |
3142 |
|
3143 |
#if defined(TARGET_PPC64)
|
3144 |
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B) |
3145 |
{ |
3146 |
#if defined(CONFIG_USER_ONLY)
|
3147 |
GEN_EXCP_PRIVOPC(ctx); |
3148 |
#else
|
3149 |
/* Restore CPU state */
|
3150 |
if (unlikely(!ctx->supervisor)) {
|
3151 |
GEN_EXCP_PRIVOPC(ctx); |
3152 |
return;
|
3153 |
} |
3154 |
gen_op_rfid(); |
3155 |
GEN_SYNC(ctx); |
3156 |
#endif
|
3157 |
} |
3158 |
|
3159 |
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H) |
3160 |
{ |
3161 |
#if defined(CONFIG_USER_ONLY)
|
3162 |
GEN_EXCP_PRIVOPC(ctx); |
3163 |
#else
|
3164 |
/* Restore CPU state */
|
3165 |
if (unlikely(ctx->supervisor <= 1)) { |
3166 |
GEN_EXCP_PRIVOPC(ctx); |
3167 |
return;
|
3168 |
} |
3169 |
gen_op_hrfid(); |
3170 |
GEN_SYNC(ctx); |
3171 |
#endif
|
3172 |
} |
3173 |
#endif
|
3174 |
|
3175 |
/* sc */
|
3176 |
#if defined(CONFIG_USER_ONLY)
|
3177 |
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
|
3178 |
#else
|
3179 |
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
|
3180 |
#endif
|
3181 |
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) |
3182 |
{ |
3183 |
uint32_t lev; |
3184 |
|
3185 |
lev = (ctx->opcode >> 5) & 0x7F; |
3186 |
GEN_EXCP(ctx, POWERPC_SYSCALL, lev); |
3187 |
} |
3188 |
|
3189 |
/*** Trap ***/
|
3190 |
/* tw */
|
3191 |
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) |
3192 |
{ |
3193 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3194 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3195 |
/* Update the nip since this might generate a trap exception */
|
3196 |
gen_update_nip(ctx, ctx->nip); |
3197 |
gen_op_tw(TO(ctx->opcode)); |
3198 |
} |
3199 |
|
3200 |
/* twi */
|
3201 |
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
3202 |
{ |
3203 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3204 |
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
3205 |
/* Update the nip since this might generate a trap exception */
|
3206 |
gen_update_nip(ctx, ctx->nip); |
3207 |
gen_op_tw(TO(ctx->opcode)); |
3208 |
} |
3209 |
|
3210 |
#if defined(TARGET_PPC64)
|
3211 |
/* td */
|
3212 |
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) |
3213 |
{ |
3214 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3215 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3216 |
/* Update the nip since this might generate a trap exception */
|
3217 |
gen_update_nip(ctx, ctx->nip); |
3218 |
gen_op_td(TO(ctx->opcode)); |
3219 |
} |
3220 |
|
3221 |
/* tdi */
|
3222 |
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) |
3223 |
{ |
3224 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3225 |
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
3226 |
/* Update the nip since this might generate a trap exception */
|
3227 |
gen_update_nip(ctx, ctx->nip); |
3228 |
gen_op_td(TO(ctx->opcode)); |
3229 |
} |
3230 |
#endif
|
3231 |
|
3232 |
/*** Processor control ***/
|
3233 |
/* mcrxr */
|
3234 |
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) |
3235 |
{ |
3236 |
gen_op_load_xer_cr(); |
3237 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); |
3238 |
gen_op_clear_xer_ov(); |
3239 |
gen_op_clear_xer_ca(); |
3240 |
} |
3241 |
|
3242 |
/* mfcr */
|
3243 |
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) |
3244 |
{ |
3245 |
uint32_t crm, crn; |
3246 |
|
3247 |
if (likely(ctx->opcode & 0x00100000)) { |
3248 |
crm = CRM(ctx->opcode); |
3249 |
if (likely((crm ^ (crm - 1)) == 0)) { |
3250 |
crn = ffs(crm); |
3251 |
tcg_gen_mov_i32(cpu_T[0], cpu_crf[7 - crn]); |
3252 |
} |
3253 |
} else {
|
3254 |
gen_op_load_cr(); |
3255 |
} |
3256 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3257 |
} |
3258 |
|
3259 |
/* mfmsr */
|
3260 |
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) |
3261 |
{ |
3262 |
#if defined(CONFIG_USER_ONLY)
|
3263 |
GEN_EXCP_PRIVREG(ctx); |
3264 |
#else
|
3265 |
if (unlikely(!ctx->supervisor)) {
|
3266 |
GEN_EXCP_PRIVREG(ctx); |
3267 |
return;
|
3268 |
} |
3269 |
gen_op_load_msr(); |
3270 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3271 |
#endif
|
3272 |
} |
3273 |
|
3274 |
#if 1 |
3275 |
#define SPR_NOACCESS ((void *)(-1UL)) |
3276 |
#else
|
3277 |
static void spr_noaccess (void *opaque, int sprn) |
3278 |
{ |
3279 |
sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3280 |
printf("ERROR: try to access SPR %d !\n", sprn);
|
3281 |
} |
3282 |
#define SPR_NOACCESS (&spr_noaccess)
|
3283 |
#endif
|
3284 |
|
3285 |
/* mfspr */
|
3286 |
static always_inline void gen_op_mfspr (DisasContext *ctx) |
3287 |
{ |
3288 |
void (*read_cb)(void *opaque, int sprn); |
3289 |
uint32_t sprn = SPR(ctx->opcode); |
3290 |
|
3291 |
#if !defined(CONFIG_USER_ONLY)
|
3292 |
if (ctx->supervisor == 2) |
3293 |
read_cb = ctx->spr_cb[sprn].hea_read; |
3294 |
else if (ctx->supervisor) |
3295 |
read_cb = ctx->spr_cb[sprn].oea_read; |
3296 |
else
|
3297 |
#endif
|
3298 |
read_cb = ctx->spr_cb[sprn].uea_read; |
3299 |
if (likely(read_cb != NULL)) { |
3300 |
if (likely(read_cb != SPR_NOACCESS)) {
|
3301 |
(*read_cb)(ctx, sprn); |
3302 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3303 |
} else {
|
3304 |
/* Privilege exception */
|
3305 |
/* This is a hack to avoid warnings when running Linux:
|
3306 |
* this OS breaks the PowerPC virtualisation model,
|
3307 |
* allowing userland application to read the PVR
|
3308 |
*/
|
3309 |
if (sprn != SPR_PVR) {
|
3310 |
if (loglevel != 0) { |
3311 |
fprintf(logfile, "Trying to read privileged spr %d %03x at "
|
3312 |
ADDRX "\n", sprn, sprn, ctx->nip);
|
3313 |
} |
3314 |
printf("Trying to read privileged spr %d %03x at " ADDRX "\n", |
3315 |
sprn, sprn, ctx->nip); |
3316 |
} |
3317 |
GEN_EXCP_PRIVREG(ctx); |
3318 |
} |
3319 |
} else {
|
3320 |
/* Not defined */
|
3321 |
if (loglevel != 0) { |
3322 |
fprintf(logfile, "Trying to read invalid spr %d %03x at "
|
3323 |
ADDRX "\n", sprn, sprn, ctx->nip);
|
3324 |
} |
3325 |
printf("Trying to read invalid spr %d %03x at " ADDRX "\n", |
3326 |
sprn, sprn, ctx->nip); |
3327 |
GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
3328 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); |
3329 |
} |
3330 |
} |
3331 |
|
3332 |
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
3333 |
{ |
3334 |
gen_op_mfspr(ctx); |
3335 |
} |
3336 |
|
3337 |
/* mftb */
|
3338 |
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB) |
3339 |
{ |
3340 |
gen_op_mfspr(ctx); |
3341 |
} |
3342 |
|
3343 |
/* mtcrf */
|
3344 |
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) |
3345 |
{ |
3346 |
uint32_t crm, crn; |
3347 |
|
3348 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3349 |
crm = CRM(ctx->opcode); |
3350 |
if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { |
3351 |
crn = ffs(crm); |
3352 |
gen_op_srli_T0(crn * 4);
|
3353 |
tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_T[0], 0xf); |
3354 |
} else {
|
3355 |
gen_op_store_cr(crm); |
3356 |
} |
3357 |
} |
3358 |
|
3359 |
/* mtmsr */
|
3360 |
#if defined(TARGET_PPC64)
|
3361 |
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) |
3362 |
{ |
3363 |
#if defined(CONFIG_USER_ONLY)
|
3364 |
GEN_EXCP_PRIVREG(ctx); |
3365 |
#else
|
3366 |
if (unlikely(!ctx->supervisor)) {
|
3367 |
GEN_EXCP_PRIVREG(ctx); |
3368 |
return;
|
3369 |
} |
3370 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3371 |
if (ctx->opcode & 0x00010000) { |
3372 |
/* Special form that does not need any synchronisation */
|
3373 |
gen_op_update_riee(); |
3374 |
} else {
|
3375 |
/* XXX: we need to update nip before the store
|
3376 |
* if we enter power saving mode, we will exit the loop
|
3377 |
* directly from ppc_store_msr
|
3378 |
*/
|
3379 |
gen_update_nip(ctx, ctx->nip); |
3380 |
gen_op_store_msr(); |
3381 |
/* Must stop the translation as machine state (may have) changed */
|
3382 |
/* Note that mtmsr is not always defined as context-synchronizing */
|
3383 |
ctx->exception = POWERPC_EXCP_STOP; |
3384 |
} |
3385 |
#endif
|
3386 |
} |
3387 |
#endif
|
3388 |
|
3389 |
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) |
3390 |
{ |
3391 |
#if defined(CONFIG_USER_ONLY)
|
3392 |
GEN_EXCP_PRIVREG(ctx); |
3393 |
#else
|
3394 |
if (unlikely(!ctx->supervisor)) {
|
3395 |
GEN_EXCP_PRIVREG(ctx); |
3396 |
return;
|
3397 |
} |
3398 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3399 |
if (ctx->opcode & 0x00010000) { |
3400 |
/* Special form that does not need any synchronisation */
|
3401 |
gen_op_update_riee(); |
3402 |
} else {
|
3403 |
/* XXX: we need to update nip before the store
|
3404 |
* if we enter power saving mode, we will exit the loop
|
3405 |
* directly from ppc_store_msr
|
3406 |
*/
|
3407 |
gen_update_nip(ctx, ctx->nip); |
3408 |
#if defined(TARGET_PPC64)
|
3409 |
if (!ctx->sf_mode)
|
3410 |
gen_op_store_msr_32(); |
3411 |
else
|
3412 |
#endif
|
3413 |
gen_op_store_msr(); |
3414 |
/* Must stop the translation as machine state (may have) changed */
|
3415 |
/* Note that mtmsrd is not always defined as context-synchronizing */
|
3416 |
ctx->exception = POWERPC_EXCP_STOP; |
3417 |
} |
3418 |
#endif
|
3419 |
} |
3420 |
|
3421 |
/* mtspr */
|
3422 |
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
3423 |
{ |
3424 |
void (*write_cb)(void *opaque, int sprn); |
3425 |
uint32_t sprn = SPR(ctx->opcode); |
3426 |
|
3427 |
#if !defined(CONFIG_USER_ONLY)
|
3428 |
if (ctx->supervisor == 2) |
3429 |
write_cb = ctx->spr_cb[sprn].hea_write; |
3430 |
else if (ctx->supervisor) |
3431 |
write_cb = ctx->spr_cb[sprn].oea_write; |
3432 |
else
|
3433 |
#endif
|
3434 |
write_cb = ctx->spr_cb[sprn].uea_write; |
3435 |
if (likely(write_cb != NULL)) { |
3436 |
if (likely(write_cb != SPR_NOACCESS)) {
|
3437 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3438 |
(*write_cb)(ctx, sprn); |
3439 |
} else {
|
3440 |
/* Privilege exception */
|
3441 |
if (loglevel != 0) { |
3442 |
fprintf(logfile, "Trying to write privileged spr %d %03x at "
|
3443 |
ADDRX "\n", sprn, sprn, ctx->nip);
|
3444 |
} |
3445 |
printf("Trying to write privileged spr %d %03x at " ADDRX "\n", |
3446 |
sprn, sprn, ctx->nip); |
3447 |
GEN_EXCP_PRIVREG(ctx); |
3448 |
} |
3449 |
} else {
|
3450 |
/* Not defined */
|
3451 |
if (loglevel != 0) { |
3452 |
fprintf(logfile, "Trying to write invalid spr %d %03x at "
|
3453 |
ADDRX "\n", sprn, sprn, ctx->nip);
|
3454 |
} |
3455 |
printf("Trying to write invalid spr %d %03x at " ADDRX "\n", |
3456 |
sprn, sprn, ctx->nip); |
3457 |
GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
3458 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); |
3459 |
} |
3460 |
} |
3461 |
|
3462 |
/*** Cache management ***/
|
3463 |
/* dcbf */
|
3464 |
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) |
3465 |
{ |
3466 |
/* XXX: specification says this is treated as a load by the MMU */
|
3467 |
gen_addr_reg_index(ctx); |
3468 |
op_ldst(lbz); |
3469 |
} |
3470 |
|
3471 |
/* dcbi (Supervisor only) */
|
3472 |
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) |
3473 |
{ |
3474 |
#if defined(CONFIG_USER_ONLY)
|
3475 |
GEN_EXCP_PRIVOPC(ctx); |
3476 |
#else
|
3477 |
if (unlikely(!ctx->supervisor)) {
|
3478 |
GEN_EXCP_PRIVOPC(ctx); |
3479 |
return;
|
3480 |
} |
3481 |
gen_addr_reg_index(ctx); |
3482 |
/* XXX: specification says this should be treated as a store by the MMU */
|
3483 |
op_ldst(lbz); |
3484 |
op_ldst(stb); |
3485 |
#endif
|
3486 |
} |
3487 |
|
3488 |
/* dcdst */
|
3489 |
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) |
3490 |
{ |
3491 |
/* XXX: specification say this is treated as a load by the MMU */
|
3492 |
gen_addr_reg_index(ctx); |
3493 |
op_ldst(lbz); |
3494 |
} |
3495 |
|
3496 |
/* dcbt */
|
3497 |
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE) |
3498 |
{ |
3499 |
/* interpreted as no-op */
|
3500 |
/* XXX: specification say this is treated as a load by the MMU
|
3501 |
* but does not generate any exception
|
3502 |
*/
|
3503 |
} |
3504 |
|
3505 |
/* dcbtst */
|
3506 |
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE) |
3507 |
{ |
3508 |
/* interpreted as no-op */
|
3509 |
/* XXX: specification say this is treated as a load by the MMU
|
3510 |
* but does not generate any exception
|
3511 |
*/
|
3512 |
} |
3513 |
|
3514 |
/* dcbz */
|
3515 |
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
|
3516 |
static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = { |
3517 |
/* 32 bytes cache line size */
|
3518 |
{ |
3519 |
#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
|
3520 |
#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
|
3521 |
#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
|
3522 |
#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
|
3523 |
#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
|
3524 |
#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
|
3525 |
#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
|
3526 |
#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
|
3527 |
GEN_MEM_FUNCS(dcbz_l32), |
3528 |
}, |
3529 |
/* 64 bytes cache line size */
|
3530 |
{ |
3531 |
#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
|
3532 |
#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
|
3533 |
#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
|
3534 |
#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
|
3535 |
#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
|
3536 |
#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
|
3537 |
#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
|
3538 |
#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
|
3539 |
GEN_MEM_FUNCS(dcbz_l64), |
3540 |
}, |
3541 |
/* 128 bytes cache line size */
|
3542 |
{ |
3543 |
#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
|
3544 |
#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
|
3545 |
#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
|
3546 |
#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
|
3547 |
#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
|
3548 |
#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
|
3549 |
#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
|
3550 |
#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
|
3551 |
GEN_MEM_FUNCS(dcbz_l128), |
3552 |
}, |
3553 |
/* tunable cache line size */
|
3554 |
{ |
3555 |
#define gen_op_dcbz_le_raw gen_op_dcbz_raw
|
3556 |
#define gen_op_dcbz_le_user gen_op_dcbz_user
|
3557 |
#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
|
3558 |
#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
|
3559 |
#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
|
3560 |
#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
|
3561 |
#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
|
3562 |
#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
|
3563 |
GEN_MEM_FUNCS(dcbz), |
3564 |
}, |
3565 |
}; |
3566 |
|
3567 |
static always_inline void handler_dcbz (DisasContext *ctx, |
3568 |
int dcache_line_size)
|
3569 |
{ |
3570 |
int n;
|
3571 |
|
3572 |
switch (dcache_line_size) {
|
3573 |
case 32: |
3574 |
n = 0;
|
3575 |
break;
|
3576 |
case 64: |
3577 |
n = 1;
|
3578 |
break;
|
3579 |
case 128: |
3580 |
n = 2;
|
3581 |
break;
|
3582 |
default:
|
3583 |
n = 3;
|
3584 |
break;
|
3585 |
} |
3586 |
op_dcbz(n); |
3587 |
} |
3588 |
|
3589 |
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ) |
3590 |
{ |
3591 |
gen_addr_reg_index(ctx); |
3592 |
handler_dcbz(ctx, ctx->dcache_line_size); |
3593 |
gen_op_check_reservation(); |
3594 |
} |
3595 |
|
3596 |
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) |
3597 |
{ |
3598 |
gen_addr_reg_index(ctx); |
3599 |
if (ctx->opcode & 0x00200000) |
3600 |
handler_dcbz(ctx, ctx->dcache_line_size); |
3601 |
else
|
3602 |
handler_dcbz(ctx, -1);
|
3603 |
gen_op_check_reservation(); |
3604 |
} |
3605 |
|
3606 |
/* icbi */
|
3607 |
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
|
3608 |
#define gen_op_icbi_le_raw gen_op_icbi_raw
|
3609 |
#define gen_op_icbi_le_user gen_op_icbi_user
|
3610 |
#define gen_op_icbi_le_kernel gen_op_icbi_kernel
|
3611 |
#define gen_op_icbi_le_hypv gen_op_icbi_hypv
|
3612 |
#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
|
3613 |
#define gen_op_icbi_le_64_user gen_op_icbi_64_user
|
3614 |
#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
|
3615 |
#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
|
3616 |
static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
|
3617 |
GEN_MEM_FUNCS(icbi), |
3618 |
}; |
3619 |
|
3620 |
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI) |
3621 |
{ |
3622 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
3623 |
gen_update_nip(ctx, ctx->nip - 4);
|
3624 |
gen_addr_reg_index(ctx); |
3625 |
op_icbi(); |
3626 |
} |
3627 |
|
3628 |
/* Optional: */
|
3629 |
/* dcba */
|
3630 |
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA) |
3631 |
{ |
3632 |
/* interpreted as no-op */
|
3633 |
/* XXX: specification say this is treated as a store by the MMU
|
3634 |
* but does not generate any exception
|
3635 |
*/
|
3636 |
} |
3637 |
|
3638 |
/*** Segment register manipulation ***/
|
3639 |
/* Supervisor only: */
|
3640 |
/* mfsr */
|
3641 |
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) |
3642 |
{ |
3643 |
#if defined(CONFIG_USER_ONLY)
|
3644 |
GEN_EXCP_PRIVREG(ctx); |
3645 |
#else
|
3646 |
if (unlikely(!ctx->supervisor)) {
|
3647 |
GEN_EXCP_PRIVREG(ctx); |
3648 |
return;
|
3649 |
} |
3650 |
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3651 |
gen_op_load_sr(); |
3652 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3653 |
#endif
|
3654 |
} |
3655 |
|
3656 |
/* mfsrin */
|
3657 |
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) |
3658 |
{ |
3659 |
#if defined(CONFIG_USER_ONLY)
|
3660 |
GEN_EXCP_PRIVREG(ctx); |
3661 |
#else
|
3662 |
if (unlikely(!ctx->supervisor)) {
|
3663 |
GEN_EXCP_PRIVREG(ctx); |
3664 |
return;
|
3665 |
} |
3666 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3667 |
gen_op_srli_T1(28);
|
3668 |
gen_op_load_sr(); |
3669 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3670 |
#endif
|
3671 |
} |
3672 |
|
3673 |
/* mtsr */
|
3674 |
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) |
3675 |
{ |
3676 |
#if defined(CONFIG_USER_ONLY)
|
3677 |
GEN_EXCP_PRIVREG(ctx); |
3678 |
#else
|
3679 |
if (unlikely(!ctx->supervisor)) {
|
3680 |
GEN_EXCP_PRIVREG(ctx); |
3681 |
return;
|
3682 |
} |
3683 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3684 |
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3685 |
gen_op_store_sr(); |
3686 |
#endif
|
3687 |
} |
3688 |
|
3689 |
/* mtsrin */
|
3690 |
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) |
3691 |
{ |
3692 |
#if defined(CONFIG_USER_ONLY)
|
3693 |
GEN_EXCP_PRIVREG(ctx); |
3694 |
#else
|
3695 |
if (unlikely(!ctx->supervisor)) {
|
3696 |
GEN_EXCP_PRIVREG(ctx); |
3697 |
return;
|
3698 |
} |
3699 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3700 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3701 |
gen_op_srli_T1(28);
|
3702 |
gen_op_store_sr(); |
3703 |
#endif
|
3704 |
} |
3705 |
|
3706 |
#if defined(TARGET_PPC64)
|
3707 |
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
|
3708 |
/* mfsr */
|
3709 |
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) |
3710 |
{ |
3711 |
#if defined(CONFIG_USER_ONLY)
|
3712 |
GEN_EXCP_PRIVREG(ctx); |
3713 |
#else
|
3714 |
if (unlikely(!ctx->supervisor)) {
|
3715 |
GEN_EXCP_PRIVREG(ctx); |
3716 |
return;
|
3717 |
} |
3718 |
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3719 |
gen_op_load_slb(); |
3720 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3721 |
#endif
|
3722 |
} |
3723 |
|
3724 |
/* mfsrin */
|
3725 |
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
3726 |
PPC_SEGMENT_64B) |
3727 |
{ |
3728 |
#if defined(CONFIG_USER_ONLY)
|
3729 |
GEN_EXCP_PRIVREG(ctx); |
3730 |
#else
|
3731 |
if (unlikely(!ctx->supervisor)) {
|
3732 |
GEN_EXCP_PRIVREG(ctx); |
3733 |
return;
|
3734 |
} |
3735 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3736 |
gen_op_srli_T1(28);
|
3737 |
gen_op_load_slb(); |
3738 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3739 |
#endif
|
3740 |
} |
3741 |
|
3742 |
/* mtsr */
|
3743 |
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) |
3744 |
{ |
3745 |
#if defined(CONFIG_USER_ONLY)
|
3746 |
GEN_EXCP_PRIVREG(ctx); |
3747 |
#else
|
3748 |
if (unlikely(!ctx->supervisor)) {
|
3749 |
GEN_EXCP_PRIVREG(ctx); |
3750 |
return;
|
3751 |
} |
3752 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3753 |
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3754 |
gen_op_store_slb(); |
3755 |
#endif
|
3756 |
} |
3757 |
|
3758 |
/* mtsrin */
|
3759 |
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
3760 |
PPC_SEGMENT_64B) |
3761 |
{ |
3762 |
#if defined(CONFIG_USER_ONLY)
|
3763 |
GEN_EXCP_PRIVREG(ctx); |
3764 |
#else
|
3765 |
if (unlikely(!ctx->supervisor)) {
|
3766 |
GEN_EXCP_PRIVREG(ctx); |
3767 |
return;
|
3768 |
} |
3769 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3770 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3771 |
gen_op_srli_T1(28);
|
3772 |
gen_op_store_slb(); |
3773 |
#endif
|
3774 |
} |
3775 |
#endif /* defined(TARGET_PPC64) */ |
3776 |
|
3777 |
/*** Lookaside buffer management ***/
|
3778 |
/* Optional & supervisor only: */
|
3779 |
/* tlbia */
|
3780 |
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) |
3781 |
{ |
3782 |
#if defined(CONFIG_USER_ONLY)
|
3783 |
GEN_EXCP_PRIVOPC(ctx); |
3784 |
#else
|
3785 |
if (unlikely(!ctx->supervisor)) {
|
3786 |
GEN_EXCP_PRIVOPC(ctx); |
3787 |
return;
|
3788 |
} |
3789 |
gen_op_tlbia(); |
3790 |
#endif
|
3791 |
} |
3792 |
|
3793 |
/* tlbie */
|
3794 |
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) |
3795 |
{ |
3796 |
#if defined(CONFIG_USER_ONLY)
|
3797 |
GEN_EXCP_PRIVOPC(ctx); |
3798 |
#else
|
3799 |
if (unlikely(!ctx->supervisor)) {
|
3800 |
GEN_EXCP_PRIVOPC(ctx); |
3801 |
return;
|
3802 |
} |
3803 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
3804 |
#if defined(TARGET_PPC64)
|
3805 |
if (ctx->sf_mode)
|
3806 |
gen_op_tlbie_64(); |
3807 |
else
|
3808 |
#endif
|
3809 |
gen_op_tlbie(); |
3810 |
#endif
|
3811 |
} |
3812 |
|
3813 |
/* tlbsync */
|
3814 |
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) |
3815 |
{ |
3816 |
#if defined(CONFIG_USER_ONLY)
|
3817 |
GEN_EXCP_PRIVOPC(ctx); |
3818 |
#else
|
3819 |
if (unlikely(!ctx->supervisor)) {
|
3820 |
GEN_EXCP_PRIVOPC(ctx); |
3821 |
return;
|
3822 |
} |
3823 |
/* This has no effect: it should ensure that all previous
|
3824 |
* tlbie have completed
|
3825 |
*/
|
3826 |
GEN_STOP(ctx); |
3827 |
#endif
|
3828 |
} |
3829 |
|
3830 |
#if defined(TARGET_PPC64)
|
3831 |
/* slbia */
|
3832 |
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) |
3833 |
{ |
3834 |
#if defined(CONFIG_USER_ONLY)
|
3835 |
GEN_EXCP_PRIVOPC(ctx); |
3836 |
#else
|
3837 |
if (unlikely(!ctx->supervisor)) {
|
3838 |
GEN_EXCP_PRIVOPC(ctx); |
3839 |
return;
|
3840 |
} |
3841 |
gen_op_slbia(); |
3842 |
#endif
|
3843 |
} |
3844 |
|
3845 |
/* slbie */
|
3846 |
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) |
3847 |
{ |
3848 |
#if defined(CONFIG_USER_ONLY)
|
3849 |
GEN_EXCP_PRIVOPC(ctx); |
3850 |
#else
|
3851 |
if (unlikely(!ctx->supervisor)) {
|
3852 |
GEN_EXCP_PRIVOPC(ctx); |
3853 |
return;
|
3854 |
} |
3855 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
3856 |
gen_op_slbie(); |
3857 |
#endif
|
3858 |
} |
3859 |
#endif
|
3860 |
|
3861 |
/*** External control ***/
|
3862 |
/* Optional: */
|
3863 |
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
|
3864 |
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
|
3865 |
static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
|
3866 |
GEN_MEM_FUNCS(eciwx), |
3867 |
}; |
3868 |
static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
|
3869 |
GEN_MEM_FUNCS(ecowx), |
3870 |
}; |
3871 |
|
3872 |
/* eciwx */
|
3873 |
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) |
3874 |
{ |
3875 |
/* Should check EAR[E] & alignment ! */
|
3876 |
gen_addr_reg_index(ctx); |
3877 |
op_eciwx(); |
3878 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3879 |
} |
3880 |
|
3881 |
/* ecowx */
|
3882 |
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) |
3883 |
{ |
3884 |
/* Should check EAR[E] & alignment ! */
|
3885 |
gen_addr_reg_index(ctx); |
3886 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
3887 |
op_ecowx(); |
3888 |
} |
3889 |
|
3890 |
/* PowerPC 601 specific instructions */
|
3891 |
/* abs - abs. */
|
3892 |
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) |
3893 |
{ |
3894 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3895 |
gen_op_POWER_abs(); |
3896 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3897 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3898 |
gen_set_Rc0(ctx); |
3899 |
} |
3900 |
|
3901 |
/* abso - abso. */
|
3902 |
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) |
3903 |
{ |
3904 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3905 |
gen_op_POWER_abso(); |
3906 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3907 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3908 |
gen_set_Rc0(ctx); |
3909 |
} |
3910 |
|
3911 |
/* clcs */
|
3912 |
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) |
3913 |
{ |
3914 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3915 |
gen_op_POWER_clcs(); |
3916 |
/* Rc=1 sets CR0 to an undefined state */
|
3917 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3918 |
} |
3919 |
|
3920 |
/* div - div. */
|
3921 |
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) |
3922 |
{ |
3923 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3924 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3925 |
gen_op_POWER_div(); |
3926 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3927 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3928 |
gen_set_Rc0(ctx); |
3929 |
} |
3930 |
|
3931 |
/* divo - divo. */
|
3932 |
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) |
3933 |
{ |
3934 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3935 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3936 |
gen_op_POWER_divo(); |
3937 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3938 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3939 |
gen_set_Rc0(ctx); |
3940 |
} |
3941 |
|
3942 |
/* divs - divs. */
|
3943 |
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) |
3944 |
{ |
3945 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3946 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3947 |
gen_op_POWER_divs(); |
3948 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3949 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3950 |
gen_set_Rc0(ctx); |
3951 |
} |
3952 |
|
3953 |
/* divso - divso. */
|
3954 |
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) |
3955 |
{ |
3956 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3957 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3958 |
gen_op_POWER_divso(); |
3959 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3960 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3961 |
gen_set_Rc0(ctx); |
3962 |
} |
3963 |
|
3964 |
/* doz - doz. */
|
3965 |
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) |
3966 |
{ |
3967 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3968 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3969 |
gen_op_POWER_doz(); |
3970 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3971 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3972 |
gen_set_Rc0(ctx); |
3973 |
} |
3974 |
|
3975 |
/* dozo - dozo. */
|
3976 |
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) |
3977 |
{ |
3978 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3979 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3980 |
gen_op_POWER_dozo(); |
3981 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3982 |
if (unlikely(Rc(ctx->opcode) != 0)) |
3983 |
gen_set_Rc0(ctx); |
3984 |
} |
3985 |
|
3986 |
/* dozi */
|
3987 |
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) |
3988 |
{ |
3989 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3990 |
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
3991 |
gen_op_POWER_doz(); |
3992 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3993 |
} |
3994 |
|
3995 |
/* As lscbx load from memory byte after byte, it's always endian safe.
|
3996 |
* Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
|
3997 |
*/
|
3998 |
#define op_POWER_lscbx(start, ra, rb) \
|
3999 |
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb) |
4000 |
#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
|
4001 |
#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
|
4002 |
#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
|
4003 |
#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
|
4004 |
#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
|
4005 |
#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
|
4006 |
#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
|
4007 |
#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
|
4008 |
#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
|
4009 |
#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
|
4010 |
#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
|
4011 |
#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
|
4012 |
static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
|
4013 |
GEN_MEM_FUNCS(POWER_lscbx), |
4014 |
}; |
4015 |
|
4016 |
/* lscbx - lscbx. */
|
4017 |
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) |
4018 |
{ |
4019 |
int ra = rA(ctx->opcode);
|
4020 |
int rb = rB(ctx->opcode);
|
4021 |
|
4022 |
gen_addr_reg_index(ctx); |
4023 |
if (ra == 0) { |
4024 |
ra = rb; |
4025 |
} |
4026 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4027 |
gen_update_nip(ctx, ctx->nip - 4);
|
4028 |
gen_op_load_xer_bc(); |
4029 |
gen_op_load_xer_cmp(); |
4030 |
op_POWER_lscbx(rD(ctx->opcode), ra, rb); |
4031 |
gen_op_store_xer_bc(); |
4032 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4033 |
gen_set_Rc0(ctx); |
4034 |
} |
4035 |
|
4036 |
/* maskg - maskg. */
|
4037 |
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) |
4038 |
{ |
4039 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4040 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4041 |
gen_op_POWER_maskg(); |
4042 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4043 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4044 |
gen_set_Rc0(ctx); |
4045 |
} |
4046 |
|
4047 |
/* maskir - maskir. */
|
4048 |
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) |
4049 |
{ |
4050 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4051 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4052 |
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
4053 |
gen_op_POWER_maskir(); |
4054 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4055 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4056 |
gen_set_Rc0(ctx); |
4057 |
} |
4058 |
|
4059 |
/* mul - mul. */
|
4060 |
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) |
4061 |
{ |
4062 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4063 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4064 |
gen_op_POWER_mul(); |
4065 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4066 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4067 |
gen_set_Rc0(ctx); |
4068 |
} |
4069 |
|
4070 |
/* mulo - mulo. */
|
4071 |
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) |
4072 |
{ |
4073 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4074 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4075 |
gen_op_POWER_mulo(); |
4076 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4077 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4078 |
gen_set_Rc0(ctx); |
4079 |
} |
4080 |
|
4081 |
/* nabs - nabs. */
|
4082 |
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) |
4083 |
{ |
4084 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4085 |
gen_op_POWER_nabs(); |
4086 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4087 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4088 |
gen_set_Rc0(ctx); |
4089 |
} |
4090 |
|
4091 |
/* nabso - nabso. */
|
4092 |
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) |
4093 |
{ |
4094 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4095 |
gen_op_POWER_nabso(); |
4096 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4097 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4098 |
gen_set_Rc0(ctx); |
4099 |
} |
4100 |
|
4101 |
/* rlmi - rlmi. */
|
4102 |
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) |
4103 |
{ |
4104 |
uint32_t mb, me; |
4105 |
|
4106 |
mb = MB(ctx->opcode); |
4107 |
me = ME(ctx->opcode); |
4108 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4109 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
4110 |
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
4111 |
gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); |
4112 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4113 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4114 |
gen_set_Rc0(ctx); |
4115 |
} |
4116 |
|
4117 |
/* rrib - rrib. */
|
4118 |
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) |
4119 |
{ |
4120 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4121 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
4122 |
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
4123 |
gen_op_POWER_rrib(); |
4124 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4125 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4126 |
gen_set_Rc0(ctx); |
4127 |
} |
4128 |
|
4129 |
/* sle - sle. */
|
4130 |
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) |
4131 |
{ |
4132 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4133 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4134 |
gen_op_POWER_sle(); |
4135 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4136 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4137 |
gen_set_Rc0(ctx); |
4138 |
} |
4139 |
|
4140 |
/* sleq - sleq. */
|
4141 |
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) |
4142 |
{ |
4143 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4144 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4145 |
gen_op_POWER_sleq(); |
4146 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4147 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4148 |
gen_set_Rc0(ctx); |
4149 |
} |
4150 |
|
4151 |
/* sliq - sliq. */
|
4152 |
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) |
4153 |
{ |
4154 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4155 |
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4156 |
gen_op_POWER_sle(); |
4157 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4158 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4159 |
gen_set_Rc0(ctx); |
4160 |
} |
4161 |
|
4162 |
/* slliq - slliq. */
|
4163 |
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) |
4164 |
{ |
4165 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4166 |
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4167 |
gen_op_POWER_sleq(); |
4168 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4169 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4170 |
gen_set_Rc0(ctx); |
4171 |
} |
4172 |
|
4173 |
/* sllq - sllq. */
|
4174 |
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) |
4175 |
{ |
4176 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4177 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4178 |
gen_op_POWER_sllq(); |
4179 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4180 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4181 |
gen_set_Rc0(ctx); |
4182 |
} |
4183 |
|
4184 |
/* slq - slq. */
|
4185 |
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) |
4186 |
{ |
4187 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4188 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4189 |
gen_op_POWER_slq(); |
4190 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4191 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4192 |
gen_set_Rc0(ctx); |
4193 |
} |
4194 |
|
4195 |
/* sraiq - sraiq. */
|
4196 |
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) |
4197 |
{ |
4198 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4199 |
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4200 |
gen_op_POWER_sraq(); |
4201 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4202 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4203 |
gen_set_Rc0(ctx); |
4204 |
} |
4205 |
|
4206 |
/* sraq - sraq. */
|
4207 |
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) |
4208 |
{ |
4209 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4210 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4211 |
gen_op_POWER_sraq(); |
4212 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4213 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4214 |
gen_set_Rc0(ctx); |
4215 |
} |
4216 |
|
4217 |
/* sre - sre. */
|
4218 |
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) |
4219 |
{ |
4220 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4221 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4222 |
gen_op_POWER_sre(); |
4223 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4224 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4225 |
gen_set_Rc0(ctx); |
4226 |
} |
4227 |
|
4228 |
/* srea - srea. */
|
4229 |
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) |
4230 |
{ |
4231 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4232 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4233 |
gen_op_POWER_srea(); |
4234 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4235 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4236 |
gen_set_Rc0(ctx); |
4237 |
} |
4238 |
|
4239 |
/* sreq */
|
4240 |
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) |
4241 |
{ |
4242 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4243 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4244 |
gen_op_POWER_sreq(); |
4245 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4246 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4247 |
gen_set_Rc0(ctx); |
4248 |
} |
4249 |
|
4250 |
/* sriq */
|
4251 |
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) |
4252 |
{ |
4253 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4254 |
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4255 |
gen_op_POWER_srq(); |
4256 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4257 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4258 |
gen_set_Rc0(ctx); |
4259 |
} |
4260 |
|
4261 |
/* srliq */
|
4262 |
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) |
4263 |
{ |
4264 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4265 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4266 |
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4267 |
gen_op_POWER_srlq(); |
4268 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4269 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4270 |
gen_set_Rc0(ctx); |
4271 |
} |
4272 |
|
4273 |
/* srlq */
|
4274 |
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) |
4275 |
{ |
4276 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4277 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4278 |
gen_op_POWER_srlq(); |
4279 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4280 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4281 |
gen_set_Rc0(ctx); |
4282 |
} |
4283 |
|
4284 |
/* srq */
|
4285 |
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) |
4286 |
{ |
4287 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4288 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4289 |
gen_op_POWER_srq(); |
4290 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4291 |
if (unlikely(Rc(ctx->opcode) != 0)) |
4292 |
gen_set_Rc0(ctx); |
4293 |
} |
4294 |
|
4295 |
/* PowerPC 602 specific instructions */
|
4296 |
/* dsa */
|
4297 |
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC) |
4298 |
{ |
4299 |
/* XXX: TODO */
|
4300 |
GEN_EXCP_INVAL(ctx); |
4301 |
} |
4302 |
|
4303 |
/* esa */
|
4304 |
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC) |
4305 |
{ |
4306 |
/* XXX: TODO */
|
4307 |
GEN_EXCP_INVAL(ctx); |
4308 |
} |
4309 |
|
4310 |
/* mfrom */
|
4311 |
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) |
4312 |
{ |
4313 |
#if defined(CONFIG_USER_ONLY)
|
4314 |
GEN_EXCP_PRIVOPC(ctx); |
4315 |
#else
|
4316 |
if (unlikely(!ctx->supervisor)) {
|
4317 |
GEN_EXCP_PRIVOPC(ctx); |
4318 |
return;
|
4319 |
} |
4320 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4321 |
gen_op_602_mfrom(); |
4322 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4323 |
#endif
|
4324 |
} |
4325 |
|
4326 |
/* 602 - 603 - G2 TLB management */
|
4327 |
/* tlbld */
|
4328 |
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) |
4329 |
{ |
4330 |
#if defined(CONFIG_USER_ONLY)
|
4331 |
GEN_EXCP_PRIVOPC(ctx); |
4332 |
#else
|
4333 |
if (unlikely(!ctx->supervisor)) {
|
4334 |
GEN_EXCP_PRIVOPC(ctx); |
4335 |
return;
|
4336 |
} |
4337 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4338 |
gen_op_6xx_tlbld(); |
4339 |
#endif
|
4340 |
} |
4341 |
|
4342 |
/* tlbli */
|
4343 |
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) |
4344 |
{ |
4345 |
#if defined(CONFIG_USER_ONLY)
|
4346 |
GEN_EXCP_PRIVOPC(ctx); |
4347 |
#else
|
4348 |
if (unlikely(!ctx->supervisor)) {
|
4349 |
GEN_EXCP_PRIVOPC(ctx); |
4350 |
return;
|
4351 |
} |
4352 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4353 |
gen_op_6xx_tlbli(); |
4354 |
#endif
|
4355 |
} |
4356 |
|
4357 |
/* 74xx TLB management */
|
4358 |
/* tlbld */
|
4359 |
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) |
4360 |
{ |
4361 |
#if defined(CONFIG_USER_ONLY)
|
4362 |
GEN_EXCP_PRIVOPC(ctx); |
4363 |
#else
|
4364 |
if (unlikely(!ctx->supervisor)) {
|
4365 |
GEN_EXCP_PRIVOPC(ctx); |
4366 |
return;
|
4367 |
} |
4368 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4369 |
gen_op_74xx_tlbld(); |
4370 |
#endif
|
4371 |
} |
4372 |
|
4373 |
/* tlbli */
|
4374 |
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) |
4375 |
{ |
4376 |
#if defined(CONFIG_USER_ONLY)
|
4377 |
GEN_EXCP_PRIVOPC(ctx); |
4378 |
#else
|
4379 |
if (unlikely(!ctx->supervisor)) {
|
4380 |
GEN_EXCP_PRIVOPC(ctx); |
4381 |
return;
|
4382 |
} |
4383 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4384 |
gen_op_74xx_tlbli(); |
4385 |
#endif
|
4386 |
} |
4387 |
|
4388 |
/* POWER instructions not in PowerPC 601 */
|
4389 |
/* clf */
|
4390 |
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER) |
4391 |
{ |
4392 |
/* Cache line flush: implemented as no-op */
|
4393 |
} |
4394 |
|
4395 |
/* cli */
|
4396 |
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER) |
4397 |
{ |
4398 |
/* Cache line invalidate: privileged and treated as no-op */
|
4399 |
#if defined(CONFIG_USER_ONLY)
|
4400 |
GEN_EXCP_PRIVOPC(ctx); |
4401 |
#else
|
4402 |
if (unlikely(!ctx->supervisor)) {
|
4403 |
GEN_EXCP_PRIVOPC(ctx); |
4404 |
return;
|
4405 |
} |
4406 |
#endif
|
4407 |
} |
4408 |
|
4409 |
/* dclst */
|
4410 |
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER) |
4411 |
{ |
4412 |
/* Data cache line store: treated as no-op */
|
4413 |
} |
4414 |
|
4415 |
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) |
4416 |
{ |
4417 |
#if defined(CONFIG_USER_ONLY)
|
4418 |
GEN_EXCP_PRIVOPC(ctx); |
4419 |
#else
|
4420 |
if (unlikely(!ctx->supervisor)) {
|
4421 |
GEN_EXCP_PRIVOPC(ctx); |
4422 |
return;
|
4423 |
} |
4424 |
int ra = rA(ctx->opcode);
|
4425 |
int rd = rD(ctx->opcode);
|
4426 |
|
4427 |
gen_addr_reg_index(ctx); |
4428 |
gen_op_POWER_mfsri(); |
4429 |
tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
|
4430 |
if (ra != 0 && ra != rd) |
4431 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
|
4432 |
#endif
|
4433 |
} |
4434 |
|
4435 |
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) |
4436 |
{ |
4437 |
#if defined(CONFIG_USER_ONLY)
|
4438 |
GEN_EXCP_PRIVOPC(ctx); |
4439 |
#else
|
4440 |
if (unlikely(!ctx->supervisor)) {
|
4441 |
GEN_EXCP_PRIVOPC(ctx); |
4442 |
return;
|
4443 |
} |
4444 |
gen_addr_reg_index(ctx); |
4445 |
gen_op_POWER_rac(); |
4446 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4447 |
#endif
|
4448 |
} |
4449 |
|
4450 |
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) |
4451 |
{ |
4452 |
#if defined(CONFIG_USER_ONLY)
|
4453 |
GEN_EXCP_PRIVOPC(ctx); |
4454 |
#else
|
4455 |
if (unlikely(!ctx->supervisor)) {
|
4456 |
GEN_EXCP_PRIVOPC(ctx); |
4457 |
return;
|
4458 |
} |
4459 |
gen_op_POWER_rfsvc(); |
4460 |
GEN_SYNC(ctx); |
4461 |
#endif
|
4462 |
} |
4463 |
|
4464 |
/* svc is not implemented for now */
|
4465 |
|
4466 |
/* POWER2 specific instructions */
|
4467 |
/* Quad manipulation (load/store two floats at a time) */
|
4468 |
/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
|
4469 |
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
|
4470 |
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
|
4471 |
#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
|
4472 |
#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
|
4473 |
#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
|
4474 |
#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
|
4475 |
#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
|
4476 |
#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
|
4477 |
#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
|
4478 |
#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
|
4479 |
#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
|
4480 |
#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
|
4481 |
#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
|
4482 |
#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
|
4483 |
#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
|
4484 |
#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
|
4485 |
#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
|
4486 |
#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
|
4487 |
static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
|
4488 |
GEN_MEM_FUNCS(POWER2_lfq), |
4489 |
}; |
4490 |
static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
|
4491 |
GEN_MEM_FUNCS(POWER2_stfq), |
4492 |
}; |
4493 |
|
4494 |
/* lfq */
|
4495 |
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4496 |
{ |
4497 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4498 |
gen_update_nip(ctx, ctx->nip - 4);
|
4499 |
gen_addr_imm_index(ctx, 0);
|
4500 |
op_POWER2_lfq(); |
4501 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4502 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4503 |
} |
4504 |
|
4505 |
/* lfqu */
|
4506 |
GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4507 |
{ |
4508 |
int ra = rA(ctx->opcode);
|
4509 |
|
4510 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4511 |
gen_update_nip(ctx, ctx->nip - 4);
|
4512 |
gen_addr_imm_index(ctx, 0);
|
4513 |
op_POWER2_lfq(); |
4514 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4515 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4516 |
if (ra != 0) |
4517 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4518 |
} |
4519 |
|
4520 |
/* lfqux */
|
4521 |
GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) |
4522 |
{ |
4523 |
int ra = rA(ctx->opcode);
|
4524 |
|
4525 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4526 |
gen_update_nip(ctx, ctx->nip - 4);
|
4527 |
gen_addr_reg_index(ctx); |
4528 |
op_POWER2_lfq(); |
4529 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4530 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4531 |
if (ra != 0) |
4532 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4533 |
} |
4534 |
|
4535 |
/* lfqx */
|
4536 |
GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) |
4537 |
{ |
4538 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4539 |
gen_update_nip(ctx, ctx->nip - 4);
|
4540 |
gen_addr_reg_index(ctx); |
4541 |
op_POWER2_lfq(); |
4542 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4543 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4544 |
} |
4545 |
|
4546 |
/* stfq */
|
4547 |
GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4548 |
{ |
4549 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4550 |
gen_update_nip(ctx, ctx->nip - 4);
|
4551 |
gen_addr_imm_index(ctx, 0);
|
4552 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4553 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4554 |
op_POWER2_stfq(); |
4555 |
} |
4556 |
|
4557 |
/* stfqu */
|
4558 |
GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4559 |
{ |
4560 |
int ra = rA(ctx->opcode);
|
4561 |
|
4562 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4563 |
gen_update_nip(ctx, ctx->nip - 4);
|
4564 |
gen_addr_imm_index(ctx, 0);
|
4565 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4566 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4567 |
op_POWER2_stfq(); |
4568 |
if (ra != 0) |
4569 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4570 |
} |
4571 |
|
4572 |
/* stfqux */
|
4573 |
GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) |
4574 |
{ |
4575 |
int ra = rA(ctx->opcode);
|
4576 |
|
4577 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4578 |
gen_update_nip(ctx, ctx->nip - 4);
|
4579 |
gen_addr_reg_index(ctx); |
4580 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4581 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4582 |
op_POWER2_stfq(); |
4583 |
if (ra != 0) |
4584 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4585 |
} |
4586 |
|
4587 |
/* stfqx */
|
4588 |
GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) |
4589 |
{ |
4590 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
4591 |
gen_update_nip(ctx, ctx->nip - 4);
|
4592 |
gen_addr_reg_index(ctx); |
4593 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4594 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4595 |
op_POWER2_stfq(); |
4596 |
} |
4597 |
|
4598 |
/* BookE specific instructions */
|
4599 |
/* XXX: not implemented on 440 ? */
|
4600 |
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI) |
4601 |
{ |
4602 |
/* XXX: TODO */
|
4603 |
GEN_EXCP_INVAL(ctx); |
4604 |
} |
4605 |
|
4606 |
/* XXX: not implemented on 440 ? */
|
4607 |
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA) |
4608 |
{ |
4609 |
#if defined(CONFIG_USER_ONLY)
|
4610 |
GEN_EXCP_PRIVOPC(ctx); |
4611 |
#else
|
4612 |
if (unlikely(!ctx->supervisor)) {
|
4613 |
GEN_EXCP_PRIVOPC(ctx); |
4614 |
return;
|
4615 |
} |
4616 |
gen_addr_reg_index(ctx); |
4617 |
/* Use the same micro-ops as for tlbie */
|
4618 |
#if defined(TARGET_PPC64)
|
4619 |
if (ctx->sf_mode)
|
4620 |
gen_op_tlbie_64(); |
4621 |
else
|
4622 |
#endif
|
4623 |
gen_op_tlbie(); |
4624 |
#endif
|
4625 |
} |
4626 |
|
4627 |
/* All 405 MAC instructions are translated here */
|
4628 |
static always_inline void gen_405_mulladd_insn (DisasContext *ctx, |
4629 |
int opc2, int opc3, |
4630 |
int ra, int rb, int rt, int Rc) |
4631 |
{ |
4632 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
|
4633 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
|
4634 |
switch (opc3 & 0x0D) { |
4635 |
case 0x05: |
4636 |
/* macchw - macchw. - macchwo - macchwo. */
|
4637 |
/* macchws - macchws. - macchwso - macchwso. */
|
4638 |
/* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
|
4639 |
/* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
|
4640 |
/* mulchw - mulchw. */
|
4641 |
gen_op_405_mulchw(); |
4642 |
break;
|
4643 |
case 0x04: |
4644 |
/* macchwu - macchwu. - macchwuo - macchwuo. */
|
4645 |
/* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
|
4646 |
/* mulchwu - mulchwu. */
|
4647 |
gen_op_405_mulchwu(); |
4648 |
break;
|
4649 |
case 0x01: |
4650 |
/* machhw - machhw. - machhwo - machhwo. */
|
4651 |
/* machhws - machhws. - machhwso - machhwso. */
|
4652 |
/* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
|
4653 |
/* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
|
4654 |
/* mulhhw - mulhhw. */
|
4655 |
gen_op_405_mulhhw(); |
4656 |
break;
|
4657 |
case 0x00: |
4658 |
/* machhwu - machhwu. - machhwuo - machhwuo. */
|
4659 |
/* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
|
4660 |
/* mulhhwu - mulhhwu. */
|
4661 |
gen_op_405_mulhhwu(); |
4662 |
break;
|
4663 |
case 0x0D: |
4664 |
/* maclhw - maclhw. - maclhwo - maclhwo. */
|
4665 |
/* maclhws - maclhws. - maclhwso - maclhwso. */
|
4666 |
/* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
|
4667 |
/* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
|
4668 |
/* mullhw - mullhw. */
|
4669 |
gen_op_405_mullhw(); |
4670 |
break;
|
4671 |
case 0x0C: |
4672 |
/* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
|
4673 |
/* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
|
4674 |
/* mullhwu - mullhwu. */
|
4675 |
gen_op_405_mullhwu(); |
4676 |
break;
|
4677 |
} |
4678 |
if (opc2 & 0x02) { |
4679 |
/* nmultiply-and-accumulate (0x0E) */
|
4680 |
gen_op_neg(); |
4681 |
} |
4682 |
if (opc2 & 0x04) { |
4683 |
/* (n)multiply-and-accumulate (0x0C - 0x0E) */
|
4684 |
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
|
4685 |
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
4686 |
gen_op_405_add_T0_T2(); |
4687 |
} |
4688 |
if (opc3 & 0x10) { |
4689 |
/* Check overflow */
|
4690 |
if (opc3 & 0x01) |
4691 |
gen_op_check_addo(); |
4692 |
else
|
4693 |
gen_op_405_check_ovu(); |
4694 |
} |
4695 |
if (opc3 & 0x02) { |
4696 |
/* Saturate */
|
4697 |
if (opc3 & 0x01) |
4698 |
gen_op_405_check_sat(); |
4699 |
else
|
4700 |
gen_op_405_check_satu(); |
4701 |
} |
4702 |
tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
|
4703 |
if (unlikely(Rc) != 0) { |
4704 |
/* Update Rc0 */
|
4705 |
gen_set_Rc0(ctx); |
4706 |
} |
4707 |
} |
4708 |
|
4709 |
#define GEN_MAC_HANDLER(name, opc2, opc3) \
|
4710 |
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ |
4711 |
{ \ |
4712 |
gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
4713 |
rD(ctx->opcode), Rc(ctx->opcode)); \ |
4714 |
} |
4715 |
|
4716 |
/* macchw - macchw. */
|
4717 |
GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
4718 |
/* macchwo - macchwo. */
|
4719 |
GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
4720 |
/* macchws - macchws. */
|
4721 |
GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
4722 |
/* macchwso - macchwso. */
|
4723 |
GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
4724 |
/* macchwsu - macchwsu. */
|
4725 |
GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
4726 |
/* macchwsuo - macchwsuo. */
|
4727 |
GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
4728 |
/* macchwu - macchwu. */
|
4729 |
GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
4730 |
/* macchwuo - macchwuo. */
|
4731 |
GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
4732 |
/* machhw - machhw. */
|
4733 |
GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
4734 |
/* machhwo - machhwo. */
|
4735 |
GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
4736 |
/* machhws - machhws. */
|
4737 |
GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
4738 |
/* machhwso - machhwso. */
|
4739 |
GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
4740 |
/* machhwsu - machhwsu. */
|
4741 |
GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
4742 |
/* machhwsuo - machhwsuo. */
|
4743 |
GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
4744 |
/* machhwu - machhwu. */
|
4745 |
GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
4746 |
/* machhwuo - machhwuo. */
|
4747 |
GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
4748 |
/* maclhw - maclhw. */
|
4749 |
GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
4750 |
/* maclhwo - maclhwo. */
|
4751 |
GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
4752 |
/* maclhws - maclhws. */
|
4753 |
GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
4754 |
/* maclhwso - maclhwso. */
|
4755 |
GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
4756 |
/* maclhwu - maclhwu. */
|
4757 |
GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
4758 |
/* maclhwuo - maclhwuo. */
|
4759 |
GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
4760 |
/* maclhwsu - maclhwsu. */
|
4761 |
GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
4762 |
/* maclhwsuo - maclhwsuo. */
|
4763 |
GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
4764 |
/* nmacchw - nmacchw. */
|
4765 |
GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
4766 |
/* nmacchwo - nmacchwo. */
|
4767 |
GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
4768 |
/* nmacchws - nmacchws. */
|
4769 |
GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
4770 |
/* nmacchwso - nmacchwso. */
|
4771 |
GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
4772 |
/* nmachhw - nmachhw. */
|
4773 |
GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
4774 |
/* nmachhwo - nmachhwo. */
|
4775 |
GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
4776 |
/* nmachhws - nmachhws. */
|
4777 |
GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
4778 |
/* nmachhwso - nmachhwso. */
|
4779 |
GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
4780 |
/* nmaclhw - nmaclhw. */
|
4781 |
GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
4782 |
/* nmaclhwo - nmaclhwo. */
|
4783 |
GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
4784 |
/* nmaclhws - nmaclhws. */
|
4785 |
GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
4786 |
/* nmaclhwso - nmaclhwso. */
|
4787 |
GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
4788 |
|
4789 |
/* mulchw - mulchw. */
|
4790 |
GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
4791 |
/* mulchwu - mulchwu. */
|
4792 |
GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
4793 |
/* mulhhw - mulhhw. */
|
4794 |
GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
4795 |
/* mulhhwu - mulhhwu. */
|
4796 |
GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
4797 |
/* mullhw - mullhw. */
|
4798 |
GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
4799 |
/* mullhwu - mullhwu. */
|
4800 |
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
4801 |
|
4802 |
/* mfdcr */
|
4803 |
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) |
4804 |
{ |
4805 |
#if defined(CONFIG_USER_ONLY)
|
4806 |
GEN_EXCP_PRIVREG(ctx); |
4807 |
#else
|
4808 |
uint32_t dcrn = SPR(ctx->opcode); |
4809 |
|
4810 |
if (unlikely(!ctx->supervisor)) {
|
4811 |
GEN_EXCP_PRIVREG(ctx); |
4812 |
return;
|
4813 |
} |
4814 |
tcg_gen_movi_tl(cpu_T[0], dcrn);
|
4815 |
gen_op_load_dcr(); |
4816 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4817 |
#endif
|
4818 |
} |
4819 |
|
4820 |
/* mtdcr */
|
4821 |
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) |
4822 |
{ |
4823 |
#if defined(CONFIG_USER_ONLY)
|
4824 |
GEN_EXCP_PRIVREG(ctx); |
4825 |
#else
|
4826 |
uint32_t dcrn = SPR(ctx->opcode); |
4827 |
|
4828 |
if (unlikely(!ctx->supervisor)) {
|
4829 |
GEN_EXCP_PRIVREG(ctx); |
4830 |
return;
|
4831 |
} |
4832 |
tcg_gen_movi_tl(cpu_T[0], dcrn);
|
4833 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4834 |
gen_op_store_dcr(); |
4835 |
#endif
|
4836 |
} |
4837 |
|
4838 |
/* mfdcrx */
|
4839 |
/* XXX: not implemented on 440 ? */
|
4840 |
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) |
4841 |
{ |
4842 |
#if defined(CONFIG_USER_ONLY)
|
4843 |
GEN_EXCP_PRIVREG(ctx); |
4844 |
#else
|
4845 |
if (unlikely(!ctx->supervisor)) {
|
4846 |
GEN_EXCP_PRIVREG(ctx); |
4847 |
return;
|
4848 |
} |
4849 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4850 |
gen_op_load_dcr(); |
4851 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4852 |
/* Note: Rc update flag set leads to undefined state of Rc0 */
|
4853 |
#endif
|
4854 |
} |
4855 |
|
4856 |
/* mtdcrx */
|
4857 |
/* XXX: not implemented on 440 ? */
|
4858 |
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) |
4859 |
{ |
4860 |
#if defined(CONFIG_USER_ONLY)
|
4861 |
GEN_EXCP_PRIVREG(ctx); |
4862 |
#else
|
4863 |
if (unlikely(!ctx->supervisor)) {
|
4864 |
GEN_EXCP_PRIVREG(ctx); |
4865 |
return;
|
4866 |
} |
4867 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4868 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4869 |
gen_op_store_dcr(); |
4870 |
/* Note: Rc update flag set leads to undefined state of Rc0 */
|
4871 |
#endif
|
4872 |
} |
4873 |
|
4874 |
/* mfdcrux (PPC 460) : user-mode access to DCR */
|
4875 |
GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) |
4876 |
{ |
4877 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4878 |
gen_op_load_dcr(); |
4879 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4880 |
/* Note: Rc update flag set leads to undefined state of Rc0 */
|
4881 |
} |
4882 |
|
4883 |
/* mtdcrux (PPC 460) : user-mode access to DCR */
|
4884 |
GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) |
4885 |
{ |
4886 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4887 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4888 |
gen_op_store_dcr(); |
4889 |
/* Note: Rc update flag set leads to undefined state of Rc0 */
|
4890 |
} |
4891 |
|
4892 |
/* dccci */
|
4893 |
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) |
4894 |
{ |
4895 |
#if defined(CONFIG_USER_ONLY)
|
4896 |
GEN_EXCP_PRIVOPC(ctx); |
4897 |
#else
|
4898 |
if (unlikely(!ctx->supervisor)) {
|
4899 |
GEN_EXCP_PRIVOPC(ctx); |
4900 |
return;
|
4901 |
} |
4902 |
/* interpreted as no-op */
|
4903 |
#endif
|
4904 |
} |
4905 |
|
4906 |
/* dcread */
|
4907 |
GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) |
4908 |
{ |
4909 |
#if defined(CONFIG_USER_ONLY)
|
4910 |
GEN_EXCP_PRIVOPC(ctx); |
4911 |
#else
|
4912 |
if (unlikely(!ctx->supervisor)) {
|
4913 |
GEN_EXCP_PRIVOPC(ctx); |
4914 |
return;
|
4915 |
} |
4916 |
gen_addr_reg_index(ctx); |
4917 |
op_ldst(lwz); |
4918 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4919 |
#endif
|
4920 |
} |
4921 |
|
4922 |
/* icbt */
|
4923 |
GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT) |
4924 |
{ |
4925 |
/* interpreted as no-op */
|
4926 |
/* XXX: specification say this is treated as a load by the MMU
|
4927 |
* but does not generate any exception
|
4928 |
*/
|
4929 |
} |
4930 |
|
4931 |
/* iccci */
|
4932 |
GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) |
4933 |
{ |
4934 |
#if defined(CONFIG_USER_ONLY)
|
4935 |
GEN_EXCP_PRIVOPC(ctx); |
4936 |
#else
|
4937 |
if (unlikely(!ctx->supervisor)) {
|
4938 |
GEN_EXCP_PRIVOPC(ctx); |
4939 |
return;
|
4940 |
} |
4941 |
/* interpreted as no-op */
|
4942 |
#endif
|
4943 |
} |
4944 |
|
4945 |
/* icread */
|
4946 |
GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) |
4947 |
{ |
4948 |
#if defined(CONFIG_USER_ONLY)
|
4949 |
GEN_EXCP_PRIVOPC(ctx); |
4950 |
#else
|
4951 |
if (unlikely(!ctx->supervisor)) {
|
4952 |
GEN_EXCP_PRIVOPC(ctx); |
4953 |
return;
|
4954 |
} |
4955 |
/* interpreted as no-op */
|
4956 |
#endif
|
4957 |
} |
4958 |
|
4959 |
/* rfci (supervisor only) */
|
4960 |
GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP) |
4961 |
{ |
4962 |
#if defined(CONFIG_USER_ONLY)
|
4963 |
GEN_EXCP_PRIVOPC(ctx); |
4964 |
#else
|
4965 |
if (unlikely(!ctx->supervisor)) {
|
4966 |
GEN_EXCP_PRIVOPC(ctx); |
4967 |
return;
|
4968 |
} |
4969 |
/* Restore CPU state */
|
4970 |
gen_op_40x_rfci(); |
4971 |
GEN_SYNC(ctx); |
4972 |
#endif
|
4973 |
} |
4974 |
|
4975 |
GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) |
4976 |
{ |
4977 |
#if defined(CONFIG_USER_ONLY)
|
4978 |
GEN_EXCP_PRIVOPC(ctx); |
4979 |
#else
|
4980 |
if (unlikely(!ctx->supervisor)) {
|
4981 |
GEN_EXCP_PRIVOPC(ctx); |
4982 |
return;
|
4983 |
} |
4984 |
/* Restore CPU state */
|
4985 |
gen_op_rfci(); |
4986 |
GEN_SYNC(ctx); |
4987 |
#endif
|
4988 |
} |
4989 |
|
4990 |
/* BookE specific */
|
4991 |
/* XXX: not implemented on 440 ? */
|
4992 |
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) |
4993 |
{ |
4994 |
#if defined(CONFIG_USER_ONLY)
|
4995 |
GEN_EXCP_PRIVOPC(ctx); |
4996 |
#else
|
4997 |
if (unlikely(!ctx->supervisor)) {
|
4998 |
GEN_EXCP_PRIVOPC(ctx); |
4999 |
return;
|
5000 |
} |
5001 |
/* Restore CPU state */
|
5002 |
gen_op_rfdi(); |
5003 |
GEN_SYNC(ctx); |
5004 |
#endif
|
5005 |
} |
5006 |
|
5007 |
/* XXX: not implemented on 440 ? */
|
5008 |
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) |
5009 |
{ |
5010 |
#if defined(CONFIG_USER_ONLY)
|
5011 |
GEN_EXCP_PRIVOPC(ctx); |
5012 |
#else
|
5013 |
if (unlikely(!ctx->supervisor)) {
|
5014 |
GEN_EXCP_PRIVOPC(ctx); |
5015 |
return;
|
5016 |
} |
5017 |
/* Restore CPU state */
|
5018 |
gen_op_rfmci(); |
5019 |
GEN_SYNC(ctx); |
5020 |
#endif
|
5021 |
} |
5022 |
|
5023 |
/* TLB management - PowerPC 405 implementation */
|
5024 |
/* tlbre */
|
5025 |
GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) |
5026 |
{ |
5027 |
#if defined(CONFIG_USER_ONLY)
|
5028 |
GEN_EXCP_PRIVOPC(ctx); |
5029 |
#else
|
5030 |
if (unlikely(!ctx->supervisor)) {
|
5031 |
GEN_EXCP_PRIVOPC(ctx); |
5032 |
return;
|
5033 |
} |
5034 |
switch (rB(ctx->opcode)) {
|
5035 |
case 0: |
5036 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5037 |
gen_op_4xx_tlbre_hi(); |
5038 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5039 |
break;
|
5040 |
case 1: |
5041 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5042 |
gen_op_4xx_tlbre_lo(); |
5043 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5044 |
break;
|
5045 |
default:
|
5046 |
GEN_EXCP_INVAL(ctx); |
5047 |
break;
|
5048 |
} |
5049 |
#endif
|
5050 |
} |
5051 |
|
5052 |
/* tlbsx - tlbsx. */
|
5053 |
GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) |
5054 |
{ |
5055 |
#if defined(CONFIG_USER_ONLY)
|
5056 |
GEN_EXCP_PRIVOPC(ctx); |
5057 |
#else
|
5058 |
if (unlikely(!ctx->supervisor)) {
|
5059 |
GEN_EXCP_PRIVOPC(ctx); |
5060 |
return;
|
5061 |
} |
5062 |
gen_addr_reg_index(ctx); |
5063 |
gen_op_4xx_tlbsx(); |
5064 |
if (Rc(ctx->opcode))
|
5065 |
gen_op_4xx_tlbsx_check(); |
5066 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5067 |
#endif
|
5068 |
} |
5069 |
|
5070 |
/* tlbwe */
|
5071 |
GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) |
5072 |
{ |
5073 |
#if defined(CONFIG_USER_ONLY)
|
5074 |
GEN_EXCP_PRIVOPC(ctx); |
5075 |
#else
|
5076 |
if (unlikely(!ctx->supervisor)) {
|
5077 |
GEN_EXCP_PRIVOPC(ctx); |
5078 |
return;
|
5079 |
} |
5080 |
switch (rB(ctx->opcode)) {
|
5081 |
case 0: |
5082 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5083 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
5084 |
gen_op_4xx_tlbwe_hi(); |
5085 |
break;
|
5086 |
case 1: |
5087 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5088 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
5089 |
gen_op_4xx_tlbwe_lo(); |
5090 |
break;
|
5091 |
default:
|
5092 |
GEN_EXCP_INVAL(ctx); |
5093 |
break;
|
5094 |
} |
5095 |
#endif
|
5096 |
} |
5097 |
|
5098 |
/* TLB management - PowerPC 440 implementation */
|
5099 |
/* tlbre */
|
5100 |
GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) |
5101 |
{ |
5102 |
#if defined(CONFIG_USER_ONLY)
|
5103 |
GEN_EXCP_PRIVOPC(ctx); |
5104 |
#else
|
5105 |
if (unlikely(!ctx->supervisor)) {
|
5106 |
GEN_EXCP_PRIVOPC(ctx); |
5107 |
return;
|
5108 |
} |
5109 |
switch (rB(ctx->opcode)) {
|
5110 |
case 0: |
5111 |
case 1: |
5112 |
case 2: |
5113 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5114 |
gen_op_440_tlbre(rB(ctx->opcode)); |
5115 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5116 |
break;
|
5117 |
default:
|
5118 |
GEN_EXCP_INVAL(ctx); |
5119 |
break;
|
5120 |
} |
5121 |
#endif
|
5122 |
} |
5123 |
|
5124 |
/* tlbsx - tlbsx. */
|
5125 |
GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) |
5126 |
{ |
5127 |
#if defined(CONFIG_USER_ONLY)
|
5128 |
GEN_EXCP_PRIVOPC(ctx); |
5129 |
#else
|
5130 |
if (unlikely(!ctx->supervisor)) {
|
5131 |
GEN_EXCP_PRIVOPC(ctx); |
5132 |
return;
|
5133 |
} |
5134 |
gen_addr_reg_index(ctx); |
5135 |
gen_op_440_tlbsx(); |
5136 |
if (Rc(ctx->opcode))
|
5137 |
gen_op_4xx_tlbsx_check(); |
5138 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5139 |
#endif
|
5140 |
} |
5141 |
|
5142 |
/* tlbwe */
|
5143 |
GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) |
5144 |
{ |
5145 |
#if defined(CONFIG_USER_ONLY)
|
5146 |
GEN_EXCP_PRIVOPC(ctx); |
5147 |
#else
|
5148 |
if (unlikely(!ctx->supervisor)) {
|
5149 |
GEN_EXCP_PRIVOPC(ctx); |
5150 |
return;
|
5151 |
} |
5152 |
switch (rB(ctx->opcode)) {
|
5153 |
case 0: |
5154 |
case 1: |
5155 |
case 2: |
5156 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5157 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
5158 |
gen_op_440_tlbwe(rB(ctx->opcode)); |
5159 |
break;
|
5160 |
default:
|
5161 |
GEN_EXCP_INVAL(ctx); |
5162 |
break;
|
5163 |
} |
5164 |
#endif
|
5165 |
} |
5166 |
|
5167 |
/* wrtee */
|
5168 |
GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) |
5169 |
{ |
5170 |
#if defined(CONFIG_USER_ONLY)
|
5171 |
GEN_EXCP_PRIVOPC(ctx); |
5172 |
#else
|
5173 |
if (unlikely(!ctx->supervisor)) {
|
5174 |
GEN_EXCP_PRIVOPC(ctx); |
5175 |
return;
|
5176 |
} |
5177 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
|
5178 |
gen_op_wrte(); |
5179 |
/* Stop translation to have a chance to raise an exception
|
5180 |
* if we just set msr_ee to 1
|
5181 |
*/
|
5182 |
GEN_STOP(ctx); |
5183 |
#endif
|
5184 |
} |
5185 |
|
5186 |
/* wrteei */
|
5187 |
GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) |
5188 |
{ |
5189 |
#if defined(CONFIG_USER_ONLY)
|
5190 |
GEN_EXCP_PRIVOPC(ctx); |
5191 |
#else
|
5192 |
if (unlikely(!ctx->supervisor)) {
|
5193 |
GEN_EXCP_PRIVOPC(ctx); |
5194 |
return;
|
5195 |
} |
5196 |
tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000); |
5197 |
gen_op_wrte(); |
5198 |
/* Stop translation to have a chance to raise an exception
|
5199 |
* if we just set msr_ee to 1
|
5200 |
*/
|
5201 |
GEN_STOP(ctx); |
5202 |
#endif
|
5203 |
} |
5204 |
|
5205 |
/* PowerPC 440 specific instructions */
|
5206 |
/* dlmzb */
|
5207 |
GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) |
5208 |
{ |
5209 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
5210 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
5211 |
gen_op_440_dlmzb(); |
5212 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
5213 |
gen_op_store_xer_bc(); |
5214 |
if (Rc(ctx->opcode)) {
|
5215 |
gen_op_440_dlmzb_update_Rc(); |
5216 |
tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf); |
5217 |
} |
5218 |
} |
5219 |
|
5220 |
/* mbar replaces eieio on 440 */
|
5221 |
GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE) |
5222 |
{ |
5223 |
/* interpreted as no-op */
|
5224 |
} |
5225 |
|
5226 |
/* msync replaces sync on 440 */
|
5227 |
GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE) |
5228 |
{ |
5229 |
/* interpreted as no-op */
|
5230 |
} |
5231 |
|
5232 |
/* icbt */
|
5233 |
GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE) |
5234 |
{ |
5235 |
/* interpreted as no-op */
|
5236 |
/* XXX: specification say this is treated as a load by the MMU
|
5237 |
* but does not generate any exception
|
5238 |
*/
|
5239 |
} |
5240 |
|
5241 |
/*** Altivec vector extension ***/
|
5242 |
/* Altivec registers moves */
|
5243 |
|
5244 |
static always_inline void gen_load_avr(int t, int reg) { |
5245 |
tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]); |
5246 |
tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]); |
5247 |
} |
5248 |
|
5249 |
static always_inline void gen_store_avr(int reg, int t) { |
5250 |
tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]); |
5251 |
tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]); |
5252 |
} |
5253 |
|
5254 |
#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
5255 |
#define OP_VR_LD_TABLE(name) \
|
5256 |
static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \ |
5257 |
GEN_MEM_FUNCS(vr_l##name), \ |
5258 |
}; |
5259 |
#define OP_VR_ST_TABLE(name) \
|
5260 |
static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \ |
5261 |
GEN_MEM_FUNCS(vr_st##name), \ |
5262 |
}; |
5263 |
|
5264 |
#define GEN_VR_LDX(name, opc2, opc3) \
|
5265 |
GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ |
5266 |
{ \ |
5267 |
if (unlikely(!ctx->altivec_enabled)) { \
|
5268 |
GEN_EXCP_NO_VR(ctx); \ |
5269 |
return; \
|
5270 |
} \ |
5271 |
gen_addr_reg_index(ctx); \ |
5272 |
op_vr_ldst(vr_l##name); \ |
5273 |
gen_store_avr(rD(ctx->opcode), 0); \
|
5274 |
} |
5275 |
|
5276 |
#define GEN_VR_STX(name, opc2, opc3) \
|
5277 |
GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ |
5278 |
{ \ |
5279 |
if (unlikely(!ctx->altivec_enabled)) { \
|
5280 |
GEN_EXCP_NO_VR(ctx); \ |
5281 |
return; \
|
5282 |
} \ |
5283 |
gen_addr_reg_index(ctx); \ |
5284 |
gen_load_avr(0, rS(ctx->opcode)); \
|
5285 |
op_vr_ldst(vr_st##name); \ |
5286 |
} |
5287 |
|
5288 |
OP_VR_LD_TABLE(vx); |
5289 |
GEN_VR_LDX(vx, 0x07, 0x03); |
5290 |
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
|
5291 |
#define gen_op_vr_lvxl gen_op_vr_lvx
|
5292 |
GEN_VR_LDX(vxl, 0x07, 0x0B); |
5293 |
|
5294 |
OP_VR_ST_TABLE(vx); |
5295 |
GEN_VR_STX(vx, 0x07, 0x07); |
5296 |
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
|
5297 |
#define gen_op_vr_stvxl gen_op_vr_stvx
|
5298 |
GEN_VR_STX(vxl, 0x07, 0x0F); |
5299 |
|
5300 |
/*** SPE extension ***/
|
5301 |
/* Register moves */
|
5302 |
|
5303 |
static always_inline void gen_load_gpr64(TCGv t, int reg) { |
5304 |
#if defined(TARGET_PPC64)
|
5305 |
tcg_gen_mov_i64(t, cpu_gpr[reg]); |
5306 |
#else
|
5307 |
tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); |
5308 |
tcg_gen_shli_i64(t, t, 32);
|
5309 |
TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); |
5310 |
tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); |
5311 |
tcg_gen_or_i64(t, t, tmp); |
5312 |
tcg_temp_free(tmp); |
5313 |
#endif
|
5314 |
} |
5315 |
|
5316 |
static always_inline void gen_store_gpr64(int reg, TCGv t) { |
5317 |
#if defined(TARGET_PPC64)
|
5318 |
tcg_gen_mov_i64(cpu_gpr[reg], t); |
5319 |
#else
|
5320 |
tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
5321 |
TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); |
5322 |
tcg_gen_shri_i64(tmp, t, 32);
|
5323 |
tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
5324 |
tcg_temp_free(tmp); |
5325 |
#endif
|
5326 |
} |
5327 |
|
5328 |
#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
5329 |
GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ |
5330 |
{ \ |
5331 |
if (Rc(ctx->opcode)) \
|
5332 |
gen_##name1(ctx); \ |
5333 |
else \
|
5334 |
gen_##name0(ctx); \ |
5335 |
} |
5336 |
|
5337 |
/* Handler for undefined SPE opcodes */
|
5338 |
static always_inline void gen_speundef (DisasContext *ctx) |
5339 |
{ |
5340 |
GEN_EXCP_INVAL(ctx); |
5341 |
} |
5342 |
|
5343 |
/* SPE load and stores */
|
5344 |
static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) |
5345 |
{ |
5346 |
target_long simm = rB(ctx->opcode); |
5347 |
|
5348 |
if (rA(ctx->opcode) == 0) { |
5349 |
tcg_gen_movi_tl(cpu_T[0], simm << sh);
|
5350 |
} else {
|
5351 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5352 |
if (likely(simm != 0)) |
5353 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh); |
5354 |
} |
5355 |
} |
5356 |
|
5357 |
#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
5358 |
#define OP_SPE_LD_TABLE(name) \
|
5359 |
static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \ |
5360 |
GEN_MEM_FUNCS(spe_l##name), \ |
5361 |
}; |
5362 |
#define OP_SPE_ST_TABLE(name) \
|
5363 |
static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \ |
5364 |
GEN_MEM_FUNCS(spe_st##name), \ |
5365 |
}; |
5366 |
|
5367 |
#define GEN_SPE_LD(name, sh) \
|
5368 |
static always_inline void gen_evl##name (DisasContext *ctx) \ |
5369 |
{ \ |
5370 |
if (unlikely(!ctx->spe_enabled)) { \
|
5371 |
GEN_EXCP_NO_AP(ctx); \ |
5372 |
return; \
|
5373 |
} \ |
5374 |
gen_addr_spe_imm_index(ctx, sh); \ |
5375 |
op_spe_ldst(spe_l##name); \ |
5376 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
|
5377 |
} |
5378 |
|
5379 |
#define GEN_SPE_LDX(name) \
|
5380 |
static always_inline void gen_evl##name##x (DisasContext *ctx) \ |
5381 |
{ \ |
5382 |
if (unlikely(!ctx->spe_enabled)) { \
|
5383 |
GEN_EXCP_NO_AP(ctx); \ |
5384 |
return; \
|
5385 |
} \ |
5386 |
gen_addr_reg_index(ctx); \ |
5387 |
op_spe_ldst(spe_l##name); \ |
5388 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
|
5389 |
} |
5390 |
|
5391 |
#define GEN_SPEOP_LD(name, sh) \
|
5392 |
OP_SPE_LD_TABLE(name); \ |
5393 |
GEN_SPE_LD(name, sh); \ |
5394 |
GEN_SPE_LDX(name) |
5395 |
|
5396 |
#define GEN_SPE_ST(name, sh) \
|
5397 |
static always_inline void gen_evst##name (DisasContext *ctx) \ |
5398 |
{ \ |
5399 |
if (unlikely(!ctx->spe_enabled)) { \
|
5400 |
GEN_EXCP_NO_AP(ctx); \ |
5401 |
return; \
|
5402 |
} \ |
5403 |
gen_addr_spe_imm_index(ctx, sh); \ |
5404 |
gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
|
5405 |
op_spe_ldst(spe_st##name); \ |
5406 |
} |
5407 |
|
5408 |
#define GEN_SPE_STX(name) \
|
5409 |
static always_inline void gen_evst##name##x (DisasContext *ctx) \ |
5410 |
{ \ |
5411 |
if (unlikely(!ctx->spe_enabled)) { \
|
5412 |
GEN_EXCP_NO_AP(ctx); \ |
5413 |
return; \
|
5414 |
} \ |
5415 |
gen_addr_reg_index(ctx); \ |
5416 |
gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
|
5417 |
op_spe_ldst(spe_st##name); \ |
5418 |
} |
5419 |
|
5420 |
#define GEN_SPEOP_ST(name, sh) \
|
5421 |
OP_SPE_ST_TABLE(name); \ |
5422 |
GEN_SPE_ST(name, sh); \ |
5423 |
GEN_SPE_STX(name) |
5424 |
|
5425 |
#define GEN_SPEOP_LDST(name, sh) \
|
5426 |
GEN_SPEOP_LD(name, sh); \ |
5427 |
GEN_SPEOP_ST(name, sh) |
5428 |
|
5429 |
/* SPE arithmetic and logic */
|
5430 |
#define GEN_SPEOP_ARITH2(name) \
|
5431 |
static always_inline void gen_##name (DisasContext *ctx) \ |
5432 |
{ \ |
5433 |
if (unlikely(!ctx->spe_enabled)) { \
|
5434 |
GEN_EXCP_NO_AP(ctx); \ |
5435 |
return; \
|
5436 |
} \ |
5437 |
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5438 |
gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
|
5439 |
gen_op_##name(); \ |
5440 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5441 |
} |
5442 |
|
5443 |
#define GEN_SPEOP_ARITH1(name) \
|
5444 |
static always_inline void gen_##name (DisasContext *ctx) \ |
5445 |
{ \ |
5446 |
if (unlikely(!ctx->spe_enabled)) { \
|
5447 |
GEN_EXCP_NO_AP(ctx); \ |
5448 |
return; \
|
5449 |
} \ |
5450 |
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5451 |
gen_op_##name(); \ |
5452 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5453 |
} |
5454 |
|
5455 |
#define GEN_SPEOP_COMP(name) \
|
5456 |
static always_inline void gen_##name (DisasContext *ctx) \ |
5457 |
{ \ |
5458 |
if (unlikely(!ctx->spe_enabled)) { \
|
5459 |
GEN_EXCP_NO_AP(ctx); \ |
5460 |
return; \
|
5461 |
} \ |
5462 |
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5463 |
gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
|
5464 |
gen_op_##name(); \ |
5465 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \ |
5466 |
} |
5467 |
|
5468 |
/* Logical */
|
5469 |
GEN_SPEOP_ARITH2(evand); |
5470 |
GEN_SPEOP_ARITH2(evandc); |
5471 |
GEN_SPEOP_ARITH2(evxor); |
5472 |
GEN_SPEOP_ARITH2(evor); |
5473 |
GEN_SPEOP_ARITH2(evnor); |
5474 |
GEN_SPEOP_ARITH2(eveqv); |
5475 |
GEN_SPEOP_ARITH2(evorc); |
5476 |
GEN_SPEOP_ARITH2(evnand); |
5477 |
GEN_SPEOP_ARITH2(evsrwu); |
5478 |
GEN_SPEOP_ARITH2(evsrws); |
5479 |
GEN_SPEOP_ARITH2(evslw); |
5480 |
GEN_SPEOP_ARITH2(evrlw); |
5481 |
GEN_SPEOP_ARITH2(evmergehi); |
5482 |
GEN_SPEOP_ARITH2(evmergelo); |
5483 |
GEN_SPEOP_ARITH2(evmergehilo); |
5484 |
GEN_SPEOP_ARITH2(evmergelohi); |
5485 |
|
5486 |
/* Arithmetic */
|
5487 |
GEN_SPEOP_ARITH2(evaddw); |
5488 |
GEN_SPEOP_ARITH2(evsubfw); |
5489 |
GEN_SPEOP_ARITH1(evabs); |
5490 |
GEN_SPEOP_ARITH1(evneg); |
5491 |
GEN_SPEOP_ARITH1(evextsb); |
5492 |
GEN_SPEOP_ARITH1(evextsh); |
5493 |
GEN_SPEOP_ARITH1(evrndw); |
5494 |
GEN_SPEOP_ARITH1(evcntlzw); |
5495 |
GEN_SPEOP_ARITH1(evcntlsw); |
5496 |
static always_inline void gen_brinc (DisasContext *ctx) |
5497 |
{ |
5498 |
/* Note: brinc is usable even if SPE is disabled */
|
5499 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5500 |
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
5501 |
gen_op_brinc(); |
5502 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5503 |
} |
5504 |
|
5505 |
#define GEN_SPEOP_ARITH_IMM2(name) \
|
5506 |
static always_inline void gen_##name##i (DisasContext *ctx) \ |
5507 |
{ \ |
5508 |
if (unlikely(!ctx->spe_enabled)) { \
|
5509 |
GEN_EXCP_NO_AP(ctx); \ |
5510 |
return; \
|
5511 |
} \ |
5512 |
gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
|
5513 |
gen_op_splatwi_T1_64(rA(ctx->opcode)); \ |
5514 |
gen_op_##name(); \ |
5515 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5516 |
} |
5517 |
|
5518 |
#define GEN_SPEOP_LOGIC_IMM2(name) \
|
5519 |
static always_inline void gen_##name##i (DisasContext *ctx) \ |
5520 |
{ \ |
5521 |
if (unlikely(!ctx->spe_enabled)) { \
|
5522 |
GEN_EXCP_NO_AP(ctx); \ |
5523 |
return; \
|
5524 |
} \ |
5525 |
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5526 |
gen_op_splatwi_T1_64(rB(ctx->opcode)); \ |
5527 |
gen_op_##name(); \ |
5528 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5529 |
} |
5530 |
|
5531 |
GEN_SPEOP_ARITH_IMM2(evaddw); |
5532 |
#define gen_evaddiw gen_evaddwi
|
5533 |
GEN_SPEOP_ARITH_IMM2(evsubfw); |
5534 |
#define gen_evsubifw gen_evsubfwi
|
5535 |
GEN_SPEOP_LOGIC_IMM2(evslw); |
5536 |
GEN_SPEOP_LOGIC_IMM2(evsrwu); |
5537 |
#define gen_evsrwis gen_evsrwsi
|
5538 |
GEN_SPEOP_LOGIC_IMM2(evsrws); |
5539 |
#define gen_evsrwiu gen_evsrwui
|
5540 |
GEN_SPEOP_LOGIC_IMM2(evrlw); |
5541 |
|
5542 |
static always_inline void gen_evsplati (DisasContext *ctx) |
5543 |
{ |
5544 |
int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27; |
5545 |
|
5546 |
gen_op_splatwi_T0_64(imm); |
5547 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
|
5548 |
} |
5549 |
|
5550 |
static always_inline void gen_evsplatfi (DisasContext *ctx) |
5551 |
{ |
5552 |
uint32_t imm = rA(ctx->opcode) << 27;
|
5553 |
|
5554 |
gen_op_splatwi_T0_64(imm); |
5555 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
|
5556 |
} |
5557 |
|
5558 |
/* Comparison */
|
5559 |
GEN_SPEOP_COMP(evcmpgtu); |
5560 |
GEN_SPEOP_COMP(evcmpgts); |
5561 |
GEN_SPEOP_COMP(evcmpltu); |
5562 |
GEN_SPEOP_COMP(evcmplts); |
5563 |
GEN_SPEOP_COMP(evcmpeq); |
5564 |
|
5565 |
GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
5566 |
GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); |
5567 |
GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// |
5568 |
GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); |
5569 |
GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// |
5570 |
GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// |
5571 |
GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// |
5572 |
GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // |
5573 |
GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
5574 |
GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// |
5575 |
GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// |
5576 |
GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// |
5577 |
GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
5578 |
GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// |
5579 |
GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// |
5580 |
GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); |
5581 |
GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// |
5582 |
GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); |
5583 |
GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // |
5584 |
GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); |
5585 |
GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// |
5586 |
GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// |
5587 |
GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// |
5588 |
GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// |
5589 |
GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
5590 |
|
5591 |
static always_inline void gen_evsel (DisasContext *ctx) |
5592 |
{ |
5593 |
if (unlikely(!ctx->spe_enabled)) {
|
5594 |
GEN_EXCP_NO_AP(ctx); |
5595 |
return;
|
5596 |
} |
5597 |
tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]); |
5598 |
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
|
5599 |
gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
|
5600 |
gen_op_evsel(); |
5601 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
|
5602 |
} |
5603 |
|
5604 |
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE) |
5605 |
{ |
5606 |
gen_evsel(ctx); |
5607 |
} |
5608 |
GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE) |
5609 |
{ |
5610 |
gen_evsel(ctx); |
5611 |
} |
5612 |
GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE) |
5613 |
{ |
5614 |
gen_evsel(ctx); |
5615 |
} |
5616 |
GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE) |
5617 |
{ |
5618 |
gen_evsel(ctx); |
5619 |
} |
5620 |
|
5621 |
/* Load and stores */
|
5622 |
#if defined(TARGET_PPC64)
|
5623 |
/* In that case, we already have 64 bits load & stores
|
5624 |
* so, spe_ldd is equivalent to ld and spe_std is equivalent to std
|
5625 |
*/
|
5626 |
#define gen_op_spe_ldd_raw gen_op_ld_raw
|
5627 |
#define gen_op_spe_ldd_user gen_op_ld_user
|
5628 |
#define gen_op_spe_ldd_kernel gen_op_ld_kernel
|
5629 |
#define gen_op_spe_ldd_hypv gen_op_ld_hypv
|
5630 |
#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
|
5631 |
#define gen_op_spe_ldd_64_user gen_op_ld_64_user
|
5632 |
#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
|
5633 |
#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
|
5634 |
#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
|
5635 |
#define gen_op_spe_ldd_le_user gen_op_ld_le_user
|
5636 |
#define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
|
5637 |
#define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
|
5638 |
#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
|
5639 |
#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
|
5640 |
#define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
|
5641 |
#define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
|
5642 |
#define gen_op_spe_stdd_raw gen_op_std_raw
|
5643 |
#define gen_op_spe_stdd_user gen_op_std_user
|
5644 |
#define gen_op_spe_stdd_kernel gen_op_std_kernel
|
5645 |
#define gen_op_spe_stdd_hypv gen_op_std_hypv
|
5646 |
#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
|
5647 |
#define gen_op_spe_stdd_64_user gen_op_std_64_user
|
5648 |
#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
|
5649 |
#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
|
5650 |
#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
|
5651 |
#define gen_op_spe_stdd_le_user gen_op_std_le_user
|
5652 |
#define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
|
5653 |
#define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
|
5654 |
#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
|
5655 |
#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
|
5656 |
#define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
|
5657 |
#define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
|
5658 |
#endif /* defined(TARGET_PPC64) */ |
5659 |
GEN_SPEOP_LDST(dd, 3);
|
5660 |
GEN_SPEOP_LDST(dw, 3);
|
5661 |
GEN_SPEOP_LDST(dh, 3);
|
5662 |
GEN_SPEOP_LDST(whe, 2);
|
5663 |
GEN_SPEOP_LD(whou, 2);
|
5664 |
GEN_SPEOP_LD(whos, 2);
|
5665 |
GEN_SPEOP_ST(who, 2);
|
5666 |
|
5667 |
#if defined(TARGET_PPC64)
|
5668 |
/* In that case, spe_stwwo is equivalent to stw */
|
5669 |
#define gen_op_spe_stwwo_raw gen_op_stw_raw
|
5670 |
#define gen_op_spe_stwwo_user gen_op_stw_user
|
5671 |
#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
|
5672 |
#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
|
5673 |
#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
|
5674 |
#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
|
5675 |
#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
|
5676 |
#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
|
5677 |
#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
|
5678 |
#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
|
5679 |
#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
|
5680 |
#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
|
5681 |
#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
|
5682 |
#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
|
5683 |
#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
|
5684 |
#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
|
5685 |
#endif
|
5686 |
#define _GEN_OP_SPE_STWWE(suffix) \
|
5687 |
static always_inline void gen_op_spe_stwwe_##suffix (void) \ |
5688 |
{ \ |
5689 |
gen_op_srli32_T1_64(); \ |
5690 |
gen_op_spe_stwwo_##suffix(); \ |
5691 |
} |
5692 |
#define _GEN_OP_SPE_STWWE_LE(suffix) \
|
5693 |
static always_inline void gen_op_spe_stwwe_le_##suffix (void) \ |
5694 |
{ \ |
5695 |
gen_op_srli32_T1_64(); \ |
5696 |
gen_op_spe_stwwo_le_##suffix(); \ |
5697 |
} |
5698 |
#if defined(TARGET_PPC64)
|
5699 |
#define GEN_OP_SPE_STWWE(suffix) \
|
5700 |
_GEN_OP_SPE_STWWE(suffix); \ |
5701 |
_GEN_OP_SPE_STWWE_LE(suffix); \ |
5702 |
static always_inline void gen_op_spe_stwwe_64_##suffix (void) \ |
5703 |
{ \ |
5704 |
gen_op_srli32_T1_64(); \ |
5705 |
gen_op_spe_stwwo_64_##suffix(); \ |
5706 |
} \ |
5707 |
static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \ |
5708 |
{ \ |
5709 |
gen_op_srli32_T1_64(); \ |
5710 |
gen_op_spe_stwwo_le_64_##suffix(); \ |
5711 |
} |
5712 |
#else
|
5713 |
#define GEN_OP_SPE_STWWE(suffix) \
|
5714 |
_GEN_OP_SPE_STWWE(suffix); \ |
5715 |
_GEN_OP_SPE_STWWE_LE(suffix) |
5716 |
#endif
|
5717 |
#if defined(CONFIG_USER_ONLY)
|
5718 |
GEN_OP_SPE_STWWE(raw); |
5719 |
#else /* defined(CONFIG_USER_ONLY) */ |
5720 |
GEN_OP_SPE_STWWE(user); |
5721 |
GEN_OP_SPE_STWWE(kernel); |
5722 |
GEN_OP_SPE_STWWE(hypv); |
5723 |
#endif /* defined(CONFIG_USER_ONLY) */ |
5724 |
GEN_SPEOP_ST(wwe, 2);
|
5725 |
GEN_SPEOP_ST(wwo, 2);
|
5726 |
|
5727 |
#define GEN_SPE_LDSPLAT(name, op, suffix) \
|
5728 |
static always_inline void gen_op_spe_l##name##_##suffix (void) \ |
5729 |
{ \ |
5730 |
gen_op_##op##_##suffix(); \ |
5731 |
gen_op_splatw_T1_64(); \ |
5732 |
} |
5733 |
|
5734 |
#define GEN_OP_SPE_LHE(suffix) \
|
5735 |
static always_inline void gen_op_spe_lhe_##suffix (void) \ |
5736 |
{ \ |
5737 |
gen_op_spe_lh_##suffix(); \ |
5738 |
gen_op_sli16_T1_64(); \ |
5739 |
} |
5740 |
|
5741 |
#define GEN_OP_SPE_LHX(suffix) \
|
5742 |
static always_inline void gen_op_spe_lhx_##suffix (void) \ |
5743 |
{ \ |
5744 |
gen_op_spe_lh_##suffix(); \ |
5745 |
gen_op_extsh_T1_64(); \ |
5746 |
} |
5747 |
|
5748 |
#if defined(CONFIG_USER_ONLY)
|
5749 |
GEN_OP_SPE_LHE(raw); |
5750 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw); |
5751 |
GEN_OP_SPE_LHE(le_raw); |
5752 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw); |
5753 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw); |
5754 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw); |
5755 |
GEN_OP_SPE_LHX(raw); |
5756 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw); |
5757 |
GEN_OP_SPE_LHX(le_raw); |
5758 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw); |
5759 |
#if defined(TARGET_PPC64)
|
5760 |
GEN_OP_SPE_LHE(64_raw);
|
5761 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
|
5762 |
GEN_OP_SPE_LHE(le_64_raw); |
5763 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw); |
5764 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
|
5765 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw); |
5766 |
GEN_OP_SPE_LHX(64_raw);
|
5767 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
|
5768 |
GEN_OP_SPE_LHX(le_64_raw); |
5769 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw); |
5770 |
#endif
|
5771 |
#else
|
5772 |
GEN_OP_SPE_LHE(user); |
5773 |
GEN_OP_SPE_LHE(kernel); |
5774 |
GEN_OP_SPE_LHE(hypv); |
5775 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user); |
5776 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel); |
5777 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv); |
5778 |
GEN_OP_SPE_LHE(le_user); |
5779 |
GEN_OP_SPE_LHE(le_kernel); |
5780 |
GEN_OP_SPE_LHE(le_hypv); |
5781 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user); |
5782 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel); |
5783 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv); |
5784 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, user); |
5785 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel); |
5786 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv); |
5787 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user); |
5788 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel); |
5789 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv); |
5790 |
GEN_OP_SPE_LHX(user); |
5791 |
GEN_OP_SPE_LHX(kernel); |
5792 |
GEN_OP_SPE_LHX(hypv); |
5793 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user); |
5794 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel); |
5795 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv); |
5796 |
GEN_OP_SPE_LHX(le_user); |
5797 |
GEN_OP_SPE_LHX(le_kernel); |
5798 |
GEN_OP_SPE_LHX(le_hypv); |
5799 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user); |
5800 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel); |
5801 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv); |
5802 |
#if defined(TARGET_PPC64)
|
5803 |
GEN_OP_SPE_LHE(64_user);
|
5804 |
GEN_OP_SPE_LHE(64_kernel);
|
5805 |
GEN_OP_SPE_LHE(64_hypv);
|
5806 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
|
5807 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
|
5808 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
|
5809 |
GEN_OP_SPE_LHE(le_64_user); |
5810 |
GEN_OP_SPE_LHE(le_64_kernel); |
5811 |
GEN_OP_SPE_LHE(le_64_hypv); |
5812 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user); |
5813 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel); |
5814 |
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv); |
5815 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
|
5816 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
|
5817 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
|
5818 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user); |
5819 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel); |
5820 |
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv); |
5821 |
GEN_OP_SPE_LHX(64_user);
|
5822 |
GEN_OP_SPE_LHX(64_kernel);
|
5823 |
GEN_OP_SPE_LHX(64_hypv);
|
5824 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
|
5825 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
|
5826 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
|
5827 |
GEN_OP_SPE_LHX(le_64_user); |
5828 |
GEN_OP_SPE_LHX(le_64_kernel); |
5829 |
GEN_OP_SPE_LHX(le_64_hypv); |
5830 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user); |
5831 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel); |
5832 |
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv); |
5833 |
#endif
|
5834 |
#endif
|
5835 |
GEN_SPEOP_LD(hhesplat, 1);
|
5836 |
GEN_SPEOP_LD(hhousplat, 1);
|
5837 |
GEN_SPEOP_LD(hhossplat, 1);
|
5838 |
GEN_SPEOP_LD(wwsplat, 2);
|
5839 |
GEN_SPEOP_LD(whsplat, 2);
|
5840 |
|
5841 |
GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); // |
5842 |
GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); // |
5843 |
GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); // |
5844 |
GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); // |
5845 |
GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); // |
5846 |
GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); // |
5847 |
GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); // |
5848 |
GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); // |
5849 |
GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); // |
5850 |
GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); // |
5851 |
GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); // |
5852 |
GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); // |
5853 |
GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); // |
5854 |
GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); // |
5855 |
GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); // |
5856 |
GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); // |
5857 |
GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); // |
5858 |
GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); // |
5859 |
|
5860 |
/* Multiply and add - TODO */
|
5861 |
#if 0
|
5862 |
GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
|
5863 |
GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
|
5864 |
GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
|
5865 |
GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
|
5866 |
GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
|
5867 |
GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
|
5868 |
GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
|
5869 |
GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
|
5870 |
GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
|
5871 |
GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
|
5872 |
GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
|
5873 |
GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
|
5874 |
|
5875 |
GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
|
5876 |
GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
|
5877 |
GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
|
5878 |
GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
|
5879 |
GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
|
5880 |
GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
|
5881 |
GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
|
5882 |
GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
|
5883 |
GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
|
5884 |
GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
|
5885 |
GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
|
5886 |
GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
|
5887 |
GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
|
5888 |
GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
|
5889 |
|
5890 |
GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
|
5891 |
GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
|
5892 |
GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
|
5893 |
GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
|
5894 |
GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
|
5895 |
GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
|
5896 |
|
5897 |
GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
|
5898 |
GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
|
5899 |
GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
|
5900 |
GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
|
5901 |
GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
|
5902 |
GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
|
5903 |
GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
|
5904 |
GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
|
5905 |
GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
|
5906 |
GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
|
5907 |
GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
|
5908 |
GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
|
5909 |
|
5910 |
GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
|
5911 |
GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
|
5912 |
GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
|
5913 |
GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
|
5914 |
GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
|
5915 |
|
5916 |
GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
|
5917 |
GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
|
5918 |
GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
|
5919 |
GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
|
5920 |
GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
|
5921 |
GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
|
5922 |
GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
|
5923 |
GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
|
5924 |
GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
|
5925 |
GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
|
5926 |
GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
|
5927 |
GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
|
5928 |
|
5929 |
GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
|
5930 |
GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
|
5931 |
GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
|
5932 |
GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
|
5933 |
GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
|
5934 |
#endif
|
5935 |
|
5936 |
/*** SPE floating-point extension ***/
|
5937 |
#define GEN_SPEFPUOP_CONV(name) \
|
5938 |
static always_inline void gen_##name (DisasContext *ctx) \ |
5939 |
{ \ |
5940 |
gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
|
5941 |
gen_op_##name(); \ |
5942 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5943 |
} |
5944 |
|
5945 |
/* Single precision floating-point vectors operations */
|
5946 |
/* Arithmetic */
|
5947 |
GEN_SPEOP_ARITH2(evfsadd); |
5948 |
GEN_SPEOP_ARITH2(evfssub); |
5949 |
GEN_SPEOP_ARITH2(evfsmul); |
5950 |
GEN_SPEOP_ARITH2(evfsdiv); |
5951 |
GEN_SPEOP_ARITH1(evfsabs); |
5952 |
GEN_SPEOP_ARITH1(evfsnabs); |
5953 |
GEN_SPEOP_ARITH1(evfsneg); |
5954 |
/* Conversion */
|
5955 |
GEN_SPEFPUOP_CONV(evfscfui); |
5956 |
GEN_SPEFPUOP_CONV(evfscfsi); |
5957 |
GEN_SPEFPUOP_CONV(evfscfuf); |
5958 |
GEN_SPEFPUOP_CONV(evfscfsf); |
5959 |
GEN_SPEFPUOP_CONV(evfsctui); |
5960 |
GEN_SPEFPUOP_CONV(evfsctsi); |
5961 |
GEN_SPEFPUOP_CONV(evfsctuf); |
5962 |
GEN_SPEFPUOP_CONV(evfsctsf); |
5963 |
GEN_SPEFPUOP_CONV(evfsctuiz); |
5964 |
GEN_SPEFPUOP_CONV(evfsctsiz); |
5965 |
/* Comparison */
|
5966 |
GEN_SPEOP_COMP(evfscmpgt); |
5967 |
GEN_SPEOP_COMP(evfscmplt); |
5968 |
GEN_SPEOP_COMP(evfscmpeq); |
5969 |
GEN_SPEOP_COMP(evfststgt); |
5970 |
GEN_SPEOP_COMP(evfststlt); |
5971 |
GEN_SPEOP_COMP(evfststeq); |
5972 |
|
5973 |
/* Opcodes definitions */
|
5974 |
GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); // |
5975 |
GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); // |
5976 |
GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); // |
5977 |
GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); // |
5978 |
GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); // |
5979 |
GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); // |
5980 |
GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); // |
5981 |
GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); // |
5982 |
GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); // |
5983 |
GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); // |
5984 |
GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); // |
5985 |
GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); // |
5986 |
GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); // |
5987 |
GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); // |
5988 |
|
5989 |
/* Single precision floating-point operations */
|
5990 |
/* Arithmetic */
|
5991 |
GEN_SPEOP_ARITH2(efsadd); |
5992 |
GEN_SPEOP_ARITH2(efssub); |
5993 |
GEN_SPEOP_ARITH2(efsmul); |
5994 |
GEN_SPEOP_ARITH2(efsdiv); |
5995 |
GEN_SPEOP_ARITH1(efsabs); |
5996 |
GEN_SPEOP_ARITH1(efsnabs); |
5997 |
GEN_SPEOP_ARITH1(efsneg); |
5998 |
/* Conversion */
|
5999 |
GEN_SPEFPUOP_CONV(efscfui); |
6000 |
GEN_SPEFPUOP_CONV(efscfsi); |
6001 |
GEN_SPEFPUOP_CONV(efscfuf); |
6002 |
GEN_SPEFPUOP_CONV(efscfsf); |
6003 |
GEN_SPEFPUOP_CONV(efsctui); |
6004 |
GEN_SPEFPUOP_CONV(efsctsi); |
6005 |
GEN_SPEFPUOP_CONV(efsctuf); |
6006 |
GEN_SPEFPUOP_CONV(efsctsf); |
6007 |
GEN_SPEFPUOP_CONV(efsctuiz); |
6008 |
GEN_SPEFPUOP_CONV(efsctsiz); |
6009 |
GEN_SPEFPUOP_CONV(efscfd); |
6010 |
/* Comparison */
|
6011 |
GEN_SPEOP_COMP(efscmpgt); |
6012 |
GEN_SPEOP_COMP(efscmplt); |
6013 |
GEN_SPEOP_COMP(efscmpeq); |
6014 |
GEN_SPEOP_COMP(efststgt); |
6015 |
GEN_SPEOP_COMP(efststlt); |
6016 |
GEN_SPEOP_COMP(efststeq); |
6017 |
|
6018 |
/* Opcodes definitions */
|
6019 |
GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); // |
6020 |
GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6021 |
GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6022 |
GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); // |
6023 |
GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); // |
6024 |
GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); // |
6025 |
GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); // |
6026 |
GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); // |
6027 |
GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); // |
6028 |
GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); // |
6029 |
GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); // |
6030 |
GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); // |
6031 |
GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); // |
6032 |
GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); // |
6033 |
|
6034 |
/* Double precision floating-point operations */
|
6035 |
/* Arithmetic */
|
6036 |
GEN_SPEOP_ARITH2(efdadd); |
6037 |
GEN_SPEOP_ARITH2(efdsub); |
6038 |
GEN_SPEOP_ARITH2(efdmul); |
6039 |
GEN_SPEOP_ARITH2(efddiv); |
6040 |
GEN_SPEOP_ARITH1(efdabs); |
6041 |
GEN_SPEOP_ARITH1(efdnabs); |
6042 |
GEN_SPEOP_ARITH1(efdneg); |
6043 |
/* Conversion */
|
6044 |
|
6045 |
GEN_SPEFPUOP_CONV(efdcfui); |
6046 |
GEN_SPEFPUOP_CONV(efdcfsi); |
6047 |
GEN_SPEFPUOP_CONV(efdcfuf); |
6048 |
GEN_SPEFPUOP_CONV(efdcfsf); |
6049 |
GEN_SPEFPUOP_CONV(efdctui); |
6050 |
GEN_SPEFPUOP_CONV(efdctsi); |
6051 |
GEN_SPEFPUOP_CONV(efdctuf); |
6052 |
GEN_SPEFPUOP_CONV(efdctsf); |
6053 |
GEN_SPEFPUOP_CONV(efdctuiz); |
6054 |
GEN_SPEFPUOP_CONV(efdctsiz); |
6055 |
GEN_SPEFPUOP_CONV(efdcfs); |
6056 |
GEN_SPEFPUOP_CONV(efdcfuid); |
6057 |
GEN_SPEFPUOP_CONV(efdcfsid); |
6058 |
GEN_SPEFPUOP_CONV(efdctuidz); |
6059 |
GEN_SPEFPUOP_CONV(efdctsidz); |
6060 |
/* Comparison */
|
6061 |
GEN_SPEOP_COMP(efdcmpgt); |
6062 |
GEN_SPEOP_COMP(efdcmplt); |
6063 |
GEN_SPEOP_COMP(efdcmpeq); |
6064 |
GEN_SPEOP_COMP(efdtstgt); |
6065 |
GEN_SPEOP_COMP(efdtstlt); |
6066 |
GEN_SPEOP_COMP(efdtsteq); |
6067 |
|
6068 |
/* Opcodes definitions */
|
6069 |
GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); // |
6070 |
GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); // |
6071 |
GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6072 |
GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6073 |
GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); // |
6074 |
GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); // |
6075 |
GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); // |
6076 |
GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); // |
6077 |
GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); // |
6078 |
GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); // |
6079 |
GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); // |
6080 |
GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); // |
6081 |
GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); // |
6082 |
GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); // |
6083 |
GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); // |
6084 |
GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); // |
6085 |
|
6086 |
/* End opcode list */
|
6087 |
GEN_OPCODE_MARK(end); |
6088 |
|
6089 |
#include "translate_init.c" |
6090 |
#include "helper_regs.h" |
6091 |
|
6092 |
/*****************************************************************************/
|
6093 |
/* Misc PowerPC helpers */
|
6094 |
void cpu_dump_state (CPUState *env, FILE *f,
|
6095 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
6096 |
int flags)
|
6097 |
{ |
6098 |
#define RGPL 4 |
6099 |
#define RFPL 4 |
6100 |
|
6101 |
int i;
|
6102 |
|
6103 |
cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n", |
6104 |
env->nip, env->lr, env->ctr, hreg_load_xer(env)); |
6105 |
cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n", |
6106 |
env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); |
6107 |
#if !defined(NO_TIMER_DUMP)
|
6108 |
cpu_fprintf(f, "TB %08x %08x "
|
6109 |
#if !defined(CONFIG_USER_ONLY)
|
6110 |
"DECR %08x"
|
6111 |
#endif
|
6112 |
"\n",
|
6113 |
cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
6114 |
#if !defined(CONFIG_USER_ONLY)
|
6115 |
, cpu_ppc_load_decr(env) |
6116 |
#endif
|
6117 |
); |
6118 |
#endif
|
6119 |
for (i = 0; i < 32; i++) { |
6120 |
if ((i & (RGPL - 1)) == 0) |
6121 |
cpu_fprintf(f, "GPR%02d", i);
|
6122 |
cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
|
6123 |
if ((i & (RGPL - 1)) == (RGPL - 1)) |
6124 |
cpu_fprintf(f, "\n");
|
6125 |
} |
6126 |
cpu_fprintf(f, "CR ");
|
6127 |
for (i = 0; i < 8; i++) |
6128 |
cpu_fprintf(f, "%01x", env->crf[i]);
|
6129 |
cpu_fprintf(f, " [");
|
6130 |
for (i = 0; i < 8; i++) { |
6131 |
char a = '-'; |
6132 |
if (env->crf[i] & 0x08) |
6133 |
a = 'L';
|
6134 |
else if (env->crf[i] & 0x04) |
6135 |
a = 'G';
|
6136 |
else if (env->crf[i] & 0x02) |
6137 |
a = 'E';
|
6138 |
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
6139 |
} |
6140 |
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); |
6141 |
for (i = 0; i < 32; i++) { |
6142 |
if ((i & (RFPL - 1)) == 0) |
6143 |
cpu_fprintf(f, "FPR%02d", i);
|
6144 |
cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
|
6145 |
if ((i & (RFPL - 1)) == (RFPL - 1)) |
6146 |
cpu_fprintf(f, "\n");
|
6147 |
} |
6148 |
#if !defined(CONFIG_USER_ONLY)
|
6149 |
cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n", |
6150 |
env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); |
6151 |
#endif
|
6152 |
|
6153 |
#undef RGPL
|
6154 |
#undef RFPL
|
6155 |
} |
6156 |
|
6157 |
void cpu_dump_statistics (CPUState *env, FILE*f,
|
6158 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
6159 |
int flags)
|
6160 |
{ |
6161 |
#if defined(DO_PPC_STATISTICS)
|
6162 |
opc_handler_t **t1, **t2, **t3, *handler; |
6163 |
int op1, op2, op3;
|
6164 |
|
6165 |
t1 = env->opcodes; |
6166 |
for (op1 = 0; op1 < 64; op1++) { |
6167 |
handler = t1[op1]; |
6168 |
if (is_indirect_opcode(handler)) {
|
6169 |
t2 = ind_table(handler); |
6170 |
for (op2 = 0; op2 < 32; op2++) { |
6171 |
handler = t2[op2]; |
6172 |
if (is_indirect_opcode(handler)) {
|
6173 |
t3 = ind_table(handler); |
6174 |
for (op3 = 0; op3 < 32; op3++) { |
6175 |
handler = t3[op3]; |
6176 |
if (handler->count == 0) |
6177 |
continue;
|
6178 |
cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
|
6179 |
"%016llx %lld\n",
|
6180 |
op1, op2, op3, op1, (op3 << 5) | op2,
|
6181 |
handler->oname, |
6182 |
handler->count, handler->count); |
6183 |
} |
6184 |
} else {
|
6185 |
if (handler->count == 0) |
6186 |
continue;
|
6187 |
cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
|
6188 |
"%016llx %lld\n",
|
6189 |
op1, op2, op1, op2, handler->oname, |
6190 |
handler->count, handler->count); |
6191 |
} |
6192 |
} |
6193 |
} else {
|
6194 |
if (handler->count == 0) |
6195 |
continue;
|
6196 |
cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
|
6197 |
op1, op1, handler->oname, |
6198 |
handler->count, handler->count); |
6199 |
} |
6200 |
} |
6201 |
#endif
|
6202 |
} |
6203 |
|
6204 |
/*****************************************************************************/
|
6205 |
static always_inline void gen_intermediate_code_internal (CPUState *env, |
6206 |
TranslationBlock *tb, |
6207 |
int search_pc)
|
6208 |
{ |
6209 |
DisasContext ctx, *ctxp = &ctx; |
6210 |
opc_handler_t **table, *handler; |
6211 |
target_ulong pc_start; |
6212 |
uint16_t *gen_opc_end; |
6213 |
int supervisor, little_endian;
|
6214 |
int j, lj = -1; |
6215 |
int num_insns;
|
6216 |
int max_insns;
|
6217 |
|
6218 |
pc_start = tb->pc; |
6219 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
6220 |
#if defined(OPTIMIZE_FPRF_UPDATE)
|
6221 |
gen_fprf_ptr = gen_fprf_buf; |
6222 |
#endif
|
6223 |
ctx.nip = pc_start; |
6224 |
ctx.tb = tb; |
6225 |
ctx.exception = POWERPC_EXCP_NONE; |
6226 |
ctx.spr_cb = env->spr_cb; |
6227 |
supervisor = env->mmu_idx; |
6228 |
#if !defined(CONFIG_USER_ONLY)
|
6229 |
ctx.supervisor = supervisor; |
6230 |
#endif
|
6231 |
little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0; |
6232 |
#if defined(TARGET_PPC64)
|
6233 |
ctx.sf_mode = msr_sf; |
6234 |
ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian; |
6235 |
#else
|
6236 |
ctx.mem_idx = (supervisor << 1) | little_endian;
|
6237 |
#endif
|
6238 |
ctx.dcache_line_size = env->dcache_line_size; |
6239 |
ctx.fpu_enabled = msr_fp; |
6240 |
if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
|
6241 |
ctx.spe_enabled = msr_spe; |
6242 |
else
|
6243 |
ctx.spe_enabled = 0;
|
6244 |
if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
|
6245 |
ctx.altivec_enabled = msr_vr; |
6246 |
else
|
6247 |
ctx.altivec_enabled = 0;
|
6248 |
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
|
6249 |
ctx.singlestep_enabled = CPU_SINGLE_STEP; |
6250 |
else
|
6251 |
ctx.singlestep_enabled = 0;
|
6252 |
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
6253 |
ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
6254 |
if (unlikely(env->singlestep_enabled))
|
6255 |
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
6256 |
#if defined (DO_SINGLE_STEP) && 0 |
6257 |
/* Single step trace mode */
|
6258 |
msr_se = 1;
|
6259 |
#endif
|
6260 |
num_insns = 0;
|
6261 |
max_insns = tb->cflags & CF_COUNT_MASK; |
6262 |
if (max_insns == 0) |
6263 |
max_insns = CF_COUNT_MASK; |
6264 |
|
6265 |
gen_icount_start(); |
6266 |
/* Set env in case of segfault during code fetch */
|
6267 |
while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
6268 |
if (unlikely(env->nb_breakpoints > 0)) { |
6269 |
for (j = 0; j < env->nb_breakpoints; j++) { |
6270 |
if (env->breakpoints[j] == ctx.nip) {
|
6271 |
gen_update_nip(&ctx, ctx.nip); |
6272 |
gen_op_debug(); |
6273 |
break;
|
6274 |
} |
6275 |
} |
6276 |
} |
6277 |
if (unlikely(search_pc)) {
|
6278 |
j = gen_opc_ptr - gen_opc_buf; |
6279 |
if (lj < j) {
|
6280 |
lj++; |
6281 |
while (lj < j)
|
6282 |
gen_opc_instr_start[lj++] = 0;
|
6283 |
gen_opc_pc[lj] = ctx.nip; |
6284 |
gen_opc_instr_start[lj] = 1;
|
6285 |
gen_opc_icount[lj] = num_insns; |
6286 |
} |
6287 |
} |
6288 |
#if defined PPC_DEBUG_DISAS
|
6289 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6290 |
fprintf(logfile, "----------------\n");
|
6291 |
fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n", |
6292 |
ctx.nip, supervisor, (int)msr_ir);
|
6293 |
} |
6294 |
#endif
|
6295 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
6296 |
gen_io_start(); |
6297 |
if (unlikely(little_endian)) {
|
6298 |
ctx.opcode = bswap32(ldl_code(ctx.nip)); |
6299 |
} else {
|
6300 |
ctx.opcode = ldl_code(ctx.nip); |
6301 |
} |
6302 |
#if defined PPC_DEBUG_DISAS
|
6303 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6304 |
fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
|
6305 |
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
6306 |
opc3(ctx.opcode), little_endian ? "little" : "big"); |
6307 |
} |
6308 |
#endif
|
6309 |
ctx.nip += 4;
|
6310 |
table = env->opcodes; |
6311 |
num_insns++; |
6312 |
handler = table[opc1(ctx.opcode)]; |
6313 |
if (is_indirect_opcode(handler)) {
|
6314 |
table = ind_table(handler); |
6315 |
handler = table[opc2(ctx.opcode)]; |
6316 |
if (is_indirect_opcode(handler)) {
|
6317 |
table = ind_table(handler); |
6318 |
handler = table[opc3(ctx.opcode)]; |
6319 |
} |
6320 |
} |
6321 |
/* Is opcode *REALLY* valid ? */
|
6322 |
if (unlikely(handler->handler == &gen_invalid)) {
|
6323 |
if (loglevel != 0) { |
6324 |
fprintf(logfile, "invalid/unsupported opcode: "
|
6325 |
"%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
6326 |
opc1(ctx.opcode), opc2(ctx.opcode), |
6327 |
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
6328 |
} else {
|
6329 |
printf("invalid/unsupported opcode: "
|
6330 |
"%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
6331 |
opc1(ctx.opcode), opc2(ctx.opcode), |
6332 |
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
6333 |
} |
6334 |
} else {
|
6335 |
if (unlikely((ctx.opcode & handler->inval) != 0)) { |
6336 |
if (loglevel != 0) { |
6337 |
fprintf(logfile, "invalid bits: %08x for opcode: "
|
6338 |
"%02x - %02x - %02x (%08x) " ADDRX "\n", |
6339 |
ctx.opcode & handler->inval, opc1(ctx.opcode), |
6340 |
opc2(ctx.opcode), opc3(ctx.opcode), |
6341 |
ctx.opcode, ctx.nip - 4);
|
6342 |
} else {
|
6343 |
printf("invalid bits: %08x for opcode: "
|
6344 |
"%02x - %02x - %02x (%08x) " ADDRX "\n", |
6345 |
ctx.opcode & handler->inval, opc1(ctx.opcode), |
6346 |
opc2(ctx.opcode), opc3(ctx.opcode), |
6347 |
ctx.opcode, ctx.nip - 4);
|
6348 |
} |
6349 |
GEN_EXCP_INVAL(ctxp); |
6350 |
break;
|
6351 |
} |
6352 |
} |
6353 |
(*(handler->handler))(&ctx); |
6354 |
#if defined(DO_PPC_STATISTICS)
|
6355 |
handler->count++; |
6356 |
#endif
|
6357 |
/* Check trace mode exceptions */
|
6358 |
if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
|
6359 |
(ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
6360 |
ctx.exception != POWERPC_SYSCALL && |
6361 |
ctx.exception != POWERPC_EXCP_TRAP && |
6362 |
ctx.exception != POWERPC_EXCP_BRANCH)) { |
6363 |
GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
|
6364 |
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
6365 |
(env->singlestep_enabled) || |
6366 |
num_insns >= max_insns)) { |
6367 |
/* if we reach a page boundary or are single stepping, stop
|
6368 |
* generation
|
6369 |
*/
|
6370 |
break;
|
6371 |
} |
6372 |
#if defined (DO_SINGLE_STEP)
|
6373 |
break;
|
6374 |
#endif
|
6375 |
} |
6376 |
if (tb->cflags & CF_LAST_IO)
|
6377 |
gen_io_end(); |
6378 |
if (ctx.exception == POWERPC_EXCP_NONE) {
|
6379 |
gen_goto_tb(&ctx, 0, ctx.nip);
|
6380 |
} else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
6381 |
if (unlikely(env->singlestep_enabled)) {
|
6382 |
gen_update_nip(&ctx, ctx.nip); |
6383 |
gen_op_debug(); |
6384 |
} |
6385 |
/* Generate the return instruction */
|
6386 |
tcg_gen_exit_tb(0);
|
6387 |
} |
6388 |
gen_icount_end(tb, num_insns); |
6389 |
*gen_opc_ptr = INDEX_op_end; |
6390 |
if (unlikely(search_pc)) {
|
6391 |
j = gen_opc_ptr - gen_opc_buf; |
6392 |
lj++; |
6393 |
while (lj <= j)
|
6394 |
gen_opc_instr_start[lj++] = 0;
|
6395 |
} else {
|
6396 |
tb->size = ctx.nip - pc_start; |
6397 |
tb->icount = num_insns; |
6398 |
} |
6399 |
#if defined(DEBUG_DISAS)
|
6400 |
if (loglevel & CPU_LOG_TB_CPU) {
|
6401 |
fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
|
6402 |
cpu_dump_state(env, logfile, fprintf, 0);
|
6403 |
} |
6404 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6405 |
int flags;
|
6406 |
flags = env->bfd_mach; |
6407 |
flags |= little_endian << 16;
|
6408 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
6409 |
target_disas(logfile, pc_start, ctx.nip - pc_start, flags); |
6410 |
fprintf(logfile, "\n");
|
6411 |
} |
6412 |
#endif
|
6413 |
} |
6414 |
|
6415 |
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
6416 |
{ |
6417 |
gen_intermediate_code_internal(env, tb, 0);
|
6418 |
} |
6419 |
|
6420 |
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
6421 |
{ |
6422 |
gen_intermediate_code_internal(env, tb, 1);
|
6423 |
} |
6424 |
|
6425 |
void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
6426 |
unsigned long searched_pc, int pc_pos, void *puc) |
6427 |
{ |
6428 |
int type, c;
|
6429 |
/* for PPC, we need to look at the micro operation to get the
|
6430 |
* access type */
|
6431 |
env->nip = gen_opc_pc[pc_pos]; |
6432 |
c = gen_opc_buf[pc_pos]; |
6433 |
switch(c) {
|
6434 |
#if defined(CONFIG_USER_ONLY)
|
6435 |
#define CASE3(op)\
|
6436 |
case INDEX_op_ ## op ## _raw |
6437 |
#else
|
6438 |
#define CASE3(op)\
|
6439 |
case INDEX_op_ ## op ## _user:\ |
6440 |
case INDEX_op_ ## op ## _kernel:\ |
6441 |
case INDEX_op_ ## op ## _hypv |
6442 |
#endif
|
6443 |
|
6444 |
CASE3(stfd): |
6445 |
CASE3(stfs): |
6446 |
CASE3(lfd): |
6447 |
CASE3(lfs): |
6448 |
type = ACCESS_FLOAT; |
6449 |
break;
|
6450 |
CASE3(lwarx): |
6451 |
type = ACCESS_RES; |
6452 |
break;
|
6453 |
CASE3(stwcx): |
6454 |
type = ACCESS_RES; |
6455 |
break;
|
6456 |
CASE3(eciwx): |
6457 |
CASE3(ecowx): |
6458 |
type = ACCESS_EXT; |
6459 |
break;
|
6460 |
default:
|
6461 |
type = ACCESS_INT; |
6462 |
break;
|
6463 |
} |
6464 |
env->access_type = type; |
6465 |
} |