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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | cb7cca1a | aurel32 | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | b346ff46 | bellard | /* is_jmp field values */
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25 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
26 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
27 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
28 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
29 | b346ff46 | bellard | |
30 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
31 | b346ff46 | bellard | |
32 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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33 | e83a8673 | edgar_igl | #define MAX_OP_PER_INSTR 64 |
34 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
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35 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
36 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
37 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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38 | b346ff46 | bellard | |
39 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
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40 | a208e54a | pbrook | single op may require several host instructions and regirster reloads.
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41 | a208e54a | pbrook | For now take a wild guess at 128 bytes, which should allow at least
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42 | a208e54a | pbrook | a couple of fixup instructions per argument. */
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43 | a208e54a | pbrook | #define TCG_MAX_OP_SIZE 128 |
44 | a208e54a | pbrook | |
45 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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46 | b346ff46 | bellard | |
47 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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48 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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49 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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50 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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51 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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52 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
53 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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54 | b346ff46 | bellard | |
55 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
56 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
57 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
58 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
59 | 3b46e624 | ths | |
60 | 79383c9c | blueswir1 | #include "qemu-log.h" |
61 | b346ff46 | bellard | |
62 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
63 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
64 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
65 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc); |
66 | d2856f1a | aurel32 | |
67 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
68 | 57fec1fe | bellard | void cpu_gen_init(void); |
69 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
70 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
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71 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
72 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
73 | 58fe2f10 | bellard | void *puc);
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74 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
75 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
76 | 58fe2f10 | bellard | void *puc);
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77 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
78 | 2e70f6ef | pbrook | void cpu_io_recompile(CPUState *env, void *retaddr); |
79 | 2e70f6ef | pbrook | TranslationBlock *tb_gen_code(CPUState *env, |
80 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
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81 | 2e70f6ef | pbrook | int cflags);
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82 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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83 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
84 | 00f82b8a | aurel32 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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85 | 2e12669a | bellard | int is_cpu_write_access);
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86 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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87 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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88 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
89 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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90 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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91 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
92 | 4d7a0880 | blueswir1 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
93 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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94 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
95 | 84b7b8e7 | bellard | { |
96 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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97 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
98 | 4d7a0880 | blueswir1 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
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99 | 84b7b8e7 | bellard | } |
100 | d4e8164f | bellard | |
101 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
102 | d4e8164f | bellard | |
103 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
104 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
105 | 4390df51 | bellard | |
106 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
107 | d4e8164f | bellard | |
108 | 4390df51 | bellard | /* estimated block size for TB allocation */
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109 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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110 | 4390df51 | bellard | according to the host CPU */
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111 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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112 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
113 | 4390df51 | bellard | #else
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114 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
115 | 4390df51 | bellard | #endif
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116 | 4390df51 | bellard | |
117 | 811d4cf4 | balrog | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
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118 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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119 | 4390df51 | bellard | #endif
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120 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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121 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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122 | d4e8164f | bellard | #endif
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123 | d4e8164f | bellard | |
124 | 2e70f6ef | pbrook | struct TranslationBlock {
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125 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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126 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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127 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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128 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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129 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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130 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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131 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
132 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
133 | 58fe2f10 | bellard | |
134 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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135 | 4390df51 | bellard | /* next matching tb for physical address. */
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136 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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137 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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138 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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139 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
140 | 5fafdf24 | ths | target_ulong page_addr[2];
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141 | 4390df51 | bellard | |
142 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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143 | d4e8164f | bellard | the code of this one. */
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144 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
145 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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146 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
147 | d4e8164f | bellard | #else
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148 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
149 | d4e8164f | bellard | #endif
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150 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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151 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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152 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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153 | d4e8164f | bellard | jmp_first */
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154 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
155 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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156 | 2e70f6ef | pbrook | uint32_t icount; |
157 | 2e70f6ef | pbrook | }; |
158 | d4e8164f | bellard | |
159 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
160 | b362e5e0 | pbrook | { |
161 | b362e5e0 | pbrook | target_ulong tmp; |
162 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
163 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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164 | b362e5e0 | pbrook | } |
165 | b362e5e0 | pbrook | |
166 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
167 | d4e8164f | bellard | { |
168 | b362e5e0 | pbrook | target_ulong tmp; |
169 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
170 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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171 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
172 | d4e8164f | bellard | } |
173 | d4e8164f | bellard | |
174 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
175 | 4390df51 | bellard | { |
176 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
177 | 4390df51 | bellard | } |
178 | 4390df51 | bellard | |
179 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
180 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
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181 | 0124311e | bellard | void tb_flush(CPUState *env);
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182 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
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183 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
184 | 2e70f6ef | pbrook | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
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185 | d4e8164f | bellard | |
186 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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187 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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188 | 26a5f13b | bellard | extern int code_gen_max_blocks; |
189 | d4e8164f | bellard | |
190 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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191 | 4390df51 | bellard | |
192 | 4390df51 | bellard | #if defined(__powerpc__)
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193 | 810260a8 | malc | extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
194 | 810260a8 | malc | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
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195 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
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196 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
197 | 4390df51 | bellard | { |
198 | 4390df51 | bellard | /* patch the branch destination */
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199 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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200 | 1235fc06 | ths | /* no need to flush icache explicitly */
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201 | 4390df51 | bellard | } |
202 | 811d4cf4 | balrog | #elif defined(__arm__)
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203 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
204 | 811d4cf4 | balrog | { |
205 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
206 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
207 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
208 | 811d4cf4 | balrog | |
209 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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210 | 811d4cf4 | balrog | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; |
211 | 811d4cf4 | balrog | |
212 | 811d4cf4 | balrog | /* flush icache */
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213 | 811d4cf4 | balrog | _beg = jmp_addr; |
214 | 811d4cf4 | balrog | _end = jmp_addr + 4;
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215 | 811d4cf4 | balrog | _flg = 0;
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216 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
217 | 811d4cf4 | balrog | } |
218 | 4390df51 | bellard | #endif
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219 | d4e8164f | bellard | |
220 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
221 | 4cbb86e1 | bellard | int n, unsigned long addr) |
222 | 4cbb86e1 | bellard | { |
223 | 4cbb86e1 | bellard | unsigned long offset; |
224 | 4cbb86e1 | bellard | |
225 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
226 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
227 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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228 | 4cbb86e1 | bellard | if (offset != 0xffff) |
229 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
230 | 4cbb86e1 | bellard | } |
231 | 4cbb86e1 | bellard | |
232 | d4e8164f | bellard | #else
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233 | d4e8164f | bellard | |
234 | d4e8164f | bellard | /* set the jump target */
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235 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
236 | d4e8164f | bellard | int n, unsigned long addr) |
237 | d4e8164f | bellard | { |
238 | 95f7652d | bellard | tb->tb_next[n] = addr; |
239 | d4e8164f | bellard | } |
240 | d4e8164f | bellard | |
241 | d4e8164f | bellard | #endif
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242 | d4e8164f | bellard | |
243 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
244 | d4e8164f | bellard | TranslationBlock *tb_next) |
245 | d4e8164f | bellard | { |
246 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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247 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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248 | cf25629d | bellard | /* patch the native jump address */
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249 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
250 | 3b46e624 | ths | |
251 | cf25629d | bellard | /* add in TB jmp circular list */
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252 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
253 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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254 | cf25629d | bellard | } |
255 | d4e8164f | bellard | } |
256 | d4e8164f | bellard | |
257 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
258 | a513fe19 | bellard | |
259 | d4e8164f | bellard | #ifndef offsetof
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260 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
261 | d4e8164f | bellard | #endif
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262 | d4e8164f | bellard | |
263 | d549f7d9 | bellard | #if defined(_WIN32)
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264 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
265 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
266 | d549f7d9 | bellard | #elif defined(__APPLE__)
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267 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
268 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
269 | d549f7d9 | bellard | #else
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270 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
271 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
272 | d549f7d9 | bellard | #endif
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273 | d549f7d9 | bellard | |
274 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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275 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
276 | 75913b72 | bellard | |
277 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
278 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
279 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
280 | 33417e70 | bellard | |
281 | d5975363 | pbrook | #include "qemu-lock.h" |
282 | d4e8164f | bellard | |
283 | d4e8164f | bellard | extern spinlock_t tb_lock;
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284 | d4e8164f | bellard | |
285 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
286 | 6e59c1db | bellard | |
287 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
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288 | 6e59c1db | bellard | |
289 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
290 | 6e59c1db | bellard | void *retaddr);
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291 | 6e59c1db | bellard | |
292 | 79383c9c | blueswir1 | #include "softmmu_defs.h" |
293 | 79383c9c | blueswir1 | |
294 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
295 | 6e59c1db | bellard | #define MEMSUFFIX _code
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296 | 6e59c1db | bellard | #define env cpu_single_env
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297 | 6e59c1db | bellard | |
298 | 6e59c1db | bellard | #define DATA_SIZE 1 |
299 | 6e59c1db | bellard | #include "softmmu_header.h" |
300 | 6e59c1db | bellard | |
301 | 6e59c1db | bellard | #define DATA_SIZE 2 |
302 | 6e59c1db | bellard | #include "softmmu_header.h" |
303 | 6e59c1db | bellard | |
304 | 6e59c1db | bellard | #define DATA_SIZE 4 |
305 | 6e59c1db | bellard | #include "softmmu_header.h" |
306 | 6e59c1db | bellard | |
307 | c27004ec | bellard | #define DATA_SIZE 8 |
308 | c27004ec | bellard | #include "softmmu_header.h" |
309 | c27004ec | bellard | |
310 | 6e59c1db | bellard | #undef ACCESS_TYPE
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311 | 6e59c1db | bellard | #undef MEMSUFFIX
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312 | 6e59c1db | bellard | #undef env
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313 | 6e59c1db | bellard | |
314 | 6e59c1db | bellard | #endif
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315 | 4390df51 | bellard | |
316 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
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317 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
318 | 4390df51 | bellard | { |
319 | 4390df51 | bellard | return addr;
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320 | 4390df51 | bellard | } |
321 | 4390df51 | bellard | #else
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322 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
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323 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
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324 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
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325 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
326 | 4390df51 | bellard | { |
327 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
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328 | 4390df51 | bellard | |
329 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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330 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
331 | 551bd27f | ths | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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332 | 551bd27f | ths | (addr & TARGET_PAGE_MASK))) { |
333 | c27004ec | bellard | ldub_code(addr); |
334 | c27004ec | bellard | } |
335 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
336 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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337 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
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338 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
339 | 6c36d3fa | blueswir1 | #else
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340 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
341 | 6c36d3fa | blueswir1 | #endif
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342 | 4390df51 | bellard | } |
343 | 4d7a0880 | blueswir1 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
344 | 4390df51 | bellard | } |
345 | 2e70f6ef | pbrook | |
346 | bf20dc07 | ths | /* Deterministic execution requires that IO only be performed on the last
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347 | 2e70f6ef | pbrook | instruction of a TB so that interrupts take effect immediately. */
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348 | 2e70f6ef | pbrook | static inline int can_do_io(CPUState *env) |
349 | 2e70f6ef | pbrook | { |
350 | 2e70f6ef | pbrook | if (!use_icount)
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351 | 2e70f6ef | pbrook | return 1; |
352 | 2e70f6ef | pbrook | |
353 | 2e70f6ef | pbrook | /* If not executing code then assume we are ok. */
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354 | 2e70f6ef | pbrook | if (!env->current_tb)
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355 | 2e70f6ef | pbrook | return 1; |
356 | 2e70f6ef | pbrook | |
357 | 2e70f6ef | pbrook | return env->can_do_io != 0; |
358 | 2e70f6ef | pbrook | } |
359 | 4390df51 | bellard | #endif
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360 | 9df217a3 | bellard | |
361 | 9df217a3 | bellard | #ifdef USE_KQEMU
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362 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
363 | f32fc648 | bellard | |
364 | da260249 | bellard | #define MSR_QPI_COMMBASE 0xfabe0010 |
365 | da260249 | bellard | |
366 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
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367 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
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368 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
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369 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
370 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
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371 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
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372 | da260249 | bellard | void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
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373 | da260249 | bellard | ram_addr_t phys_offset); |
374 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
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375 | f32fc648 | bellard | void kqemu_record_dump(void); |
376 | 9df217a3 | bellard | |
377 | da260249 | bellard | extern uint32_t kqemu_comm_base;
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378 | da260249 | bellard | |
379 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
380 | 9df217a3 | bellard | { |
381 | 9df217a3 | bellard | return(env->kqemu_enabled &&
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382 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
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383 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
384 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
385 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
386 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
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387 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
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388 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
389 | 9df217a3 | bellard | } |
390 | 9df217a3 | bellard | |
391 | 9df217a3 | bellard | #endif |