Revision 3a807dec target-arm/helper.c
| b/target-arm/helper.c | ||
|---|---|---|
| 203 | 203 |
cpu_reset_model_id(env, id); |
| 204 | 204 |
#if defined (CONFIG_USER_ONLY) |
| 205 | 205 |
env->uncached_cpsr = ARM_CPU_MODE_USR; |
| 206 |
/* For user mode we must enable access to coprocessors */ |
|
| 206 | 207 |
env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
| 208 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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|
| 209 |
env->cp15.c15_cpar = 3; |
|
| 210 |
} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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|
| 211 |
env->cp15.c15_cpar = 1; |
|
| 212 |
} |
|
| 207 | 213 |
#else |
| 208 | 214 |
/* SVC mode with interrupts disabled. */ |
| 209 | 215 |
env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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