Revision 3aa22b4b

b/target-arm/translate.c
1930 1930 
            break;
1931 1931 
        case 0x2: /* lsl */
1932 1932 
            gen_op_shll_T1_T0_cc();
1933 
            gen_op_logic_T1_cc();
1933 1934 
            break;
1934 1935 
        case 0x3: /* lsr */
1935 1936 
            gen_op_shrl_T1_T0_cc();
1937 
            gen_op_logic_T1_cc();
1936 1938 
            break;
1937 1939 
        case 0x4: /* asr */
1938 1940 
            gen_op_sarl_T1_T0_cc();
1941 
            gen_op_logic_T1_cc();
1939 1942 
            break;
1940 1943 
        case 0x5: /* adc */
1941 1944 
            gen_op_adcl_T0_T1_cc();
......
1945 1948 
            break;
1946 1949 
        case 0x7: /* ror */
1947 1950 
            gen_op_rorl_T1_T0_cc();
1951 
            gen_op_logic_T1_cc();
1948 1952 
            break;
1949 1953 
        case 0x8: /* tst */
1950 1954 
            gen_op_andl_T0_T1();

Also available in: Unified diff