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@item Avnet LX60/LX110/LX200 boards (Xtensa)

* Xtensa System emulator::

@node Xtensa System emulator

@section Xtensa System emulator

@cindex system emulation (Xtensa)

Two executables cover simulation of both Xtensa endian options,

@file{qemu-system-xtensa} and @file{qemu-system-xtensaeb}.

Two different machine types are emulated:

@itemize @minus

@item

Xtensa emulator pseudo board "sim"

@item

Avnet LX60/LX110/LX200 board

@end itemize

The sim pseudo board emulation provides an environment similiar

to one provided by the proprietary Tensilica ISS.

It supports:

@itemize @minus

@item

A range of Xtensa CPUs, default is the DC232B

@item

Console and filesystem access via semihosting calls

@end itemize

The Avnet LX60/LX110/LX200 emulation supports:

@itemize @minus

@item

A range of Xtensa CPUs, default is the DC232B

@item

16550 UART

@item

OpenCores 10/100 Mbps Ethernet MAC

@end itemize

@c man begin OPTIONS

The following options are specific to the Xtensa emulation:

@table @option

@item -semihosting

Enable semihosting syscall emulation.

Xtensa semihosting provides basic file IO calls, such as open/read/write/seek/select.

Tensilica baremetal libc for ISS and linux platform "sim" use this interface.

Note that this allows guest direct access to the host filesystem,

so should only be used with trusted guest OS.

@end table

* intro_features::         Features

* intro_x86_emulation::    x86 and x86-64 emulation

* intro_arm_emulation::    ARM emulation

* intro_mips_emulation::   MIPS emulation

* intro_ppc_emulation::    PowerPC emulation

* intro_sparc_emulation::  Sparc32 and Sparc64 emulation

* intro_xtensa_emulation:: Xtensa emulation

* intro_other_emulation::  Other CPU emulation

@node intro_xtensa_emulation

@section Xtensa emulation

@itemize

@item Core Xtensa ISA emulation, including most options: code density,

loop, extended L32R, 16- and 32-bit multiplication, 32-bit division,

MAC16, miscellaneous operations, boolean, multiprocessor synchronization,

conditional store, exceptions, relocatable vectors, unaligned exception,

interrupts (including high priority and timer), hardware alignment,

region protection, region translation, MMU, windowed registers, thread

pointer, processor ID.

@item Not implemented options: FP coprocessor, coprocessor context,

data/instruction cache (including cache prefetch and locking), XLMI,

processor interface, debug. Also options not covered by the core ISA

(e.g. FLIX, wide branches) are not implemented.

@item Can run most Xtensa Linux binaries.

@item New core configuration that requires no additional instructions

may be created from overlay with minimal amount of hand-written code.

@end itemize