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1 | 7e7c5e4c | balrog | /*
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2 | 7e7c5e4c | balrog | * TI TWL92230C energy-management companion device for the OMAP24xx.
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3 | 7e7c5e4c | balrog | * Aka. Menelaus (N4200 MENELAUS1_V2.2)
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4 | 7e7c5e4c | balrog | *
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5 | 7e7c5e4c | balrog | * Copyright (C) 2008 Nokia Corporation
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6 | 7e7c5e4c | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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7 | 7e7c5e4c | balrog | *
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8 | 7e7c5e4c | balrog | * This program is free software; you can redistribute it and/or
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9 | 7e7c5e4c | balrog | * modify it under the terms of the GNU General Public License as
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10 | 7e7c5e4c | balrog | * published by the Free Software Foundation; either version 2 or
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11 | 7e7c5e4c | balrog | * (at your option) version 3 of the License.
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12 | 7e7c5e4c | balrog | *
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13 | 7e7c5e4c | balrog | * This program is distributed in the hope that it will be useful,
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14 | 7e7c5e4c | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 7e7c5e4c | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 7e7c5e4c | balrog | * GNU General Public License for more details.
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17 | 7e7c5e4c | balrog | *
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18 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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19 | fad6cb1a | aurel32 | * with this program; if not, write to the Free Software Foundation, Inc.,
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20 | fad6cb1a | aurel32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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21 | 7e7c5e4c | balrog | */
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22 | 7e7c5e4c | balrog | |
23 | 7e7c5e4c | balrog | #include "hw.h" |
24 | 7e7c5e4c | balrog | #include "qemu-timer.h" |
25 | 7e7c5e4c | balrog | #include "i2c.h" |
26 | 7e7c5e4c | balrog | #include "sysemu.h" |
27 | 7e7c5e4c | balrog | #include "console.h" |
28 | 7e7c5e4c | balrog | |
29 | 7e7c5e4c | balrog | #define VERBOSE 1 |
30 | 7e7c5e4c | balrog | |
31 | bc24a225 | Paul Brook | typedef struct { |
32 | 7e7c5e4c | balrog | i2c_slave i2c; |
33 | 7e7c5e4c | balrog | |
34 | 7e7c5e4c | balrog | int firstbyte;
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35 | 7e7c5e4c | balrog | uint8_t reg; |
36 | 7e7c5e4c | balrog | |
37 | 7e7c5e4c | balrog | uint8_t vcore[5];
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38 | 7e7c5e4c | balrog | uint8_t dcdc[3];
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39 | 7e7c5e4c | balrog | uint8_t ldo[8];
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40 | 7e7c5e4c | balrog | uint8_t sleep[2];
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41 | 7e7c5e4c | balrog | uint8_t osc; |
42 | 7e7c5e4c | balrog | uint8_t detect; |
43 | 7e7c5e4c | balrog | uint16_t mask; |
44 | 7e7c5e4c | balrog | uint16_t status; |
45 | 7e7c5e4c | balrog | uint8_t dir; |
46 | 7e7c5e4c | balrog | uint8_t inputs; |
47 | 7e7c5e4c | balrog | uint8_t outputs; |
48 | 7e7c5e4c | balrog | uint8_t bbsms; |
49 | 7e7c5e4c | balrog | uint8_t pull[4];
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50 | 7e7c5e4c | balrog | uint8_t mmc_ctrl[3];
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51 | 7e7c5e4c | balrog | uint8_t mmc_debounce; |
52 | 7e7c5e4c | balrog | struct {
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53 | 7e7c5e4c | balrog | uint8_t ctrl; |
54 | 7e7c5e4c | balrog | uint16_t comp; |
55 | b0f74c87 | balrog | QEMUTimer *hz_tm; |
56 | 7e7c5e4c | balrog | int64_t next; |
57 | 7e7c5e4c | balrog | struct tm tm;
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58 | 7e7c5e4c | balrog | struct tm new;
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59 | 7e7c5e4c | balrog | struct tm alm;
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60 | aec454d2 | balrog | int sec_offset;
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61 | aec454d2 | balrog | int alm_sec;
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62 | aec454d2 | balrog | int next_comp;
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63 | 7e7c5e4c | balrog | } rtc; |
64 | d3356811 | Paul Brook | qemu_irq out[4];
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65 | 7e7c5e4c | balrog | qemu_irq *in; |
66 | 7e7c5e4c | balrog | int pwrbtn_state;
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67 | 7e7c5e4c | balrog | qemu_irq pwrbtn; |
68 | bc24a225 | Paul Brook | } MenelausState; |
69 | 7e7c5e4c | balrog | |
70 | bc24a225 | Paul Brook | static inline void menelaus_update(MenelausState *s) |
71 | 7e7c5e4c | balrog | { |
72 | d3356811 | Paul Brook | qemu_set_irq(s->out[3], s->status & ~s->mask);
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73 | 7e7c5e4c | balrog | } |
74 | 7e7c5e4c | balrog | |
75 | bc24a225 | Paul Brook | static inline void menelaus_rtc_start(MenelausState *s) |
76 | 7e7c5e4c | balrog | { |
77 | 7e7c5e4c | balrog | s->rtc.next =+ qemu_get_clock(rt_clock); |
78 | b0f74c87 | balrog | qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); |
79 | 7e7c5e4c | balrog | } |
80 | 7e7c5e4c | balrog | |
81 | bc24a225 | Paul Brook | static inline void menelaus_rtc_stop(MenelausState *s) |
82 | 7e7c5e4c | balrog | { |
83 | b0f74c87 | balrog | qemu_del_timer(s->rtc.hz_tm); |
84 | 7e7c5e4c | balrog | s->rtc.next =- qemu_get_clock(rt_clock); |
85 | 7e7c5e4c | balrog | if (s->rtc.next < 1) |
86 | 7e7c5e4c | balrog | s->rtc.next = 1;
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87 | 7e7c5e4c | balrog | } |
88 | 7e7c5e4c | balrog | |
89 | bc24a225 | Paul Brook | static void menelaus_rtc_update(MenelausState *s) |
90 | 7e7c5e4c | balrog | { |
91 | aec454d2 | balrog | qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset); |
92 | 7e7c5e4c | balrog | } |
93 | 7e7c5e4c | balrog | |
94 | bc24a225 | Paul Brook | static void menelaus_alm_update(MenelausState *s) |
95 | 7e7c5e4c | balrog | { |
96 | 7e7c5e4c | balrog | if ((s->rtc.ctrl & 3) == 3) |
97 | aec454d2 | balrog | s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset; |
98 | 7e7c5e4c | balrog | } |
99 | 7e7c5e4c | balrog | |
100 | 7e7c5e4c | balrog | static void menelaus_rtc_hz(void *opaque) |
101 | 7e7c5e4c | balrog | { |
102 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
103 | 7e7c5e4c | balrog | |
104 | aec454d2 | balrog | s->rtc.next_comp --; |
105 | aec454d2 | balrog | s->rtc.alm_sec --; |
106 | 7e7c5e4c | balrog | s->rtc.next += 1000;
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107 | b0f74c87 | balrog | qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); |
108 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */ |
109 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
110 | 7e7c5e4c | balrog | if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec) |
111 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
112 | 7e7c5e4c | balrog | else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min) |
113 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
114 | 7e7c5e4c | balrog | else if (!s->rtc.tm.tm_hour) |
115 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
116 | 7e7c5e4c | balrog | } else
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117 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
118 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */ |
119 | aec454d2 | balrog | if (s->rtc.alm_sec == 0) |
120 | 7e7c5e4c | balrog | s->status |= 1 << 9; /* RTCALM */ |
121 | 7e7c5e4c | balrog | /* TODO: wake-up */
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122 | 7e7c5e4c | balrog | } |
123 | aec454d2 | balrog | if (s->rtc.next_comp <= 0) { |
124 | 7e7c5e4c | balrog | s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000); |
125 | aec454d2 | balrog | s->rtc.next_comp = 3600;
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126 | 7e7c5e4c | balrog | } |
127 | 7e7c5e4c | balrog | menelaus_update(s); |
128 | 7e7c5e4c | balrog | } |
129 | 7e7c5e4c | balrog | |
130 | 8fcd3692 | blueswir1 | static void menelaus_reset(i2c_slave *i2c) |
131 | 7e7c5e4c | balrog | { |
132 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) i2c; |
133 | 7e7c5e4c | balrog | s->reg = 0x00;
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134 | 7e7c5e4c | balrog | |
135 | 7e7c5e4c | balrog | s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */ |
136 | 7e7c5e4c | balrog | s->vcore[1] = 0x05; |
137 | 7e7c5e4c | balrog | s->vcore[2] = 0x02; |
138 | 7e7c5e4c | balrog | s->vcore[3] = 0x0c; |
139 | 7e7c5e4c | balrog | s->vcore[4] = 0x03; |
140 | 7e7c5e4c | balrog | s->dcdc[0] = 0x33; /* Depends on wiring */ |
141 | 7e7c5e4c | balrog | s->dcdc[1] = 0x03; |
142 | 7e7c5e4c | balrog | s->dcdc[2] = 0x00; |
143 | 7e7c5e4c | balrog | s->ldo[0] = 0x95; |
144 | 7e7c5e4c | balrog | s->ldo[1] = 0x7e; |
145 | 7e7c5e4c | balrog | s->ldo[2] = 0x00; |
146 | 7e7c5e4c | balrog | s->ldo[3] = 0x00; /* Depends on wiring */ |
147 | 7e7c5e4c | balrog | s->ldo[4] = 0x03; /* Depends on wiring */ |
148 | 7e7c5e4c | balrog | s->ldo[5] = 0x00; |
149 | 7e7c5e4c | balrog | s->ldo[6] = 0x00; |
150 | 7e7c5e4c | balrog | s->ldo[7] = 0x00; |
151 | 7e7c5e4c | balrog | s->sleep[0] = 0x00; |
152 | 7e7c5e4c | balrog | s->sleep[1] = 0x00; |
153 | 7e7c5e4c | balrog | s->osc = 0x01;
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154 | 7e7c5e4c | balrog | s->detect = 0x09;
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155 | 7e7c5e4c | balrog | s->mask = 0x0fff;
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156 | 7e7c5e4c | balrog | s->status = 0;
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157 | 7e7c5e4c | balrog | s->dir = 0x07;
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158 | 7e7c5e4c | balrog | s->outputs = 0x00;
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159 | 7e7c5e4c | balrog | s->bbsms = 0x00;
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160 | 7e7c5e4c | balrog | s->pull[0] = 0x00; |
161 | 7e7c5e4c | balrog | s->pull[1] = 0x00; |
162 | 7e7c5e4c | balrog | s->pull[2] = 0x00; |
163 | 7e7c5e4c | balrog | s->pull[3] = 0x00; |
164 | 7e7c5e4c | balrog | s->mmc_ctrl[0] = 0x03; |
165 | 7e7c5e4c | balrog | s->mmc_ctrl[1] = 0xc0; |
166 | 7e7c5e4c | balrog | s->mmc_ctrl[2] = 0x00; |
167 | 7e7c5e4c | balrog | s->mmc_debounce = 0x05;
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168 | 7e7c5e4c | balrog | |
169 | 7e7c5e4c | balrog | if (s->rtc.ctrl & 1) |
170 | 7e7c5e4c | balrog | menelaus_rtc_stop(s); |
171 | 7e7c5e4c | balrog | s->rtc.ctrl = 0x00;
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172 | 7e7c5e4c | balrog | s->rtc.comp = 0x0000;
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173 | 7e7c5e4c | balrog | s->rtc.next = 1000;
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174 | aec454d2 | balrog | s->rtc.sec_offset = 0;
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175 | aec454d2 | balrog | s->rtc.next_comp = 1800;
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176 | aec454d2 | balrog | s->rtc.alm_sec = 1800;
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177 | 7e7c5e4c | balrog | s->rtc.alm.tm_sec = 0x00;
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178 | 7e7c5e4c | balrog | s->rtc.alm.tm_min = 0x00;
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179 | 7e7c5e4c | balrog | s->rtc.alm.tm_hour = 0x00;
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180 | 7e7c5e4c | balrog | s->rtc.alm.tm_mday = 0x01;
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181 | 7e7c5e4c | balrog | s->rtc.alm.tm_mon = 0x00;
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182 | 7e7c5e4c | balrog | s->rtc.alm.tm_year = 2004;
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183 | 7e7c5e4c | balrog | menelaus_update(s); |
184 | 7e7c5e4c | balrog | } |
185 | 7e7c5e4c | balrog | |
186 | 7e7c5e4c | balrog | static inline uint8_t to_bcd(int val) |
187 | 7e7c5e4c | balrog | { |
188 | 7e7c5e4c | balrog | return ((val / 10) << 4) | (val % 10); |
189 | 7e7c5e4c | balrog | } |
190 | 7e7c5e4c | balrog | |
191 | 7e7c5e4c | balrog | static inline int from_bcd(uint8_t val) |
192 | 7e7c5e4c | balrog | { |
193 | 7e7c5e4c | balrog | return ((val >> 4) * 10) + (val & 0x0f); |
194 | 7e7c5e4c | balrog | } |
195 | 7e7c5e4c | balrog | |
196 | 7e7c5e4c | balrog | static void menelaus_gpio_set(void *opaque, int line, int level) |
197 | 7e7c5e4c | balrog | { |
198 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
199 | 7e7c5e4c | balrog | |
200 | 7e7c5e4c | balrog | /* No interrupt generated */
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201 | 7e7c5e4c | balrog | s->inputs &= ~(1 << line);
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202 | 7e7c5e4c | balrog | s->inputs |= level << line; |
203 | 7e7c5e4c | balrog | } |
204 | 7e7c5e4c | balrog | |
205 | 7e7c5e4c | balrog | static void menelaus_pwrbtn_set(void *opaque, int line, int level) |
206 | 7e7c5e4c | balrog | { |
207 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
208 | 7e7c5e4c | balrog | |
209 | 7e7c5e4c | balrog | if (!s->pwrbtn_state && level) {
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210 | 7e7c5e4c | balrog | s->status |= 1 << 11; /* PSHBTN */ |
211 | 7e7c5e4c | balrog | menelaus_update(s); |
212 | 7e7c5e4c | balrog | } |
213 | 7e7c5e4c | balrog | s->pwrbtn_state = level; |
214 | 7e7c5e4c | balrog | } |
215 | 7e7c5e4c | balrog | |
216 | 7e7c5e4c | balrog | #define MENELAUS_REV 0x01 |
217 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL1 0x02 |
218 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL2 0x03 |
219 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL3 0x04 |
220 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL4 0x05 |
221 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL5 0x06 |
222 | 7e7c5e4c | balrog | #define MENELAUS_DCDC_CTRL1 0x07 |
223 | 7e7c5e4c | balrog | #define MENELAUS_DCDC_CTRL2 0x08 |
224 | 7e7c5e4c | balrog | #define MENELAUS_DCDC_CTRL3 0x09 |
225 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL1 0x0a |
226 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL2 0x0b |
227 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL3 0x0c |
228 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL4 0x0d |
229 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL5 0x0e |
230 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL6 0x0f |
231 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL7 0x10 |
232 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL8 0x11 |
233 | 7e7c5e4c | balrog | #define MENELAUS_SLEEP_CTRL1 0x12 |
234 | 7e7c5e4c | balrog | #define MENELAUS_SLEEP_CTRL2 0x13 |
235 | 7e7c5e4c | balrog | #define MENELAUS_DEVICE_OFF 0x14 |
236 | 7e7c5e4c | balrog | #define MENELAUS_OSC_CTRL 0x15 |
237 | 7e7c5e4c | balrog | #define MENELAUS_DETECT_CTRL 0x16 |
238 | 7e7c5e4c | balrog | #define MENELAUS_INT_MASK1 0x17 |
239 | 7e7c5e4c | balrog | #define MENELAUS_INT_MASK2 0x18 |
240 | 7e7c5e4c | balrog | #define MENELAUS_INT_STATUS1 0x19 |
241 | 7e7c5e4c | balrog | #define MENELAUS_INT_STATUS2 0x1a |
242 | 7e7c5e4c | balrog | #define MENELAUS_INT_ACK1 0x1b |
243 | 7e7c5e4c | balrog | #define MENELAUS_INT_ACK2 0x1c |
244 | 7e7c5e4c | balrog | #define MENELAUS_GPIO_CTRL 0x1d |
245 | 7e7c5e4c | balrog | #define MENELAUS_GPIO_IN 0x1e |
246 | 7e7c5e4c | balrog | #define MENELAUS_GPIO_OUT 0x1f |
247 | 7e7c5e4c | balrog | #define MENELAUS_BBSMS 0x20 |
248 | 7e7c5e4c | balrog | #define MENELAUS_RTC_CTRL 0x21 |
249 | 7e7c5e4c | balrog | #define MENELAUS_RTC_UPDATE 0x22 |
250 | 7e7c5e4c | balrog | #define MENELAUS_RTC_SEC 0x23 |
251 | 7e7c5e4c | balrog | #define MENELAUS_RTC_MIN 0x24 |
252 | 7e7c5e4c | balrog | #define MENELAUS_RTC_HR 0x25 |
253 | 7e7c5e4c | balrog | #define MENELAUS_RTC_DAY 0x26 |
254 | 7e7c5e4c | balrog | #define MENELAUS_RTC_MON 0x27 |
255 | 7e7c5e4c | balrog | #define MENELAUS_RTC_YR 0x28 |
256 | 7e7c5e4c | balrog | #define MENELAUS_RTC_WKDAY 0x29 |
257 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_SEC 0x2a |
258 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_MIN 0x2b |
259 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_HR 0x2c |
260 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_DAY 0x2d |
261 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_MON 0x2e |
262 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_YR 0x2f |
263 | 7e7c5e4c | balrog | #define MENELAUS_RTC_COMP_MSB 0x30 |
264 | 7e7c5e4c | balrog | #define MENELAUS_RTC_COMP_LSB 0x31 |
265 | 7e7c5e4c | balrog | #define MENELAUS_S1_PULL_EN 0x32 |
266 | 7e7c5e4c | balrog | #define MENELAUS_S1_PULL_DIR 0x33 |
267 | 7e7c5e4c | balrog | #define MENELAUS_S2_PULL_EN 0x34 |
268 | 7e7c5e4c | balrog | #define MENELAUS_S2_PULL_DIR 0x35 |
269 | 7e7c5e4c | balrog | #define MENELAUS_MCT_CTRL1 0x36 |
270 | 7e7c5e4c | balrog | #define MENELAUS_MCT_CTRL2 0x37 |
271 | 7e7c5e4c | balrog | #define MENELAUS_MCT_CTRL3 0x38 |
272 | 7e7c5e4c | balrog | #define MENELAUS_MCT_PIN_ST 0x39 |
273 | 7e7c5e4c | balrog | #define MENELAUS_DEBOUNCE1 0x3a |
274 | 7e7c5e4c | balrog | |
275 | 7e7c5e4c | balrog | static uint8_t menelaus_read(void *opaque, uint8_t addr) |
276 | 7e7c5e4c | balrog | { |
277 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
278 | 7e7c5e4c | balrog | int reg = 0; |
279 | 7e7c5e4c | balrog | |
280 | 7e7c5e4c | balrog | switch (addr) {
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281 | 7e7c5e4c | balrog | case MENELAUS_REV:
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282 | 7e7c5e4c | balrog | return 0x22; |
283 | 7e7c5e4c | balrog | |
284 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL5: reg ++;
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285 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL4: reg ++;
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286 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL3: reg ++;
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287 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL2: reg ++;
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288 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL1:
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289 | 7e7c5e4c | balrog | return s->vcore[reg];
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290 | 7e7c5e4c | balrog | |
291 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL3: reg ++;
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292 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL2: reg ++;
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293 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL1:
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294 | 7e7c5e4c | balrog | return s->dcdc[reg];
|
295 | 7e7c5e4c | balrog | |
296 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL8: reg ++;
|
297 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL7: reg ++;
|
298 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL6: reg ++;
|
299 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL5: reg ++;
|
300 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL4: reg ++;
|
301 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL3: reg ++;
|
302 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL2: reg ++;
|
303 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL1:
|
304 | 7e7c5e4c | balrog | return s->ldo[reg];
|
305 | 7e7c5e4c | balrog | |
306 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL2: reg ++;
|
307 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL1:
|
308 | 7e7c5e4c | balrog | return s->sleep[reg];
|
309 | 7e7c5e4c | balrog | |
310 | 7e7c5e4c | balrog | case MENELAUS_DEVICE_OFF:
|
311 | 7e7c5e4c | balrog | return 0; |
312 | 7e7c5e4c | balrog | |
313 | 7e7c5e4c | balrog | case MENELAUS_OSC_CTRL:
|
314 | 7e7c5e4c | balrog | return s->osc | (1 << 7); /* CLK32K_GOOD */ |
315 | 7e7c5e4c | balrog | |
316 | 7e7c5e4c | balrog | case MENELAUS_DETECT_CTRL:
|
317 | 7e7c5e4c | balrog | return s->detect;
|
318 | 7e7c5e4c | balrog | |
319 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK1:
|
320 | 7e7c5e4c | balrog | return (s->mask >> 0) & 0xff; |
321 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK2:
|
322 | 7e7c5e4c | balrog | return (s->mask >> 8) & 0xff; |
323 | 7e7c5e4c | balrog | |
324 | 7e7c5e4c | balrog | case MENELAUS_INT_STATUS1:
|
325 | 7e7c5e4c | balrog | return (s->status >> 0) & 0xff; |
326 | 7e7c5e4c | balrog | case MENELAUS_INT_STATUS2:
|
327 | 7e7c5e4c | balrog | return (s->status >> 8) & 0xff; |
328 | 7e7c5e4c | balrog | |
329 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK1:
|
330 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK2:
|
331 | 7e7c5e4c | balrog | return 0; |
332 | 7e7c5e4c | balrog | |
333 | 7e7c5e4c | balrog | case MENELAUS_GPIO_CTRL:
|
334 | 7e7c5e4c | balrog | return s->dir;
|
335 | 7e7c5e4c | balrog | case MENELAUS_GPIO_IN:
|
336 | 7e7c5e4c | balrog | return s->inputs | (~s->dir & s->outputs);
|
337 | 7e7c5e4c | balrog | case MENELAUS_GPIO_OUT:
|
338 | 7e7c5e4c | balrog | return s->outputs;
|
339 | 7e7c5e4c | balrog | |
340 | 7e7c5e4c | balrog | case MENELAUS_BBSMS:
|
341 | 7e7c5e4c | balrog | return s->bbsms;
|
342 | 7e7c5e4c | balrog | |
343 | 7e7c5e4c | balrog | case MENELAUS_RTC_CTRL:
|
344 | 7e7c5e4c | balrog | return s->rtc.ctrl;
|
345 | 7e7c5e4c | balrog | case MENELAUS_RTC_UPDATE:
|
346 | 7e7c5e4c | balrog | return 0x00; |
347 | 7e7c5e4c | balrog | case MENELAUS_RTC_SEC:
|
348 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
349 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_sec);
|
350 | 7e7c5e4c | balrog | case MENELAUS_RTC_MIN:
|
351 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
352 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_min);
|
353 | 7e7c5e4c | balrog | case MENELAUS_RTC_HR:
|
354 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
355 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */ |
356 | 7e7c5e4c | balrog | return to_bcd((s->rtc.tm.tm_hour % 12) + 1) | |
357 | 7e7c5e4c | balrog | (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */ |
358 | 7e7c5e4c | balrog | else
|
359 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_hour);
|
360 | 7e7c5e4c | balrog | case MENELAUS_RTC_DAY:
|
361 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
362 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_mday);
|
363 | 7e7c5e4c | balrog | case MENELAUS_RTC_MON:
|
364 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
365 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_mon + 1); |
366 | 7e7c5e4c | balrog | case MENELAUS_RTC_YR:
|
367 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
368 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_year - 2000); |
369 | 7e7c5e4c | balrog | case MENELAUS_RTC_WKDAY:
|
370 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
371 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_wday);
|
372 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_SEC:
|
373 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_sec);
|
374 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MIN:
|
375 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_min);
|
376 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_HR:
|
377 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */ |
378 | 7e7c5e4c | balrog | return to_bcd((s->rtc.alm.tm_hour % 12) + 1) | |
379 | 7e7c5e4c | balrog | (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */ |
380 | 7e7c5e4c | balrog | else
|
381 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_hour);
|
382 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_DAY:
|
383 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_mday);
|
384 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MON:
|
385 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_mon + 1); |
386 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_YR:
|
387 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_year - 2000); |
388 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_MSB:
|
389 | 7e7c5e4c | balrog | return (s->rtc.comp >> 8) & 0xff; |
390 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_LSB:
|
391 | 7e7c5e4c | balrog | return (s->rtc.comp >> 0) & 0xff; |
392 | 7e7c5e4c | balrog | |
393 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_EN:
|
394 | 7e7c5e4c | balrog | return s->pull[0]; |
395 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_DIR:
|
396 | 7e7c5e4c | balrog | return s->pull[1]; |
397 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_EN:
|
398 | 7e7c5e4c | balrog | return s->pull[2]; |
399 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_DIR:
|
400 | 7e7c5e4c | balrog | return s->pull[3]; |
401 | 7e7c5e4c | balrog | |
402 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL3: reg ++;
|
403 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL2: reg ++;
|
404 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL1:
|
405 | 7e7c5e4c | balrog | return s->mmc_ctrl[reg];
|
406 | 7e7c5e4c | balrog | case MENELAUS_MCT_PIN_ST:
|
407 | 7e7c5e4c | balrog | /* TODO: return the real Card Detect */
|
408 | 7e7c5e4c | balrog | return 0; |
409 | 7e7c5e4c | balrog | case MENELAUS_DEBOUNCE1:
|
410 | 7e7c5e4c | balrog | return s->mmc_debounce;
|
411 | 7e7c5e4c | balrog | |
412 | 7e7c5e4c | balrog | default:
|
413 | 7e7c5e4c | balrog | #ifdef VERBOSE
|
414 | 7e7c5e4c | balrog | printf("%s: unknown register %02x\n", __FUNCTION__, addr);
|
415 | 7e7c5e4c | balrog | #endif
|
416 | 7e7c5e4c | balrog | break;
|
417 | 7e7c5e4c | balrog | } |
418 | 7e7c5e4c | balrog | return 0; |
419 | 7e7c5e4c | balrog | } |
420 | 7e7c5e4c | balrog | |
421 | 7e7c5e4c | balrog | static void menelaus_write(void *opaque, uint8_t addr, uint8_t value) |
422 | 7e7c5e4c | balrog | { |
423 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
424 | 7e7c5e4c | balrog | int line;
|
425 | 7e7c5e4c | balrog | int reg = 0; |
426 | 7e7c5e4c | balrog | struct tm tm;
|
427 | 7e7c5e4c | balrog | |
428 | 7e7c5e4c | balrog | switch (addr) {
|
429 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL1:
|
430 | 7e7c5e4c | balrog | s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12); |
431 | 7e7c5e4c | balrog | break;
|
432 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL2:
|
433 | 7e7c5e4c | balrog | s->vcore[1] = value;
|
434 | 7e7c5e4c | balrog | break;
|
435 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL3:
|
436 | 7e7c5e4c | balrog | s->vcore[2] = MIN(value & 0x1f, 0x12); |
437 | 7e7c5e4c | balrog | break;
|
438 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL4:
|
439 | 7e7c5e4c | balrog | s->vcore[3] = MIN(value & 0x1f, 0x12); |
440 | 7e7c5e4c | balrog | break;
|
441 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL5:
|
442 | 7e7c5e4c | balrog | s->vcore[4] = value & 3; |
443 | 7e7c5e4c | balrog | /* XXX
|
444 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
445 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
446 | 7e7c5e4c | balrog | */
|
447 | 7e7c5e4c | balrog | break;
|
448 | 7e7c5e4c | balrog | |
449 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL1:
|
450 | 7e7c5e4c | balrog | s->dcdc[0] = value & 0x3f; |
451 | 7e7c5e4c | balrog | break;
|
452 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL2:
|
453 | 7e7c5e4c | balrog | s->dcdc[1] = value & 0x07; |
454 | 7e7c5e4c | balrog | /* XXX
|
455 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
456 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
457 | 7e7c5e4c | balrog | */
|
458 | 7e7c5e4c | balrog | break;
|
459 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL3:
|
460 | 7e7c5e4c | balrog | s->dcdc[2] = value & 0x07; |
461 | 7e7c5e4c | balrog | break;
|
462 | 7e7c5e4c | balrog | |
463 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL1:
|
464 | 7e7c5e4c | balrog | s->ldo[0] = value;
|
465 | 7e7c5e4c | balrog | break;
|
466 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL2:
|
467 | 7e7c5e4c | balrog | s->ldo[1] = value & 0x7f; |
468 | 7e7c5e4c | balrog | /* XXX
|
469 | 7e7c5e4c | balrog | * auto set to 0x7e on M_WaitOn, M_Backup
|
470 | 7e7c5e4c | balrog | */
|
471 | 7e7c5e4c | balrog | break;
|
472 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL3:
|
473 | 7e7c5e4c | balrog | s->ldo[2] = value & 3; |
474 | 7e7c5e4c | balrog | /* XXX
|
475 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
476 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
477 | 7e7c5e4c | balrog | */
|
478 | 7e7c5e4c | balrog | break;
|
479 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL4:
|
480 | 7e7c5e4c | balrog | s->ldo[3] = value & 3; |
481 | 7e7c5e4c | balrog | /* XXX
|
482 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
483 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
484 | 7e7c5e4c | balrog | */
|
485 | 7e7c5e4c | balrog | break;
|
486 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL5:
|
487 | 7e7c5e4c | balrog | s->ldo[4] = value & 3; |
488 | 7e7c5e4c | balrog | /* XXX
|
489 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
490 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
491 | 7e7c5e4c | balrog | */
|
492 | 7e7c5e4c | balrog | break;
|
493 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL6:
|
494 | 7e7c5e4c | balrog | s->ldo[5] = value & 3; |
495 | 7e7c5e4c | balrog | break;
|
496 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL7:
|
497 | 7e7c5e4c | balrog | s->ldo[6] = value & 3; |
498 | 7e7c5e4c | balrog | break;
|
499 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL8:
|
500 | 7e7c5e4c | balrog | s->ldo[7] = value & 3; |
501 | 7e7c5e4c | balrog | break;
|
502 | 7e7c5e4c | balrog | |
503 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL2: reg ++;
|
504 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL1:
|
505 | 7e7c5e4c | balrog | s->sleep[reg] = value; |
506 | 7e7c5e4c | balrog | break;
|
507 | 7e7c5e4c | balrog | |
508 | 7e7c5e4c | balrog | case MENELAUS_DEVICE_OFF:
|
509 | 7e7c5e4c | balrog | if (value & 1) |
510 | 7e7c5e4c | balrog | menelaus_reset(&s->i2c); |
511 | 7e7c5e4c | balrog | break;
|
512 | 7e7c5e4c | balrog | |
513 | 7e7c5e4c | balrog | case MENELAUS_OSC_CTRL:
|
514 | 7e7c5e4c | balrog | s->osc = value & 7;
|
515 | 7e7c5e4c | balrog | break;
|
516 | 7e7c5e4c | balrog | |
517 | 7e7c5e4c | balrog | case MENELAUS_DETECT_CTRL:
|
518 | 7e7c5e4c | balrog | s->detect = value & 0x7f;
|
519 | 7e7c5e4c | balrog | break;
|
520 | 7e7c5e4c | balrog | |
521 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK1:
|
522 | 7e7c5e4c | balrog | s->mask &= 0xf00;
|
523 | 7e7c5e4c | balrog | s->mask |= value << 0;
|
524 | 7e7c5e4c | balrog | menelaus_update(s); |
525 | 7e7c5e4c | balrog | break;
|
526 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK2:
|
527 | 7e7c5e4c | balrog | s->mask &= 0x0ff;
|
528 | 7e7c5e4c | balrog | s->mask |= value << 8;
|
529 | 7e7c5e4c | balrog | menelaus_update(s); |
530 | 7e7c5e4c | balrog | break;
|
531 | 7e7c5e4c | balrog | |
532 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK1:
|
533 | 7e7c5e4c | balrog | s->status &= ~(((uint16_t) value) << 0);
|
534 | 7e7c5e4c | balrog | menelaus_update(s); |
535 | 7e7c5e4c | balrog | break;
|
536 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK2:
|
537 | 7e7c5e4c | balrog | s->status &= ~(((uint16_t) value) << 8);
|
538 | 7e7c5e4c | balrog | menelaus_update(s); |
539 | 7e7c5e4c | balrog | break;
|
540 | 7e7c5e4c | balrog | |
541 | 7e7c5e4c | balrog | case MENELAUS_GPIO_CTRL:
|
542 | d3356811 | Paul Brook | for (line = 0; line < 3; line ++) { |
543 | d3356811 | Paul Brook | if (((s->dir ^ value) >> line) & 1) { |
544 | d3356811 | Paul Brook | qemu_set_irq(s->out[line], |
545 | d3356811 | Paul Brook | ((s->outputs & ~s->dir) >> line) & 1);
|
546 | d3356811 | Paul Brook | } |
547 | d3356811 | Paul Brook | } |
548 | 7e7c5e4c | balrog | s->dir = value & 0x67;
|
549 | 7e7c5e4c | balrog | break;
|
550 | 7e7c5e4c | balrog | case MENELAUS_GPIO_OUT:
|
551 | d3356811 | Paul Brook | for (line = 0; line < 3; line ++) { |
552 | d3356811 | Paul Brook | if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) { |
553 | d3356811 | Paul Brook | qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
|
554 | d3356811 | Paul Brook | } |
555 | d3356811 | Paul Brook | } |
556 | 7e7c5e4c | balrog | s->outputs = value & 0x07;
|
557 | 7e7c5e4c | balrog | break;
|
558 | 7e7c5e4c | balrog | |
559 | 7e7c5e4c | balrog | case MENELAUS_BBSMS:
|
560 | 7e7c5e4c | balrog | s->bbsms = 0x0d;
|
561 | 7e7c5e4c | balrog | break;
|
562 | 7e7c5e4c | balrog | |
563 | 7e7c5e4c | balrog | case MENELAUS_RTC_CTRL:
|
564 | 7e7c5e4c | balrog | if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */ |
565 | 7e7c5e4c | balrog | if (value & 1) |
566 | 7e7c5e4c | balrog | menelaus_rtc_start(s); |
567 | 7e7c5e4c | balrog | else
|
568 | 7e7c5e4c | balrog | menelaus_rtc_stop(s); |
569 | 7e7c5e4c | balrog | } |
570 | 7e7c5e4c | balrog | s->rtc.ctrl = value & 0x1f;
|
571 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
572 | 7e7c5e4c | balrog | break;
|
573 | 7e7c5e4c | balrog | case MENELAUS_RTC_UPDATE:
|
574 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
575 | 7e7c5e4c | balrog | memcpy(&tm, &s->rtc.tm, sizeof(tm));
|
576 | 7e7c5e4c | balrog | switch (value & 0xf) { |
577 | 7e7c5e4c | balrog | case 0: |
578 | 7e7c5e4c | balrog | break;
|
579 | 7e7c5e4c | balrog | case 1: |
580 | 7e7c5e4c | balrog | tm.tm_sec = s->rtc.new.tm_sec; |
581 | 7e7c5e4c | balrog | break;
|
582 | 7e7c5e4c | balrog | case 2: |
583 | 7e7c5e4c | balrog | tm.tm_min = s->rtc.new.tm_min; |
584 | 7e7c5e4c | balrog | break;
|
585 | 7e7c5e4c | balrog | case 3: |
586 | 7e7c5e4c | balrog | if (s->rtc.new.tm_hour > 23) |
587 | 7e7c5e4c | balrog | goto rtc_badness;
|
588 | 7e7c5e4c | balrog | tm.tm_hour = s->rtc.new.tm_hour; |
589 | 7e7c5e4c | balrog | break;
|
590 | 7e7c5e4c | balrog | case 4: |
591 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mday < 1) |
592 | 7e7c5e4c | balrog | goto rtc_badness;
|
593 | 7e7c5e4c | balrog | /* TODO check range */
|
594 | 7e7c5e4c | balrog | tm.tm_mday = s->rtc.new.tm_mday; |
595 | 7e7c5e4c | balrog | break;
|
596 | 7e7c5e4c | balrog | case 5: |
597 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11) |
598 | 7e7c5e4c | balrog | goto rtc_badness;
|
599 | 7e7c5e4c | balrog | tm.tm_mon = s->rtc.new.tm_mon; |
600 | 7e7c5e4c | balrog | break;
|
601 | 7e7c5e4c | balrog | case 6: |
602 | 7e7c5e4c | balrog | tm.tm_year = s->rtc.new.tm_year; |
603 | 7e7c5e4c | balrog | break;
|
604 | 7e7c5e4c | balrog | case 7: |
605 | 7e7c5e4c | balrog | /* TODO set .tm_mday instead */
|
606 | 7e7c5e4c | balrog | tm.tm_wday = s->rtc.new.tm_wday; |
607 | 7e7c5e4c | balrog | break;
|
608 | 7e7c5e4c | balrog | case 8: |
609 | 7e7c5e4c | balrog | if (s->rtc.new.tm_hour > 23) |
610 | 7e7c5e4c | balrog | goto rtc_badness;
|
611 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mday < 1) |
612 | 7e7c5e4c | balrog | goto rtc_badness;
|
613 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11) |
614 | 7e7c5e4c | balrog | goto rtc_badness;
|
615 | 7e7c5e4c | balrog | tm.tm_sec = s->rtc.new.tm_sec; |
616 | 7e7c5e4c | balrog | tm.tm_min = s->rtc.new.tm_min; |
617 | 7e7c5e4c | balrog | tm.tm_hour = s->rtc.new.tm_hour; |
618 | 7e7c5e4c | balrog | tm.tm_mday = s->rtc.new.tm_mday; |
619 | 7e7c5e4c | balrog | tm.tm_mon = s->rtc.new.tm_mon; |
620 | 7e7c5e4c | balrog | tm.tm_year = s->rtc.new.tm_year; |
621 | 7e7c5e4c | balrog | break;
|
622 | 7e7c5e4c | balrog | rtc_badness:
|
623 | 7e7c5e4c | balrog | default:
|
624 | 7e7c5e4c | balrog | fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
|
625 | 7e7c5e4c | balrog | __FUNCTION__, value); |
626 | 7e7c5e4c | balrog | s->status |= 1 << 10; /* RTCERR */ |
627 | 7e7c5e4c | balrog | menelaus_update(s); |
628 | 7e7c5e4c | balrog | } |
629 | aec454d2 | balrog | s->rtc.sec_offset = qemu_timedate_diff(&tm); |
630 | 7e7c5e4c | balrog | break;
|
631 | 7e7c5e4c | balrog | case MENELAUS_RTC_SEC:
|
632 | 7e7c5e4c | balrog | s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
|
633 | 7e7c5e4c | balrog | break;
|
634 | 7e7c5e4c | balrog | case MENELAUS_RTC_MIN:
|
635 | 7e7c5e4c | balrog | s->rtc.tm.tm_min = from_bcd(value & 0x7f);
|
636 | 7e7c5e4c | balrog | break;
|
637 | 7e7c5e4c | balrog | case MENELAUS_RTC_HR:
|
638 | 7e7c5e4c | balrog | s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */ |
639 | 7e7c5e4c | balrog | MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) : |
640 | 7e7c5e4c | balrog | from_bcd(value & 0x3f);
|
641 | 7e7c5e4c | balrog | break;
|
642 | 7e7c5e4c | balrog | case MENELAUS_RTC_DAY:
|
643 | 7e7c5e4c | balrog | s->rtc.tm.tm_mday = from_bcd(value); |
644 | 7e7c5e4c | balrog | break;
|
645 | 7e7c5e4c | balrog | case MENELAUS_RTC_MON:
|
646 | 7e7c5e4c | balrog | s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1; |
647 | 7e7c5e4c | balrog | break;
|
648 | 7e7c5e4c | balrog | case MENELAUS_RTC_YR:
|
649 | 7e7c5e4c | balrog | s->rtc.tm.tm_year = 2000 + from_bcd(value);
|
650 | 7e7c5e4c | balrog | break;
|
651 | 7e7c5e4c | balrog | case MENELAUS_RTC_WKDAY:
|
652 | 7e7c5e4c | balrog | s->rtc.tm.tm_mday = from_bcd(value); |
653 | 7e7c5e4c | balrog | break;
|
654 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_SEC:
|
655 | 7e7c5e4c | balrog | s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
|
656 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
657 | 7e7c5e4c | balrog | break;
|
658 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MIN:
|
659 | 7e7c5e4c | balrog | s->rtc.alm.tm_min = from_bcd(value & 0x7f);
|
660 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
661 | 7e7c5e4c | balrog | break;
|
662 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_HR:
|
663 | 7e7c5e4c | balrog | s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */ |
664 | 7e7c5e4c | balrog | MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) : |
665 | 7e7c5e4c | balrog | from_bcd(value & 0x3f);
|
666 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
667 | 7e7c5e4c | balrog | break;
|
668 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_DAY:
|
669 | 7e7c5e4c | balrog | s->rtc.alm.tm_mday = from_bcd(value); |
670 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
671 | 7e7c5e4c | balrog | break;
|
672 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MON:
|
673 | 7e7c5e4c | balrog | s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1; |
674 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
675 | 7e7c5e4c | balrog | break;
|
676 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_YR:
|
677 | 7e7c5e4c | balrog | s->rtc.alm.tm_year = 2000 + from_bcd(value);
|
678 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
679 | 7e7c5e4c | balrog | break;
|
680 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_MSB:
|
681 | 7e7c5e4c | balrog | s->rtc.comp &= 0xff;
|
682 | 7e7c5e4c | balrog | s->rtc.comp |= value << 8;
|
683 | 7e7c5e4c | balrog | break;
|
684 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_LSB:
|
685 | 7e7c5e4c | balrog | s->rtc.comp &= 0xff << 8; |
686 | 7e7c5e4c | balrog | s->rtc.comp |= value; |
687 | 7e7c5e4c | balrog | break;
|
688 | 7e7c5e4c | balrog | |
689 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_EN:
|
690 | 7e7c5e4c | balrog | s->pull[0] = value;
|
691 | 7e7c5e4c | balrog | break;
|
692 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_DIR:
|
693 | 7e7c5e4c | balrog | s->pull[1] = value & 0x1f; |
694 | 7e7c5e4c | balrog | break;
|
695 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_EN:
|
696 | 7e7c5e4c | balrog | s->pull[2] = value;
|
697 | 7e7c5e4c | balrog | break;
|
698 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_DIR:
|
699 | 7e7c5e4c | balrog | s->pull[3] = value & 0x1f; |
700 | 7e7c5e4c | balrog | break;
|
701 | 7e7c5e4c | balrog | |
702 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL1:
|
703 | 7e7c5e4c | balrog | s->mmc_ctrl[0] = value & 0x7f; |
704 | 7e7c5e4c | balrog | break;
|
705 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL2:
|
706 | 7e7c5e4c | balrog | s->mmc_ctrl[1] = value;
|
707 | 7e7c5e4c | balrog | /* TODO update Card Detect interrupts */
|
708 | 7e7c5e4c | balrog | break;
|
709 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL3:
|
710 | 7e7c5e4c | balrog | s->mmc_ctrl[2] = value & 0xf; |
711 | 7e7c5e4c | balrog | break;
|
712 | 7e7c5e4c | balrog | case MENELAUS_DEBOUNCE1:
|
713 | 7e7c5e4c | balrog | s->mmc_debounce = value & 0x3f;
|
714 | 7e7c5e4c | balrog | break;
|
715 | 7e7c5e4c | balrog | |
716 | 7e7c5e4c | balrog | default:
|
717 | 7e7c5e4c | balrog | #ifdef VERBOSE
|
718 | 7e7c5e4c | balrog | printf("%s: unknown register %02x\n", __FUNCTION__, addr);
|
719 | 7e7c5e4c | balrog | #endif
|
720 | 7e7c5e4c | balrog | } |
721 | 7e7c5e4c | balrog | } |
722 | 7e7c5e4c | balrog | |
723 | 7e7c5e4c | balrog | static void menelaus_event(i2c_slave *i2c, enum i2c_event event) |
724 | 7e7c5e4c | balrog | { |
725 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) i2c; |
726 | 7e7c5e4c | balrog | |
727 | 7e7c5e4c | balrog | if (event == I2C_START_SEND)
|
728 | 7e7c5e4c | balrog | s->firstbyte = 1;
|
729 | 7e7c5e4c | balrog | } |
730 | 7e7c5e4c | balrog | |
731 | 7e7c5e4c | balrog | static int menelaus_tx(i2c_slave *i2c, uint8_t data) |
732 | 7e7c5e4c | balrog | { |
733 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) i2c; |
734 | 7e7c5e4c | balrog | /* Interpret register address byte */
|
735 | 7e7c5e4c | balrog | if (s->firstbyte) {
|
736 | 7e7c5e4c | balrog | s->reg = data; |
737 | 7e7c5e4c | balrog | s->firstbyte = 0;
|
738 | 7e7c5e4c | balrog | } else
|
739 | 7e7c5e4c | balrog | menelaus_write(s, s->reg ++, data); |
740 | 7e7c5e4c | balrog | |
741 | 7e7c5e4c | balrog | return 0; |
742 | 7e7c5e4c | balrog | } |
743 | 7e7c5e4c | balrog | |
744 | 7e7c5e4c | balrog | static int menelaus_rx(i2c_slave *i2c) |
745 | 7e7c5e4c | balrog | { |
746 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) i2c; |
747 | 7e7c5e4c | balrog | |
748 | 7e7c5e4c | balrog | return menelaus_read(s, s->reg ++);
|
749 | 7e7c5e4c | balrog | } |
750 | 7e7c5e4c | balrog | |
751 | 7e7c5e4c | balrog | static void tm_put(QEMUFile *f, struct tm *tm) { |
752 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_sec); |
753 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_min); |
754 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_hour); |
755 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_mday); |
756 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_min); |
757 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_year); |
758 | 7e7c5e4c | balrog | } |
759 | 7e7c5e4c | balrog | |
760 | 7e7c5e4c | balrog | static void tm_get(QEMUFile *f, struct tm *tm) { |
761 | 7e7c5e4c | balrog | tm->tm_sec = qemu_get_be16(f); |
762 | 7e7c5e4c | balrog | tm->tm_min = qemu_get_be16(f); |
763 | 7e7c5e4c | balrog | tm->tm_hour = qemu_get_be16(f); |
764 | 7e7c5e4c | balrog | tm->tm_mday = qemu_get_be16(f); |
765 | 7e7c5e4c | balrog | tm->tm_min = qemu_get_be16(f); |
766 | 7e7c5e4c | balrog | tm->tm_year = qemu_get_be16(f); |
767 | 7e7c5e4c | balrog | } |
768 | 7e7c5e4c | balrog | |
769 | 7e7c5e4c | balrog | static void menelaus_save(QEMUFile *f, void *opaque) |
770 | 7e7c5e4c | balrog | { |
771 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
772 | 7e7c5e4c | balrog | |
773 | 7e7c5e4c | balrog | qemu_put_be32(f, s->firstbyte); |
774 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->reg); |
775 | 7e7c5e4c | balrog | |
776 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[0]);
|
777 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[1]);
|
778 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[2]);
|
779 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[3]);
|
780 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[4]);
|
781 | 2ba2d706 | balrog | qemu_put_8s(f, &s->dcdc[0]);
|
782 | 2ba2d706 | balrog | qemu_put_8s(f, &s->dcdc[1]);
|
783 | 2ba2d706 | balrog | qemu_put_8s(f, &s->dcdc[2]);
|
784 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[0]);
|
785 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[1]);
|
786 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[2]);
|
787 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[3]);
|
788 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[4]);
|
789 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[5]);
|
790 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[6]);
|
791 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[7]);
|
792 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->sleep[0]);
|
793 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->sleep[1]);
|
794 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->osc); |
795 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->detect); |
796 | 7e7c5e4c | balrog | qemu_put_be16s(f, &s->mask); |
797 | 7e7c5e4c | balrog | qemu_put_be16s(f, &s->status); |
798 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->dir); |
799 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->inputs); |
800 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->outputs); |
801 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->bbsms); |
802 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[0]);
|
803 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[1]);
|
804 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[2]);
|
805 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[3]);
|
806 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_ctrl[0]);
|
807 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_ctrl[1]);
|
808 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_ctrl[2]);
|
809 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_debounce); |
810 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->rtc.ctrl); |
811 | 7e7c5e4c | balrog | qemu_put_be16s(f, &s->rtc.comp); |
812 | 7e7c5e4c | balrog | /* Should be <= 1000 */
|
813 | 7e7c5e4c | balrog | qemu_put_be16(f, s->rtc.next - qemu_get_clock(rt_clock)); |
814 | 7e7c5e4c | balrog | tm_put(f, &s->rtc.new); |
815 | 7e7c5e4c | balrog | tm_put(f, &s->rtc.alm); |
816 | 7e7c5e4c | balrog | qemu_put_byte(f, s->pwrbtn_state); |
817 | 7e7c5e4c | balrog | |
818 | 7e7c5e4c | balrog | i2c_slave_save(f, &s->i2c); |
819 | 7e7c5e4c | balrog | } |
820 | 7e7c5e4c | balrog | |
821 | 7e7c5e4c | balrog | static int menelaus_load(QEMUFile *f, void *opaque, int version_id) |
822 | 7e7c5e4c | balrog | { |
823 | bc24a225 | Paul Brook | MenelausState *s = (MenelausState *) opaque; |
824 | 7e7c5e4c | balrog | |
825 | 7e7c5e4c | balrog | s->firstbyte = qemu_get_be32(f); |
826 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->reg); |
827 | 7e7c5e4c | balrog | |
828 | 7e7c5e4c | balrog | if (s->rtc.ctrl & 1) /* RTC_EN */ |
829 | 7e7c5e4c | balrog | menelaus_rtc_stop(s); |
830 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[0]);
|
831 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[1]);
|
832 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[2]);
|
833 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[3]);
|
834 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[4]);
|
835 | 2ba2d706 | balrog | qemu_get_8s(f, &s->dcdc[0]);
|
836 | 2ba2d706 | balrog | qemu_get_8s(f, &s->dcdc[1]);
|
837 | 2ba2d706 | balrog | qemu_get_8s(f, &s->dcdc[2]);
|
838 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[0]);
|
839 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[1]);
|
840 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[2]);
|
841 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[3]);
|
842 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[4]);
|
843 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[5]);
|
844 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[6]);
|
845 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[7]);
|
846 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->sleep[0]);
|
847 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->sleep[1]);
|
848 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->osc); |
849 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->detect); |
850 | 7e7c5e4c | balrog | qemu_get_be16s(f, &s->mask); |
851 | 7e7c5e4c | balrog | qemu_get_be16s(f, &s->status); |
852 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->dir); |
853 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->inputs); |
854 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->outputs); |
855 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->bbsms); |
856 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[0]);
|
857 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[1]);
|
858 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[2]);
|
859 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[3]);
|
860 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_ctrl[0]);
|
861 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_ctrl[1]);
|
862 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_ctrl[2]);
|
863 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_debounce); |
864 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->rtc.ctrl); |
865 | 7e7c5e4c | balrog | qemu_get_be16s(f, &s->rtc.comp); |
866 | 7e7c5e4c | balrog | s->rtc.next = qemu_get_be16(f); |
867 | 7e7c5e4c | balrog | tm_get(f, &s->rtc.new); |
868 | 7e7c5e4c | balrog | tm_get(f, &s->rtc.alm); |
869 | 7e7c5e4c | balrog | s->pwrbtn_state = qemu_get_byte(f); |
870 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
871 | 7e7c5e4c | balrog | menelaus_update(s); |
872 | 7e7c5e4c | balrog | if (s->rtc.ctrl & 1) /* RTC_EN */ |
873 | 7e7c5e4c | balrog | menelaus_rtc_start(s); |
874 | 7e7c5e4c | balrog | |
875 | 7e7c5e4c | balrog | i2c_slave_load(f, &s->i2c); |
876 | 7e7c5e4c | balrog | return 0; |
877 | 7e7c5e4c | balrog | } |
878 | 7e7c5e4c | balrog | |
879 | d3356811 | Paul Brook | static void twl92230_init(i2c_slave *i2c) |
880 | 7e7c5e4c | balrog | { |
881 | d3356811 | Paul Brook | MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c); |
882 | 7e7c5e4c | balrog | |
883 | b0f74c87 | balrog | s->rtc.hz_tm = qemu_new_timer(rt_clock, menelaus_rtc_hz, s); |
884 | d3356811 | Paul Brook | /* Three output pins plus one interrupt pin. */
|
885 | d3356811 | Paul Brook | qdev_init_gpio_out(&i2c->qdev, s->out, 4);
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886 | d3356811 | Paul Brook | qdev_init_gpio_in(&i2c->qdev, menelaus_gpio_set, 3);
|
887 | 7e7c5e4c | balrog | s->pwrbtn = qemu_allocate_irqs(menelaus_pwrbtn_set, s, 1)[0]; |
888 | 7e7c5e4c | balrog | |
889 | 7e7c5e4c | balrog | menelaus_reset(&s->i2c); |
890 | 7e7c5e4c | balrog | |
891 | 18be5187 | pbrook | register_savevm("menelaus", -1, 0, menelaus_save, menelaus_load, s); |
892 | 7e7c5e4c | balrog | } |
893 | 7e7c5e4c | balrog | |
894 | d3356811 | Paul Brook | static I2CSlaveInfo twl92230_info = {
|
895 | d3356811 | Paul Brook | .init = twl92230_init, |
896 | d3356811 | Paul Brook | .event = menelaus_event, |
897 | d3356811 | Paul Brook | .recv = menelaus_rx, |
898 | d3356811 | Paul Brook | .send = menelaus_tx |
899 | d3356811 | Paul Brook | }; |
900 | 7e7c5e4c | balrog | |
901 | d3356811 | Paul Brook | static void twl92230_register_devices(void) |
902 | 7e7c5e4c | balrog | { |
903 | d3356811 | Paul Brook | i2c_register_slave("twl92230", sizeof(MenelausState), &twl92230_info); |
904 | 7e7c5e4c | balrog | } |
905 | d3356811 | Paul Brook | |
906 | d3356811 | Paul Brook | device_init(twl92230_register_devices) |