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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <sys/time.h>
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#include "hw.h"
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#include "sysbus.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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#include "etraxfs.h"
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#define D(x)
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... | ... | |
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#define R_INTR 0x50
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#define R_MASKED_INTR 0x54
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43 |
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struct fs_timer_t {
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CPUState *env;
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qemu_irq *irq;
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qemu_irq *nmi;
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struct etrax_timer {
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SysBusDevice busdev;
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qemu_irq irq;
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qemu_irq nmi;
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QEMUBH *bh_t0;
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QEMUBH *bh_t1;
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... | ... | |
78 |
75 |
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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80 |
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{
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struct fs_timer_t *t = opaque;
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struct etrax_timer *t = opaque;
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uint32_t r = 0;
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80 |
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switch (addr) {
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... | ... | |
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}
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#define TIMER_SLOWDOWN 1
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108 |
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static void update_ctrl(struct fs_timer_t *t, int tnum)
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static void update_ctrl(struct etrax_timer *t, int tnum)
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109 |
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{
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110 |
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unsigned int op;
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111 |
108 |
unsigned int freq;
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... | ... | |
172 |
169 |
}
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}
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174 |
171 |
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175 |
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static void timer_update_irq(struct fs_timer_t *t)
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static void timer_update_irq(struct etrax_timer *t)
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{
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t->r_intr &= ~(t->rw_ack_intr);
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178 |
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t->r_masked_intr = t->r_intr & t->rw_intr_mask;
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179 |
176 |
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D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
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qemu_set_irq(t->irq[0], !!t->r_masked_intr);
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qemu_set_irq(t->irq, !!t->r_masked_intr);
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182 |
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}
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183 |
180 |
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184 |
181 |
static void timer0_hit(void *opaque)
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185 |
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{
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186 |
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struct fs_timer_t *t = opaque;
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struct etrax_timer *t = opaque;
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187 |
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t->r_intr |= 1;
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188 |
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timer_update_irq(t);
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189 |
186 |
}
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190 |
187 |
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static void timer1_hit(void *opaque)
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192 |
189 |
{
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193 |
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struct fs_timer_t *t = opaque;
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struct etrax_timer *t = opaque;
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t->r_intr |= 2;
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195 |
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timer_update_irq(t);
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196 |
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}
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static void watchdog_hit(void *opaque)
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{
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200 |
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struct fs_timer_t *t = opaque;
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struct etrax_timer *t = opaque;
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201 |
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if (t->wd_hits == 0) {
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202 |
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/* real hw gives a single tick before reseting but we are
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203 |
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a bit friendlier to compensate for our slower execution. */
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204 |
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ptimer_set_count(t->ptimer_wd, 10);
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205 |
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ptimer_run(t->ptimer_wd, 1);
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qemu_irq_raise(t->nmi[0]);
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qemu_irq_raise(t->nmi);
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}
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else
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209 |
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qemu_system_reset_request();
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... | ... | |
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t->wd_hits++;
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}
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210 |
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214 |
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static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
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211 |
static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
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215 |
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{
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216 |
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unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
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217 |
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unsigned int wd_key = t->rw_wd_ctrl >> 9;
|
... | ... | |
230 |
227 |
wd_en, new_key, wd_key, new_cmd, wd_cnt));
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231 |
228 |
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232 |
229 |
if (t->wd_hits)
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233 |
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qemu_irq_lower(t->nmi[0]);
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qemu_irq_lower(t->nmi);
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234 |
231 |
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235 |
232 |
t->wd_hits = 0;
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236 |
233 |
|
... | ... | |
249 |
246 |
static void
|
250 |
247 |
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
251 |
248 |
{
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252 |
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struct fs_timer_t *t = opaque;
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249 |
struct etrax_timer *t = opaque;
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253 |
250 |
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254 |
251 |
switch (addr)
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255 |
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{
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... | ... | |
301 |
298 |
|
302 |
299 |
static void etraxfs_timer_reset(void *opaque)
|
303 |
300 |
{
|
304 |
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struct fs_timer_t *t = opaque;
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301 |
struct etrax_timer *t = opaque;
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305 |
302 |
|
306 |
303 |
ptimer_stop(t->ptimer_t0);
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307 |
304 |
ptimer_stop(t->ptimer_t1);
|
... | ... | |
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306 |
t->rw_wd_ctrl = 0;
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310 |
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t->r_intr = 0;
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311 |
308 |
t->rw_intr_mask = 0;
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312 |
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qemu_irq_lower(t->irq[0]);
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qemu_irq_lower(t->irq);
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310 |
}
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314 |
311 |
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315 |
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
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316 |
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target_phys_addr_t base)
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312 |
static void etraxfs_timer_init(SysBusDevice *dev)
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317 |
313 |
{
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318 |
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static struct fs_timer_t *t;
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|
314 |
struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
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319 |
315 |
int timer_regs;
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320 |
316 |
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321 |
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t = qemu_mallocz(sizeof *t);
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322 |
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323 |
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t->bh_t0 = qemu_bh_new(timer0_hit, t);
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324 |
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t->bh_t1 = qemu_bh_new(timer1_hit, t);
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325 |
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t->bh_wd = qemu_bh_new(watchdog_hit, t);
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326 |
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t->ptimer_t0 = ptimer_init(t->bh_t0);
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327 |
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t->ptimer_t1 = ptimer_init(t->bh_t1);
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t->ptimer_wd = ptimer_init(t->bh_wd);
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329 |
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t->irq = irqs;
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330 |
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t->nmi = nmi;
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331 |
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t->env = env;
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323 |
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324 |
sysbus_init_irq(dev, &t->irq);
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325 |
sysbus_init_irq(dev, &t->nmi);
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332 |
326 |
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333 |
327 |
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
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334 |
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cpu_register_physical_memory (base, 0x5c, timer_regs);
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|
328 |
sysbus_init_mmio(dev, 0x5c, timer_regs);
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335 |
329 |
|
336 |
330 |
qemu_register_reset(etraxfs_timer_reset, t);
|
337 |
331 |
}
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|
332 |
|
|
333 |
static void etraxfs_timer_register(void)
|
|
334 |
{
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|
335 |
sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
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|
336 |
etraxfs_timer_init);
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|
337 |
}
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|
338 |
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|
339 |
device_init(etraxfs_timer_register)
|