Revision 3b1fd90e hw/etraxfs_timer.c

b/hw/etraxfs_timer.c
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include <stdio.h>
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#include <sys/time.h>
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#include "hw.h"
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#include "sysbus.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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#include "etraxfs.h"
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#define D(x)
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......
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#define R_INTR        0x50
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#define R_MASKED_INTR 0x54
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struct fs_timer_t {
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    CPUState *env;
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    qemu_irq *irq;
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    qemu_irq *nmi;
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struct etrax_timer {
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    SysBusDevice busdev;
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    qemu_irq irq;
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    qemu_irq nmi;
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    QEMUBH *bh_t0;
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    QEMUBH *bh_t1;
......
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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{
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    struct fs_timer_t *t = opaque;
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    struct etrax_timer *t = opaque;
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    uint32_t r = 0;
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    switch (addr) {
......
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}
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#define TIMER_SLOWDOWN 1
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static void update_ctrl(struct fs_timer_t *t, int tnum)
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static void update_ctrl(struct etrax_timer *t, int tnum)
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{
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    unsigned int op;
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    unsigned int freq;
......
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    }
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}
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static void timer_update_irq(struct fs_timer_t *t)
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static void timer_update_irq(struct etrax_timer *t)
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{
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    t->r_intr &= ~(t->rw_ack_intr);
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    t->r_masked_intr = t->r_intr & t->rw_intr_mask;
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    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
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    qemu_set_irq(t->irq[0], !!t->r_masked_intr);
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    qemu_set_irq(t->irq, !!t->r_masked_intr);
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}
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static void timer0_hit(void *opaque)
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{
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    struct fs_timer_t *t = opaque;
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    struct etrax_timer *t = opaque;
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    t->r_intr |= 1;
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    timer_update_irq(t);
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}
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static void timer1_hit(void *opaque)
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{
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    struct fs_timer_t *t = opaque;
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    struct etrax_timer *t = opaque;
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    t->r_intr |= 2;
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    timer_update_irq(t);
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}
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static void watchdog_hit(void *opaque)
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{
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    struct fs_timer_t *t = opaque;
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    struct etrax_timer *t = opaque;
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    if (t->wd_hits == 0) {
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        /* real hw gives a single tick before reseting but we are
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           a bit friendlier to compensate for our slower execution.  */
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        ptimer_set_count(t->ptimer_wd, 10);
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        ptimer_run(t->ptimer_wd, 1);
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        qemu_irq_raise(t->nmi[0]);
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        qemu_irq_raise(t->nmi);
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    }
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    else
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        qemu_system_reset_request();
......
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    t->wd_hits++;
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}
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static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
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static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
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{
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    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
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    unsigned int wd_key = t->rw_wd_ctrl >> 9;
......
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         wd_en, new_key, wd_key, new_cmd, wd_cnt));
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    if (t->wd_hits)
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        qemu_irq_lower(t->nmi[0]);
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        qemu_irq_lower(t->nmi);
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    t->wd_hits = 0;
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......
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static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    struct fs_timer_t *t = opaque;
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    struct etrax_timer *t = opaque;
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    switch (addr)
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    {
......
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static void etraxfs_timer_reset(void *opaque)
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{
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    struct fs_timer_t *t = opaque;
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    struct etrax_timer *t = opaque;
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    ptimer_stop(t->ptimer_t0);
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    ptimer_stop(t->ptimer_t1);
......
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    t->rw_wd_ctrl = 0;
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    t->r_intr = 0;
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    t->rw_intr_mask = 0;
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    qemu_irq_lower(t->irq[0]);
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    qemu_irq_lower(t->irq);
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}
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
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            target_phys_addr_t base)
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static void etraxfs_timer_init(SysBusDevice *dev)
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{
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    static struct fs_timer_t *t;
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    struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
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    int timer_regs;
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    t = qemu_mallocz(sizeof *t);
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    t->bh_t0 = qemu_bh_new(timer0_hit, t);
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    t->bh_t1 = qemu_bh_new(timer1_hit, t);
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    t->bh_wd = qemu_bh_new(watchdog_hit, t);
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    t->ptimer_t0 = ptimer_init(t->bh_t0);
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    t->ptimer_t1 = ptimer_init(t->bh_t1);
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    t->ptimer_wd = ptimer_init(t->bh_wd);
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    t->irq = irqs;
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    t->nmi = nmi;
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    t->env = env;
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    sysbus_init_irq(dev, &t->irq);
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    sysbus_init_irq(dev, &t->nmi);
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    timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
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    cpu_register_physical_memory (base, 0x5c, timer_regs);
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    sysbus_init_mmio(dev, 0x5c, timer_regs);
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    qemu_register_reset(etraxfs_timer_reset, t);
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}
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static void etraxfs_timer_register(void)
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{
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    sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
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                        etraxfs_timer_init);
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}
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device_init(etraxfs_timer_register)

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