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1 | 0d78f544 | ths | /*
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2 | 0d78f544 | ths | * Renesas SH7751R R2D-PLUS emulation
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3 | 0d78f544 | ths | *
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4 | 0d78f544 | ths | * Copyright (c) 2007 Magnus Damm
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5 | b319feb7 | aurel32 | * Copyright (c) 2008 Paul Mundt
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6 | 0d78f544 | ths | *
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7 | 0d78f544 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 0d78f544 | ths | * of this software and associated documentation files (the "Software"), to deal
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9 | 0d78f544 | ths | * in the Software without restriction, including without limitation the rights
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10 | 0d78f544 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 0d78f544 | ths | * copies of the Software, and to permit persons to whom the Software is
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12 | 0d78f544 | ths | * furnished to do so, subject to the following conditions:
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13 | 0d78f544 | ths | *
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14 | 0d78f544 | ths | * The above copyright notice and this permission notice shall be included in
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15 | 0d78f544 | ths | * all copies or substantial portions of the Software.
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16 | 0d78f544 | ths | *
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17 | 0d78f544 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 0d78f544 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 0d78f544 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 0d78f544 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 0d78f544 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 0d78f544 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 0d78f544 | ths | * THE SOFTWARE.
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24 | 0d78f544 | ths | */
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25 | 0d78f544 | ths | |
26 | cf154394 | Aurelien Jarno | #include "sysbus.h" |
27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "sh.h" |
29 | ffd39257 | blueswir1 | #include "devices.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "boards.h" |
32 | c2f01775 | balrog | #include "pci.h" |
33 | c2f01775 | balrog | #include "net.h" |
34 | c2f01775 | balrog | #include "sh7750_regs.h" |
35 | 3d2bf4a1 | Gerd Hoffmann | #include "ide.h" |
36 | ca20cf32 | Blue Swirl | #include "loader.h" |
37 | 9caa3ec1 | Aurelien Jarno | #include "usb.h" |
38 | 56839a19 | Aurelien Jarno | #include "flash.h" |
39 | 2446333c | Blue Swirl | #include "blockdev.h" |
40 | 56839a19 | Aurelien Jarno | |
41 | 56839a19 | Aurelien Jarno | #define FLASH_BASE 0x00000000 |
42 | 56839a19 | Aurelien Jarno | #define FLASH_SIZE 0x02000000 |
43 | 0d78f544 | ths | |
44 | 0d78f544 | ths | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
45 | 0d78f544 | ths | #define SDRAM_SIZE 0x04000000 |
46 | 0d78f544 | ths | |
47 | ffd39257 | blueswir1 | #define SM501_VRAM_SIZE 0x800000 |
48 | ffd39257 | blueswir1 | |
49 | 73f19035 | Aurelien Jarno | #define BOOT_PARAMS_OFFSET 0x0010000 |
50 | e8afa065 | aurel32 | /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
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51 | 73f19035 | Aurelien Jarno | #define LINUX_LOAD_OFFSET 0x0800000 |
52 | 73f19035 | Aurelien Jarno | #define INITRD_LOAD_OFFSET 0x1800000 |
53 | e8afa065 | aurel32 | |
54 | d47ede60 | balrog | #define PA_IRLMSK 0x00 |
55 | b319feb7 | aurel32 | #define PA_POWOFF 0x30 |
56 | b319feb7 | aurel32 | #define PA_VERREG 0x32 |
57 | b319feb7 | aurel32 | #define PA_OUTPORT 0x36 |
58 | b319feb7 | aurel32 | |
59 | b319feb7 | aurel32 | typedef struct { |
60 | b319feb7 | aurel32 | uint16_t bcr; |
61 | d47ede60 | balrog | uint16_t irlmsk; |
62 | b319feb7 | aurel32 | uint16_t irlmon; |
63 | b319feb7 | aurel32 | uint16_t cfctl; |
64 | b319feb7 | aurel32 | uint16_t cfpow; |
65 | b319feb7 | aurel32 | uint16_t dispctl; |
66 | b319feb7 | aurel32 | uint16_t sdmpow; |
67 | b319feb7 | aurel32 | uint16_t rtcce; |
68 | b319feb7 | aurel32 | uint16_t pcicd; |
69 | b319feb7 | aurel32 | uint16_t voyagerrts; |
70 | b319feb7 | aurel32 | uint16_t cfrst; |
71 | b319feb7 | aurel32 | uint16_t admrts; |
72 | b319feb7 | aurel32 | uint16_t extrst; |
73 | b319feb7 | aurel32 | uint16_t cfcdintclr; |
74 | b319feb7 | aurel32 | uint16_t keyctlclr; |
75 | b319feb7 | aurel32 | uint16_t pad0; |
76 | b319feb7 | aurel32 | uint16_t pad1; |
77 | b319feb7 | aurel32 | uint16_t verreg; |
78 | b319feb7 | aurel32 | uint16_t inport; |
79 | b319feb7 | aurel32 | uint16_t outport; |
80 | b319feb7 | aurel32 | uint16_t bverreg; |
81 | d47ede60 | balrog | |
82 | d47ede60 | balrog | /* output pin */
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83 | d47ede60 | balrog | qemu_irq irl; |
84 | c227f099 | Anthony Liguori | } r2d_fpga_t; |
85 | b319feb7 | aurel32 | |
86 | d47ede60 | balrog | enum r2d_fpga_irq {
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87 | d47ede60 | balrog | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
88 | d47ede60 | balrog | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
89 | d47ede60 | balrog | NR_IRQS |
90 | d47ede60 | balrog | }; |
91 | d47ede60 | balrog | |
92 | d47ede60 | balrog | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { |
93 | d47ede60 | balrog | [CF_IDE] = { 1, 1<<9 }, |
94 | d47ede60 | balrog | [CF_CD] = { 2, 1<<8 }, |
95 | d47ede60 | balrog | [PCI_INTA] = { 9, 1<<14 }, |
96 | d47ede60 | balrog | [PCI_INTB] = { 10, 1<<13 }, |
97 | d47ede60 | balrog | [PCI_INTC] = { 3, 1<<12 }, |
98 | d47ede60 | balrog | [PCI_INTD] = { 0, 1<<11 }, |
99 | d47ede60 | balrog | [SM501] = { 4, 1<<10 }, |
100 | d47ede60 | balrog | [KEY] = { 5, 1<<6 }, |
101 | d47ede60 | balrog | [RTC_A] = { 6, 1<<5 }, |
102 | d47ede60 | balrog | [RTC_T] = { 7, 1<<4 }, |
103 | d47ede60 | balrog | [SDCARD] = { 8, 1<<7 }, |
104 | d47ede60 | balrog | [EXT] = { 11, 1<<0 }, |
105 | d47ede60 | balrog | [TP] = { 12, 1<<15 }, |
106 | d47ede60 | balrog | }; |
107 | d47ede60 | balrog | |
108 | c227f099 | Anthony Liguori | static void update_irl(r2d_fpga_t *fpga) |
109 | d47ede60 | balrog | { |
110 | d47ede60 | balrog | int i, irl = 15; |
111 | d47ede60 | balrog | for (i = 0; i < NR_IRQS; i++) |
112 | d47ede60 | balrog | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
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113 | d47ede60 | balrog | if (irqtab[i].irl < irl)
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114 | d47ede60 | balrog | irl = irqtab[i].irl; |
115 | d47ede60 | balrog | qemu_set_irq(fpga->irl, irl ^ 15);
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116 | d47ede60 | balrog | } |
117 | d47ede60 | balrog | |
118 | d47ede60 | balrog | static void r2d_fpga_irq_set(void *opaque, int n, int level) |
119 | d47ede60 | balrog | { |
120 | c227f099 | Anthony Liguori | r2d_fpga_t *fpga = opaque; |
121 | d47ede60 | balrog | if (level)
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122 | d47ede60 | balrog | fpga->irlmon |= irqtab[n].msk; |
123 | d47ede60 | balrog | else
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124 | d47ede60 | balrog | fpga->irlmon &= ~irqtab[n].msk; |
125 | d47ede60 | balrog | update_irl(fpga); |
126 | d47ede60 | balrog | } |
127 | d47ede60 | balrog | |
128 | c227f099 | Anthony Liguori | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
129 | b319feb7 | aurel32 | { |
130 | c227f099 | Anthony Liguori | r2d_fpga_t *s = opaque; |
131 | b319feb7 | aurel32 | |
132 | b319feb7 | aurel32 | switch (addr) {
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133 | d47ede60 | balrog | case PA_IRLMSK:
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134 | d47ede60 | balrog | return s->irlmsk;
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135 | b319feb7 | aurel32 | case PA_OUTPORT:
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136 | b319feb7 | aurel32 | return s->outport;
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137 | b319feb7 | aurel32 | case PA_POWOFF:
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138 | 37cc0b44 | Aurelien Jarno | return 0x00; |
139 | b319feb7 | aurel32 | case PA_VERREG:
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140 | b319feb7 | aurel32 | return 0x10; |
141 | b319feb7 | aurel32 | } |
142 | b319feb7 | aurel32 | |
143 | b319feb7 | aurel32 | return 0; |
144 | b319feb7 | aurel32 | } |
145 | b319feb7 | aurel32 | |
146 | b319feb7 | aurel32 | static void |
147 | c227f099 | Anthony Liguori | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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148 | b319feb7 | aurel32 | { |
149 | c227f099 | Anthony Liguori | r2d_fpga_t *s = opaque; |
150 | b319feb7 | aurel32 | |
151 | b319feb7 | aurel32 | switch (addr) {
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152 | d47ede60 | balrog | case PA_IRLMSK:
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153 | d47ede60 | balrog | s->irlmsk = value; |
154 | d47ede60 | balrog | update_irl(s); |
155 | d47ede60 | balrog | break;
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156 | b319feb7 | aurel32 | case PA_OUTPORT:
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157 | b319feb7 | aurel32 | s->outport = value; |
158 | b319feb7 | aurel32 | break;
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159 | b319feb7 | aurel32 | case PA_POWOFF:
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160 | 37cc0b44 | Aurelien Jarno | if (value & 1) { |
161 | 37cc0b44 | Aurelien Jarno | qemu_system_shutdown_request(); |
162 | 37cc0b44 | Aurelien Jarno | } |
163 | 37cc0b44 | Aurelien Jarno | break;
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164 | b319feb7 | aurel32 | case PA_VERREG:
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165 | b319feb7 | aurel32 | /* Discard writes */
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166 | b319feb7 | aurel32 | break;
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167 | b319feb7 | aurel32 | } |
168 | b319feb7 | aurel32 | } |
169 | b319feb7 | aurel32 | |
170 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const r2d_fpga_readfn[] = { |
171 | b319feb7 | aurel32 | r2d_fpga_read, |
172 | b319feb7 | aurel32 | r2d_fpga_read, |
173 | b2463a64 | aurel32 | NULL,
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174 | b319feb7 | aurel32 | }; |
175 | b319feb7 | aurel32 | |
176 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = { |
177 | b319feb7 | aurel32 | r2d_fpga_write, |
178 | b319feb7 | aurel32 | r2d_fpga_write, |
179 | b2463a64 | aurel32 | NULL,
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180 | b319feb7 | aurel32 | }; |
181 | b319feb7 | aurel32 | |
182 | c227f099 | Anthony Liguori | static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
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183 | b319feb7 | aurel32 | { |
184 | b319feb7 | aurel32 | int iomemtype;
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185 | c227f099 | Anthony Liguori | r2d_fpga_t *s; |
186 | b319feb7 | aurel32 | |
187 | c227f099 | Anthony Liguori | s = qemu_mallocz(sizeof(r2d_fpga_t));
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188 | d47ede60 | balrog | |
189 | d47ede60 | balrog | s->irl = irl; |
190 | b319feb7 | aurel32 | |
191 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(r2d_fpga_readfn, |
192 | 2507c12a | Alexander Graf | r2d_fpga_writefn, s, |
193 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
194 | b319feb7 | aurel32 | cpu_register_physical_memory(base, 0x40, iomemtype);
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195 | d47ede60 | balrog | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
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196 | b319feb7 | aurel32 | } |
197 | b319feb7 | aurel32 | |
198 | 4f6493ff | Aurelien Jarno | typedef struct ResetData { |
199 | 4f6493ff | Aurelien Jarno | CPUState *env; |
200 | 4f6493ff | Aurelien Jarno | uint32_t vector; |
201 | 4f6493ff | Aurelien Jarno | } ResetData; |
202 | 4f6493ff | Aurelien Jarno | |
203 | 4f6493ff | Aurelien Jarno | static void main_cpu_reset(void *opaque) |
204 | 4f6493ff | Aurelien Jarno | { |
205 | 4f6493ff | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
206 | 4f6493ff | Aurelien Jarno | CPUState *env = s->env; |
207 | 4f6493ff | Aurelien Jarno | |
208 | 4f6493ff | Aurelien Jarno | cpu_reset(env); |
209 | 4f6493ff | Aurelien Jarno | env->pc = s->vector; |
210 | 4f6493ff | Aurelien Jarno | } |
211 | 4f6493ff | Aurelien Jarno | |
212 | 73f19035 | Aurelien Jarno | static struct __attribute__((__packed__)) |
213 | 73f19035 | Aurelien Jarno | { |
214 | 73f19035 | Aurelien Jarno | int mount_root_rdonly;
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215 | 73f19035 | Aurelien Jarno | int ramdisk_flags;
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216 | 73f19035 | Aurelien Jarno | int orig_root_dev;
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217 | 73f19035 | Aurelien Jarno | int loader_type;
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218 | 73f19035 | Aurelien Jarno | int initrd_start;
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219 | 73f19035 | Aurelien Jarno | int initrd_size;
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220 | 73f19035 | Aurelien Jarno | |
221 | 73f19035 | Aurelien Jarno | char pad[232]; |
222 | 73f19035 | Aurelien Jarno | |
223 | 73f19035 | Aurelien Jarno | char kernel_cmdline[256]; |
224 | 73f19035 | Aurelien Jarno | } boot_params; |
225 | 73f19035 | Aurelien Jarno | |
226 | c227f099 | Anthony Liguori | static void r2d_init(ram_addr_t ram_size, |
227 | 3023f332 | aliguori | const char *boot_device, |
228 | 0d78f544 | ths | const char *kernel_filename, const char *kernel_cmdline, |
229 | 0d78f544 | ths | const char *initrd_filename, const char *cpu_model) |
230 | 0d78f544 | ths | { |
231 | 0d78f544 | ths | CPUState *env; |
232 | 4f6493ff | Aurelien Jarno | ResetData *reset_info; |
233 | 0d78f544 | ths | struct SH7750State *s;
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234 | c227f099 | Anthony Liguori | ram_addr_t sdram_addr; |
235 | d47ede60 | balrog | qemu_irq *irq; |
236 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
237 | c2f01775 | balrog | int i;
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238 | 0d78f544 | ths | |
239 | aaed909a | bellard | if (!cpu_model)
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240 | 0fd3ca30 | aurel32 | cpu_model = "SH7751R";
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241 | aaed909a | bellard | |
242 | aaed909a | bellard | env = cpu_init(cpu_model); |
243 | aaed909a | bellard | if (!env) {
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244 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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245 | aaed909a | bellard | exit(1);
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246 | aaed909a | bellard | } |
247 | 4f6493ff | Aurelien Jarno | reset_info = qemu_mallocz(sizeof(ResetData));
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248 | 4f6493ff | Aurelien Jarno | reset_info->env = env; |
249 | 4f6493ff | Aurelien Jarno | reset_info->vector = env->pc; |
250 | 4f6493ff | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
251 | 0d78f544 | ths | |
252 | 0d78f544 | ths | /* Allocate memory space */
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253 | 1724f049 | Alex Williamson | sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE); |
254 | ffd39257 | blueswir1 | cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
255 | 0d78f544 | ths | /* Register peripherals */
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256 | 0d78f544 | ths | s = sh7750_init(env); |
257 | d47ede60 | balrog | irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
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258 | cf154394 | Aurelien Jarno | sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB], |
259 | cf154394 | Aurelien Jarno | irq[PCI_INTC], irq[PCI_INTD], NULL);
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260 | d47ede60 | balrog | |
261 | ac611340 | aurel32 | sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]); |
262 | a4a771c0 | balrog | |
263 | a4a771c0 | balrog | /* onboard CF (True IDE mode, Master only). */
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264 | 612b2bd0 | Aurelien Jarno | dinfo = drive_get(IF_IDE, 0, 0); |
265 | 612b2bd0 | Aurelien Jarno | mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, |
266 | 612b2bd0 | Aurelien Jarno | dinfo, NULL);
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267 | a4a771c0 | balrog | |
268 | 56839a19 | Aurelien Jarno | /* onboard flash memory */
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269 | 45e7e4bc | Aurelien Jarno | dinfo = drive_get(IF_PFLASH, 0, 0); |
270 | 1724f049 | Alex Williamson | pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE), |
271 | 612b2bd0 | Aurelien Jarno | dinfo ? dinfo->bdrv : NULL, (16 * 1024), |
272 | 612b2bd0 | Aurelien Jarno | FLASH_SIZE >> 16,
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273 | 612b2bd0 | Aurelien Jarno | 1, 4, 0x0000, 0x0000, 0x0000, 0x0000, |
274 | 612b2bd0 | Aurelien Jarno | 0x555, 0x2aa, 0); |
275 | 56839a19 | Aurelien Jarno | |
276 | c2f01775 | balrog | /* NIC: rtl8139 on-board, and 2 slots. */
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277 | ab2da564 | aurel32 | for (i = 0; i < nb_nics; i++) |
278 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL); |
279 | c2f01775 | balrog | |
280 | 9caa3ec1 | Aurelien Jarno | /* USB keyboard */
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281 | 9caa3ec1 | Aurelien Jarno | usbdevice_create("keyboard");
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282 | 9caa3ec1 | Aurelien Jarno | |
283 | 0d78f544 | ths | /* Todo: register on board registers */
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284 | 73f19035 | Aurelien Jarno | memset(&boot_params, 0, sizeof(boot_params)); |
285 | 73f19035 | Aurelien Jarno | |
286 | e8afa065 | aurel32 | if (kernel_filename) {
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287 | 73f19035 | Aurelien Jarno | int kernel_size;
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288 | 73f19035 | Aurelien Jarno | |
289 | 73f19035 | Aurelien Jarno | kernel_size = load_image_targphys(kernel_filename, |
290 | 73f19035 | Aurelien Jarno | SDRAM_BASE + LINUX_LOAD_OFFSET, |
291 | 73f19035 | Aurelien Jarno | INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); |
292 | 73f19035 | Aurelien Jarno | if (kernel_size < 0) { |
293 | 73f19035 | Aurelien Jarno | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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294 | 73f19035 | Aurelien Jarno | exit(1);
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295 | 73f19035 | Aurelien Jarno | } |
296 | 73f19035 | Aurelien Jarno | |
297 | 73f19035 | Aurelien Jarno | /* initialization which should be done by firmware */
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298 | 73f19035 | Aurelien Jarno | stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */ |
299 | 73f19035 | Aurelien Jarno | stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */ |
300 | 4f6493ff | Aurelien Jarno | reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ |
301 | 0d78f544 | ths | } |
302 | 73f19035 | Aurelien Jarno | |
303 | 73f19035 | Aurelien Jarno | if (initrd_filename) {
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304 | 73f19035 | Aurelien Jarno | int initrd_size;
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305 | 73f19035 | Aurelien Jarno | |
306 | 73f19035 | Aurelien Jarno | initrd_size = load_image_targphys(initrd_filename, |
307 | 73f19035 | Aurelien Jarno | SDRAM_BASE + INITRD_LOAD_OFFSET, |
308 | 73f19035 | Aurelien Jarno | SDRAM_SIZE - INITRD_LOAD_OFFSET); |
309 | 73f19035 | Aurelien Jarno | |
310 | 73f19035 | Aurelien Jarno | if (initrd_size < 0) { |
311 | 73f19035 | Aurelien Jarno | fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
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312 | 73f19035 | Aurelien Jarno | exit(1);
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313 | 73f19035 | Aurelien Jarno | } |
314 | 73f19035 | Aurelien Jarno | |
315 | 73f19035 | Aurelien Jarno | /* initialization which should be done by firmware */
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316 | 73f19035 | Aurelien Jarno | boot_params.loader_type = 1;
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317 | 73f19035 | Aurelien Jarno | boot_params.initrd_start = INITRD_LOAD_OFFSET; |
318 | 73f19035 | Aurelien Jarno | boot_params.initrd_size = initrd_size; |
319 | 73f19035 | Aurelien Jarno | } |
320 | 73f19035 | Aurelien Jarno | |
321 | 73f19035 | Aurelien Jarno | if (kernel_cmdline) {
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322 | 73f19035 | Aurelien Jarno | strncpy(boot_params.kernel_cmdline, kernel_cmdline, |
323 | 73f19035 | Aurelien Jarno | sizeof(boot_params.kernel_cmdline));
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324 | 73f19035 | Aurelien Jarno | } |
325 | 73f19035 | Aurelien Jarno | |
326 | 73f19035 | Aurelien Jarno | rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), |
327 | 73f19035 | Aurelien Jarno | SDRAM_BASE + BOOT_PARAMS_OFFSET); |
328 | 0d78f544 | ths | } |
329 | 0d78f544 | ths | |
330 | f80f9ec9 | Anthony Liguori | static QEMUMachine r2d_machine = {
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331 | 4b32e168 | aliguori | .name = "r2d",
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332 | 4b32e168 | aliguori | .desc = "r2d-plus board",
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333 | 4b32e168 | aliguori | .init = r2d_init, |
334 | 0d78f544 | ths | }; |
335 | f80f9ec9 | Anthony Liguori | |
336 | f80f9ec9 | Anthony Liguori | static void r2d_machine_init(void) |
337 | f80f9ec9 | Anthony Liguori | { |
338 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&r2d_machine); |
339 | f80f9ec9 | Anthony Liguori | } |
340 | f80f9ec9 | Anthony Liguori | |
341 | f80f9ec9 | Anthony Liguori | machine_init(r2d_machine_init); |