powerpc: add PVR mask support
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits anda CPU version in lower 16 bits. Since there is no significant changein behavior between versions, there is no point to add every single CPUversion in QEMU's CPU list. Also, new CPU versions of already supported...
target-ppc: add stubs for KVM breakpoints
The latest update to v3.13-rc3 (bf63839f) breaks theppc build with KVM:
kvm-all.o: In function `kvm_update_guest_debug':kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'kvm-all.o: In function `kvm_insert_breakpoint':...
target-ppc: Update slb array with correct index values.
Without this, a value of rb=0 and rs=0 results in replacing the 0thindex. This can be observed when using gdb remote debugging support.
(gdb) x/10i do_fork 0xc000000000085330 <do_fork>: Cannot access memory at address 0xc000000000085330...
target-ppc: Use #define for max slb entries
Instead of opencoding 64 use MAX_SLB_ENTRIES. We don't update the kernelheader here.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: dump-guest-memory support
This patch add support for dumping guest memory using dump-guest-memorymonitor command.
Before patch:
(qemu) dump-guest-memory testcrashthis feature or command is not currently supported(qemu)
After patch:
(qemu) dump-guest-memory testcrash...
target-ppc: Fill in OpenFirmware names for some PowerPCCPU families
Set the expected values for POWER7, POWER7+, POWER8 and POWER5+.Note that POWER5+ and POWER7+ are intentionally lacking the '+', so thelack of a POWER7P family constitutes no problem....
spapr: Use DeviceClass::fw_name for device tree CPU node
Instead of relying on cpu_model, obtain the device tree node labelper CPU. Use DeviceClass::fw_name as source.
Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN".
As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name,...
target-ppc: Add helper for KVM_PPC_RTAS_DEFINE_TOKEN
Recent PowerKVM allows the kernel to intercept some RTAS calls from theguest directly. This is used to implement the more efficient in-kernelXICS for example. qemu is still responsible for assigning the RTAS token...
target-ppc: Little Endian Correction to Load/Store Vector Element
The Load Vector Element (lve*x) and Store Vector Element (stve*x)instructions not only byte-swap in Little Endian mode, they alsoinvert the element that is accessed. For example, the RTL for...
PPC: Fix L2CR write accesses
Commit 2345f1c01 was supposed to render L2CR writes into noops. Instead,it made them illegal instruction traps which apparently didn't confuseXNU, but can easily confuse other OSs.
Fix it up by actually doing nothing when we write to L2CR....
Merge remote-tracking branch 'bonzini/configure' into staging
Makefile.target: CONFIG_NO_* variables removed
CONFIG_NO_* variables replaced with the lnot logical function
Signed-off-by: Ákos Kovács <akoskovacs@gmx.com>[PMM: fixed a few CONFIG_NO_* uses that were missed]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
Merge remote-tracking branch 'rth/tcg-pull' into staging
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Remove stray semi-colons from target-*/helper.h
During GEN_HELPER=1, these are actually stray top-level semi-colonswhich are technically invalid ISO C, but GCC accepts as an extension.If we added enough extension markers that we could dare use...
cpu: Drop cpu_model_str from CPU_COMMON
Since this is only read in cpu_copy() and linux-user has a globalcpu_model, drop the field from generic code.
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move cpu state syncs up into cpu_dump_state()
The x86 and ppc targets call cpu_synchronize_state() from their*_cpu_dump_state() callbacks to ensure that up to date state is dumpedwhen KVM is enabled (for example when a KVM internal error occurs)....
cpu: Use QTAILQ for CPU list
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthandmacros.
Merge branch 'tcg-next' of git://github.com/rth7680/qemu
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
target: Include softmmu_exec.h where forgotten
Several targets forgot to include softmmu_exec.h, which wouldbreak them with a header cleanup to follow.
target-ppc: fix bit extraction for FPBF and FPL
Bit extraction for the FP BF and L field of the MTFSFI and MTFSFinstructions is wrong and doesn't match the reference manual (whichexplain the bit number in big endian format). It has been broken incommit 7d08d85645def18eac2a9d672c1868a35e0bcf79....
target-ppc: Use #define instead of opencoding SLB valid bit
Use SLB_ESID_V instead of (1 << 27) in the code
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: KVM: Compile fix for qemu_notify_event
The function qemu_notify_event is defined by a header that we don'tinclude in the PPC KVM code. Include it to get the code buildingagain.
target-ppc/kvm_ppc.c: In function 'kvmppc_timer_hack': target-ppc/kvm_ppc.c:26:5: error: implicit declaration of function 'qemu_notify_event' [-Werror=implicit-function-declaration]...
target-ppc: USE LPCR_ILE to control exception endian on POWER7
On POWER7, LPCR_ILE is used to control what endian guests taketheir exceptions in so use it instead of MSR_ILE.
Signed-off-by: Anton Blanchard <anton@samba.org>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>...
target-ppc: POWER7 supports the MSR_LE bit
Add MSR_LE to the msr_mask for POWER7.
Signed-off-by: Anton Blanchard <anton@samba.org>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Merge remote-tracking branch 'stefanha/block' into staging
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
Convert stderr message calling error_get_pretty() to error_report()
Convert stderr messages calling error_get_pretty()to error_report().
Timestamp is prepended by -msg timstamp option with it.
Per Markus's comment below, A conversion from fprintf() to...
target-ppc: Turn POWER5gr CPU into alias for POWER5
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Message-id: 1375321323-29954-3-git-send-email-afaerber@suse.deSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-ppc: Prepare POWER5P CPU family
It is ISA 2.03. Modelled as 970FX minus AltiVec flag.
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>Cc: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Add POWER5+ v2.1 CPU model
Let's avoid -cpu host barfing at this PVR.Linux recognizes it as "POWER5+ (gs) v2.1".
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Message-id: 1375321323-29954-5-git-send-email-afaerber@suse.de...
target-ppc: Turn POWER5gs CPU into alias for POWER5+
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Message-id: 1375321323-29954-2-git-send-email-afaerber@suse.deSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-ppc: Fix POWER7+ model
Commit 03a15a5436ed7723f406f15cc3798aa9991e75b5 claimed to add a POWER7+model but instead added a "POWER7P" model, with an unhelpful "POWER7P" description on top. Fix this to "POWER7+" as we already have "POWER3+","POWER4+" and "POWER5+" and there being no reason to deviate with the...
target-ppc: Add POWER7+ CPU model
This patch adds CPU PVR definition for POWER7+.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Message-id: 1375412374-24701-1-git-send-email-aik@ozlabs.ruSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-ppc: Suppress TCG instruction emulation warnings for qtest
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Andreas Färber <afaerber@suse.de>Message-id: 1375106733-832-2-git-send-email-afaerber@suse.de...
target-ppc/kvm.c: Rename 'dprintf' to 'DPRINTF'
'dprintf' is the name of a POSIX standard function so we should not bestealing it for our debug macro. Rename to 'DPRINTF' (in line witha number of other source files.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
pseries: savevm support with KVM
At present, the savevm / migration support for the pseries machine will notwork when KVM is enabled. That's because KVM manages the guest's hash pagetable in the host kernel, so qemu has no visibility of it. This patch...
spapr-tce: make sPAPRTCETable a proper device
Model TCE tables as a device that's hooked up as a child object tothe owner. Besides the code cleanup, we get a few nice benefits:
1) free actually works now (it was dead code before)
2) the TCE information is visible in the device tree...
target-ppc: Convert ppc cpu savevm to VMStateDescription
The savevm code for the powerpc cpu emulation is currently based aroundthe old register_savevm() rather than register_vmstate() method. It's alsorather broken, missing some important state on some CPU models....
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".
The reason for the failure is that CPUClass::kvm_fd is not yet...
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro andmakes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g., sed i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target*/gdbstub.c...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field.Use first_cpu for qSupported and qXfer:features:read: for now.Add a stub for xml_builtin.
target-ppc: Move cpu_gdb_{read,write}_register()
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
gdbstub: Change gdb_register_coprocessor() argument to CPUState
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
e600 core for MPC86xx processors
MPC86xx processors are based on the e600 core, which is not the casein qemu where it is based on the 7400 processor.
This patch creates the e600 core and instantiates the MPC86xxprocessors based on it. Therefore, adding the high BATs, the SPRG...
target-ppc: Add POWER8 v1.0 CPU model
This patch adds CPU PVR definition for POWER8,and enables QEMU to launch guests on POWER8 hardware.
Signed-off-by: Prerna Saxena
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org>...
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
target-ppc: Change LOG_MMU_STATE() argument to CPUState
Choose CPUState rather than PowerPCCPU since doing a CPU cast on themacro argument would hide type mismatches.
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Don't overuse ENV_GET_CPU()
Commit b632a148b677b773ff155f9de840b37a653567b9 (target-ppc: QOM methoddispatch for MMU fault handling) introduced a use of ENV_GET_CPU()inside target-ppc/ code. Use ppc_env_get_cpu() instead.
Purely cosmetic, non-functional change to aid in locating and removing...
cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.Move first_cpu variable to qom/cpu.h.
gdbstub needs to use CPUState::env_ptr for now.cpu_copy() no longer needs to save and restore cpu_next.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPUrelated -- they are specific to the TLS ABI for a a particular OS.Move them into the linux-user/ tree where they belong....
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
A transition from CPUFooState to FooCPU can be considered safe,just like FooCPU::env access in the opposite direction.The only benefit of the FOO_CPU() casts would be protection againstbogus CPUFooState pointers, but then surrounding code would likely...
memory: add owner argument to initialization functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
PPC: Add dump_mmu() for 6xx
"(qemu) info tlb" is a very useful tool for debugging, so I implementedthe missing 6xx version.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>[agraf: fix printfs on hwaddr to PRI]Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Fix GDB read on code area for PPC6xx
On PPC 6xx, data and code have separated TLBs. Until now QEMU was onlylooking at data TLBs, which is not good when GDB wants to read code.
This patch adds a second call to get_physical_address() with anACCESS_CODE type of access when the first call with ACCESS_INT fails....
PPC: Introduce an alias cache for faster lookups
When running QEMU with "-cpu ?" we walk through every alias for everytarget CPU we know about. This takes several seconds on my very fasthost system.
Let's introduce a class object cache in the alias table. Using that we...
PPC: Ignore writes to L2CR
The L2CR register contains a number of bits that either impose configurationwhich we can't deal with or mean "something is in progress until the bit is0 again".
Since we don't model the former and we do want to accomodate guests using the...
target-ppc kvm: save cr register
This adds a missing code to save CR (condition register) viakvm_arch_put_registers(). kvm_arch_get_registers() already has it.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
target-ppc: Introduce unrealizefn for PowerPCCPU
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Drop redundant flags assignments from CPU families
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in someplaces for macrofied assignment to insns_flags2 field.
PPC_NONE is defined as zero though and QOM classes are zero-initialized,...
ppc: do not register IABR SPR twice for 603e
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E().
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Add non-kvm stub file
There are cases where a kvm provided function is called from generichw code that doesn't know whether kvm is available or not. Providea stub file which can provide simple replacement functions for thosecases.
Signed-off-by: Alexander Graf <agraf@suse.de>...
kvm/openpic: in-kernel mpic support
Enables support for the in-kernel MPIC that thas been merged into theKVM next branch. This includes irqfd/KVM_IRQ_LINE support from AlexGraf (along with some other improvements).
Note from Alex regarding kvm_irqchip_create():...
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
kvm: Change cpu_synchronize_state() argument to CPUState
Change Monitor::mon_cpu to CPUState as well.
Reviewed-by: liguang <lig.fnst@cn.fujitsu.com>Acked-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
KVM: PPC: Add dummy kvm_arch_init_irq_routing()
The common KVM code insists on calling kvm_arch_init_irq_routing()as soon as it sees kernel header support for it (regardless of whetherQEMU supports it). Provide a dummy function to satisfy this.
Unlike x86, PPC does not have one default irqchip, so there's no common...
remove some double-includes
Some source files #include the same header more thanonce for no good reason. Remove second #includes insuch cases.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
PPC: Depend behavior of cmp instructions only on instruction encoding
When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, itstill behaves identical to what it does when SF is on. Remove the implicitdifference in the code.
Also, on most 32bit CPUs we should always treat the compare as 32bit...
PPC: Fix rldcl
The implementation for rldcl tried to always fetch itsparameters from the opcode, even though the opcode wasalready passed in in decoded and different forms.
Use the parameters instead, fixing rldcl.
Reported-by: Torbjorn Granlund <tg@gmplib.org>...
PPC: Add MMU type for 2.06 with AMR but no TB pages
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TBMMU capability from the MMU type mask, but not the AMR bit.
This leads to us having a new MMU type that we don't check for in ourMMU management functions....
target-ppc: Fix invalid SPR read/write warnings
Invalid and privileged SPR warnings currently print the wrongaddress. While fixing that, also make it clear that we areprinting both the decimal and hexadecimal SPR number.
Before:
Trying to read invalid spr 896 380 at 0000000000000714...
target-ppc: Add read and write of PPR SPR
Recent Linux kernels save and restore the PPR across exceptionsso we need to handle it.
Signed-off-by: Anton Blanchard <anton@au1.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: slightly optimize lfiwax
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: emulate lfiwax instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix tcg debug error]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate load doubleword pair instructions
Needed for Power ISA version 2.05 compliance. The check for odd registerpairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate store doubleword pair instructions
target-ppc: add support for extended mtfsf/mtfsfi forms
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a newW field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with...
powerpc: correctly handle fpu exceptions.
Raise the exception on the first occurence, do not wait for the nextfloating point operation.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Fix dcbz for linux-user on 970
The default with linux-user for dcbz on 970 is to emulate 32 byte clears.However, redoing the dcbzl support we added a check to not honor the bitin HID5 that sets this.
Remove the #ifdef check on linux user, so that we get 32 byte clears again....
target-ppc: optimize fabs, fnabs, fneg
fabs, fnabs and fneg are just flipping the bit sign of an FP register,this can be implemented in TCG instead of using softfloat.
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate cmpb instruction
target-ppc: emulate prtyw and prtyd instructions
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix 32-bit host compile, simplify code]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate fcpsgn instruction
pseries: Fix incorrect calculation of RMA size in certain configurations
For the pseries machine, we need to advertise to the guest the size of itsRMA - that is the amount of memory it can access with the MMU off. For HVKVM, this is constrained by the hardware limitations on the virtual RMA of...
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several propertieswith information about the L1 cache. We already create two of theseproperties, but with incorrect names - "[id]cache-block-size" instead...
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and anextra control register (MMCRA). This patch adds stub support for them to...
target-ppc: Synchronize VPA state with KVM
For PAPR guests, KVM tracks the various areas registered with theH_REGISTER_VPA hypercall. For full emulation, of course, these are trackedwithin qemu. At present these values are not synchronized. This is a...
Enable kvm emulated watchdog
Enable the KVM emulated watchdog if KVM supports (use thecapability enablement in watchdog handler). Also watchdog exit(KVM_EXIT_WATCHDOG) handling is added.Watchdog state machine is cleared whenever VM state changes to running....