Revision 3c1cf9fa cpu-i386.h
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#define PG_ERROR_U_MASK 0x04 |
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#define PG_ERROR_RSVD_MASK 0x08 |
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#define MSR_IA32_APICBASE 0x1b |
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#define MSR_IA32_APICBASE_BSP (1<<8) |
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#define MSR_IA32_APICBASE_ENABLE (1<<11) |
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
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#define MSR_IA32_SYSENTER_CS 0x174 |
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#define MSR_IA32_SYSENTER_ESP 0x175 |
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#define MSR_IA32_SYSENTER_EIP 0x176 |
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#define EXCP00_DIVZ 0 |
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#define EXCP01_SSTP 1 |
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#define EXCP02_NMI 2 |
| ... | ... | |
| 244 | 253 |
SegmentCache tr; |
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SegmentCache gdt; /* only base and limit are used */ |
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SegmentCache idt; /* only base and limit are used */ |
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/* sysenter registers */ |
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uint32_t sysenter_cs; |
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uint32_t sysenter_esp; |
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uint32_t sysenter_eip; |
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/* exception/interrupt handling */ |
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jmp_buf jmp_env; |
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