root / hw / sh_intc.h @ 3c4cf535
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1 | 80f515e6 | balrog | #ifndef __SH_INTC_H__
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2 | 80f515e6 | balrog | #define __SH_INTC_H__
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3 | 80f515e6 | balrog | |
4 | 96e2fc41 | aurel32 | #include "qemu-common.h" |
5 | 96e2fc41 | aurel32 | #include "irq.h" |
6 | 96e2fc41 | aurel32 | |
7 | 80f515e6 | balrog | typedef unsigned char intc_enum; |
8 | 80f515e6 | balrog | |
9 | 80f515e6 | balrog | struct intc_vect {
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10 | 80f515e6 | balrog | intc_enum enum_id; |
11 | 80f515e6 | balrog | unsigned short vect; |
12 | 80f515e6 | balrog | }; |
13 | 80f515e6 | balrog | |
14 | 80f515e6 | balrog | #define INTC_VECT(enum_id, vect) { enum_id, vect }
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15 | 80f515e6 | balrog | |
16 | 80f515e6 | balrog | struct intc_group {
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17 | 80f515e6 | balrog | intc_enum enum_id; |
18 | 80f515e6 | balrog | intc_enum enum_ids[32];
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19 | 80f515e6 | balrog | }; |
20 | 80f515e6 | balrog | |
21 | 80f515e6 | balrog | #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
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22 | 80f515e6 | balrog | |
23 | 80f515e6 | balrog | struct intc_mask_reg {
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24 | 80f515e6 | balrog | unsigned long set_reg, clr_reg, reg_width; |
25 | 80f515e6 | balrog | intc_enum enum_ids[32];
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26 | 80f515e6 | balrog | unsigned long value; |
27 | 80f515e6 | balrog | }; |
28 | 80f515e6 | balrog | |
29 | 80f515e6 | balrog | struct intc_prio_reg {
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30 | 80f515e6 | balrog | unsigned long set_reg, clr_reg, reg_width, field_width; |
31 | 80f515e6 | balrog | intc_enum enum_ids[16];
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32 | 80f515e6 | balrog | unsigned long value; |
33 | 80f515e6 | balrog | }; |
34 | 80f515e6 | balrog | |
35 | b1503cda | malc | #define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
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36 | 80f515e6 | balrog | |
37 | 80f515e6 | balrog | struct intc_source {
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38 | 80f515e6 | balrog | unsigned short vect; |
39 | 80f515e6 | balrog | intc_enum next_enum_id; |
40 | 80f515e6 | balrog | |
41 | e96e2044 | ths | int asserted; /* emulates the interrupt signal line from device to intc */ |
42 | 80f515e6 | balrog | int enable_count;
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43 | 80f515e6 | balrog | int enable_max;
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44 | e96e2044 | ths | int pending; /* emulates the result of signal and masking */ |
45 | e96e2044 | ths | struct intc_desc *parent;
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46 | 80f515e6 | balrog | }; |
47 | 80f515e6 | balrog | |
48 | 80f515e6 | balrog | struct intc_desc {
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49 | 96e2fc41 | aurel32 | qemu_irq *irqs; |
50 | 80f515e6 | balrog | struct intc_source *sources;
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51 | 80f515e6 | balrog | int nr_sources;
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52 | 80f515e6 | balrog | struct intc_mask_reg *mask_regs;
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53 | 80f515e6 | balrog | int nr_mask_regs;
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54 | 80f515e6 | balrog | struct intc_prio_reg *prio_regs;
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55 | 80f515e6 | balrog | int nr_prio_regs;
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56 | 80f515e6 | balrog | int iomemtype;
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57 | e96e2044 | ths | int pending; /* number of interrupt sources that has pending set */ |
58 | 80f515e6 | balrog | }; |
59 | 80f515e6 | balrog | |
60 | e96e2044 | ths | int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); |
61 | 80f515e6 | balrog | struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id); |
62 | e96e2044 | ths | void sh_intc_toggle_source(struct intc_source *source, |
63 | e96e2044 | ths | int enable_adj, int assert_adj); |
64 | 80f515e6 | balrog | |
65 | 80f515e6 | balrog | void sh_intc_register_sources(struct intc_desc *desc, |
66 | 80f515e6 | balrog | struct intc_vect *vectors,
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67 | 80f515e6 | balrog | int nr_vectors,
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68 | 80f515e6 | balrog | struct intc_group *groups,
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69 | 80f515e6 | balrog | int nr_groups);
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70 | 80f515e6 | balrog | |
71 | 80f515e6 | balrog | int sh_intc_init(struct intc_desc *desc, |
72 | 80f515e6 | balrog | int nr_sources,
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73 | 80f515e6 | balrog | struct intc_mask_reg *mask_regs,
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74 | 80f515e6 | balrog | int nr_mask_regs,
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75 | 80f515e6 | balrog | struct intc_prio_reg *prio_regs,
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76 | 80f515e6 | balrog | int nr_prio_regs);
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77 | 80f515e6 | balrog | |
78 | c6d86a33 | balrog | void sh_intc_set_irl(void *opaque, int n, int level); |
79 | c6d86a33 | balrog | |
80 | 80f515e6 | balrog | #endif /* __SH_INTC_H__ */ |