root / hw / tc6393xb.c @ 3c4cf535
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1 | 7880febd | pbrook | /*
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2 | 7880febd | pbrook | * Toshiba TC6393XB I/O Controller.
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3 | 7880febd | pbrook | * Found in Sharp Zaurus SL-6000 (tosa) or some
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4 | 7880febd | pbrook | * Toshiba e-Series PDAs.
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5 | 7880febd | pbrook | *
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6 | 7880febd | pbrook | * Most features are currently unsupported!!!
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7 | 7880febd | pbrook | *
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8 | 7880febd | pbrook | * This code is licensed under the GNU GPL v2.
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9 | 7880febd | pbrook | */
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10 | 88d2c950 | balrog | #include "hw.h" |
11 | 88d2c950 | balrog | #include "pxa.h" |
12 | 88d2c950 | balrog | #include "devices.h" |
13 | a6569fc5 | balrog | #include "flash.h" |
14 | 64b40bc5 | balrog | #include "console.h" |
15 | 64b40bc5 | balrog | #include "pixel_ops.h" |
16 | a6569fc5 | balrog | |
17 | a6569fc5 | balrog | #define IRQ_TC6393_NAND 0 |
18 | a6569fc5 | balrog | #define IRQ_TC6393_MMC 1 |
19 | a6569fc5 | balrog | #define IRQ_TC6393_OHCI 2 |
20 | a6569fc5 | balrog | #define IRQ_TC6393_SERIAL 3 |
21 | a6569fc5 | balrog | #define IRQ_TC6393_FB 4 |
22 | a6569fc5 | balrog | |
23 | a6569fc5 | balrog | #define TC6393XB_NR_IRQS 8 |
24 | 88d2c950 | balrog | |
25 | 88d2c950 | balrog | #define TC6393XB_GPIOS 16 |
26 | 88d2c950 | balrog | |
27 | 88d2c950 | balrog | #define SCR_REVID 0x08 /* b Revision ID */ |
28 | 88d2c950 | balrog | #define SCR_ISR 0x50 /* b Interrupt Status */ |
29 | 88d2c950 | balrog | #define SCR_IMR 0x52 /* b Interrupt Mask */ |
30 | 88d2c950 | balrog | #define SCR_IRR 0x54 /* b Interrupt Routing */ |
31 | 88d2c950 | balrog | #define SCR_GPER 0x60 /* w GP Enable */ |
32 | 88d2c950 | balrog | #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ |
33 | 88d2c950 | balrog | #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ |
34 | 88d2c950 | balrog | #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ |
35 | 88d2c950 | balrog | #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ |
36 | 88d2c950 | balrog | #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ |
37 | 88d2c950 | balrog | #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ |
38 | 88d2c950 | balrog | #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ |
39 | 88d2c950 | balrog | #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ |
40 | 88d2c950 | balrog | #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ |
41 | 88d2c950 | balrog | #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ |
42 | 88d2c950 | balrog | #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ |
43 | 88d2c950 | balrog | #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ |
44 | 88d2c950 | balrog | #define SCR_CCR 0x98 /* w Clock Control */ |
45 | 88d2c950 | balrog | #define SCR_PLL2CR 0x9a /* w PLL2 Control */ |
46 | 88d2c950 | balrog | #define SCR_PLL1CR 0x9c /* l PLL1 Control */ |
47 | 88d2c950 | balrog | #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ |
48 | 88d2c950 | balrog | #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ |
49 | 88d2c950 | balrog | #define SCR_FER 0xe0 /* b Function Enable */ |
50 | 88d2c950 | balrog | #define SCR_MCR 0xe4 /* w Mode Control */ |
51 | 88d2c950 | balrog | #define SCR_CONFIG 0xfc /* b Configuration Control */ |
52 | 88d2c950 | balrog | #define SCR_DEBUG 0xff /* b Debug */ |
53 | 88d2c950 | balrog | |
54 | a6569fc5 | balrog | #define NAND_CFG_COMMAND 0x04 /* w Command */ |
55 | a6569fc5 | balrog | #define NAND_CFG_BASE 0x10 /* l Control Base Address */ |
56 | a6569fc5 | balrog | #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ |
57 | a6569fc5 | balrog | #define NAND_CFG_INTE 0x48 /* b Int Enable */ |
58 | a6569fc5 | balrog | #define NAND_CFG_EC 0x4a /* b Event Control */ |
59 | a6569fc5 | balrog | #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ |
60 | a6569fc5 | balrog | #define NAND_CFG_ECCC 0x5b /* b ECC Control */ |
61 | a6569fc5 | balrog | #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ |
62 | a6569fc5 | balrog | #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ |
63 | a6569fc5 | balrog | #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ |
64 | a6569fc5 | balrog | #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ |
65 | a6569fc5 | balrog | |
66 | a6569fc5 | balrog | #define NAND_DATA 0x00 /* l Data */ |
67 | a6569fc5 | balrog | #define NAND_MODE 0x04 /* b Mode */ |
68 | a6569fc5 | balrog | #define NAND_STATUS 0x05 /* b Status */ |
69 | a6569fc5 | balrog | #define NAND_ISR 0x06 /* b Interrupt Status */ |
70 | a6569fc5 | balrog | #define NAND_IMR 0x07 /* b Interrupt Mask */ |
71 | a6569fc5 | balrog | |
72 | a6569fc5 | balrog | #define NAND_MODE_WP 0x80 |
73 | a6569fc5 | balrog | #define NAND_MODE_CE 0x10 |
74 | a6569fc5 | balrog | #define NAND_MODE_ALE 0x02 |
75 | a6569fc5 | balrog | #define NAND_MODE_CLE 0x01 |
76 | a6569fc5 | balrog | #define NAND_MODE_ECC_MASK 0x60 |
77 | a6569fc5 | balrog | #define NAND_MODE_ECC_EN 0x20 |
78 | a6569fc5 | balrog | #define NAND_MODE_ECC_READ 0x40 |
79 | a6569fc5 | balrog | #define NAND_MODE_ECC_RST 0x60 |
80 | a6569fc5 | balrog | |
81 | 88d2c950 | balrog | struct tc6393xb_s {
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82 | a6569fc5 | balrog | qemu_irq irq; |
83 | a6569fc5 | balrog | qemu_irq *sub_irqs; |
84 | 88d2c950 | balrog | struct {
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85 | 88d2c950 | balrog | uint8_t ISR; |
86 | 88d2c950 | balrog | uint8_t IMR; |
87 | 88d2c950 | balrog | uint8_t IRR; |
88 | 88d2c950 | balrog | uint16_t GPER; |
89 | 88d2c950 | balrog | uint8_t GPI_SR[3];
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90 | 88d2c950 | balrog | uint8_t GPI_IMR[3];
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91 | 88d2c950 | balrog | uint8_t GPI_EDER[3];
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92 | 88d2c950 | balrog | uint8_t GPI_LIR[3];
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93 | 88d2c950 | balrog | uint8_t GP_IARCR[3];
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94 | 88d2c950 | balrog | uint8_t GP_IARLCR[3];
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95 | 88d2c950 | balrog | uint8_t GPI_BCR[3];
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96 | 88d2c950 | balrog | uint16_t GPA_IARCR; |
97 | 88d2c950 | balrog | uint16_t GPA_IARLCR; |
98 | 88d2c950 | balrog | uint16_t CCR; |
99 | 88d2c950 | balrog | uint16_t PLL2CR; |
100 | 88d2c950 | balrog | uint32_t PLL1CR; |
101 | 88d2c950 | balrog | uint8_t DIARCR; |
102 | 88d2c950 | balrog | uint8_t DBOCR; |
103 | 88d2c950 | balrog | uint8_t FER; |
104 | 88d2c950 | balrog | uint16_t MCR; |
105 | 88d2c950 | balrog | uint8_t CONFIG; |
106 | 88d2c950 | balrog | uint8_t DEBUG; |
107 | 88d2c950 | balrog | } scr; |
108 | 88d2c950 | balrog | uint32_t gpio_dir; |
109 | 88d2c950 | balrog | uint32_t gpio_level; |
110 | 88d2c950 | balrog | uint32_t prev_level; |
111 | 88d2c950 | balrog | qemu_irq handler[TC6393XB_GPIOS]; |
112 | 88d2c950 | balrog | qemu_irq *gpio_in; |
113 | a6569fc5 | balrog | |
114 | a6569fc5 | balrog | struct {
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115 | a6569fc5 | balrog | uint8_t mode; |
116 | a6569fc5 | balrog | uint8_t isr; |
117 | a6569fc5 | balrog | uint8_t imr; |
118 | a6569fc5 | balrog | } nand; |
119 | a6569fc5 | balrog | int nand_enable;
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120 | a6569fc5 | balrog | uint32_t nand_phys; |
121 | a6569fc5 | balrog | struct nand_flash_s *flash;
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122 | a6569fc5 | balrog | struct ecc_state_s ecc;
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123 | 64b40bc5 | balrog | |
124 | 64b40bc5 | balrog | DisplayState *ds; |
125 | 64b40bc5 | balrog | ram_addr_t vram_addr; |
126 | 64b40bc5 | balrog | uint32_t scr_width, scr_height; /* in pixels */
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127 | 64b40bc5 | balrog | qemu_irq l3v; |
128 | 64b40bc5 | balrog | unsigned blank : 1, |
129 | 64b40bc5 | balrog | blanked : 1;
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130 | 88d2c950 | balrog | }; |
131 | 88d2c950 | balrog | |
132 | 88d2c950 | balrog | qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
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133 | 88d2c950 | balrog | { |
134 | 88d2c950 | balrog | return s->gpio_in;
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135 | 88d2c950 | balrog | } |
136 | 88d2c950 | balrog | |
137 | 88d2c950 | balrog | static void tc6393xb_gpio_set(void *opaque, int line, int level) |
138 | 88d2c950 | balrog | { |
139 | 88d2c950 | balrog | // struct tc6393xb_s *s = opaque;
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140 | 88d2c950 | balrog | |
141 | 88d2c950 | balrog | if (line > TC6393XB_GPIOS) {
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142 | 88d2c950 | balrog | printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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143 | 88d2c950 | balrog | return;
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144 | 88d2c950 | balrog | } |
145 | 88d2c950 | balrog | |
146 | 88d2c950 | balrog | // FIXME: how does the chip reflect the GPIO input level change?
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147 | 88d2c950 | balrog | } |
148 | 88d2c950 | balrog | |
149 | 88d2c950 | balrog | void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line, |
150 | 88d2c950 | balrog | qemu_irq handler) |
151 | 88d2c950 | balrog | { |
152 | 88d2c950 | balrog | if (line >= TC6393XB_GPIOS) {
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153 | 88d2c950 | balrog | fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
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154 | 88d2c950 | balrog | return;
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155 | 88d2c950 | balrog | } |
156 | 88d2c950 | balrog | |
157 | 88d2c950 | balrog | s->handler[line] = handler; |
158 | 88d2c950 | balrog | } |
159 | 88d2c950 | balrog | |
160 | 88d2c950 | balrog | static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s) |
161 | 88d2c950 | balrog | { |
162 | 88d2c950 | balrog | uint32_t level, diff; |
163 | 88d2c950 | balrog | int bit;
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164 | 88d2c950 | balrog | |
165 | 88d2c950 | balrog | level = s->gpio_level & s->gpio_dir; |
166 | 88d2c950 | balrog | |
167 | 88d2c950 | balrog | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
168 | 88d2c950 | balrog | bit = ffs(diff) - 1;
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169 | 88d2c950 | balrog | qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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170 | 88d2c950 | balrog | } |
171 | 88d2c950 | balrog | |
172 | 88d2c950 | balrog | s->prev_level = level; |
173 | 88d2c950 | balrog | } |
174 | 88d2c950 | balrog | |
175 | 64b40bc5 | balrog | qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s)
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176 | 64b40bc5 | balrog | { |
177 | 64b40bc5 | balrog | return s->l3v;
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178 | 64b40bc5 | balrog | } |
179 | 64b40bc5 | balrog | |
180 | 64b40bc5 | balrog | static void tc6393xb_l3v(void *opaque, int line, int level) |
181 | 64b40bc5 | balrog | { |
182 | 64b40bc5 | balrog | struct tc6393xb_s *s = opaque;
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183 | 64b40bc5 | balrog | s->blank = !level; |
184 | 64b40bc5 | balrog | fprintf(stderr, "L3V: %d\n", level);
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185 | 64b40bc5 | balrog | } |
186 | 64b40bc5 | balrog | |
187 | a6569fc5 | balrog | static void tc6393xb_sub_irq(void *opaque, int line, int level) { |
188 | a6569fc5 | balrog | struct tc6393xb_s *s = opaque;
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189 | a6569fc5 | balrog | uint8_t isr = s->scr.ISR; |
190 | a6569fc5 | balrog | if (level)
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191 | a6569fc5 | balrog | isr |= 1 << line;
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192 | a6569fc5 | balrog | else
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193 | a6569fc5 | balrog | isr &= ~(1 << line);
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194 | a6569fc5 | balrog | s->scr.ISR = isr; |
195 | a6569fc5 | balrog | qemu_set_irq(s->irq, isr & s->scr.IMR); |
196 | a6569fc5 | balrog | } |
197 | a6569fc5 | balrog | |
198 | 88d2c950 | balrog | #define SCR_REG_B(N) \
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199 | 88d2c950 | balrog | case SCR_ ##N: return s->scr.N |
200 | 88d2c950 | balrog | #define SCR_REG_W(N) \
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201 | 88d2c950 | balrog | case SCR_ ##N: return s->scr.N; \ |
202 | 88d2c950 | balrog | case SCR_ ##N + 1: return s->scr.N >> 8; |
203 | 88d2c950 | balrog | #define SCR_REG_L(N) \
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204 | 88d2c950 | balrog | case SCR_ ##N: return s->scr.N; \ |
205 | 88d2c950 | balrog | case SCR_ ##N + 1: return s->scr.N >> 8; \ |
206 | 88d2c950 | balrog | case SCR_ ##N + 2: return s->scr.N >> 16; \ |
207 | 88d2c950 | balrog | case SCR_ ##N + 3: return s->scr.N >> 24; |
208 | 88d2c950 | balrog | #define SCR_REG_A(N) \
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209 | 88d2c950 | balrog | case SCR_ ##N(0): return s->scr.N[0]; \ |
210 | 88d2c950 | balrog | case SCR_ ##N(1): return s->scr.N[1]; \ |
211 | 88d2c950 | balrog | case SCR_ ##N(2): return s->scr.N[2] |
212 | 88d2c950 | balrog | |
213 | a6569fc5 | balrog | static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr) |
214 | 88d2c950 | balrog | { |
215 | 88d2c950 | balrog | switch (addr) {
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216 | 88d2c950 | balrog | case SCR_REVID:
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217 | 88d2c950 | balrog | return 3; |
218 | 88d2c950 | balrog | case SCR_REVID+1: |
219 | 88d2c950 | balrog | return 0; |
220 | 88d2c950 | balrog | SCR_REG_B(ISR); |
221 | 88d2c950 | balrog | SCR_REG_B(IMR); |
222 | 88d2c950 | balrog | SCR_REG_B(IRR); |
223 | 88d2c950 | balrog | SCR_REG_W(GPER); |
224 | 88d2c950 | balrog | SCR_REG_A(GPI_SR); |
225 | 88d2c950 | balrog | SCR_REG_A(GPI_IMR); |
226 | 88d2c950 | balrog | SCR_REG_A(GPI_EDER); |
227 | 88d2c950 | balrog | SCR_REG_A(GPI_LIR); |
228 | 88d2c950 | balrog | case SCR_GPO_DSR(0): |
229 | 88d2c950 | balrog | case SCR_GPO_DSR(1): |
230 | 88d2c950 | balrog | case SCR_GPO_DSR(2): |
231 | 88d2c950 | balrog | return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; |
232 | 88d2c950 | balrog | case SCR_GPO_DOECR(0): |
233 | 88d2c950 | balrog | case SCR_GPO_DOECR(1): |
234 | 88d2c950 | balrog | case SCR_GPO_DOECR(2): |
235 | 88d2c950 | balrog | return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; |
236 | 88d2c950 | balrog | SCR_REG_A(GP_IARCR); |
237 | 88d2c950 | balrog | SCR_REG_A(GP_IARLCR); |
238 | 88d2c950 | balrog | SCR_REG_A(GPI_BCR); |
239 | 88d2c950 | balrog | SCR_REG_W(GPA_IARCR); |
240 | 88d2c950 | balrog | SCR_REG_W(GPA_IARLCR); |
241 | 88d2c950 | balrog | SCR_REG_W(CCR); |
242 | 88d2c950 | balrog | SCR_REG_W(PLL2CR); |
243 | 88d2c950 | balrog | SCR_REG_L(PLL1CR); |
244 | 88d2c950 | balrog | SCR_REG_B(DIARCR); |
245 | 88d2c950 | balrog | SCR_REG_B(DBOCR); |
246 | 88d2c950 | balrog | SCR_REG_B(FER); |
247 | 88d2c950 | balrog | SCR_REG_W(MCR); |
248 | 88d2c950 | balrog | SCR_REG_B(CONFIG); |
249 | 88d2c950 | balrog | SCR_REG_B(DEBUG); |
250 | 88d2c950 | balrog | } |
251 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
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252 | 88d2c950 | balrog | return 0; |
253 | 88d2c950 | balrog | } |
254 | 88d2c950 | balrog | #undef SCR_REG_B
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255 | 88d2c950 | balrog | #undef SCR_REG_W
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256 | 88d2c950 | balrog | #undef SCR_REG_L
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257 | 88d2c950 | balrog | #undef SCR_REG_A
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258 | 88d2c950 | balrog | |
259 | 88d2c950 | balrog | #define SCR_REG_B(N) \
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260 | a6569fc5 | balrog | case SCR_ ##N: s->scr.N = value; return; |
261 | 88d2c950 | balrog | #define SCR_REG_W(N) \
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262 | a6569fc5 | balrog | case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
263 | a6569fc5 | balrog | case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return |
264 | 88d2c950 | balrog | #define SCR_REG_L(N) \
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265 | a6569fc5 | balrog | case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
266 | a6569fc5 | balrog | case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ |
267 | a6569fc5 | balrog | case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ |
268 | a6569fc5 | balrog | case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; |
269 | 88d2c950 | balrog | #define SCR_REG_A(N) \
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270 | a6569fc5 | balrog | case SCR_ ##N(0): s->scr.N[0] = value; return; \ |
271 | a6569fc5 | balrog | case SCR_ ##N(1): s->scr.N[1] = value; return; \ |
272 | a6569fc5 | balrog | case SCR_ ##N(2): s->scr.N[2] = value; return |
273 | 88d2c950 | balrog | |
274 | a6569fc5 | balrog | static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) |
275 | 88d2c950 | balrog | { |
276 | 88d2c950 | balrog | switch (addr) {
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277 | 88d2c950 | balrog | SCR_REG_B(ISR); |
278 | 88d2c950 | balrog | SCR_REG_B(IMR); |
279 | 88d2c950 | balrog | SCR_REG_B(IRR); |
280 | 88d2c950 | balrog | SCR_REG_W(GPER); |
281 | 88d2c950 | balrog | SCR_REG_A(GPI_SR); |
282 | 88d2c950 | balrog | SCR_REG_A(GPI_IMR); |
283 | 88d2c950 | balrog | SCR_REG_A(GPI_EDER); |
284 | 88d2c950 | balrog | SCR_REG_A(GPI_LIR); |
285 | 88d2c950 | balrog | case SCR_GPO_DSR(0): |
286 | 88d2c950 | balrog | case SCR_GPO_DSR(1): |
287 | 88d2c950 | balrog | case SCR_GPO_DSR(2): |
288 | 88d2c950 | balrog | s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); |
289 | 88d2c950 | balrog | tc6393xb_gpio_handler_update(s); |
290 | a6569fc5 | balrog | return;
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291 | 88d2c950 | balrog | case SCR_GPO_DOECR(0): |
292 | 88d2c950 | balrog | case SCR_GPO_DOECR(1): |
293 | 88d2c950 | balrog | case SCR_GPO_DOECR(2): |
294 | 88d2c950 | balrog | s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); |
295 | 88d2c950 | balrog | tc6393xb_gpio_handler_update(s); |
296 | a6569fc5 | balrog | return;
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297 | 88d2c950 | balrog | SCR_REG_A(GP_IARCR); |
298 | 88d2c950 | balrog | SCR_REG_A(GP_IARLCR); |
299 | 88d2c950 | balrog | SCR_REG_A(GPI_BCR); |
300 | 88d2c950 | balrog | SCR_REG_W(GPA_IARCR); |
301 | 88d2c950 | balrog | SCR_REG_W(GPA_IARLCR); |
302 | 88d2c950 | balrog | SCR_REG_W(CCR); |
303 | 88d2c950 | balrog | SCR_REG_W(PLL2CR); |
304 | 88d2c950 | balrog | SCR_REG_L(PLL1CR); |
305 | 88d2c950 | balrog | SCR_REG_B(DIARCR); |
306 | 88d2c950 | balrog | SCR_REG_B(DBOCR); |
307 | 88d2c950 | balrog | SCR_REG_B(FER); |
308 | 88d2c950 | balrog | SCR_REG_W(MCR); |
309 | 88d2c950 | balrog | SCR_REG_B(CONFIG); |
310 | 88d2c950 | balrog | SCR_REG_B(DEBUG); |
311 | 88d2c950 | balrog | } |
312 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
|
313 | a6569fc5 | balrog | (uint32_t) addr, value & 0xff);
|
314 | 88d2c950 | balrog | } |
315 | 88d2c950 | balrog | #undef SCR_REG_B
|
316 | 88d2c950 | balrog | #undef SCR_REG_W
|
317 | 88d2c950 | balrog | #undef SCR_REG_L
|
318 | 88d2c950 | balrog | #undef SCR_REG_A
|
319 | 88d2c950 | balrog | |
320 | a6569fc5 | balrog | static void tc6393xb_nand_irq(struct tc6393xb_s *s) { |
321 | a6569fc5 | balrog | qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], |
322 | a6569fc5 | balrog | (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
|
323 | a6569fc5 | balrog | } |
324 | a6569fc5 | balrog | |
325 | a6569fc5 | balrog | static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { |
326 | a6569fc5 | balrog | switch (addr) {
|
327 | a6569fc5 | balrog | case NAND_CFG_COMMAND:
|
328 | a6569fc5 | balrog | return s->nand_enable ? 2 : 0; |
329 | a6569fc5 | balrog | case NAND_CFG_BASE:
|
330 | a6569fc5 | balrog | case NAND_CFG_BASE + 1: |
331 | a6569fc5 | balrog | case NAND_CFG_BASE + 2: |
332 | a6569fc5 | balrog | case NAND_CFG_BASE + 3: |
333 | a6569fc5 | balrog | return s->nand_phys >> (addr - NAND_CFG_BASE);
|
334 | a6569fc5 | balrog | } |
335 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
|
336 | a6569fc5 | balrog | return 0; |
337 | a6569fc5 | balrog | } |
338 | a6569fc5 | balrog | static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { |
339 | a6569fc5 | balrog | switch (addr) {
|
340 | a6569fc5 | balrog | case NAND_CFG_COMMAND:
|
341 | a6569fc5 | balrog | s->nand_enable = (value & 0x2);
|
342 | a6569fc5 | balrog | return;
|
343 | a6569fc5 | balrog | case NAND_CFG_BASE:
|
344 | a6569fc5 | balrog | case NAND_CFG_BASE + 1: |
345 | a6569fc5 | balrog | case NAND_CFG_BASE + 2: |
346 | a6569fc5 | balrog | case NAND_CFG_BASE + 3: |
347 | a6569fc5 | balrog | s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); |
348 | a6569fc5 | balrog | s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); |
349 | a6569fc5 | balrog | return;
|
350 | a6569fc5 | balrog | } |
351 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
|
352 | a6569fc5 | balrog | (uint32_t) addr, value & 0xff);
|
353 | a6569fc5 | balrog | } |
354 | a6569fc5 | balrog | |
355 | a6569fc5 | balrog | static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { |
356 | a6569fc5 | balrog | switch (addr) {
|
357 | a6569fc5 | balrog | case NAND_DATA + 0: |
358 | a6569fc5 | balrog | case NAND_DATA + 1: |
359 | a6569fc5 | balrog | case NAND_DATA + 2: |
360 | a6569fc5 | balrog | case NAND_DATA + 3: |
361 | a6569fc5 | balrog | return nand_getio(s->flash);
|
362 | a6569fc5 | balrog | case NAND_MODE:
|
363 | a6569fc5 | balrog | return s->nand.mode;
|
364 | a6569fc5 | balrog | case NAND_STATUS:
|
365 | a6569fc5 | balrog | return 0x14; |
366 | a6569fc5 | balrog | case NAND_ISR:
|
367 | a6569fc5 | balrog | return s->nand.isr;
|
368 | a6569fc5 | balrog | case NAND_IMR:
|
369 | a6569fc5 | balrog | return s->nand.imr;
|
370 | a6569fc5 | balrog | } |
371 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
|
372 | a6569fc5 | balrog | return 0; |
373 | a6569fc5 | balrog | } |
374 | a6569fc5 | balrog | static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { |
375 | a6569fc5 | balrog | // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
|
376 | a6569fc5 | balrog | // (uint32_t) addr, value & 0xff);
|
377 | a6569fc5 | balrog | switch (addr) {
|
378 | a6569fc5 | balrog | case NAND_DATA + 0: |
379 | a6569fc5 | balrog | case NAND_DATA + 1: |
380 | a6569fc5 | balrog | case NAND_DATA + 2: |
381 | a6569fc5 | balrog | case NAND_DATA + 3: |
382 | a6569fc5 | balrog | nand_setio(s->flash, value); |
383 | a6569fc5 | balrog | s->nand.isr &= 1;
|
384 | a6569fc5 | balrog | tc6393xb_nand_irq(s); |
385 | a6569fc5 | balrog | return;
|
386 | a6569fc5 | balrog | case NAND_MODE:
|
387 | a6569fc5 | balrog | s->nand.mode = value; |
388 | a6569fc5 | balrog | nand_setpins(s->flash, |
389 | a6569fc5 | balrog | value & NAND_MODE_CLE, |
390 | a6569fc5 | balrog | value & NAND_MODE_ALE, |
391 | a6569fc5 | balrog | !(value & NAND_MODE_CE), |
392 | a6569fc5 | balrog | value & NAND_MODE_WP, |
393 | a6569fc5 | balrog | 0); // FIXME: gnd |
394 | a6569fc5 | balrog | switch (value & NAND_MODE_ECC_MASK) {
|
395 | a6569fc5 | balrog | case NAND_MODE_ECC_RST:
|
396 | a6569fc5 | balrog | ecc_reset(&s->ecc); |
397 | a6569fc5 | balrog | break;
|
398 | a6569fc5 | balrog | case NAND_MODE_ECC_READ:
|
399 | a6569fc5 | balrog | // FIXME
|
400 | a6569fc5 | balrog | break;
|
401 | a6569fc5 | balrog | case NAND_MODE_ECC_EN:
|
402 | a6569fc5 | balrog | ecc_reset(&s->ecc); |
403 | a6569fc5 | balrog | } |
404 | a6569fc5 | balrog | return;
|
405 | a6569fc5 | balrog | case NAND_ISR:
|
406 | a6569fc5 | balrog | s->nand.isr = value; |
407 | a6569fc5 | balrog | tc6393xb_nand_irq(s); |
408 | a6569fc5 | balrog | return;
|
409 | a6569fc5 | balrog | case NAND_IMR:
|
410 | a6569fc5 | balrog | s->nand.imr = value; |
411 | a6569fc5 | balrog | tc6393xb_nand_irq(s); |
412 | a6569fc5 | balrog | return;
|
413 | a6569fc5 | balrog | } |
414 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
|
415 | a6569fc5 | balrog | (uint32_t) addr, value & 0xff);
|
416 | a6569fc5 | balrog | } |
417 | a6569fc5 | balrog | |
418 | 64b40bc5 | balrog | #define BITS 8 |
419 | 64b40bc5 | balrog | #include "tc6393xb_template.h" |
420 | 64b40bc5 | balrog | #define BITS 15 |
421 | 64b40bc5 | balrog | #include "tc6393xb_template.h" |
422 | 64b40bc5 | balrog | #define BITS 16 |
423 | 64b40bc5 | balrog | #include "tc6393xb_template.h" |
424 | 64b40bc5 | balrog | #define BITS 24 |
425 | 64b40bc5 | balrog | #include "tc6393xb_template.h" |
426 | 64b40bc5 | balrog | #define BITS 32 |
427 | 64b40bc5 | balrog | #include "tc6393xb_template.h" |
428 | 64b40bc5 | balrog | |
429 | 64b40bc5 | balrog | static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update) |
430 | 64b40bc5 | balrog | { |
431 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
432 | 64b40bc5 | balrog | case 8: |
433 | 64b40bc5 | balrog | tc6393xb_draw_graphic8(s); |
434 | 64b40bc5 | balrog | break;
|
435 | 64b40bc5 | balrog | case 15: |
436 | 64b40bc5 | balrog | tc6393xb_draw_graphic15(s); |
437 | 64b40bc5 | balrog | break;
|
438 | 64b40bc5 | balrog | case 16: |
439 | 64b40bc5 | balrog | tc6393xb_draw_graphic16(s); |
440 | 64b40bc5 | balrog | break;
|
441 | 64b40bc5 | balrog | case 24: |
442 | 64b40bc5 | balrog | tc6393xb_draw_graphic24(s); |
443 | 64b40bc5 | balrog | break;
|
444 | 64b40bc5 | balrog | case 32: |
445 | 64b40bc5 | balrog | tc6393xb_draw_graphic32(s); |
446 | 64b40bc5 | balrog | break;
|
447 | 64b40bc5 | balrog | default:
|
448 | 0e1f5a0c | aliguori | printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
|
449 | 64b40bc5 | balrog | return;
|
450 | 64b40bc5 | balrog | } |
451 | 64b40bc5 | balrog | |
452 | 64b40bc5 | balrog | dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
453 | 64b40bc5 | balrog | } |
454 | 64b40bc5 | balrog | |
455 | 64b40bc5 | balrog | static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update) |
456 | 64b40bc5 | balrog | { |
457 | 64b40bc5 | balrog | int i, w;
|
458 | 64b40bc5 | balrog | uint8_t *d; |
459 | 64b40bc5 | balrog | |
460 | 64b40bc5 | balrog | if (!full_update)
|
461 | 64b40bc5 | balrog | return;
|
462 | 64b40bc5 | balrog | |
463 | 0e1f5a0c | aliguori | w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); |
464 | 0e1f5a0c | aliguori | d = ds_get_data(s->ds); |
465 | 64b40bc5 | balrog | for(i = 0; i < s->scr_height; i++) { |
466 | 64b40bc5 | balrog | memset(d, 0, w);
|
467 | 0e1f5a0c | aliguori | d += ds_get_linesize(s->ds); |
468 | 64b40bc5 | balrog | } |
469 | 64b40bc5 | balrog | |
470 | 64b40bc5 | balrog | dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
471 | 64b40bc5 | balrog | } |
472 | 64b40bc5 | balrog | |
473 | 64b40bc5 | balrog | static void tc6393xb_update_display(void *opaque) |
474 | 64b40bc5 | balrog | { |
475 | 64b40bc5 | balrog | struct tc6393xb_s *s = opaque;
|
476 | 64b40bc5 | balrog | int full_update;
|
477 | 64b40bc5 | balrog | |
478 | 64b40bc5 | balrog | if (s->scr_width == 0 || s->scr_height == 0) |
479 | 64b40bc5 | balrog | return;
|
480 | 64b40bc5 | balrog | |
481 | 64b40bc5 | balrog | full_update = 0;
|
482 | 64b40bc5 | balrog | if (s->blanked != s->blank) {
|
483 | 64b40bc5 | balrog | s->blanked = s->blank; |
484 | 64b40bc5 | balrog | full_update = 1;
|
485 | 64b40bc5 | balrog | } |
486 | 0e1f5a0c | aliguori | if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
|
487 | 3023f332 | aliguori | qemu_console_resize(s->ds, s->scr_width, s->scr_height); |
488 | 64b40bc5 | balrog | full_update = 1;
|
489 | 64b40bc5 | balrog | } |
490 | 64b40bc5 | balrog | if (s->blanked)
|
491 | 64b40bc5 | balrog | tc6393xb_draw_blank(s, full_update); |
492 | 64b40bc5 | balrog | else
|
493 | 64b40bc5 | balrog | tc6393xb_draw_graphic(s, full_update); |
494 | 64b40bc5 | balrog | } |
495 | 64b40bc5 | balrog | |
496 | 64b40bc5 | balrog | |
497 | a6569fc5 | balrog | static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { |
498 | a6569fc5 | balrog | struct tc6393xb_s *s = opaque;
|
499 | a6569fc5 | balrog | |
500 | a6569fc5 | balrog | switch (addr >> 8) { |
501 | a6569fc5 | balrog | case 0: |
502 | a6569fc5 | balrog | return tc6393xb_scr_readb(s, addr & 0xff); |
503 | a6569fc5 | balrog | case 1: |
504 | a6569fc5 | balrog | return tc6393xb_nand_cfg_readb(s, addr & 0xff); |
505 | a6569fc5 | balrog | }; |
506 | a6569fc5 | balrog | |
507 | a6569fc5 | balrog | if ((addr &~0xff) == s->nand_phys && s->nand_enable) { |
508 | a6569fc5 | balrog | // return tc6393xb_nand_readb(s, addr & 0xff);
|
509 | a6569fc5 | balrog | uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
|
510 | a6569fc5 | balrog | // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
|
511 | a6569fc5 | balrog | return d;
|
512 | a6569fc5 | balrog | } |
513 | a6569fc5 | balrog | |
514 | a6569fc5 | balrog | // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
|
515 | a6569fc5 | balrog | return 0; |
516 | a6569fc5 | balrog | } |
517 | a6569fc5 | balrog | |
518 | a6569fc5 | balrog | static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { |
519 | a6569fc5 | balrog | struct tc6393xb_s *s = opaque;
|
520 | a6569fc5 | balrog | |
521 | a6569fc5 | balrog | switch (addr >> 8) { |
522 | a6569fc5 | balrog | case 0: |
523 | a6569fc5 | balrog | tc6393xb_scr_writeb(s, addr & 0xff, value);
|
524 | a6569fc5 | balrog | return;
|
525 | a6569fc5 | balrog | case 1: |
526 | a6569fc5 | balrog | tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
|
527 | a6569fc5 | balrog | return;
|
528 | a6569fc5 | balrog | }; |
529 | a6569fc5 | balrog | |
530 | a6569fc5 | balrog | if ((addr &~0xff) == s->nand_phys && s->nand_enable) |
531 | a6569fc5 | balrog | tc6393xb_nand_writeb(s, addr & 0xff, value);
|
532 | a6569fc5 | balrog | else
|
533 | a6569fc5 | balrog | fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
|
534 | a6569fc5 | balrog | (uint32_t) addr, value & 0xff);
|
535 | a6569fc5 | balrog | } |
536 | a6569fc5 | balrog | |
537 | 88d2c950 | balrog | static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr) |
538 | 88d2c950 | balrog | { |
539 | 88d2c950 | balrog | return (tc6393xb_readb(opaque, addr) & 0xff) | |
540 | 88d2c950 | balrog | (tc6393xb_readb(opaque, addr + 1) << 8); |
541 | 88d2c950 | balrog | } |
542 | 88d2c950 | balrog | |
543 | 88d2c950 | balrog | static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) |
544 | 88d2c950 | balrog | { |
545 | 88d2c950 | balrog | return (tc6393xb_readb(opaque, addr) & 0xff) | |
546 | 88d2c950 | balrog | ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) | |
547 | 88d2c950 | balrog | ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) | |
548 | 88d2c950 | balrog | ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24); |
549 | 88d2c950 | balrog | } |
550 | 88d2c950 | balrog | |
551 | 88d2c950 | balrog | static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
552 | 88d2c950 | balrog | { |
553 | 88d2c950 | balrog | tc6393xb_writeb(opaque, addr, value); |
554 | 88d2c950 | balrog | tc6393xb_writeb(opaque, addr + 1, value >> 8); |
555 | 88d2c950 | balrog | } |
556 | 88d2c950 | balrog | |
557 | 88d2c950 | balrog | static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value) |
558 | 88d2c950 | balrog | { |
559 | 88d2c950 | balrog | tc6393xb_writeb(opaque, addr, value); |
560 | 88d2c950 | balrog | tc6393xb_writeb(opaque, addr + 1, value >> 8); |
561 | 88d2c950 | balrog | tc6393xb_writeb(opaque, addr + 2, value >> 16); |
562 | 88d2c950 | balrog | tc6393xb_writeb(opaque, addr + 3, value >> 24); |
563 | 88d2c950 | balrog | } |
564 | 88d2c950 | balrog | |
565 | 3023f332 | aliguori | struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
|
566 | 88d2c950 | balrog | { |
567 | 88d2c950 | balrog | int iomemtype;
|
568 | 88d2c950 | balrog | struct tc6393xb_s *s;
|
569 | 88d2c950 | balrog | CPUReadMemoryFunc *tc6393xb_readfn[] = { |
570 | 88d2c950 | balrog | tc6393xb_readb, |
571 | 88d2c950 | balrog | tc6393xb_readw, |
572 | 88d2c950 | balrog | tc6393xb_readl, |
573 | 88d2c950 | balrog | }; |
574 | 88d2c950 | balrog | CPUWriteMemoryFunc *tc6393xb_writefn[] = { |
575 | 88d2c950 | balrog | tc6393xb_writeb, |
576 | 88d2c950 | balrog | tc6393xb_writew, |
577 | 88d2c950 | balrog | tc6393xb_writel, |
578 | 88d2c950 | balrog | }; |
579 | 88d2c950 | balrog | |
580 | 88d2c950 | balrog | s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s)); |
581 | a6569fc5 | balrog | s->irq = irq; |
582 | 88d2c950 | balrog | s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); |
583 | 88d2c950 | balrog | |
584 | 64b40bc5 | balrog | s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
|
585 | 64b40bc5 | balrog | s->blanked = 1;
|
586 | 64b40bc5 | balrog | |
587 | a6569fc5 | balrog | s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); |
588 | a6569fc5 | balrog | |
589 | a6569fc5 | balrog | s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
|
590 | a6569fc5 | balrog | |
591 | 88d2c950 | balrog | iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
|
592 | 88d2c950 | balrog | tc6393xb_writefn, s); |
593 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x10000, iomemtype);
|
594 | 64b40bc5 | balrog | |
595 | 3023f332 | aliguori | s->vram_addr = qemu_ram_alloc(0x100000);
|
596 | 3023f332 | aliguori | cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr); |
597 | 3023f332 | aliguori | s->scr_width = 480;
|
598 | 3023f332 | aliguori | s->scr_height = 640;
|
599 | 3023f332 | aliguori | s->ds = graphic_console_init(tc6393xb_update_display, |
600 | 3023f332 | aliguori | NULL, /* invalidate */ |
601 | 3023f332 | aliguori | NULL, /* screen_dump */ |
602 | 3023f332 | aliguori | NULL, /* text_update */ |
603 | 3023f332 | aliguori | s); |
604 | 88d2c950 | balrog | |
605 | 88d2c950 | balrog | return s;
|
606 | 88d2c950 | balrog | } |