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| 1 | 450d4ff5 | ths | /* Disassembler code for CRIS.
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| 2 | 450d4ff5 | ths | Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
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| 3 | 450d4ff5 | ths | Contributed by Axis Communications AB, Lund, Sweden.
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| 4 | 450d4ff5 | ths | Written by Hans-Peter Nilsson.
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| 5 | 450d4ff5 | ths | |
| 6 | 450d4ff5 | ths | This file is part of the GNU binutils and GDB, the GNU debugger.
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| 7 | 450d4ff5 | ths | |
| 8 | 450d4ff5 | ths | This program is free software; you can redistribute it and/or modify it
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| 9 | 450d4ff5 | ths | under the terms of the GNU General Public License as published by the
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| 10 | 450d4ff5 | ths | Free Software Foundation; either version 2, or (at your option) any later
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| 11 | 450d4ff5 | ths | version.
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| 12 | 450d4ff5 | ths | |
| 13 | 450d4ff5 | ths | This program is distributed in the hope that it will be useful, but WITHOUT
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| 14 | 450d4ff5 | ths | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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| 15 | 450d4ff5 | ths | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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| 16 | 450d4ff5 | ths | more details.
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| 17 | 450d4ff5 | ths | |
| 18 | 450d4ff5 | ths | You should have received a copy of the GNU General Public License
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| 19 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
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| 20 | 450d4ff5 | ths | |
| 21 | 450d4ff5 | ths | #include "dis-asm.h" |
| 22 | 450d4ff5 | ths | //#include "sysdep.h"
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| 23 | 450d4ff5 | ths | #include "target-cris/opcode-cris.h" |
| 24 | 450d4ff5 | ths | //#include "libiberty.h"
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| 25 | 450d4ff5 | ths | |
| 26 | 450d4ff5 | ths | |
| 27 | 1eec614b | aliguori | void *qemu_malloc(size_t len); /* can't include qemu-common.h here */ |
| 28 | 1eec614b | aliguori | |
| 29 | 450d4ff5 | ths | #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0) |
| 30 | 450d4ff5 | ths | |
| 31 | 450d4ff5 | ths | /* cris-opc.c -- Table of opcodes for the CRIS processor.
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| 32 | 450d4ff5 | ths | Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
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| 33 | 450d4ff5 | ths | Contributed by Axis Communications AB, Lund, Sweden.
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| 34 | 450d4ff5 | ths | Originally written for GAS 1.38.1 by Mikael Asker.
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| 35 | 450d4ff5 | ths | Reorganized by Hans-Peter Nilsson.
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| 36 | 450d4ff5 | ths | |
| 37 | 450d4ff5 | ths | This file is part of GAS, GDB and the GNU binutils.
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| 38 | 450d4ff5 | ths | |
| 39 | 450d4ff5 | ths | GAS, GDB, and GNU binutils is free software; you can redistribute it
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| 40 | 450d4ff5 | ths | and/or modify it under the terms of the GNU General Public License as
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| 41 | 450d4ff5 | ths | published by the Free Software Foundation; either version 2, or (at your
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| 42 | 450d4ff5 | ths | option) any later version.
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| 43 | 450d4ff5 | ths | |
| 44 | 450d4ff5 | ths | GAS, GDB, and GNU binutils are distributed in the hope that they will be
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| 45 | 450d4ff5 | ths | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 46 | 450d4ff5 | ths | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 47 | 450d4ff5 | ths | GNU General Public License for more details.
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| 48 | 450d4ff5 | ths | |
| 49 | 450d4ff5 | ths | You should have received a copy of the GNU General Public License
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| 50 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
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| 51 | 450d4ff5 | ths | |
| 52 | 450d4ff5 | ths | #ifndef NULL |
| 53 | 450d4ff5 | ths | #define NULL (0) |
| 54 | 450d4ff5 | ths | #endif
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| 55 | 450d4ff5 | ths | |
| 56 | 450d4ff5 | ths | /* This table isn't used for CRISv32 and the size of immediate operands. */
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| 57 | 450d4ff5 | ths | const struct cris_spec_reg |
| 58 | 450d4ff5 | ths | cris_spec_regs[] = |
| 59 | 450d4ff5 | ths | {
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| 60 | 450d4ff5 | ths | {"bz", 0, 1, cris_ver_v32p, NULL},
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| 61 | 450d4ff5 | ths | {"p0", 0, 1, 0, NULL},
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| 62 | 450d4ff5 | ths | {"vr", 1, 1, 0, NULL},
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| 63 | 450d4ff5 | ths | {"p1", 1, 1, 0, NULL},
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| 64 | 450d4ff5 | ths | {"pid", 2, 1, cris_ver_v32p, NULL},
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| 65 | 450d4ff5 | ths | {"p2", 2, 1, cris_ver_v32p, NULL},
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| 66 | 450d4ff5 | ths | {"p2", 2, 1, cris_ver_warning, NULL},
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| 67 | 450d4ff5 | ths | {"srs", 3, 1, cris_ver_v32p, NULL},
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| 68 | 450d4ff5 | ths | {"p3", 3, 1, cris_ver_v32p, NULL},
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| 69 | 450d4ff5 | ths | {"p3", 3, 1, cris_ver_warning, NULL},
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| 70 | 450d4ff5 | ths | {"wz", 4, 2, cris_ver_v32p, NULL},
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| 71 | 450d4ff5 | ths | {"p4", 4, 2, 0, NULL},
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| 72 | 450d4ff5 | ths | {"ccr", 5, 2, cris_ver_v0_10, NULL},
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| 73 | 450d4ff5 | ths | {"exs", 5, 4, cris_ver_v32p, NULL},
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| 74 | 450d4ff5 | ths | {"p5", 5, 2, cris_ver_v0_10, NULL},
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| 75 | 450d4ff5 | ths | {"p5", 5, 4, cris_ver_v32p, NULL},
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| 76 | 450d4ff5 | ths | {"dcr0",6, 2, cris_ver_v0_3, NULL},
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| 77 | 450d4ff5 | ths | {"eda", 6, 4, cris_ver_v32p, NULL},
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| 78 | 450d4ff5 | ths | {"p6", 6, 2, cris_ver_v0_3, NULL},
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| 79 | 450d4ff5 | ths | {"p6", 6, 4, cris_ver_v32p, NULL},
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| 80 | 450d4ff5 | ths | {"dcr1/mof", 7, 4, cris_ver_v10p,
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| 81 | 450d4ff5 | ths | "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
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| 82 | 450d4ff5 | ths | {"dcr1/mof", 7, 2, cris_ver_v0_3,
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| 83 | 450d4ff5 | ths | "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
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| 84 | 450d4ff5 | ths | {"mof", 7, 4, cris_ver_v10p, NULL},
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| 85 | 450d4ff5 | ths | {"dcr1",7, 2, cris_ver_v0_3, NULL},
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| 86 | 450d4ff5 | ths | {"p7", 7, 4, cris_ver_v10p, NULL},
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| 87 | 450d4ff5 | ths | {"p7", 7, 2, cris_ver_v0_3, NULL},
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| 88 | 450d4ff5 | ths | {"dz", 8, 4, cris_ver_v32p, NULL},
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| 89 | 450d4ff5 | ths | {"p8", 8, 4, 0, NULL},
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| 90 | 450d4ff5 | ths | {"ibr", 9, 4, cris_ver_v0_10, NULL},
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| 91 | 450d4ff5 | ths | {"ebp", 9, 4, cris_ver_v32p, NULL},
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| 92 | 450d4ff5 | ths | {"p9", 9, 4, 0, NULL},
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| 93 | 450d4ff5 | ths | {"irp", 10, 4, cris_ver_v0_10, NULL},
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| 94 | 450d4ff5 | ths | {"erp", 10, 4, cris_ver_v32p, NULL},
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| 95 | 450d4ff5 | ths | {"p10", 10, 4, 0, NULL},
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| 96 | 450d4ff5 | ths | {"srp", 11, 4, 0, NULL},
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| 97 | 450d4ff5 | ths | {"p11", 11, 4, 0, NULL},
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| 98 | 450d4ff5 | ths | /* For disassembly use only. Accept at assembly with a warning. */
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| 99 | 450d4ff5 | ths | {"bar/dtp0", 12, 4, cris_ver_warning,
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| 100 | 450d4ff5 | ths | "Ambiguous register `bar/dtp0' specified"},
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| 101 | 450d4ff5 | ths | {"nrp", 12, 4, cris_ver_v32p, NULL},
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| 102 | 450d4ff5 | ths | {"bar", 12, 4, cris_ver_v8_10, NULL},
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| 103 | 450d4ff5 | ths | {"dtp0",12, 4, cris_ver_v0_3, NULL},
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| 104 | 450d4ff5 | ths | {"p12", 12, 4, 0, NULL},
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| 105 | 450d4ff5 | ths | /* For disassembly use only. Accept at assembly with a warning. */
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| 106 | 450d4ff5 | ths | {"dccr/dtp1",13, 4, cris_ver_warning,
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| 107 | 450d4ff5 | ths | "Ambiguous register `dccr/dtp1' specified"},
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| 108 | 450d4ff5 | ths | {"ccs", 13, 4, cris_ver_v32p, NULL},
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| 109 | 450d4ff5 | ths | {"dccr",13, 4, cris_ver_v8_10, NULL},
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| 110 | 450d4ff5 | ths | {"dtp1",13, 4, cris_ver_v0_3, NULL},
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| 111 | 450d4ff5 | ths | {"p13", 13, 4, 0, NULL},
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| 112 | 450d4ff5 | ths | {"brp", 14, 4, cris_ver_v3_10, NULL},
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| 113 | 450d4ff5 | ths | {"usp", 14, 4, cris_ver_v32p, NULL},
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| 114 | 450d4ff5 | ths | {"p14", 14, 4, cris_ver_v3p, NULL},
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| 115 | 450d4ff5 | ths | {"usp", 15, 4, cris_ver_v10, NULL},
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| 116 | 450d4ff5 | ths | {"spc", 15, 4, cris_ver_v32p, NULL},
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| 117 | 450d4ff5 | ths | {"p15", 15, 4, cris_ver_v10p, NULL},
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| 118 | 450d4ff5 | ths | {NULL, 0, 0, cris_ver_version_all, NULL}
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| 119 | 450d4ff5 | ths | }; |
| 120 | 450d4ff5 | ths | |
| 121 | 450d4ff5 | ths | /* Add version specifiers to this table when necessary.
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| 122 | 450d4ff5 | ths | The (now) regular coding of register names suggests a simpler
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| 123 | 450d4ff5 | ths | implementation. */
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| 124 | 450d4ff5 | ths | const struct cris_support_reg cris_support_regs[] = |
| 125 | 450d4ff5 | ths | {
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| 126 | 450d4ff5 | ths | {"s0", 0},
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| 127 | 450d4ff5 | ths | {"s1", 1},
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| 128 | 450d4ff5 | ths | {"s2", 2},
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| 129 | 450d4ff5 | ths | {"s3", 3},
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| 130 | 450d4ff5 | ths | {"s4", 4},
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| 131 | 450d4ff5 | ths | {"s5", 5},
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| 132 | 450d4ff5 | ths | {"s6", 6},
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| 133 | 450d4ff5 | ths | {"s7", 7},
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| 134 | 450d4ff5 | ths | {"s8", 8},
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| 135 | 450d4ff5 | ths | {"s9", 9},
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| 136 | 450d4ff5 | ths | {"s10", 10},
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| 137 | 450d4ff5 | ths | {"s11", 11},
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| 138 | 450d4ff5 | ths | {"s12", 12},
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| 139 | 450d4ff5 | ths | {"s13", 13},
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| 140 | 450d4ff5 | ths | {"s14", 14},
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| 141 | 450d4ff5 | ths | {"s15", 15},
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| 142 | 450d4ff5 | ths | {NULL, 0}
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| 143 | 450d4ff5 | ths | }; |
| 144 | 450d4ff5 | ths | |
| 145 | 450d4ff5 | ths | /* All CRIS opcodes are 16 bits.
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| 146 | 450d4ff5 | ths | |
| 147 | 450d4ff5 | ths | - The match component is a mask saying which bits must match a
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| 148 | 450d4ff5 | ths | particular opcode in order for an instruction to be an instance
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| 149 | 450d4ff5 | ths | of that opcode.
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| 150 | 450d4ff5 | ths | |
| 151 | 450d4ff5 | ths | - The args component is a string containing characters symbolically
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| 152 | 450d4ff5 | ths | matching the operands of an instruction. Used for both assembly
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| 153 | 450d4ff5 | ths | and disassembly.
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| 154 | 450d4ff5 | ths | |
| 155 | 450d4ff5 | ths | Operand-matching characters:
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| 156 | 450d4ff5 | ths | [ ] , space
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| 157 | 450d4ff5 | ths | Verbatim.
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| 158 | 450d4ff5 | ths | A The string "ACR" (case-insensitive).
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| 159 | 450d4ff5 | ths | B Not really an operand. It causes a "BDAP -size,SP" prefix to be
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| 160 | 450d4ff5 | ths | output for the PUSH alias-instructions and recognizes a push-
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| 161 | 450d4ff5 | ths | prefix at disassembly. This letter isn't recognized for v32.
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| 162 | 450d4ff5 | ths | Must be followed by a R or P letter.
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| 163 | 450d4ff5 | ths | ! Non-match pattern, will not match if there's a prefix insn.
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| 164 | 450d4ff5 | ths | b Non-matching operand, used for branches with 16-bit
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| 165 | 450d4ff5 | ths | displacement. Only recognized by the disassembler.
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| 166 | 450d4ff5 | ths | c 5-bit unsigned immediate in bits <4:0>.
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| 167 | 450d4ff5 | ths | C 4-bit unsigned immediate in bits <3:0>.
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| 168 | 450d4ff5 | ths | d At assembly, optionally (as in put other cases before this one)
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| 169 | 450d4ff5 | ths | ".d" or ".D" at the start of the operands, followed by one space
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| 170 | 450d4ff5 | ths | character. At disassembly, nothing.
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| 171 | 450d4ff5 | ths | D General register in bits <15:12> and <3:0>.
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| 172 | 450d4ff5 | ths | f List of flags in bits <15:12> and <3:0>.
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| 173 | 450d4ff5 | ths | i 6-bit signed immediate in bits <5:0>.
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| 174 | 450d4ff5 | ths | I 6-bit unsigned immediate in bits <5:0>.
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| 175 | 450d4ff5 | ths | M Size modifier (B, W or D) for CLEAR instructions.
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| 176 | 450d4ff5 | ths | m Size modifier (B, W or D) in bits <5:4>
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| 177 | 450d4ff5 | ths | N A 32-bit dword, like in the difference between s and y.
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| 178 | 450d4ff5 | ths | This has no effect on bits in the opcode. Can also be expressed
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| 179 | 450d4ff5 | ths | as "[pc+]" in input.
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| 180 | 450d4ff5 | ths | n As N, but PC-relative (to the start of the instruction).
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| 181 | 450d4ff5 | ths | o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
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| 182 | 450d4ff5 | ths | branch instructions.
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| 183 | 450d4ff5 | ths | O [-128..127] offset in bits <7:0>. Also matches a comma and a
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| 184 | 450d4ff5 | ths | general register after the expression, in bits <15:12>. Used
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| 185 | 450d4ff5 | ths | only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
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| 186 | 450d4ff5 | ths | P Special register in bits <15:12>.
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| 187 | 450d4ff5 | ths | p Indicates that the insn is a prefix insn. Must be first
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| 188 | 450d4ff5 | ths | character.
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| 189 | 450d4ff5 | ths | Q As O, but don't relax; force an 8-bit offset.
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| 190 | 450d4ff5 | ths | R General register in bits <15:12>.
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| 191 | 450d4ff5 | ths | r General register in bits <3:0>.
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| 192 | 450d4ff5 | ths | S Source operand in bit <10> and a prefix; a 3-operand prefix
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| 193 | 450d4ff5 | ths | without side-effect.
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| 194 | 450d4ff5 | ths | s Source operand in bits <10> and <3:0>, optionally with a
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| 195 | 450d4ff5 | ths | side-effect prefix, except [pc] (the name, not R15 as in ACR)
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| 196 | 450d4ff5 | ths | isn't allowed for v32 and higher.
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| 197 | 450d4ff5 | ths | T Support register in bits <15:12>.
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| 198 | 450d4ff5 | ths | u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
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| 199 | 450d4ff5 | ths | U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
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| 200 | 450d4ff5 | ths | Not recognized at disassembly.
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| 201 | 450d4ff5 | ths | x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
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| 202 | 450d4ff5 | ths | y Like 's' but do not allow an integer at assembly.
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| 203 | 450d4ff5 | ths | Y The difference s-y; only an integer is allowed.
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| 204 | 450d4ff5 | ths | z Size modifier (B or W) in bit <4>. */
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| 205 | 450d4ff5 | ths | |
| 206 | 450d4ff5 | ths | |
| 207 | 450d4ff5 | ths | /* Please note the order of the opcodes in this table is significant.
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| 208 | 450d4ff5 | ths | The assembler requires that all instances of the same mnemonic must
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| 209 | 450d4ff5 | ths | be consecutive. If they aren't, the assembler might not recognize
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| 210 | 450d4ff5 | ths | them, or may indicate an internal error.
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| 211 | 450d4ff5 | ths | |
| 212 | 450d4ff5 | ths | The disassembler should not normally care about the order of the
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| 213 | 450d4ff5 | ths | opcodes, but will prefer an earlier alternative if the "match-score"
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| 214 | 450d4ff5 | ths | (see cris-dis.c) is computed as equal.
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| 215 | 450d4ff5 | ths | |
| 216 | 450d4ff5 | ths | It should not be significant for proper execution that this table is
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| 217 | 450d4ff5 | ths | in alphabetical order, but please follow that convention for an easy
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| 218 | 450d4ff5 | ths | overview. */
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| 219 | 450d4ff5 | ths | |
| 220 | 450d4ff5 | ths | const struct cris_opcode |
| 221 | 450d4ff5 | ths | cris_opcodes[] = |
| 222 | 450d4ff5 | ths | {
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| 223 | 450d4ff5 | ths | {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
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| 224 | 450d4ff5 | ths | cris_abs_op}, |
| 225 | 450d4ff5 | ths | |
| 226 | 450d4ff5 | ths | {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
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| 227 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 228 | 450d4ff5 | ths | |
| 229 | 450d4ff5 | ths | {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
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| 230 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 231 | 450d4ff5 | ths | |
| 232 | 450d4ff5 | ths | {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
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| 233 | 450d4ff5 | ths | cris_ver_v0_10, |
| 234 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 235 | 450d4ff5 | ths | |
| 236 | 450d4ff5 | ths | {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
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| 237 | 450d4ff5 | ths | cris_ver_v0_10, |
| 238 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 239 | 450d4ff5 | ths | |
| 240 | 450d4ff5 | ths | {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
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| 241 | 450d4ff5 | ths | cris_ver_v32p, |
| 242 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 243 | 450d4ff5 | ths | |
| 244 | 450d4ff5 | ths | {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
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| 245 | 450d4ff5 | ths | cris_ver_v32p, |
| 246 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 247 | 450d4ff5 | ths | |
| 248 | 450d4ff5 | ths | {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
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| 249 | 450d4ff5 | ths | cris_ver_v32p, |
| 250 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 251 | 450d4ff5 | ths | |
| 252 | 450d4ff5 | ths | {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
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| 253 | 450d4ff5 | ths | cris_ver_v32p, |
| 254 | 450d4ff5 | ths | cris_addi_op}, |
| 255 | 450d4ff5 | ths | |
| 256 | 450d4ff5 | ths | {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
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| 257 | 450d4ff5 | ths | cris_addi_op}, |
| 258 | 450d4ff5 | ths | |
| 259 | 450d4ff5 | ths | /* This collates after "addo", but we want to disassemble as "addoq",
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| 260 | 450d4ff5 | ths | not "addo". */
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| 261 | 450d4ff5 | ths | {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
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| 262 | 450d4ff5 | ths | cris_ver_v32p, |
| 263 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 264 | 450d4ff5 | ths | |
| 265 | 450d4ff5 | ths | {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
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| 266 | 450d4ff5 | ths | cris_ver_v32p, |
| 267 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 268 | 450d4ff5 | ths | |
| 269 | 450d4ff5 | ths | /* This must be located after the insn above, lest we misinterpret
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| 270 | 450d4ff5 | ths | "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
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| 271 | 450d4ff5 | ths | parser bug. */
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| 272 | 450d4ff5 | ths | {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
|
| 273 | 450d4ff5 | ths | cris_ver_v32p, |
| 274 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 275 | 450d4ff5 | ths | |
| 276 | 450d4ff5 | ths | {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
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| 277 | 450d4ff5 | ths | cris_quick_mode_add_sub_op}, |
| 278 | 450d4ff5 | ths | |
| 279 | 450d4ff5 | ths | {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
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| 280 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 281 | 450d4ff5 | ths | |
| 282 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
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| 283 | 450d4ff5 | ths | {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
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| 284 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 285 | 450d4ff5 | ths | |
| 286 | 450d4ff5 | ths | {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
|
| 287 | 450d4ff5 | ths | cris_ver_v0_10, |
| 288 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 289 | 450d4ff5 | ths | |
| 290 | 450d4ff5 | ths | {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
|
| 291 | 450d4ff5 | ths | cris_ver_v0_10, |
| 292 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 293 | 450d4ff5 | ths | |
| 294 | 450d4ff5 | ths | {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
|
| 295 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 296 | 450d4ff5 | ths | |
| 297 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
| 298 | 450d4ff5 | ths | {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
|
| 299 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 300 | 450d4ff5 | ths | |
| 301 | 450d4ff5 | ths | {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
|
| 302 | 450d4ff5 | ths | cris_ver_v0_10, |
| 303 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 304 | 450d4ff5 | ths | |
| 305 | 450d4ff5 | ths | {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
|
| 306 | 450d4ff5 | ths | cris_ver_v0_10, |
| 307 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 308 | 450d4ff5 | ths | |
| 309 | 450d4ff5 | ths | {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
|
| 310 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 311 | 450d4ff5 | ths | |
| 312 | 450d4ff5 | ths | {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
|
| 313 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 314 | 450d4ff5 | ths | |
| 315 | 450d4ff5 | ths | {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
|
| 316 | 450d4ff5 | ths | cris_ver_v0_10, |
| 317 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 318 | 450d4ff5 | ths | |
| 319 | 450d4ff5 | ths | {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
|
| 320 | 450d4ff5 | ths | cris_ver_v0_10, |
| 321 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 322 | 450d4ff5 | ths | |
| 323 | 450d4ff5 | ths | {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
|
| 324 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
| 325 | 450d4ff5 | ths | |
| 326 | 450d4ff5 | ths | {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
|
| 327 | 450d4ff5 | ths | cris_asr_op}, |
| 328 | 450d4ff5 | ths | |
| 329 | 450d4ff5 | ths | {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
|
| 330 | 450d4ff5 | ths | cris_asrq_op}, |
| 331 | 450d4ff5 | ths | |
| 332 | 450d4ff5 | ths | {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
|
| 333 | 450d4ff5 | ths | cris_ax_ei_setf_op}, |
| 334 | 450d4ff5 | ths | |
| 335 | 450d4ff5 | ths | /* FIXME: Should use branch #defines. */
|
| 336 | 450d4ff5 | ths | {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
|
| 337 | 450d4ff5 | ths | cris_sixteen_bit_offset_branch_op}, |
| 338 | 450d4ff5 | ths | |
| 339 | 450d4ff5 | ths | {"ba",
|
| 340 | 450d4ff5 | ths | BA_QUICK_OPCODE, |
| 341 | 450d4ff5 | ths | 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, |
| 342 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 343 | 450d4ff5 | ths | |
| 344 | 450d4ff5 | ths | /* Needs to come after the usual "ba o", which might be relaxed to
|
| 345 | 450d4ff5 | ths | this one. */
|
| 346 | 450d4ff5 | ths | {"ba", BA_DWORD_OPCODE,
|
| 347 | 450d4ff5 | ths | 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, |
| 348 | 450d4ff5 | ths | cris_ver_v32p, |
| 349 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 350 | 450d4ff5 | ths | |
| 351 | 450d4ff5 | ths | {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
|
| 352 | 450d4ff5 | ths | cris_ver_v32p, |
| 353 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 354 | 450d4ff5 | ths | |
| 355 | 450d4ff5 | ths | {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
|
| 356 | 450d4ff5 | ths | cris_ver_v32p, |
| 357 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 358 | 450d4ff5 | ths | |
| 359 | 450d4ff5 | ths | {"bcc",
|
| 360 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_CC*0x1000,
|
| 361 | 450d4ff5 | ths | 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, |
| 362 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 363 | 450d4ff5 | ths | |
| 364 | 450d4ff5 | ths | {"bcs",
|
| 365 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_CS*0x1000,
|
| 366 | 450d4ff5 | ths | 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 367 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 368 | 450d4ff5 | ths | |
| 369 | 450d4ff5 | ths | {"bdap",
|
| 370 | 450d4ff5 | ths | BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED, |
| 371 | 450d4ff5 | ths | cris_ver_v0_10, |
| 372 | 450d4ff5 | ths | cris_bdap_prefix}, |
| 373 | 450d4ff5 | ths | |
| 374 | 450d4ff5 | ths | {"bdap",
|
| 375 | 450d4ff5 | ths | BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, |
| 376 | 450d4ff5 | ths | cris_ver_v0_10, |
| 377 | 450d4ff5 | ths | cris_quick_mode_bdap_prefix}, |
| 378 | 450d4ff5 | ths | |
| 379 | 450d4ff5 | ths | {"beq",
|
| 380 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
|
| 381 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, |
| 382 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 383 | 450d4ff5 | ths | |
| 384 | 450d4ff5 | ths | /* This is deliberately put before "bext" to trump it, even though not
|
| 385 | 450d4ff5 | ths | in alphabetical order, since we don't do excluding version checks
|
| 386 | 450d4ff5 | ths | for v0..v10. */
|
| 387 | 450d4ff5 | ths | {"bwf",
|
| 388 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
|
| 389 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
| 390 | 450d4ff5 | ths | cris_ver_v10, |
| 391 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 392 | 450d4ff5 | ths | |
| 393 | 450d4ff5 | ths | {"bext",
|
| 394 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
|
| 395 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
| 396 | 450d4ff5 | ths | cris_ver_v0_3, |
| 397 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 398 | 450d4ff5 | ths | |
| 399 | 450d4ff5 | ths | {"bge",
|
| 400 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_GE*0x1000,
|
| 401 | 450d4ff5 | ths | 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, |
| 402 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 403 | 450d4ff5 | ths | |
| 404 | 450d4ff5 | ths | {"bgt",
|
| 405 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_GT*0x1000,
|
| 406 | 450d4ff5 | ths | 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, |
| 407 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 408 | 450d4ff5 | ths | |
| 409 | 450d4ff5 | ths | {"bhi",
|
| 410 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_HI*0x1000,
|
| 411 | 450d4ff5 | ths | 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, |
| 412 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 413 | 450d4ff5 | ths | |
| 414 | 450d4ff5 | ths | {"bhs",
|
| 415 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_HS*0x1000,
|
| 416 | 450d4ff5 | ths | 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 417 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 418 | 450d4ff5 | ths | |
| 419 | 450d4ff5 | ths | {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
|
| 420 | 450d4ff5 | ths | cris_ver_v0_10, |
| 421 | 450d4ff5 | ths | cris_biap_prefix}, |
| 422 | 450d4ff5 | ths | |
| 423 | 450d4ff5 | ths | {"ble",
|
| 424 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LE*0x1000,
|
| 425 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, |
| 426 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 427 | 450d4ff5 | ths | |
| 428 | 450d4ff5 | ths | {"blo",
|
| 429 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LO*0x1000,
|
| 430 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, |
| 431 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 432 | 450d4ff5 | ths | |
| 433 | 450d4ff5 | ths | {"bls",
|
| 434 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LS*0x1000,
|
| 435 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 436 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 437 | 450d4ff5 | ths | |
| 438 | 450d4ff5 | ths | {"blt",
|
| 439 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LT*0x1000,
|
| 440 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, |
| 441 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 442 | 450d4ff5 | ths | |
| 443 | 450d4ff5 | ths | {"bmi",
|
| 444 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_MI*0x1000,
|
| 445 | 450d4ff5 | ths | 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, |
| 446 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 447 | 450d4ff5 | ths | |
| 448 | 450d4ff5 | ths | {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
|
| 449 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
| 450 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 451 | 450d4ff5 | ths | |
| 452 | 450d4ff5 | ths | {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
|
| 453 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
| 454 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 455 | 450d4ff5 | ths | |
| 456 | 450d4ff5 | ths | {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
|
| 457 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
| 458 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 459 | 450d4ff5 | ths | |
| 460 | 450d4ff5 | ths | {"bne",
|
| 461 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_NE*0x1000,
|
| 462 | 450d4ff5 | ths | 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, |
| 463 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 464 | 450d4ff5 | ths | |
| 465 | 450d4ff5 | ths | {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
|
| 466 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
| 467 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
| 468 | 450d4ff5 | ths | {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
|
| 469 | 450d4ff5 | ths | cris_ver_v0_10, |
| 470 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
| 471 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
| 472 | 450d4ff5 | ths | {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
|
| 473 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
| 474 | 450d4ff5 | ths | {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
|
| 475 | 450d4ff5 | ths | cris_ver_v0_10, |
| 476 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
| 477 | 450d4ff5 | ths | {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
|
| 478 | 450d4ff5 | ths | cris_ver_v0_10, |
| 479 | 450d4ff5 | ths | cris_three_operand_bound_op}, |
| 480 | 450d4ff5 | ths | |
| 481 | 450d4ff5 | ths | {"bpl",
|
| 482 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_PL*0x1000,
|
| 483 | 450d4ff5 | ths | 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, |
| 484 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 485 | 450d4ff5 | ths | |
| 486 | 450d4ff5 | ths | {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
|
| 487 | 450d4ff5 | ths | cris_ver_v3p, |
| 488 | 450d4ff5 | ths | cris_break_op}, |
| 489 | 450d4ff5 | ths | |
| 490 | 450d4ff5 | ths | {"bsb",
|
| 491 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
|
| 492 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
| 493 | 450d4ff5 | ths | cris_ver_v32p, |
| 494 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 495 | 450d4ff5 | ths | |
| 496 | 450d4ff5 | ths | {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
|
| 497 | 450d4ff5 | ths | cris_ver_v32p, |
| 498 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 499 | 450d4ff5 | ths | |
| 500 | 450d4ff5 | ths | {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
|
| 501 | 450d4ff5 | ths | cris_ver_v32p, |
| 502 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 503 | 450d4ff5 | ths | |
| 504 | 450d4ff5 | ths | {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
|
| 505 | 450d4ff5 | ths | cris_ver_warning, |
| 506 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 507 | 450d4ff5 | ths | |
| 508 | 450d4ff5 | ths | {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
|
| 509 | 450d4ff5 | ths | cris_ver_warning, |
| 510 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 511 | 450d4ff5 | ths | |
| 512 | 450d4ff5 | ths | {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
|
| 513 | 450d4ff5 | ths | cris_ver_warning, |
| 514 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 515 | 450d4ff5 | ths | |
| 516 | 450d4ff5 | ths | {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
|
| 517 | 450d4ff5 | ths | cris_btst_nop_op}, |
| 518 | 450d4ff5 | ths | {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
|
| 519 | 450d4ff5 | ths | cris_btst_nop_op}, |
| 520 | 450d4ff5 | ths | |
| 521 | 450d4ff5 | ths | {"bvc",
|
| 522 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_VC*0x1000,
|
| 523 | 450d4ff5 | ths | 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, |
| 524 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 525 | 450d4ff5 | ths | |
| 526 | 450d4ff5 | ths | {"bvs",
|
| 527 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_VS*0x1000,
|
| 528 | 450d4ff5 | ths | 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 529 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
| 530 | 450d4ff5 | ths | |
| 531 | 450d4ff5 | ths | {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
|
| 532 | 450d4ff5 | ths | cris_reg_mode_clear_op}, |
| 533 | 450d4ff5 | ths | |
| 534 | 450d4ff5 | ths | {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
|
| 535 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
| 536 | 450d4ff5 | ths | |
| 537 | 450d4ff5 | ths | {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
|
| 538 | 450d4ff5 | ths | cris_ver_v0_10, |
| 539 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
| 540 | 450d4ff5 | ths | |
| 541 | 450d4ff5 | ths | {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
|
| 542 | 450d4ff5 | ths | cris_clearf_di_op}, |
| 543 | 450d4ff5 | ths | |
| 544 | 450d4ff5 | ths | {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
|
| 545 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 546 | 450d4ff5 | ths | |
| 547 | 450d4ff5 | ths | {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
|
| 548 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 549 | 450d4ff5 | ths | |
| 550 | 450d4ff5 | ths | {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
|
| 551 | 450d4ff5 | ths | cris_ver_v0_10, |
| 552 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 553 | 450d4ff5 | ths | |
| 554 | 450d4ff5 | ths | {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
|
| 555 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
| 556 | 450d4ff5 | ths | |
| 557 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
|
| 558 | 450d4ff5 | ths | {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
|
| 559 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 560 | 450d4ff5 | ths | |
| 561 | 450d4ff5 | ths | {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
|
| 562 | 450d4ff5 | ths | cris_ver_v0_10, |
| 563 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 564 | 450d4ff5 | ths | |
| 565 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
| 566 | 450d4ff5 | ths | {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
|
| 567 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 568 | 450d4ff5 | ths | |
| 569 | 450d4ff5 | ths | {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
|
| 570 | 450d4ff5 | ths | cris_ver_v0_10, |
| 571 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 572 | 450d4ff5 | ths | |
| 573 | 450d4ff5 | ths | {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
|
| 574 | 450d4ff5 | ths | cris_clearf_di_op}, |
| 575 | 450d4ff5 | ths | |
| 576 | 450d4ff5 | ths | {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
|
| 577 | 450d4ff5 | ths | cris_ver_v0_10, |
| 578 | 450d4ff5 | ths | cris_dip_prefix}, |
| 579 | 450d4ff5 | ths | |
| 580 | 450d4ff5 | ths | {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
|
| 581 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 582 | 450d4ff5 | ths | |
| 583 | 450d4ff5 | ths | {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
|
| 584 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 585 | 450d4ff5 | ths | |
| 586 | 450d4ff5 | ths | {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
|
| 587 | 450d4ff5 | ths | cris_ax_ei_setf_op}, |
| 588 | 450d4ff5 | ths | |
| 589 | 450d4ff5 | ths | {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
|
| 590 | 450d4ff5 | ths | cris_ver_v32p, |
| 591 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 592 | 450d4ff5 | ths | |
| 593 | 450d4ff5 | ths | {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
|
| 594 | 450d4ff5 | ths | cris_ver_v32p, |
| 595 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 596 | 450d4ff5 | ths | |
| 597 | 450d4ff5 | ths | {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
|
| 598 | 450d4ff5 | ths | cris_ver_v32p, |
| 599 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 600 | 450d4ff5 | ths | |
| 601 | 450d4ff5 | ths | {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
|
| 602 | 450d4ff5 | ths | cris_ver_v32p, |
| 603 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 604 | 450d4ff5 | ths | |
| 605 | 450d4ff5 | ths | {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
|
| 606 | 450d4ff5 | ths | cris_ver_v32p, |
| 607 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 608 | 450d4ff5 | ths | |
| 609 | 450d4ff5 | ths | {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
|
| 610 | 450d4ff5 | ths | cris_ver_v32p, |
| 611 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 612 | 450d4ff5 | ths | |
| 613 | 450d4ff5 | ths | {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
|
| 614 | 450d4ff5 | ths | cris_ver_v32p, |
| 615 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 616 | 450d4ff5 | ths | |
| 617 | 450d4ff5 | ths | {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
|
| 618 | 450d4ff5 | ths | cris_ver_v32p, |
| 619 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 620 | 450d4ff5 | ths | |
| 621 | 450d4ff5 | ths | {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
|
| 622 | 450d4ff5 | ths | cris_ver_v32p, |
| 623 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 624 | 450d4ff5 | ths | |
| 625 | 450d4ff5 | ths | {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
|
| 626 | 450d4ff5 | ths | cris_ver_v8_10, |
| 627 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 628 | 450d4ff5 | ths | |
| 629 | 450d4ff5 | ths | {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
|
| 630 | 450d4ff5 | ths | cris_ver_v8_10, |
| 631 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 632 | 450d4ff5 | ths | |
| 633 | 450d4ff5 | ths | {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
|
| 634 | 450d4ff5 | ths | cris_ver_v8_10, |
| 635 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 636 | 450d4ff5 | ths | |
| 637 | 450d4ff5 | ths | {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
|
| 638 | 450d4ff5 | ths | cris_ver_v8_10, |
| 639 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 640 | 450d4ff5 | ths | |
| 641 | 450d4ff5 | ths | {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
|
| 642 | 450d4ff5 | ths | cris_ver_v8_10, |
| 643 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 644 | 450d4ff5 | ths | |
| 645 | 450d4ff5 | ths | {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
|
| 646 | 450d4ff5 | ths | cris_ver_v8_10, |
| 647 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 648 | 450d4ff5 | ths | |
| 649 | 450d4ff5 | ths | {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
|
| 650 | 450d4ff5 | ths | cris_ver_v8_10, |
| 651 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 652 | 450d4ff5 | ths | |
| 653 | 450d4ff5 | ths | {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
|
| 654 | 450d4ff5 | ths | cris_ver_v8_10, |
| 655 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 656 | 450d4ff5 | ths | |
| 657 | 450d4ff5 | ths | {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
|
| 658 | 450d4ff5 | ths | cris_ver_v8_10, |
| 659 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 660 | 450d4ff5 | ths | |
| 661 | 450d4ff5 | ths | {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
|
| 662 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 663 | 450d4ff5 | ths | |
| 664 | 450d4ff5 | ths | {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
|
| 665 | 450d4ff5 | ths | cris_ver_v0_10, |
| 666 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 667 | 450d4ff5 | ths | |
| 668 | 450d4ff5 | ths | {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
|
| 669 | 450d4ff5 | ths | cris_ver_v32p, |
| 670 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 671 | 450d4ff5 | ths | |
| 672 | 450d4ff5 | ths | {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
|
| 673 | 450d4ff5 | ths | cris_ver_v0_10, |
| 674 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 675 | 450d4ff5 | ths | |
| 676 | 450d4ff5 | ths | {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
|
| 677 | 450d4ff5 | ths | cris_ver_v8_10, |
| 678 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 679 | 450d4ff5 | ths | |
| 680 | 450d4ff5 | ths | {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
|
| 681 | 450d4ff5 | ths | cris_ver_v8_10, |
| 682 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 683 | 450d4ff5 | ths | |
| 684 | 450d4ff5 | ths | {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
|
| 685 | 450d4ff5 | ths | cris_ver_v8_10, |
| 686 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 687 | 450d4ff5 | ths | |
| 688 | 450d4ff5 | ths | {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
|
| 689 | 450d4ff5 | ths | cris_ver_v32p, |
| 690 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 691 | 450d4ff5 | ths | |
| 692 | 450d4ff5 | ths | {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
|
| 693 | 450d4ff5 | ths | cris_ver_v32p, |
| 694 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 695 | 450d4ff5 | ths | |
| 696 | 450d4ff5 | ths | {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
|
| 697 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
| 698 | 450d4ff5 | ths | |
| 699 | 450d4ff5 | ths | {"jump",
|
| 700 | 450d4ff5 | ths | JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, |
| 701 | 450d4ff5 | ths | cris_ver_v0_10, |
| 702 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 703 | 450d4ff5 | ths | |
| 704 | 450d4ff5 | ths | {"jump",
|
| 705 | 450d4ff5 | ths | JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, |
| 706 | 450d4ff5 | ths | cris_ver_v0_10, |
| 707 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 708 | 450d4ff5 | ths | |
| 709 | 450d4ff5 | ths | {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
|
| 710 | 450d4ff5 | ths | cris_ver_v32p, |
| 711 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 712 | 450d4ff5 | ths | |
| 713 | 450d4ff5 | ths | {"jump",
|
| 714 | 450d4ff5 | ths | JUMP_PC_INCR_OPCODE_V32, |
| 715 | 450d4ff5 | ths | (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, |
| 716 | 450d4ff5 | ths | cris_ver_v32p, |
| 717 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 718 | 450d4ff5 | ths | |
| 719 | 450d4ff5 | ths | {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
|
| 720 | 450d4ff5 | ths | cris_ver_v10, |
| 721 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 722 | 450d4ff5 | ths | |
| 723 | 450d4ff5 | ths | {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
|
| 724 | 450d4ff5 | ths | cris_ver_v10, |
| 725 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
| 726 | 450d4ff5 | ths | |
| 727 | 450d4ff5 | ths | {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
|
| 728 | 450d4ff5 | ths | cris_ver_v32p, |
| 729 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 730 | 450d4ff5 | ths | |
| 731 | 450d4ff5 | ths | {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
|
| 732 | 450d4ff5 | ths | cris_ver_v32p, |
| 733 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 734 | 450d4ff5 | ths | |
| 735 | 450d4ff5 | ths | {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
|
| 736 | 450d4ff5 | ths | cris_ver_v32p, |
| 737 | 450d4ff5 | ths | cris_addi_op}, |
| 738 | 450d4ff5 | ths | |
| 739 | 450d4ff5 | ths | {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
|
| 740 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 741 | 450d4ff5 | ths | |
| 742 | 450d4ff5 | ths | {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
|
| 743 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 744 | 450d4ff5 | ths | |
| 745 | 450d4ff5 | ths | {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
|
| 746 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 747 | 450d4ff5 | ths | |
| 748 | 450d4ff5 | ths | {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
|
| 749 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 750 | 450d4ff5 | ths | |
| 751 | 450d4ff5 | ths | {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
|
| 752 | 450d4ff5 | ths | cris_ver_v3p, |
| 753 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 754 | 450d4ff5 | ths | |
| 755 | 450d4ff5 | ths | {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
|
| 756 | 450d4ff5 | ths | cris_ver_v32p, |
| 757 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 758 | 450d4ff5 | ths | |
| 759 | 450d4ff5 | ths | {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
|
| 760 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 761 | 450d4ff5 | ths | |
| 762 | 450d4ff5 | ths | {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
|
| 763 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 764 | 450d4ff5 | ths | |
| 765 | 450d4ff5 | ths | {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
|
| 766 | 450d4ff5 | ths | cris_ver_v0_10, |
| 767 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 768 | 450d4ff5 | ths | |
| 769 | 450d4ff5 | ths | {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
|
| 770 | 450d4ff5 | ths | cris_move_to_preg_op}, |
| 771 | 450d4ff5 | ths | |
| 772 | 450d4ff5 | ths | {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
|
| 773 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 774 | 450d4ff5 | ths | |
| 775 | 450d4ff5 | ths | {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
|
| 776 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 777 | 450d4ff5 | ths | |
| 778 | 450d4ff5 | ths | {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
|
| 779 | 450d4ff5 | ths | cris_ver_v0_10, |
| 780 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 781 | 450d4ff5 | ths | |
| 782 | 450d4ff5 | ths | {"move",
|
| 783 | 450d4ff5 | ths | MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS, |
| 784 | 450d4ff5 | ths | "s,P", 0, SIZE_SPEC_REG, 0, |
| 785 | 450d4ff5 | ths | cris_move_to_preg_op}, |
| 786 | 450d4ff5 | ths | |
| 787 | 450d4ff5 | ths | {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
|
| 788 | 450d4ff5 | ths | cris_ver_v0_10, |
| 789 | 450d4ff5 | ths | cris_move_to_preg_op}, |
| 790 | 450d4ff5 | ths | |
| 791 | 450d4ff5 | ths | {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
|
| 792 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op}, |
| 793 | 450d4ff5 | ths | |
| 794 | 450d4ff5 | ths | {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
|
| 795 | 450d4ff5 | ths | cris_ver_v0_10, |
| 796 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op}, |
| 797 | 450d4ff5 | ths | |
| 798 | 450d4ff5 | ths | {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
|
| 799 | 450d4ff5 | ths | cris_ver_v32p, |
| 800 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 801 | 450d4ff5 | ths | |
| 802 | 450d4ff5 | ths | {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
|
| 803 | 450d4ff5 | ths | cris_ver_v32p, |
| 804 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 805 | 450d4ff5 | ths | |
| 806 | 450d4ff5 | ths | {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
|
| 807 | 450d4ff5 | ths | cris_move_reg_to_mem_movem_op}, |
| 808 | 450d4ff5 | ths | |
| 809 | 450d4ff5 | ths | {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
|
| 810 | 450d4ff5 | ths | cris_ver_v0_10, |
| 811 | 450d4ff5 | ths | cris_move_reg_to_mem_movem_op}, |
| 812 | 450d4ff5 | ths | |
| 813 | 450d4ff5 | ths | {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
|
| 814 | 450d4ff5 | ths | cris_move_mem_to_reg_movem_op}, |
| 815 | 450d4ff5 | ths | |
| 816 | 450d4ff5 | ths | {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
|
| 817 | 450d4ff5 | ths | cris_ver_v0_10, |
| 818 | 450d4ff5 | ths | cris_move_mem_to_reg_movem_op}, |
| 819 | 450d4ff5 | ths | |
| 820 | 450d4ff5 | ths | {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
|
| 821 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
| 822 | 450d4ff5 | ths | |
| 823 | 450d4ff5 | ths | {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
|
| 824 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 825 | 450d4ff5 | ths | |
| 826 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
|
| 827 | 450d4ff5 | ths | {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
|
| 828 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 829 | 450d4ff5 | ths | |
| 830 | 450d4ff5 | ths | {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
|
| 831 | 450d4ff5 | ths | cris_ver_v0_10, |
| 832 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 833 | 450d4ff5 | ths | |
| 834 | 450d4ff5 | ths | {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
|
| 835 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 836 | 450d4ff5 | ths | |
| 837 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
| 838 | 450d4ff5 | ths | {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
|
| 839 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 840 | 450d4ff5 | ths | |
| 841 | 450d4ff5 | ths | {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
|
| 842 | 450d4ff5 | ths | cris_ver_v0_10, |
| 843 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 844 | 450d4ff5 | ths | |
| 845 | 450d4ff5 | ths | {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
|
| 846 | 450d4ff5 | ths | cris_ver_v0_10, |
| 847 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 848 | 450d4ff5 | ths | |
| 849 | 450d4ff5 | ths | {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
|
| 850 | 450d4ff5 | ths | cris_ver_v10p, |
| 851 | 450d4ff5 | ths | cris_muls_op}, |
| 852 | 450d4ff5 | ths | |
| 853 | 450d4ff5 | ths | {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
|
| 854 | 450d4ff5 | ths | cris_ver_v10p, |
| 855 | 450d4ff5 | ths | cris_mulu_op}, |
| 856 | 450d4ff5 | ths | |
| 857 | 450d4ff5 | ths | {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
|
| 858 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 859 | 450d4ff5 | ths | |
| 860 | 450d4ff5 | ths | {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
|
| 861 | 450d4ff5 | ths | cris_ver_v0_10, |
| 862 | 450d4ff5 | ths | cris_btst_nop_op}, |
| 863 | 450d4ff5 | ths | |
| 864 | 450d4ff5 | ths | {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
|
| 865 | 450d4ff5 | ths | cris_ver_v32p, |
| 866 | 450d4ff5 | ths | cris_btst_nop_op}, |
| 867 | 450d4ff5 | ths | |
| 868 | 450d4ff5 | ths | {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
|
| 869 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
| 870 | 450d4ff5 | ths | |
| 871 | 450d4ff5 | ths | {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
|
| 872 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 873 | 450d4ff5 | ths | |
| 874 | 450d4ff5 | ths | {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
|
| 875 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 876 | 450d4ff5 | ths | |
| 877 | 450d4ff5 | ths | {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
|
| 878 | 450d4ff5 | ths | cris_ver_v0_10, |
| 879 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 880 | 450d4ff5 | ths | |
| 881 | 450d4ff5 | ths | {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
|
| 882 | 450d4ff5 | ths | cris_ver_v0_10, |
| 883 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 884 | 450d4ff5 | ths | |
| 885 | 450d4ff5 | ths | {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
|
| 886 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
| 887 | 450d4ff5 | ths | |
| 888 | 450d4ff5 | ths | {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
|
| 889 | 450d4ff5 | ths | cris_ver_v0_10, |
| 890 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 891 | 450d4ff5 | ths | |
| 892 | 450d4ff5 | ths | {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
|
| 893 | 450d4ff5 | ths | cris_ver_v0_10, |
| 894 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op}, |
| 895 | 450d4ff5 | ths | |
| 896 | 450d4ff5 | ths | {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
|
| 897 | 450d4ff5 | ths | cris_ver_v0_10, |
| 898 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 899 | 450d4ff5 | ths | |
| 900 | 450d4ff5 | ths | {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
|
| 901 | 450d4ff5 | ths | cris_ver_v0_10, |
| 902 | 450d4ff5 | ths | cris_move_to_preg_op}, |
| 903 | 450d4ff5 | ths | |
| 904 | 450d4ff5 | ths | {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
|
| 905 | 450d4ff5 | ths | cris_ver_v10, |
| 906 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 907 | 450d4ff5 | ths | |
| 908 | 450d4ff5 | ths | {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
|
| 909 | 450d4ff5 | ths | cris_ver_v10, |
| 910 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 911 | 450d4ff5 | ths | |
| 912 | 450d4ff5 | ths | {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
|
| 913 | 450d4ff5 | ths | cris_ver_v32p, |
| 914 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 915 | 450d4ff5 | ths | |
| 916 | 450d4ff5 | ths | {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
|
| 917 | 450d4ff5 | ths | cris_ver_v32p, |
| 918 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 919 | 450d4ff5 | ths | |
| 920 | 450d4ff5 | ths | {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
|
| 921 | 450d4ff5 | ths | cris_ver_v32p, |
| 922 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 923 | 450d4ff5 | ths | |
| 924 | 450d4ff5 | ths | {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
|
| 925 | 450d4ff5 | ths | cris_ver_v0_10, |
| 926 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 927 | 450d4ff5 | ths | |
| 928 | 450d4ff5 | ths | {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
|
| 929 | 450d4ff5 | ths | cris_ver_v32p, |
| 930 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 931 | 450d4ff5 | ths | |
| 932 | 450d4ff5 | ths | {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
|
| 933 | 450d4ff5 | ths | cris_ver_v0_10, |
| 934 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 935 | 450d4ff5 | ths | |
| 936 | 450d4ff5 | ths | {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
|
| 937 | 450d4ff5 | ths | cris_ver_v32p, |
| 938 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 939 | 450d4ff5 | ths | |
| 940 | 450d4ff5 | ths | {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
|
| 941 | 450d4ff5 | ths | cris_ver_v0_10, |
| 942 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 943 | 450d4ff5 | ths | |
| 944 | 450d4ff5 | ths | {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
|
| 945 | 450d4ff5 | ths | cris_ver_v32p, |
| 946 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
| 947 | 450d4ff5 | ths | |
| 948 | 450d4ff5 | ths | {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
|
| 949 | 450d4ff5 | ths | cris_ver_v10, |
| 950 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 951 | 450d4ff5 | ths | |
| 952 | 450d4ff5 | ths | {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
|
| 953 | 450d4ff5 | ths | cris_ver_v10, |
| 954 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 955 | 450d4ff5 | ths | |
| 956 | 450d4ff5 | ths | {"sa",
|
| 957 | 450d4ff5 | ths | 0x0530+CC_A*0x1000, |
| 958 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, |
| 959 | 450d4ff5 | ths | cris_scc_op}, |
| 960 | 450d4ff5 | ths | |
| 961 | 450d4ff5 | ths | {"ssb",
|
| 962 | 450d4ff5 | ths | 0x0530+CC_EXT*0x1000, |
| 963 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
| 964 | 450d4ff5 | ths | cris_ver_v32p, |
| 965 | 450d4ff5 | ths | cris_scc_op}, |
| 966 | 450d4ff5 | ths | |
| 967 | 450d4ff5 | ths | {"scc",
|
| 968 | 450d4ff5 | ths | 0x0530+CC_CC*0x1000, |
| 969 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, |
| 970 | 450d4ff5 | ths | cris_scc_op}, |
| 971 | 450d4ff5 | ths | |
| 972 | 450d4ff5 | ths | {"scs",
|
| 973 | 450d4ff5 | ths | 0x0530+CC_CS*0x1000, |
| 974 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 975 | 450d4ff5 | ths | cris_scc_op}, |
| 976 | 450d4ff5 | ths | |
| 977 | 450d4ff5 | ths | {"seq",
|
| 978 | 450d4ff5 | ths | 0x0530+CC_EQ*0x1000, |
| 979 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, |
| 980 | 450d4ff5 | ths | cris_scc_op}, |
| 981 | 450d4ff5 | ths | |
| 982 | 450d4ff5 | ths | {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
|
| 983 | 450d4ff5 | ths | cris_ax_ei_setf_op}, |
| 984 | 450d4ff5 | ths | |
| 985 | 450d4ff5 | ths | {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
|
| 986 | 450d4ff5 | ths | cris_ver_v32p, |
| 987 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 988 | 450d4ff5 | ths | |
| 989 | 450d4ff5 | ths | /* Need to have "swf" in front of "sext" so it is the one displayed in
|
| 990 | 450d4ff5 | ths | disassembly. */
|
| 991 | 450d4ff5 | ths | {"swf",
|
| 992 | 450d4ff5 | ths | 0x0530+CC_EXT*0x1000, |
| 993 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
| 994 | 450d4ff5 | ths | cris_ver_v10, |
| 995 | 450d4ff5 | ths | cris_scc_op}, |
| 996 | 450d4ff5 | ths | |
| 997 | 450d4ff5 | ths | {"sext",
|
| 998 | 450d4ff5 | ths | 0x0530+CC_EXT*0x1000, |
| 999 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
| 1000 | 450d4ff5 | ths | cris_ver_v0_3, |
| 1001 | 450d4ff5 | ths | cris_scc_op}, |
| 1002 | 450d4ff5 | ths | |
| 1003 | 450d4ff5 | ths | {"sge",
|
| 1004 | 450d4ff5 | ths | 0x0530+CC_GE*0x1000, |
| 1005 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1006 | 450d4ff5 | ths | cris_scc_op}, |
| 1007 | 450d4ff5 | ths | |
| 1008 | 450d4ff5 | ths | {"sgt",
|
| 1009 | 450d4ff5 | ths | 0x0530+CC_GT*0x1000, |
| 1010 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1011 | 450d4ff5 | ths | cris_scc_op}, |
| 1012 | 450d4ff5 | ths | |
| 1013 | 450d4ff5 | ths | {"shi",
|
| 1014 | 450d4ff5 | ths | 0x0530+CC_HI*0x1000, |
| 1015 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1016 | 450d4ff5 | ths | cris_scc_op}, |
| 1017 | 450d4ff5 | ths | |
| 1018 | 450d4ff5 | ths | {"shs",
|
| 1019 | 450d4ff5 | ths | 0x0530+CC_HS*0x1000, |
| 1020 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1021 | 450d4ff5 | ths | cris_scc_op}, |
| 1022 | 450d4ff5 | ths | |
| 1023 | 450d4ff5 | ths | {"sle",
|
| 1024 | 450d4ff5 | ths | 0x0530+CC_LE*0x1000, |
| 1025 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1026 | 450d4ff5 | ths | cris_scc_op}, |
| 1027 | 450d4ff5 | ths | |
| 1028 | 450d4ff5 | ths | {"slo",
|
| 1029 | 450d4ff5 | ths | 0x0530+CC_LO*0x1000, |
| 1030 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1031 | 450d4ff5 | ths | cris_scc_op}, |
| 1032 | 450d4ff5 | ths | |
| 1033 | 450d4ff5 | ths | {"sls",
|
| 1034 | 450d4ff5 | ths | 0x0530+CC_LS*0x1000, |
| 1035 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1036 | 450d4ff5 | ths | cris_scc_op}, |
| 1037 | 450d4ff5 | ths | |
| 1038 | 450d4ff5 | ths | {"slt",
|
| 1039 | 450d4ff5 | ths | 0x0530+CC_LT*0x1000, |
| 1040 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1041 | 450d4ff5 | ths | cris_scc_op}, |
| 1042 | 450d4ff5 | ths | |
| 1043 | 450d4ff5 | ths | {"smi",
|
| 1044 | 450d4ff5 | ths | 0x0530+CC_MI*0x1000, |
| 1045 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1046 | 450d4ff5 | ths | cris_scc_op}, |
| 1047 | 450d4ff5 | ths | |
| 1048 | 450d4ff5 | ths | {"sne",
|
| 1049 | 450d4ff5 | ths | 0x0530+CC_NE*0x1000, |
| 1050 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1051 | 450d4ff5 | ths | cris_scc_op}, |
| 1052 | 450d4ff5 | ths | |
| 1053 | 450d4ff5 | ths | {"spl",
|
| 1054 | 450d4ff5 | ths | 0x0530+CC_PL*0x1000, |
| 1055 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1056 | 450d4ff5 | ths | cris_scc_op}, |
| 1057 | 450d4ff5 | ths | |
| 1058 | 450d4ff5 | ths | {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
|
| 1059 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1060 | 450d4ff5 | ths | |
| 1061 | 450d4ff5 | ths | {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
|
| 1062 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1063 | 450d4ff5 | ths | |
| 1064 | 450d4ff5 | ths | {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
|
| 1065 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1066 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1067 | 450d4ff5 | ths | |
| 1068 | 450d4ff5 | ths | {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
|
| 1069 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1070 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 1071 | 450d4ff5 | ths | |
| 1072 | 450d4ff5 | ths | {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
|
| 1073 | 450d4ff5 | ths | cris_quick_mode_add_sub_op}, |
| 1074 | 450d4ff5 | ths | |
| 1075 | 450d4ff5 | ths | {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
|
| 1076 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1077 | 450d4ff5 | ths | |
| 1078 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
|
| 1079 | 450d4ff5 | ths | {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
|
| 1080 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1081 | 450d4ff5 | ths | |
| 1082 | 450d4ff5 | ths | {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
|
| 1083 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1084 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1085 | 450d4ff5 | ths | |
| 1086 | 450d4ff5 | ths | {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
|
| 1087 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1088 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 1089 | 450d4ff5 | ths | |
| 1090 | 450d4ff5 | ths | {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
|
| 1091 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1092 | 450d4ff5 | ths | |
| 1093 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
| 1094 | 450d4ff5 | ths | {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
|
| 1095 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1096 | 450d4ff5 | ths | |
| 1097 | 450d4ff5 | ths | {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
|
| 1098 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1099 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 1100 | 450d4ff5 | ths | |
| 1101 | 450d4ff5 | ths | {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
|
| 1102 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1103 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
| 1104 | 450d4ff5 | ths | |
| 1105 | 450d4ff5 | ths | {"svc",
|
| 1106 | 450d4ff5 | ths | 0x0530+CC_VC*0x1000, |
| 1107 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1108 | 450d4ff5 | ths | cris_scc_op}, |
| 1109 | 450d4ff5 | ths | |
| 1110 | 450d4ff5 | ths | {"svs",
|
| 1111 | 450d4ff5 | ths | 0x0530+CC_VS*0x1000, |
| 1112 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 1113 | 450d4ff5 | ths | cris_scc_op}, |
| 1114 | 450d4ff5 | ths | |
| 1115 | 450d4ff5 | ths | /* The insn "swapn" is the same as "not" and will be disassembled as
|
| 1116 | 450d4ff5 | ths | such, but the swap* family of mnmonics are generally v8-and-higher
|
| 1117 | 450d4ff5 | ths | only, so count it in. */
|
| 1118 | 450d4ff5 | ths | {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
|
| 1119 | 450d4ff5 | ths | cris_ver_v8p, |
| 1120 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1121 | 450d4ff5 | ths | |
| 1122 | 450d4ff5 | ths | {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
|
| 1123 | 450d4ff5 | ths | cris_ver_v8p, |
| 1124 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1125 | 450d4ff5 | ths | |
| 1126 | 450d4ff5 | ths | {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
|
| 1127 | 450d4ff5 | ths | cris_ver_v8p, |
| 1128 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1129 | 450d4ff5 | ths | |
| 1130 | 450d4ff5 | ths | {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
|
| 1131 | 450d4ff5 | ths | cris_ver_v8p, |
| 1132 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1133 | 450d4ff5 | ths | |
| 1134 | 450d4ff5 | ths | {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
|
| 1135 | 450d4ff5 | ths | cris_ver_v8p, |
| 1136 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1137 | 450d4ff5 | ths | |
| 1138 | 450d4ff5 | ths | {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
|
| 1139 | 450d4ff5 | ths | cris_ver_v8p, |
| 1140 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1141 | 450d4ff5 | ths | |
| 1142 | 450d4ff5 | ths | {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
|
| 1143 | 450d4ff5 | ths | cris_ver_v8p, |
| 1144 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1145 | 450d4ff5 | ths | |
| 1146 | 450d4ff5 | ths | {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
|
| 1147 | 450d4ff5 | ths | cris_ver_v8p, |
| 1148 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1149 | 450d4ff5 | ths | |
| 1150 | 450d4ff5 | ths | {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
|
| 1151 | 450d4ff5 | ths | cris_ver_v8p, |
| 1152 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1153 | 450d4ff5 | ths | |
| 1154 | 450d4ff5 | ths | {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
|
| 1155 | 450d4ff5 | ths | cris_ver_v8p, |
| 1156 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1157 | 450d4ff5 | ths | |
| 1158 | 450d4ff5 | ths | {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
|
| 1159 | 450d4ff5 | ths | cris_ver_v8p, |
| 1160 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1161 | 450d4ff5 | ths | |
| 1162 | 450d4ff5 | ths | {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
|
| 1163 | 450d4ff5 | ths | cris_ver_v8p, |
| 1164 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1165 | 450d4ff5 | ths | |
| 1166 | 450d4ff5 | ths | {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
|
| 1167 | 450d4ff5 | ths | cris_ver_v8p, |
| 1168 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1169 | 450d4ff5 | ths | |
| 1170 | 450d4ff5 | ths | {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
|
| 1171 | 450d4ff5 | ths | cris_ver_v8p, |
| 1172 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1173 | 450d4ff5 | ths | |
| 1174 | 450d4ff5 | ths | {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
|
| 1175 | 450d4ff5 | ths | cris_ver_v8p, |
| 1176 | 450d4ff5 | ths | cris_not_implemented_op}, |
| 1177 | 450d4ff5 | ths | |
| 1178 | 450d4ff5 | ths | {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
|
| 1179 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1180 | 450d4ff5 | ths | cris_reg_mode_test_op}, |
| 1181 | 450d4ff5 | ths | |
| 1182 | 450d4ff5 | ths | {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
|
| 1183 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
| 1184 | 450d4ff5 | ths | |
| 1185 | 450d4ff5 | ths | {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
|
| 1186 | 450d4ff5 | ths | cris_ver_v0_10, |
| 1187 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
| 1188 | 450d4ff5 | ths | |
| 1189 | 450d4ff5 | ths | {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
|
| 1190 | 450d4ff5 | ths | cris_xor_op}, |
| 1191 | 450d4ff5 | ths | |
| 1192 | 450d4ff5 | ths | {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
|
| 1193 | 450d4ff5 | ths | }; |
| 1194 | 450d4ff5 | ths | |
| 1195 | 450d4ff5 | ths | /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
|
| 1196 | 450d4ff5 | ths | const char * const |
| 1197 | 450d4ff5 | ths | cris_cc_strings[] = |
| 1198 | 450d4ff5 | ths | {
|
| 1199 | 450d4ff5 | ths | "hs",
|
| 1200 | 450d4ff5 | ths | "lo",
|
| 1201 | 450d4ff5 | ths | "ne",
|
| 1202 | 450d4ff5 | ths | "eq",
|
| 1203 | 450d4ff5 | ths | "vc",
|
| 1204 | 450d4ff5 | ths | "vs",
|
| 1205 | 450d4ff5 | ths | "pl",
|
| 1206 | 450d4ff5 | ths | "mi",
|
| 1207 | 450d4ff5 | ths | "ls",
|
| 1208 | 450d4ff5 | ths | "hi",
|
| 1209 | 450d4ff5 | ths | "ge",
|
| 1210 | 450d4ff5 | ths | "lt",
|
| 1211 | 450d4ff5 | ths | "gt",
|
| 1212 | 450d4ff5 | ths | "le",
|
| 1213 | 450d4ff5 | ths | "a",
|
| 1214 | 450d4ff5 | ths | /* This is a placeholder. In v0, this would be "ext". In v32, this
|
| 1215 | 450d4ff5 | ths | is "sb". See cris_conds15. */
|
| 1216 | 450d4ff5 | ths | "wf"
|
| 1217 | 450d4ff5 | ths | }; |
| 1218 | 450d4ff5 | ths | |
| 1219 | 450d4ff5 | ths | /* Different names and semantics for condition 1111 (0xf). */
|
| 1220 | 450d4ff5 | ths | const struct cris_cond15 cris_cond15s[] = |
| 1221 | 450d4ff5 | ths | {
|
| 1222 | 450d4ff5 | ths | /* FIXME: In what version did condition "ext" disappear? */
|
| 1223 | 450d4ff5 | ths | {"ext", cris_ver_v0_3},
|
| 1224 | 450d4ff5 | ths | {"wf", cris_ver_v10},
|
| 1225 | 450d4ff5 | ths | {"sb", cris_ver_v32p},
|
| 1226 | 450d4ff5 | ths | {NULL, 0}
|
| 1227 | 450d4ff5 | ths | }; |
| 1228 | 450d4ff5 | ths | |
| 1229 | 450d4ff5 | ths | |
| 1230 | 450d4ff5 | ths | /*
|
| 1231 | 450d4ff5 | ths | * Local variables:
|
| 1232 | 450d4ff5 | ths | * eval: (c-set-style "gnu")
|
| 1233 | 450d4ff5 | ths | * indent-tabs-mode: t
|
| 1234 | 450d4ff5 | ths | * End:
|
| 1235 | 450d4ff5 | ths | */
|
| 1236 | 450d4ff5 | ths | |
| 1237 | 450d4ff5 | ths | |
| 1238 | 450d4ff5 | ths | /* No instruction will be disassembled longer than this. In theory, and
|
| 1239 | 450d4ff5 | ths | in silicon, address prefixes can be cascaded. In practice, cascading
|
| 1240 | 450d4ff5 | ths | is not used by GCC, and not supported by the assembler. */
|
| 1241 | 450d4ff5 | ths | #ifndef MAX_BYTES_PER_CRIS_INSN
|
| 1242 | 450d4ff5 | ths | #define MAX_BYTES_PER_CRIS_INSN 8 |
| 1243 | 450d4ff5 | ths | #endif
|
| 1244 | 450d4ff5 | ths | |
| 1245 | 450d4ff5 | ths | /* Whether or not to decode prefixes, folding it into the following
|
| 1246 | 450d4ff5 | ths | instruction. FIXME: Make this optional later. */
|
| 1247 | 450d4ff5 | ths | #ifndef PARSE_PREFIX
|
| 1248 | 450d4ff5 | ths | #define PARSE_PREFIX 1 |
| 1249 | 450d4ff5 | ths | #endif
|
| 1250 | 450d4ff5 | ths | |
| 1251 | 450d4ff5 | ths | /* Sometimes we prefix all registers with this character. */
|
| 1252 | 450d4ff5 | ths | #define REGISTER_PREFIX_CHAR '$' |
| 1253 | 450d4ff5 | ths | |
| 1254 | 450d4ff5 | ths | /* Whether or not to trace the following sequence:
|
| 1255 | 450d4ff5 | ths | sub* X,r%d
|
| 1256 | 450d4ff5 | ths | bound* Y,r%d
|
| 1257 | 450d4ff5 | ths | adds.w [pc+r%d.w],pc
|
| 1258 | 450d4ff5 | ths | |
| 1259 | 450d4ff5 | ths | This is the assembly form of a switch-statement in C.
|
| 1260 | 450d4ff5 | ths | The "sub is optional. If there is none, then X will be zero.
|
| 1261 | 450d4ff5 | ths | X is the value of the first case,
|
| 1262 | 450d4ff5 | ths | Y is the number of cases (including default).
|
| 1263 | 450d4ff5 | ths | |
| 1264 | 450d4ff5 | ths | This results in case offsets printed on the form:
|
| 1265 | 450d4ff5 | ths | case N: -> case_address
|
| 1266 | 450d4ff5 | ths | where N is an estimation on the corresponding 'case' operand in C,
|
| 1267 | 450d4ff5 | ths | and case_address is where execution of that case continues after the
|
| 1268 | 450d4ff5 | ths | sequence presented above.
|
| 1269 | 450d4ff5 | ths | |
| 1270 | 450d4ff5 | ths | The old style of output was to print the offsets as instructions,
|
| 1271 | 450d4ff5 | ths | which made it hard to follow "case"-constructs in the disassembly,
|
| 1272 | 450d4ff5 | ths | and caused a lot of annoying warnings about undefined instructions.
|
| 1273 | 450d4ff5 | ths | |
| 1274 | 450d4ff5 | ths | FIXME: Make this optional later. */
|
| 1275 | 450d4ff5 | ths | #ifndef TRACE_CASE
|
| 1276 | 450d4ff5 | ths | #define TRACE_CASE (disdata->trace_case)
|
| 1277 | 450d4ff5 | ths | #endif
|
| 1278 | 450d4ff5 | ths | |
| 1279 | 450d4ff5 | ths | enum cris_disass_family
|
| 1280 | 450d4ff5 | ths | { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
|
| 1281 | 450d4ff5 | ths | |
| 1282 | 450d4ff5 | ths | /* Stored in the disasm_info->private_data member. */
|
| 1283 | 450d4ff5 | ths | struct cris_disasm_data
|
| 1284 | 450d4ff5 | ths | {
|
| 1285 | 450d4ff5 | ths | /* Whether to print something less confusing if we find something
|
| 1286 | 450d4ff5 | ths | matching a switch-construct. */
|
| 1287 | 450d4ff5 | ths | bfd_boolean trace_case; |
| 1288 | 450d4ff5 | ths | |
| 1289 | 450d4ff5 | ths | /* Whether this code is flagged as crisv32. FIXME: Should be an enum
|
| 1290 | 450d4ff5 | ths | that includes "compatible". */
|
| 1291 | 450d4ff5 | ths | enum cris_disass_family distype;
|
| 1292 | 450d4ff5 | ths | }; |
| 1293 | 450d4ff5 | ths | |
| 1294 | 450d4ff5 | ths | /* Value of first element in switch. */
|
| 1295 | 450d4ff5 | ths | static long case_offset = 0; |
| 1296 | 450d4ff5 | ths | |
| 1297 | 450d4ff5 | ths | /* How many more case-offsets to print. */
|
| 1298 | 450d4ff5 | ths | static long case_offset_counter = 0; |
| 1299 | 450d4ff5 | ths | |
| 1300 | 450d4ff5 | ths | /* Number of case offsets. */
|
| 1301 | 450d4ff5 | ths | static long no_of_case_offsets = 0; |
| 1302 | 450d4ff5 | ths | |
| 1303 | 450d4ff5 | ths | /* Candidate for next case_offset. */
|
| 1304 | 450d4ff5 | ths | static long last_immediate = 0; |
| 1305 | 450d4ff5 | ths | |
| 1306 | 450d4ff5 | ths | static int cris_constraint |
| 1307 | 450d4ff5 | ths | (const char *, unsigned, unsigned, struct cris_disasm_data *); |
| 1308 | 450d4ff5 | ths | |
| 1309 | 450d4ff5 | ths | /* Parse disassembler options and store state in info. FIXME: For the
|
| 1310 | 450d4ff5 | ths | time being, we abuse static variables. */
|
| 1311 | 450d4ff5 | ths | |
| 1312 | 450d4ff5 | ths | static bfd_boolean
|
| 1313 | 450d4ff5 | ths | cris_parse_disassembler_options (disassemble_info *info, |
| 1314 | 450d4ff5 | ths | enum cris_disass_family distype)
|
| 1315 | 450d4ff5 | ths | {
|
| 1316 | 450d4ff5 | ths | struct cris_disasm_data *disdata;
|
| 1317 | 450d4ff5 | ths | |
| 1318 | 450d4ff5 | ths | info->private_data = calloc (1, sizeof (struct cris_disasm_data)); |
| 1319 | 450d4ff5 | ths | disdata = (struct cris_disasm_data *) info->private_data;
|
| 1320 | 450d4ff5 | ths | if (disdata == NULL) |
| 1321 | 47cbc7aa | Juan Quintela | return false; |
| 1322 | 450d4ff5 | ths | |
| 1323 | 450d4ff5 | ths | /* Default true. */
|
| 1324 | 450d4ff5 | ths | disdata->trace_case |
| 1325 | 450d4ff5 | ths | = (info->disassembler_options == NULL
|
| 1326 | 450d4ff5 | ths | || (strcmp (info->disassembler_options, "nocase") != 0)); |
| 1327 | 450d4ff5 | ths | |
| 1328 | 450d4ff5 | ths | disdata->distype = distype; |
| 1329 | 47cbc7aa | Juan Quintela | return true; |
| 1330 | 450d4ff5 | ths | } |
| 1331 | 450d4ff5 | ths | |
| 1332 | 450d4ff5 | ths | static const struct cris_spec_reg * |
| 1333 | 450d4ff5 | ths | spec_reg_info (unsigned int sreg, enum cris_disass_family distype) |
| 1334 | 450d4ff5 | ths | {
|
| 1335 | 450d4ff5 | ths | int i;
|
| 1336 | 450d4ff5 | ths | |
| 1337 | 450d4ff5 | ths | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1338 | 450d4ff5 | ths | {
|
| 1339 | 450d4ff5 | ths | if (cris_spec_regs[i].number == sreg)
|
| 1340 | 450d4ff5 | ths | {
|
| 1341 | 450d4ff5 | ths | if (distype == cris_dis_v32)
|
| 1342 | 450d4ff5 | ths | switch (cris_spec_regs[i].applicable_version)
|
| 1343 | 450d4ff5 | ths | {
|
| 1344 | 450d4ff5 | ths | case cris_ver_warning:
|
| 1345 | 450d4ff5 | ths | case cris_ver_version_all:
|
| 1346 | 450d4ff5 | ths | case cris_ver_v3p:
|
| 1347 | 450d4ff5 | ths | case cris_ver_v8p:
|
| 1348 | 450d4ff5 | ths | case cris_ver_v10p:
|
| 1349 | 450d4ff5 | ths | case cris_ver_v32p:
|
| 1350 | 450d4ff5 | ths | /* No ambiguous sizes or register names with CRISv32. */
|
| 1351 | 450d4ff5 | ths | if (cris_spec_regs[i].warning == NULL) |
| 1352 | 450d4ff5 | ths | return &cris_spec_regs[i];
|
| 1353 | 450d4ff5 | ths | default:
|
| 1354 | 450d4ff5 | ths | ; |
| 1355 | 450d4ff5 | ths | } |
| 1356 | 450d4ff5 | ths | else if (cris_spec_regs[i].applicable_version != cris_ver_v32p) |
| 1357 | 450d4ff5 | ths | return &cris_spec_regs[i];
|
| 1358 | 450d4ff5 | ths | } |
| 1359 | 450d4ff5 | ths | } |
| 1360 | 450d4ff5 | ths | |
| 1361 | 450d4ff5 | ths | return NULL; |
| 1362 | 450d4ff5 | ths | } |
| 1363 | 450d4ff5 | ths | |
| 1364 | 450d4ff5 | ths | /* Return the number of bits in the argument. */
|
| 1365 | 450d4ff5 | ths | |
| 1366 | 450d4ff5 | ths | static int |
| 1367 | 450d4ff5 | ths | number_of_bits (unsigned int val) |
| 1368 | 450d4ff5 | ths | {
|
| 1369 | 450d4ff5 | ths | int bits;
|
| 1370 | 450d4ff5 | ths | |
| 1371 | 450d4ff5 | ths | for (bits = 0; val != 0; val &= val - 1) |
| 1372 | 450d4ff5 | ths | bits++; |
| 1373 | 450d4ff5 | ths | |
| 1374 | 450d4ff5 | ths | return bits;
|
| 1375 | 450d4ff5 | ths | } |
| 1376 | 450d4ff5 | ths | |
| 1377 | 450d4ff5 | ths | /* Get an entry in the opcode-table. */
|
| 1378 | 450d4ff5 | ths | |
| 1379 | 450d4ff5 | ths | static const struct cris_opcode * |
| 1380 | 450d4ff5 | ths | get_opcode_entry (unsigned int insn, |
| 1381 | 450d4ff5 | ths | unsigned int prefix_insn, |
| 1382 | 450d4ff5 | ths | struct cris_disasm_data *disdata)
|
| 1383 | 450d4ff5 | ths | {
|
| 1384 | 450d4ff5 | ths | /* For non-prefixed insns, we keep a table of pointers, indexed by the
|
| 1385 | 450d4ff5 | ths | insn code. Each entry is initialized when found to be NULL. */
|
| 1386 | 450d4ff5 | ths | static const struct cris_opcode **opc_table = NULL; |
| 1387 | 450d4ff5 | ths | |
| 1388 | 450d4ff5 | ths | const struct cris_opcode *max_matchedp = NULL; |
| 1389 | 450d4ff5 | ths | const struct cris_opcode **prefix_opc_table = NULL; |
| 1390 | 450d4ff5 | ths | |
| 1391 | 450d4ff5 | ths | /* We hold a table for each prefix that need to be handled differently. */
|
| 1392 | 450d4ff5 | ths | static const struct cris_opcode **dip_prefixes = NULL; |
| 1393 | 450d4ff5 | ths | static const struct cris_opcode **bdapq_m1_prefixes = NULL; |
| 1394 | 450d4ff5 | ths | static const struct cris_opcode **bdapq_m2_prefixes = NULL; |
| 1395 | 450d4ff5 | ths | static const struct cris_opcode **bdapq_m4_prefixes = NULL; |
| 1396 | 450d4ff5 | ths | static const struct cris_opcode **rest_prefixes = NULL; |
| 1397 | 450d4ff5 | ths | |
| 1398 | 450d4ff5 | ths | /* Allocate and clear the opcode-table. */
|
| 1399 | 450d4ff5 | ths | if (opc_table == NULL) |
| 1400 | 450d4ff5 | ths | {
|
| 1401 | 1eec614b | aliguori | opc_table = qemu_malloc (65536 * sizeof (opc_table[0])); |
| 1402 | 450d4ff5 | ths | |
| 1403 | 450d4ff5 | ths | memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *)); |
| 1404 | 450d4ff5 | ths | |
| 1405 | 450d4ff5 | ths | dip_prefixes |
| 1406 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
| 1407 | 450d4ff5 | ths | |
| 1408 | 450d4ff5 | ths | memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0])); |
| 1409 | 450d4ff5 | ths | |
| 1410 | 450d4ff5 | ths | bdapq_m1_prefixes |
| 1411 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
| 1412 | 450d4ff5 | ths | |
| 1413 | 450d4ff5 | ths | memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0])); |
| 1414 | 450d4ff5 | ths | |
| 1415 | 450d4ff5 | ths | bdapq_m2_prefixes |
| 1416 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
| 1417 | 450d4ff5 | ths | |
| 1418 | 450d4ff5 | ths | memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0])); |
| 1419 | 450d4ff5 | ths | |
| 1420 | 450d4ff5 | ths | bdapq_m4_prefixes |
| 1421 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
| 1422 | 450d4ff5 | ths | |
| 1423 | 450d4ff5 | ths | memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0])); |
| 1424 | 450d4ff5 | ths | |
| 1425 | 450d4ff5 | ths | rest_prefixes |
| 1426 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
| 1427 | 450d4ff5 | ths | |
| 1428 | 450d4ff5 | ths | memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0])); |
| 1429 | 450d4ff5 | ths | } |
| 1430 | 450d4ff5 | ths | |
| 1431 | 450d4ff5 | ths | /* Get the right table if this is a prefix.
|
| 1432 | 450d4ff5 | ths | This code is connected to cris_constraints in that it knows what
|
| 1433 | 450d4ff5 | ths | prefixes play a role in recognition of patterns; the necessary
|
| 1434 | 450d4ff5 | ths | state is reflected by which table is used. If constraints
|
| 1435 | 450d4ff5 | ths | involving match or non-match of prefix insns are changed, then this
|
| 1436 | 450d4ff5 | ths | probably needs changing too. */
|
| 1437 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX)
|
| 1438 | 450d4ff5 | ths | {
|
| 1439 | 450d4ff5 | ths | const struct cris_opcode *popcodep |
| 1440 | 450d4ff5 | ths | = (opc_table[prefix_insn] != NULL
|
| 1441 | 450d4ff5 | ths | ? opc_table[prefix_insn] |
| 1442 | 450d4ff5 | ths | : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); |
| 1443 | 450d4ff5 | ths | |
| 1444 | 450d4ff5 | ths | if (popcodep == NULL) |
| 1445 | 450d4ff5 | ths | return NULL; |
| 1446 | 450d4ff5 | ths | |
| 1447 | 450d4ff5 | ths | if (popcodep->match == BDAP_QUICK_OPCODE)
|
| 1448 | 450d4ff5 | ths | {
|
| 1449 | 450d4ff5 | ths | /* Since some offsets are recognized with "push" macros, we
|
| 1450 | 450d4ff5 | ths | have to have different tables for them. */
|
| 1451 | 450d4ff5 | ths | int offset = (prefix_insn & 255); |
| 1452 | 450d4ff5 | ths | |
| 1453 | 450d4ff5 | ths | if (offset > 127) |
| 1454 | 450d4ff5 | ths | offset -= 256;
|
| 1455 | 450d4ff5 | ths | |
| 1456 | 450d4ff5 | ths | switch (offset)
|
| 1457 | 450d4ff5 | ths | {
|
| 1458 | 450d4ff5 | ths | case -4: |
| 1459 | 450d4ff5 | ths | prefix_opc_table = bdapq_m4_prefixes; |
| 1460 | 450d4ff5 | ths | break;
|
| 1461 | 450d4ff5 | ths | |
| 1462 | 450d4ff5 | ths | case -2: |
| 1463 | 450d4ff5 | ths | prefix_opc_table = bdapq_m2_prefixes; |
| 1464 | 450d4ff5 | ths | break;
|
| 1465 | 450d4ff5 | ths | |
| 1466 | 450d4ff5 | ths | case -1: |
| 1467 | 450d4ff5 | ths | prefix_opc_table = bdapq_m1_prefixes; |
| 1468 | 450d4ff5 | ths | break;
|
| 1469 | 450d4ff5 | ths | |
| 1470 | 450d4ff5 | ths | default:
|
| 1471 | 450d4ff5 | ths | prefix_opc_table = rest_prefixes; |
| 1472 | 450d4ff5 | ths | break;
|
| 1473 | 450d4ff5 | ths | } |
| 1474 | 450d4ff5 | ths | } |
| 1475 | 450d4ff5 | ths | else if (popcodep->match == DIP_OPCODE) |
| 1476 | 450d4ff5 | ths | /* We don't allow postincrement when the prefix is DIP, so use a
|
| 1477 | 450d4ff5 | ths | different table for DIP. */
|
| 1478 | 450d4ff5 | ths | prefix_opc_table = dip_prefixes; |
| 1479 | 450d4ff5 | ths | else
|
| 1480 | 450d4ff5 | ths | prefix_opc_table = rest_prefixes; |
| 1481 | 450d4ff5 | ths | } |
| 1482 | 450d4ff5 | ths | |
| 1483 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX
|
| 1484 | 450d4ff5 | ths | && prefix_opc_table[insn] != NULL)
|
| 1485 | 450d4ff5 | ths | max_matchedp = prefix_opc_table[insn]; |
| 1486 | 450d4ff5 | ths | else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) |
| 1487 | 450d4ff5 | ths | max_matchedp = opc_table[insn]; |
| 1488 | 450d4ff5 | ths | else
|
| 1489 | 450d4ff5 | ths | {
|
| 1490 | 450d4ff5 | ths | const struct cris_opcode *opcodep; |
| 1491 | 450d4ff5 | ths | int max_level_of_match = -1; |
| 1492 | 450d4ff5 | ths | |
| 1493 | 450d4ff5 | ths | for (opcodep = cris_opcodes;
|
| 1494 | 450d4ff5 | ths | opcodep->name != NULL;
|
| 1495 | 450d4ff5 | ths | opcodep++) |
| 1496 | 450d4ff5 | ths | {
|
| 1497 | 450d4ff5 | ths | int level_of_match;
|
| 1498 | 450d4ff5 | ths | |
| 1499 | 450d4ff5 | ths | if (disdata->distype == cris_dis_v32)
|
| 1500 | 450d4ff5 | ths | {
|
| 1501 | 450d4ff5 | ths | switch (opcodep->applicable_version)
|
| 1502 | 450d4ff5 | ths | {
|
| 1503 | 450d4ff5 | ths | case cris_ver_version_all:
|
| 1504 | 450d4ff5 | ths | break;
|
| 1505 | 450d4ff5 | ths | |
| 1506 | 450d4ff5 | ths | case cris_ver_v0_3:
|
| 1507 | 450d4ff5 | ths | case cris_ver_v0_10:
|
| 1508 | 450d4ff5 | ths | case cris_ver_v3_10:
|
| 1509 | 450d4ff5 | ths | case cris_ver_sim_v0_10:
|
| 1510 | 450d4ff5 | ths | case cris_ver_v8_10:
|
| 1511 | 450d4ff5 | ths | case cris_ver_v10:
|
| 1512 | 450d4ff5 | ths | case cris_ver_warning:
|
| 1513 | 450d4ff5 | ths | continue;
|
| 1514 | 450d4ff5 | ths | |
| 1515 | 450d4ff5 | ths | case cris_ver_v3p:
|
| 1516 | 450d4ff5 | ths | case cris_ver_v8p:
|
| 1517 | 450d4ff5 | ths | case cris_ver_v10p:
|
| 1518 | 450d4ff5 | ths | case cris_ver_v32p:
|
| 1519 | 450d4ff5 | ths | break;
|
| 1520 | 450d4ff5 | ths | |
| 1521 | 450d4ff5 | ths | case cris_ver_v8:
|
| 1522 | 450d4ff5 | ths | abort (); |
| 1523 | 450d4ff5 | ths | default:
|
| 1524 | 450d4ff5 | ths | abort (); |
| 1525 | 450d4ff5 | ths | } |
| 1526 | 450d4ff5 | ths | } |
| 1527 | 450d4ff5 | ths | else
|
| 1528 | 450d4ff5 | ths | {
|
| 1529 | 450d4ff5 | ths | switch (opcodep->applicable_version)
|
| 1530 | 450d4ff5 | ths | {
|
| 1531 | 450d4ff5 | ths | case cris_ver_version_all:
|
| 1532 | 450d4ff5 | ths | case cris_ver_v0_3:
|
| 1533 | 450d4ff5 | ths | case cris_ver_v3p:
|
| 1534 | 450d4ff5 | ths | case cris_ver_v0_10:
|
| 1535 | 450d4ff5 | ths | case cris_ver_v8p:
|
| 1536 | 450d4ff5 | ths | case cris_ver_v8_10:
|
| 1537 | 450d4ff5 | ths | case cris_ver_v10:
|
| 1538 | 450d4ff5 | ths | case cris_ver_sim_v0_10:
|
| 1539 | 450d4ff5 | ths | case cris_ver_v10p:
|
| 1540 | 450d4ff5 | ths | case cris_ver_warning:
|
| 1541 | 450d4ff5 | ths | break;
|
| 1542 | 450d4ff5 | ths | |
| 1543 | 450d4ff5 | ths | case cris_ver_v32p:
|
| 1544 | 450d4ff5 | ths | continue;
|
| 1545 | 450d4ff5 | ths | |
| 1546 | 450d4ff5 | ths | case cris_ver_v8:
|
| 1547 | 450d4ff5 | ths | abort (); |
| 1548 | 450d4ff5 | ths | default:
|
| 1549 | 450d4ff5 | ths | abort (); |
| 1550 | 450d4ff5 | ths | } |
| 1551 | 450d4ff5 | ths | } |
| 1552 | 450d4ff5 | ths | |
| 1553 | 450d4ff5 | ths | /* We give a double lead for bits matching the template in
|
| 1554 | 450d4ff5 | ths | cris_opcodes. Not even, because then "move p8,r10" would
|
| 1555 | 450d4ff5 | ths | be given 2 bits lead over "clear.d r10". When there's a
|
| 1556 | 450d4ff5 | ths | tie, the first entry in the table wins. This is
|
| 1557 | 450d4ff5 | ths | deliberate, to avoid a more complicated recognition
|
| 1558 | 450d4ff5 | ths | formula. */
|
| 1559 | 450d4ff5 | ths | if ((opcodep->match & insn) == opcodep->match
|
| 1560 | 450d4ff5 | ths | && (opcodep->lose & insn) == 0
|
| 1561 | 450d4ff5 | ths | && ((level_of_match |
| 1562 | 450d4ff5 | ths | = cris_constraint (opcodep->args, |
| 1563 | 450d4ff5 | ths | insn, |
| 1564 | 450d4ff5 | ths | prefix_insn, |
| 1565 | 450d4ff5 | ths | disdata)) |
| 1566 | 450d4ff5 | ths | >= 0)
|
| 1567 | 450d4ff5 | ths | && ((level_of_match |
| 1568 | 450d4ff5 | ths | += 2 * number_of_bits (opcodep->match
|
| 1569 | 450d4ff5 | ths | | opcodep->lose)) |
| 1570 | 450d4ff5 | ths | > max_level_of_match)) |
| 1571 | 450d4ff5 | ths | {
|
| 1572 | 450d4ff5 | ths | max_matchedp = opcodep; |
| 1573 | 450d4ff5 | ths | max_level_of_match = level_of_match; |
| 1574 | 450d4ff5 | ths | |
| 1575 | 450d4ff5 | ths | /* If there was a full match, never mind looking
|
| 1576 | 450d4ff5 | ths | further. */
|
| 1577 | 450d4ff5 | ths | if (level_of_match >= 2 * 16) |
| 1578 | 450d4ff5 | ths | break;
|
| 1579 | 450d4ff5 | ths | } |
| 1580 | 450d4ff5 | ths | } |
| 1581 | 450d4ff5 | ths | /* Fill in the new entry.
|
| 1582 | 450d4ff5 | ths | |
| 1583 | 450d4ff5 | ths | If there are changes to the opcode-table involving prefixes, and
|
| 1584 | 450d4ff5 | ths | disassembly then does not work correctly, try removing the
|
| 1585 | 450d4ff5 | ths | else-clause below that fills in the prefix-table. If that
|
| 1586 | 450d4ff5 | ths | helps, you need to change the prefix_opc_table setting above, or
|
| 1587 | 450d4ff5 | ths | something related. */
|
| 1588 | 450d4ff5 | ths | if (prefix_insn == NO_CRIS_PREFIX)
|
| 1589 | 450d4ff5 | ths | opc_table[insn] = max_matchedp; |
| 1590 | 450d4ff5 | ths | else
|
| 1591 | 450d4ff5 | ths | prefix_opc_table[insn] = max_matchedp; |
| 1592 | 450d4ff5 | ths | } |
| 1593 | 450d4ff5 | ths | |
| 1594 | 450d4ff5 | ths | return max_matchedp;
|
| 1595 | 450d4ff5 | ths | } |
| 1596 | 450d4ff5 | ths | |
| 1597 | 450d4ff5 | ths | /* Return -1 if the constraints of a bitwise-matched instruction say
|
| 1598 | 450d4ff5 | ths | that there is no match. Otherwise return a nonnegative number
|
| 1599 | 450d4ff5 | ths | indicating the confidence in the match (higher is better). */
|
| 1600 | 450d4ff5 | ths | |
| 1601 | 450d4ff5 | ths | static int |
| 1602 | 450d4ff5 | ths | cris_constraint (const char *cs, |
| 1603 | 450d4ff5 | ths | unsigned int insn, |
| 1604 | 450d4ff5 | ths | unsigned int prefix_insn, |
| 1605 | 450d4ff5 | ths | struct cris_disasm_data *disdata)
|
| 1606 | 450d4ff5 | ths | {
|
| 1607 | 450d4ff5 | ths | int retval = 0; |
| 1608 | 450d4ff5 | ths | int tmp;
|
| 1609 | 450d4ff5 | ths | int prefix_ok = 0; |
| 1610 | 450d4ff5 | ths | const char *s; |
| 1611 | 450d4ff5 | ths | |
| 1612 | 450d4ff5 | ths | for (s = cs; *s; s++)
|
| 1613 | 450d4ff5 | ths | switch (*s)
|
| 1614 | 450d4ff5 | ths | {
|
| 1615 | 450d4ff5 | ths | case '!': |
| 1616 | 450d4ff5 | ths | /* Do not recognize "pop" if there's a prefix and then only for
|
| 1617 | 450d4ff5 | ths | v0..v10. */
|
| 1618 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX
|
| 1619 | 450d4ff5 | ths | || disdata->distype != cris_dis_v0_v10) |
| 1620 | 450d4ff5 | ths | return -1; |
| 1621 | 450d4ff5 | ths | break;
|
| 1622 | 450d4ff5 | ths | |
| 1623 | 450d4ff5 | ths | case 'U': |
| 1624 | 450d4ff5 | ths | /* Not recognized at disassembly. */
|
| 1625 | 450d4ff5 | ths | return -1; |
| 1626 | 450d4ff5 | ths | |
| 1627 | 450d4ff5 | ths | case 'M': |
| 1628 | 450d4ff5 | ths | /* Size modifier for "clear", i.e. special register 0, 4 or 8.
|
| 1629 | 450d4ff5 | ths | Check that it is one of them. Only special register 12 could
|
| 1630 | 450d4ff5 | ths | be mismatched, but checking for matches is more logical than
|
| 1631 | 450d4ff5 | ths | checking for mismatches when there are only a few cases. */
|
| 1632 | 450d4ff5 | ths | tmp = ((insn >> 12) & 0xf); |
| 1633 | 450d4ff5 | ths | if (tmp != 0 && tmp != 4 && tmp != 8) |
| 1634 | 450d4ff5 | ths | return -1; |
| 1635 | 450d4ff5 | ths | break;
|
| 1636 | 450d4ff5 | ths | |
| 1637 | 450d4ff5 | ths | case 'm': |
| 1638 | 450d4ff5 | ths | if ((insn & 0x30) == 0x30) |
| 1639 | 450d4ff5 | ths | return -1; |
| 1640 | 450d4ff5 | ths | break;
|
| 1641 | 450d4ff5 | ths | |
| 1642 | 450d4ff5 | ths | case 'S': |
| 1643 | 450d4ff5 | ths | /* A prefix operand without side-effect. */
|
| 1644 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0) |
| 1645 | 450d4ff5 | ths | {
|
| 1646 | 450d4ff5 | ths | prefix_ok = 1;
|
| 1647 | 450d4ff5 | ths | break;
|
| 1648 | 450d4ff5 | ths | } |
| 1649 | 450d4ff5 | ths | else
|
| 1650 | 450d4ff5 | ths | return -1; |
| 1651 | 450d4ff5 | ths | |
| 1652 | 450d4ff5 | ths | case 's': |
| 1653 | 450d4ff5 | ths | case 'y': |
| 1654 | 450d4ff5 | ths | case 'Y': |
| 1655 | 450d4ff5 | ths | /* If this is a prefixed insn with postincrement (side-effect),
|
| 1656 | 450d4ff5 | ths | the prefix must not be DIP. */
|
| 1657 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX)
|
| 1658 | 450d4ff5 | ths | {
|
| 1659 | 450d4ff5 | ths | if (insn & 0x400) |
| 1660 | 450d4ff5 | ths | {
|
| 1661 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep |
| 1662 | 450d4ff5 | ths | = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); |
| 1663 | 450d4ff5 | ths | |
| 1664 | 450d4ff5 | ths | if (prefix_opcodep->match == DIP_OPCODE)
|
| 1665 | 450d4ff5 | ths | return -1; |
| 1666 | 450d4ff5 | ths | } |
| 1667 | 450d4ff5 | ths | |
| 1668 | 450d4ff5 | ths | prefix_ok = 1;
|
| 1669 | 450d4ff5 | ths | } |
| 1670 | 450d4ff5 | ths | break;
|
| 1671 | 450d4ff5 | ths | |
| 1672 | 450d4ff5 | ths | case 'B': |
| 1673 | 450d4ff5 | ths | /* If we don't fall through, then the prefix is ok. */
|
| 1674 | 450d4ff5 | ths | prefix_ok = 1;
|
| 1675 | 450d4ff5 | ths | |
| 1676 | 450d4ff5 | ths | /* A "push" prefix. Check for valid "push" size.
|
| 1677 | 450d4ff5 | ths | In case of special register, it may be != 4. */
|
| 1678 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX)
|
| 1679 | 450d4ff5 | ths | {
|
| 1680 | 450d4ff5 | ths | /* Match the prefix insn to BDAPQ. */
|
| 1681 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep |
| 1682 | 450d4ff5 | ths | = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); |
| 1683 | 450d4ff5 | ths | |
| 1684 | 450d4ff5 | ths | if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
|
| 1685 | 450d4ff5 | ths | {
|
| 1686 | 450d4ff5 | ths | int pushsize = (prefix_insn & 255); |
| 1687 | 450d4ff5 | ths | |
| 1688 | 450d4ff5 | ths | if (pushsize > 127) |
| 1689 | 450d4ff5 | ths | pushsize -= 256;
|
| 1690 | 450d4ff5 | ths | |
| 1691 | 450d4ff5 | ths | if (s[1] == 'P') |
| 1692 | 450d4ff5 | ths | {
|
| 1693 | 450d4ff5 | ths | unsigned int spec_reg = (insn >> 12) & 15; |
| 1694 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
| 1695 | 450d4ff5 | ths | = spec_reg_info (spec_reg, disdata->distype); |
| 1696 | 450d4ff5 | ths | |
| 1697 | 450d4ff5 | ths | /* For a special-register, the "prefix size" must
|
| 1698 | 450d4ff5 | ths | match the size of the register. */
|
| 1699 | 450d4ff5 | ths | if (sregp && sregp->reg_size == (unsigned int) -pushsize) |
| 1700 | 450d4ff5 | ths | break;
|
| 1701 | 450d4ff5 | ths | } |
| 1702 | 450d4ff5 | ths | else if (s[1] == 'R') |
| 1703 | 450d4ff5 | ths | {
|
| 1704 | 450d4ff5 | ths | if ((insn & 0x30) == 0x20 && pushsize == -4) |
| 1705 | 450d4ff5 | ths | break;
|
| 1706 | 450d4ff5 | ths | } |
| 1707 | 450d4ff5 | ths | /* FIXME: Should abort here; next constraint letter
|
| 1708 | 450d4ff5 | ths | *must* be 'P' or 'R'. */
|
| 1709 | 450d4ff5 | ths | } |
| 1710 | 450d4ff5 | ths | } |
| 1711 | 450d4ff5 | ths | return -1; |
| 1712 | 450d4ff5 | ths | |
| 1713 | 450d4ff5 | ths | case 'D': |
| 1714 | 450d4ff5 | ths | retval = (((insn >> 12) & 15) == (insn & 15)); |
| 1715 | 450d4ff5 | ths | if (!retval)
|
| 1716 | 450d4ff5 | ths | return -1; |
| 1717 | 450d4ff5 | ths | else
|
| 1718 | 450d4ff5 | ths | retval += 4;
|
| 1719 | 450d4ff5 | ths | break;
|
| 1720 | 450d4ff5 | ths | |
| 1721 | 450d4ff5 | ths | case 'P': |
| 1722 | 450d4ff5 | ths | {
|
| 1723 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
| 1724 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
| 1725 | 450d4ff5 | ths | |
| 1726 | 450d4ff5 | ths | /* Since we match four bits, we will give a value of 4-1 = 3
|
| 1727 | 450d4ff5 | ths | in a match. If there is a corresponding exact match of a
|
| 1728 | 450d4ff5 | ths | special register in another pattern, it will get a value of
|
| 1729 | 450d4ff5 | ths | 4, which will be higher. This should be correct in that an
|
| 1730 | 450d4ff5 | ths | exact pattern would match better than a general pattern.
|
| 1731 | 450d4ff5 | ths | |
| 1732 | 450d4ff5 | ths | Note that there is a reason for not returning zero; the
|
| 1733 | 450d4ff5 | ths | pattern for "clear" is partly matched in the bit-pattern
|
| 1734 | 450d4ff5 | ths | (the two lower bits must be zero), while the bit-pattern
|
| 1735 | 450d4ff5 | ths | for a move from a special register is matched in the
|
| 1736 | 450d4ff5 | ths | register constraint. */
|
| 1737 | 450d4ff5 | ths | |
| 1738 | 450d4ff5 | ths | if (sregp != NULL) |
| 1739 | 450d4ff5 | ths | {
|
| 1740 | 450d4ff5 | ths | retval += 3;
|
| 1741 | 450d4ff5 | ths | break;
|
| 1742 | 450d4ff5 | ths | } |
| 1743 | 450d4ff5 | ths | else
|
| 1744 | 450d4ff5 | ths | return -1; |
| 1745 | 450d4ff5 | ths | } |
| 1746 | 450d4ff5 | ths | } |
| 1747 | 450d4ff5 | ths | |
| 1748 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
|
| 1749 | 450d4ff5 | ths | return -1; |
| 1750 | 450d4ff5 | ths | |
| 1751 | 450d4ff5 | ths | return retval;
|
| 1752 | 450d4ff5 | ths | } |
| 1753 | 450d4ff5 | ths | |
| 1754 | 450d4ff5 | ths | /* Format number as hex with a leading "0x" into outbuffer. */
|
| 1755 | 450d4ff5 | ths | |
| 1756 | 450d4ff5 | ths | static char * |
| 1757 | 450d4ff5 | ths | format_hex (unsigned long number, |
| 1758 | 450d4ff5 | ths | char *outbuffer,
|
| 1759 | 450d4ff5 | ths | struct cris_disasm_data *disdata)
|
| 1760 | 450d4ff5 | ths | {
|
| 1761 | 450d4ff5 | ths | /* Truncate negative numbers on >32-bit hosts. */
|
| 1762 | 450d4ff5 | ths | number &= 0xffffffff;
|
| 1763 | 450d4ff5 | ths | |
| 1764 | 450d4ff5 | ths | sprintf (outbuffer, "0x%lx", number);
|
| 1765 | 450d4ff5 | ths | |
| 1766 | 450d4ff5 | ths | /* Save this value for the "case" support. */
|
| 1767 | 450d4ff5 | ths | if (TRACE_CASE)
|
| 1768 | 450d4ff5 | ths | last_immediate = number; |
| 1769 | 450d4ff5 | ths | |
| 1770 | 450d4ff5 | ths | return outbuffer + strlen (outbuffer);
|
| 1771 | 450d4ff5 | ths | } |
| 1772 | 450d4ff5 | ths | |
| 1773 | 450d4ff5 | ths | /* Format number as decimal into outbuffer. Parameter signedp says
|
| 1774 | 450d4ff5 | ths | whether the number should be formatted as signed (!= 0) or
|
| 1775 | 450d4ff5 | ths | unsigned (== 0). */
|
| 1776 | 450d4ff5 | ths | |
| 1777 | 450d4ff5 | ths | static char * |
| 1778 | 450d4ff5 | ths | format_dec (long number, char *outbuffer, int signedp) |
| 1779 | 450d4ff5 | ths | {
|
| 1780 | 450d4ff5 | ths | last_immediate = number; |
| 1781 | 450d4ff5 | ths | sprintf (outbuffer, signedp ? "%ld" : "%lu", number); |
| 1782 | 450d4ff5 | ths | |
| 1783 | 450d4ff5 | ths | return outbuffer + strlen (outbuffer);
|
| 1784 | 450d4ff5 | ths | } |
| 1785 | 450d4ff5 | ths | |
| 1786 | 450d4ff5 | ths | /* Format the name of the general register regno into outbuffer. */
|
| 1787 | 450d4ff5 | ths | |
| 1788 | 450d4ff5 | ths | static char * |
| 1789 | 450d4ff5 | ths | format_reg (struct cris_disasm_data *disdata,
|
| 1790 | 450d4ff5 | ths | int regno,
|
| 1791 | 450d4ff5 | ths | char *outbuffer_start,
|
| 1792 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
| 1793 | 450d4ff5 | ths | {
|
| 1794 | 450d4ff5 | ths | char *outbuffer = outbuffer_start;
|
| 1795 | 450d4ff5 | ths | |
| 1796 | 450d4ff5 | ths | if (with_reg_prefix)
|
| 1797 | 450d4ff5 | ths | *outbuffer++ = REGISTER_PREFIX_CHAR; |
| 1798 | 450d4ff5 | ths | |
| 1799 | 450d4ff5 | ths | switch (regno)
|
| 1800 | 450d4ff5 | ths | {
|
| 1801 | 450d4ff5 | ths | case 15: |
| 1802 | 450d4ff5 | ths | /* For v32, there is no context in which we output PC. */
|
| 1803 | 450d4ff5 | ths | if (disdata->distype == cris_dis_v32)
|
| 1804 | 450d4ff5 | ths | strcpy (outbuffer, "acr");
|
| 1805 | 450d4ff5 | ths | else
|
| 1806 | 450d4ff5 | ths | strcpy (outbuffer, "pc");
|
| 1807 | 450d4ff5 | ths | break;
|
| 1808 | 450d4ff5 | ths | |
| 1809 | 450d4ff5 | ths | case 14: |
| 1810 | 450d4ff5 | ths | strcpy (outbuffer, "sp");
|
| 1811 | 450d4ff5 | ths | break;
|
| 1812 | 450d4ff5 | ths | |
| 1813 | 450d4ff5 | ths | default:
|
| 1814 | 450d4ff5 | ths | sprintf (outbuffer, "r%d", regno);
|
| 1815 | 450d4ff5 | ths | break;
|
| 1816 | 450d4ff5 | ths | } |
| 1817 | 450d4ff5 | ths | |
| 1818 | 450d4ff5 | ths | return outbuffer_start + strlen (outbuffer_start);
|
| 1819 | 450d4ff5 | ths | } |
| 1820 | 450d4ff5 | ths | |
| 1821 | 450d4ff5 | ths | /* Format the name of a support register into outbuffer. */
|
| 1822 | 450d4ff5 | ths | |
| 1823 | 450d4ff5 | ths | static char * |
| 1824 | 450d4ff5 | ths | format_sup_reg (unsigned int regno, |
| 1825 | 450d4ff5 | ths | char *outbuffer_start,
|
| 1826 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
| 1827 | 450d4ff5 | ths | {
|
| 1828 | 450d4ff5 | ths | char *outbuffer = outbuffer_start;
|
| 1829 | 450d4ff5 | ths | int i;
|
| 1830 | 450d4ff5 | ths | |
| 1831 | 450d4ff5 | ths | if (with_reg_prefix)
|
| 1832 | 450d4ff5 | ths | *outbuffer++ = REGISTER_PREFIX_CHAR; |
| 1833 | 450d4ff5 | ths | |
| 1834 | 450d4ff5 | ths | for (i = 0; cris_support_regs[i].name != NULL; i++) |
| 1835 | 450d4ff5 | ths | if (cris_support_regs[i].number == regno)
|
| 1836 | 450d4ff5 | ths | {
|
| 1837 | 450d4ff5 | ths | sprintf (outbuffer, "%s", cris_support_regs[i].name);
|
| 1838 | 450d4ff5 | ths | return outbuffer_start + strlen (outbuffer_start);
|
| 1839 | 450d4ff5 | ths | } |
| 1840 | 450d4ff5 | ths | |
| 1841 | 450d4ff5 | ths | /* There's supposed to be register names covering all numbers, though
|
| 1842 | 450d4ff5 | ths | some may be generic names. */
|
| 1843 | 450d4ff5 | ths | sprintf (outbuffer, "format_sup_reg-BUG");
|
| 1844 | 450d4ff5 | ths | return outbuffer_start + strlen (outbuffer_start);
|
| 1845 | 450d4ff5 | ths | } |
| 1846 | 450d4ff5 | ths | |
| 1847 | 450d4ff5 | ths | /* Return the length of an instruction. */
|
| 1848 | 450d4ff5 | ths | |
| 1849 | 450d4ff5 | ths | static unsigned |
| 1850 | 450d4ff5 | ths | bytes_to_skip (unsigned int insn, |
| 1851 | 450d4ff5 | ths | const struct cris_opcode *matchedp, |
| 1852 | 450d4ff5 | ths | enum cris_disass_family distype,
|
| 1853 | 450d4ff5 | ths | const struct cris_opcode *prefix_matchedp) |
| 1854 | 450d4ff5 | ths | {
|
| 1855 | 450d4ff5 | ths | /* Each insn is a word plus "immediate" operands. */
|
| 1856 | 450d4ff5 | ths | unsigned to_skip = 2; |
| 1857 | 450d4ff5 | ths | const char *template = matchedp->args; |
| 1858 | 450d4ff5 | ths | const char *s; |
| 1859 | 450d4ff5 | ths | |
| 1860 | 450d4ff5 | ths | for (s = template; *s; s++)
|
| 1861 | 450d4ff5 | ths | if ((*s == 's' || *s == 'N' || *s == 'Y') |
| 1862 | 450d4ff5 | ths | && (insn & 0x400) && (insn & 15) == 15 |
| 1863 | 450d4ff5 | ths | && prefix_matchedp == NULL)
|
| 1864 | 450d4ff5 | ths | {
|
| 1865 | 450d4ff5 | ths | /* Immediate via [pc+], so we have to check the size of the
|
| 1866 | 450d4ff5 | ths | operand. */
|
| 1867 | 450d4ff5 | ths | int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3)); |
| 1868 | 450d4ff5 | ths | |
| 1869 | 450d4ff5 | ths | if (matchedp->imm_oprnd_size == SIZE_FIX_32)
|
| 1870 | 450d4ff5 | ths | to_skip += 4;
|
| 1871 | 450d4ff5 | ths | else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG) |
| 1872 | 450d4ff5 | ths | {
|
| 1873 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
| 1874 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, distype); |
| 1875 | 450d4ff5 | ths | |
| 1876 | 450d4ff5 | ths | /* FIXME: Improve error handling; should have been caught
|
| 1877 | 450d4ff5 | ths | earlier. */
|
| 1878 | 450d4ff5 | ths | if (sregp == NULL) |
| 1879 | 450d4ff5 | ths | return 2; |
| 1880 | 450d4ff5 | ths | |
| 1881 | 450d4ff5 | ths | /* PC is incremented by two, not one, for a byte. Except on
|
| 1882 | 450d4ff5 | ths | CRISv32, where constants are always DWORD-size for
|
| 1883 | 450d4ff5 | ths | special registers. */
|
| 1884 | 450d4ff5 | ths | to_skip += |
| 1885 | 450d4ff5 | ths | distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; |
| 1886 | 450d4ff5 | ths | } |
| 1887 | 450d4ff5 | ths | else
|
| 1888 | 450d4ff5 | ths | to_skip += (mode_size + 1) & ~1; |
| 1889 | 450d4ff5 | ths | } |
| 1890 | 450d4ff5 | ths | else if (*s == 'n') |
| 1891 | 450d4ff5 | ths | to_skip += 4;
|
| 1892 | 450d4ff5 | ths | else if (*s == 'b') |
| 1893 | 450d4ff5 | ths | to_skip += 2;
|
| 1894 | 450d4ff5 | ths | |
| 1895 | 450d4ff5 | ths | return to_skip;
|
| 1896 | 450d4ff5 | ths | } |
| 1897 | 450d4ff5 | ths | |
| 1898 | 450d4ff5 | ths | /* Print condition code flags. */
|
| 1899 | 450d4ff5 | ths | |
| 1900 | 450d4ff5 | ths | static char * |
| 1901 | 450d4ff5 | ths | print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp) |
| 1902 | 450d4ff5 | ths | {
|
| 1903 | 450d4ff5 | ths | /* Use the v8 (Etrax 100) flag definitions for disassembly.
|
| 1904 | 450d4ff5 | ths | The differences with v0 (Etrax 1..4) vs. Svinto are:
|
| 1905 | 450d4ff5 | ths | v0 'd' <=> v8 'm'
|
| 1906 | 450d4ff5 | ths | v0 'e' <=> v8 'b'.
|
| 1907 | 450d4ff5 | ths | FIXME: Emit v0..v3 flag names somehow. */
|
| 1908 | 450d4ff5 | ths | static const char v8_fnames[] = "cvznxibm"; |
| 1909 | 450d4ff5 | ths | static const char v32_fnames[] = "cvznxiup"; |
| 1910 | 450d4ff5 | ths | const char *fnames |
| 1911 | 450d4ff5 | ths | = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames; |
| 1912 | 450d4ff5 | ths | |
| 1913 | 450d4ff5 | ths | unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); |
| 1914 | 450d4ff5 | ths | int i;
|
| 1915 | 450d4ff5 | ths | |
| 1916 | 450d4ff5 | ths | for (i = 0; i < 8; i++) |
| 1917 | 450d4ff5 | ths | if (flagbits & (1 << i)) |
| 1918 | 450d4ff5 | ths | *cp++ = fnames[i]; |
| 1919 | 450d4ff5 | ths | |
| 1920 | 450d4ff5 | ths | return cp;
|
| 1921 | 450d4ff5 | ths | } |
| 1922 | 450d4ff5 | ths | |
| 1923 | 450d4ff5 | ths | /* Print out an insn with its operands, and update the info->insn_type
|
| 1924 | 450d4ff5 | ths | fields. The prefix_opcodep and the rest hold a prefix insn that is
|
| 1925 | 450d4ff5 | ths | supposed to be output as an address mode. */
|
| 1926 | 450d4ff5 | ths | |
| 1927 | 450d4ff5 | ths | static void |
| 1928 | 450d4ff5 | ths | print_with_operands (const struct cris_opcode *opcodep, |
| 1929 | 450d4ff5 | ths | unsigned int insn, |
| 1930 | 450d4ff5 | ths | unsigned char *buffer, |
| 1931 | 450d4ff5 | ths | bfd_vma addr, |
| 1932 | 450d4ff5 | ths | disassemble_info *info, |
| 1933 | 450d4ff5 | ths | /* If a prefix insn was before this insn (and is supposed
|
| 1934 | 450d4ff5 | ths | to be output as an address), here is a description of
|
| 1935 | 450d4ff5 | ths | it. */
|
| 1936 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep, |
| 1937 | 450d4ff5 | ths | unsigned int prefix_insn, |
| 1938 | 450d4ff5 | ths | unsigned char *prefix_buffer, |
| 1939 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
| 1940 | 450d4ff5 | ths | {
|
| 1941 | 450d4ff5 | ths | /* Get a buffer of somewhat reasonable size where we store
|
| 1942 | 450d4ff5 | ths | intermediate parts of the insn. */
|
| 1943 | 450d4ff5 | ths | char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2]; |
| 1944 | 450d4ff5 | ths | char *tp = temp;
|
| 1945 | 450d4ff5 | ths | static const char mode_char[] = "bwd?"; |
| 1946 | 450d4ff5 | ths | const char *s; |
| 1947 | 450d4ff5 | ths | const char *cs; |
| 1948 | 450d4ff5 | ths | struct cris_disasm_data *disdata
|
| 1949 | 450d4ff5 | ths | = (struct cris_disasm_data *) info->private_data;
|
| 1950 | 450d4ff5 | ths | |
| 1951 | 450d4ff5 | ths | /* Print out the name first thing we do. */
|
| 1952 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", opcodep->name);
|
| 1953 | 450d4ff5 | ths | |
| 1954 | 450d4ff5 | ths | cs = opcodep->args; |
| 1955 | 450d4ff5 | ths | s = cs; |
| 1956 | 450d4ff5 | ths | |
| 1957 | 450d4ff5 | ths | /* Ignore any prefix indicator. */
|
| 1958 | 450d4ff5 | ths | if (*s == 'p') |
| 1959 | 450d4ff5 | ths | s++; |
| 1960 | 450d4ff5 | ths | |
| 1961 | 450d4ff5 | ths | if (*s == 'm' || *s == 'M' || *s == 'z') |
| 1962 | 450d4ff5 | ths | {
|
| 1963 | 450d4ff5 | ths | *tp++ = '.';
|
| 1964 | 450d4ff5 | ths | |
| 1965 | 450d4ff5 | ths | /* Get the size-letter. */
|
| 1966 | 450d4ff5 | ths | *tp++ = *s == 'M'
|
| 1967 | 450d4ff5 | ths | ? (insn & 0x8000 ? 'd' |
| 1968 | 450d4ff5 | ths | : insn & 0x4000 ? 'w' : 'b') |
| 1969 | 450d4ff5 | ths | : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)]; |
| 1970 | 450d4ff5 | ths | |
| 1971 | 450d4ff5 | ths | /* Ignore the size and the space character that follows. */
|
| 1972 | 450d4ff5 | ths | s += 2;
|
| 1973 | 450d4ff5 | ths | } |
| 1974 | 450d4ff5 | ths | |
| 1975 | 450d4ff5 | ths | /* Add a space if this isn't a long-branch, because for those will add
|
| 1976 | 450d4ff5 | ths | the condition part of the name later. */
|
| 1977 | 450d4ff5 | ths | if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) |
| 1978 | 450d4ff5 | ths | *tp++ = ' ';
|
| 1979 | 450d4ff5 | ths | |
| 1980 | 450d4ff5 | ths | /* Fill in the insn-type if deducible from the name (and there's no
|
| 1981 | 450d4ff5 | ths | better way). */
|
| 1982 | 450d4ff5 | ths | if (opcodep->name[0] == 'j') |
| 1983 | 450d4ff5 | ths | {
|
| 1984 | 450d4ff5 | ths | if (CONST_STRNEQ (opcodep->name, "jsr")) |
| 1985 | 450d4ff5 | ths | /* It's "jsr" or "jsrc". */
|
| 1986 | 450d4ff5 | ths | info->insn_type = dis_jsr; |
| 1987 | 450d4ff5 | ths | else
|
| 1988 | 450d4ff5 | ths | /* Any other jump-type insn is considered a branch. */
|
| 1989 | 450d4ff5 | ths | info->insn_type = dis_branch; |
| 1990 | 450d4ff5 | ths | } |
| 1991 | 450d4ff5 | ths | |
| 1992 | 450d4ff5 | ths | /* We might know some more fields right now. */
|
| 1993 | 450d4ff5 | ths | info->branch_delay_insns = opcodep->delayed; |
| 1994 | 450d4ff5 | ths | |
| 1995 | 450d4ff5 | ths | /* Handle operands. */
|
| 1996 | 450d4ff5 | ths | for (; *s; s++)
|
| 1997 | 450d4ff5 | ths | {
|
| 1998 | 450d4ff5 | ths | switch (*s)
|
| 1999 | 450d4ff5 | ths | {
|
| 2000 | 450d4ff5 | ths | case 'T': |
| 2001 | 450d4ff5 | ths | tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); |
| 2002 | 450d4ff5 | ths | break;
|
| 2003 | 450d4ff5 | ths | |
| 2004 | 450d4ff5 | ths | case 'A': |
| 2005 | 450d4ff5 | ths | if (with_reg_prefix)
|
| 2006 | 450d4ff5 | ths | *tp++ = REGISTER_PREFIX_CHAR; |
| 2007 | 450d4ff5 | ths | *tp++ = 'a';
|
| 2008 | 450d4ff5 | ths | *tp++ = 'c';
|
| 2009 | 450d4ff5 | ths | *tp++ = 'r';
|
| 2010 | 450d4ff5 | ths | break;
|
| 2011 | 450d4ff5 | ths | |
| 2012 | 450d4ff5 | ths | case '[': |
| 2013 | 450d4ff5 | ths | case ']': |
| 2014 | 450d4ff5 | ths | case ',': |
| 2015 | 450d4ff5 | ths | *tp++ = *s; |
| 2016 | 450d4ff5 | ths | break;
|
| 2017 | 450d4ff5 | ths | |
| 2018 | 450d4ff5 | ths | case '!': |
| 2019 | 450d4ff5 | ths | /* Ignore at this point; used at earlier stages to avoid
|
| 2020 | 450d4ff5 | ths | recognition if there's a prefix at something that in other
|
| 2021 | 450d4ff5 | ths | ways looks like a "pop". */
|
| 2022 | 450d4ff5 | ths | break;
|
| 2023 | 450d4ff5 | ths | |
| 2024 | 450d4ff5 | ths | case 'd': |
| 2025 | 450d4ff5 | ths | /* Ignore. This is an optional ".d " on the large one of
|
| 2026 | 450d4ff5 | ths | relaxable insns. */
|
| 2027 | 450d4ff5 | ths | break;
|
| 2028 | 450d4ff5 | ths | |
| 2029 | 450d4ff5 | ths | case 'B': |
| 2030 | 450d4ff5 | ths | /* This was the prefix that made this a "push". We've already
|
| 2031 | 450d4ff5 | ths | handled it by recognizing it, so signal that the prefix is
|
| 2032 | 450d4ff5 | ths | handled by setting it to NULL. */
|
| 2033 | 450d4ff5 | ths | prefix_opcodep = NULL;
|
| 2034 | 450d4ff5 | ths | break;
|
| 2035 | 450d4ff5 | ths | |
| 2036 | 450d4ff5 | ths | case 'D': |
| 2037 | 450d4ff5 | ths | case 'r': |
| 2038 | 450d4ff5 | ths | tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
|
| 2039 | 450d4ff5 | ths | break;
|
| 2040 | 450d4ff5 | ths | |
| 2041 | 450d4ff5 | ths | case 'R': |
| 2042 | 450d4ff5 | ths | tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); |
| 2043 | 450d4ff5 | ths | break;
|
| 2044 | 450d4ff5 | ths | |
| 2045 | 450d4ff5 | ths | case 'n': |
| 2046 | 450d4ff5 | ths | {
|
| 2047 | 450d4ff5 | ths | /* Like N but pc-relative to the start of the insn. */
|
| 2048 | 450d4ff5 | ths | unsigned long number |
| 2049 | 450d4ff5 | ths | = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 |
| 2050 | 450d4ff5 | ths | + buffer[5] * 0x1000000 + addr); |
| 2051 | 450d4ff5 | ths | |
| 2052 | 450d4ff5 | ths | /* Finish off and output previous formatted bytes. */
|
| 2053 | 450d4ff5 | ths | *tp = 0;
|
| 2054 | 450d4ff5 | ths | if (temp[0]) |
| 2055 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2056 | 450d4ff5 | ths | tp = temp; |
| 2057 | 450d4ff5 | ths | |
| 2058 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
| 2059 | 450d4ff5 | ths | } |
| 2060 | 450d4ff5 | ths | break;
|
| 2061 | 450d4ff5 | ths | |
| 2062 | 450d4ff5 | ths | case 'u': |
| 2063 | 450d4ff5 | ths | {
|
| 2064 | 450d4ff5 | ths | /* Like n but the offset is bits <3:0> in the instruction. */
|
| 2065 | 450d4ff5 | ths | unsigned long number = (buffer[0] & 0xf) * 2 + addr; |
| 2066 | 450d4ff5 | ths | |
| 2067 | 450d4ff5 | ths | /* Finish off and output previous formatted bytes. */
|
| 2068 | 450d4ff5 | ths | *tp = 0;
|
| 2069 | 450d4ff5 | ths | if (temp[0]) |
| 2070 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2071 | 450d4ff5 | ths | tp = temp; |
| 2072 | 450d4ff5 | ths | |
| 2073 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
| 2074 | 450d4ff5 | ths | } |
| 2075 | 450d4ff5 | ths | break;
|
| 2076 | 450d4ff5 | ths | |
| 2077 | 450d4ff5 | ths | case 'N': |
| 2078 | 450d4ff5 | ths | case 'y': |
| 2079 | 450d4ff5 | ths | case 'Y': |
| 2080 | 450d4ff5 | ths | case 'S': |
| 2081 | 450d4ff5 | ths | case 's': |
| 2082 | 450d4ff5 | ths | /* Any "normal" memory operand. */
|
| 2083 | 450d4ff5 | ths | if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL) |
| 2084 | 450d4ff5 | ths | {
|
| 2085 | 450d4ff5 | ths | /* We're looking at [pc+], i.e. we need to output an immediate
|
| 2086 | 450d4ff5 | ths | number, where the size can depend on different things. */
|
| 2087 | 450d4ff5 | ths | long number;
|
| 2088 | 450d4ff5 | ths | int signedp
|
| 2089 | 450d4ff5 | ths | = ((*cs == 'z' && (insn & 0x20)) |
| 2090 | 450d4ff5 | ths | || opcodep->match == BDAP_QUICK_OPCODE); |
| 2091 | 450d4ff5 | ths | int nbytes;
|
| 2092 | 450d4ff5 | ths | |
| 2093 | 450d4ff5 | ths | if (opcodep->imm_oprnd_size == SIZE_FIX_32)
|
| 2094 | 450d4ff5 | ths | nbytes = 4;
|
| 2095 | 450d4ff5 | ths | else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) |
| 2096 | 450d4ff5 | ths | {
|
| 2097 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
| 2098 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
| 2099 | 450d4ff5 | ths | |
| 2100 | 450d4ff5 | ths | /* A NULL return should have been as a non-match earlier,
|
| 2101 | 450d4ff5 | ths | so catch it as an internal error in the error-case
|
| 2102 | 450d4ff5 | ths | below. */
|
| 2103 | 450d4ff5 | ths | if (sregp == NULL) |
| 2104 | 450d4ff5 | ths | /* Whatever non-valid size. */
|
| 2105 | 450d4ff5 | ths | nbytes = 42;
|
| 2106 | 450d4ff5 | ths | else
|
| 2107 | 450d4ff5 | ths | /* PC is always incremented by a multiple of two.
|
| 2108 | 450d4ff5 | ths | For CRISv32, immediates are always 4 bytes for
|
| 2109 | 450d4ff5 | ths | special registers. */
|
| 2110 | 450d4ff5 | ths | nbytes = disdata->distype == cris_dis_v32 |
| 2111 | 450d4ff5 | ths | ? 4 : (sregp->reg_size + 1) & ~1; |
| 2112 | 450d4ff5 | ths | } |
| 2113 | 450d4ff5 | ths | else
|
| 2114 | 450d4ff5 | ths | {
|
| 2115 | 450d4ff5 | ths | int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3)); |
| 2116 | 450d4ff5 | ths | |
| 2117 | 450d4ff5 | ths | if (mode_size == 1) |
| 2118 | 450d4ff5 | ths | nbytes = 2;
|
| 2119 | 450d4ff5 | ths | else
|
| 2120 | 450d4ff5 | ths | nbytes = mode_size; |
| 2121 | 450d4ff5 | ths | } |
| 2122 | 450d4ff5 | ths | |
| 2123 | 450d4ff5 | ths | switch (nbytes)
|
| 2124 | 450d4ff5 | ths | {
|
| 2125 | 450d4ff5 | ths | case 1: |
| 2126 | 450d4ff5 | ths | number = buffer[2];
|
| 2127 | 450d4ff5 | ths | if (signedp && number > 127) |
| 2128 | 450d4ff5 | ths | number -= 256;
|
| 2129 | 450d4ff5 | ths | break;
|
| 2130 | 450d4ff5 | ths | |
| 2131 | 450d4ff5 | ths | case 2: |
| 2132 | 450d4ff5 | ths | number = buffer[2] + buffer[3] * 256; |
| 2133 | 450d4ff5 | ths | if (signedp && number > 32767) |
| 2134 | 450d4ff5 | ths | number -= 65536;
|
| 2135 | 450d4ff5 | ths | break;
|
| 2136 | 450d4ff5 | ths | |
| 2137 | 450d4ff5 | ths | case 4: |
| 2138 | 450d4ff5 | ths | number |
| 2139 | 450d4ff5 | ths | = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 |
| 2140 | 450d4ff5 | ths | + buffer[5] * 0x1000000; |
| 2141 | 450d4ff5 | ths | break;
|
| 2142 | 450d4ff5 | ths | |
| 2143 | 450d4ff5 | ths | default:
|
| 2144 | 450d4ff5 | ths | strcpy (tp, "bug");
|
| 2145 | 450d4ff5 | ths | tp += 3;
|
| 2146 | 450d4ff5 | ths | number = 42;
|
| 2147 | 450d4ff5 | ths | } |
| 2148 | 450d4ff5 | ths | |
| 2149 | 450d4ff5 | ths | if ((*cs == 'z' && (insn & 0x20)) |
| 2150 | 450d4ff5 | ths | || (opcodep->match == BDAP_QUICK_OPCODE |
| 2151 | 450d4ff5 | ths | && (nbytes <= 2 || buffer[1 + nbytes] == 0))) |
| 2152 | 450d4ff5 | ths | tp = format_dec (number, tp, signedp); |
| 2153 | 450d4ff5 | ths | else
|
| 2154 | 450d4ff5 | ths | {
|
| 2155 | 450d4ff5 | ths | unsigned int highbyte = (number >> 24) & 0xff; |
| 2156 | 450d4ff5 | ths | |
| 2157 | 450d4ff5 | ths | /* Either output this as an address or as a number. If it's
|
| 2158 | 450d4ff5 | ths | a dword with the same high-byte as the address of the
|
| 2159 | 450d4ff5 | ths | insn, assume it's an address, and also if it's a non-zero
|
| 2160 | 450d4ff5 | ths | non-0xff high-byte. If this is a jsr or a jump, then
|
| 2161 | 450d4ff5 | ths | it's definitely an address. */
|
| 2162 | 450d4ff5 | ths | if (nbytes == 4 |
| 2163 | 450d4ff5 | ths | && (highbyte == ((addr >> 24) & 0xff) |
| 2164 | 450d4ff5 | ths | || (highbyte != 0 && highbyte != 0xff) |
| 2165 | 450d4ff5 | ths | || info->insn_type == dis_branch |
| 2166 | 450d4ff5 | ths | || info->insn_type == dis_jsr)) |
| 2167 | 450d4ff5 | ths | {
|
| 2168 | 450d4ff5 | ths | /* Finish off and output previous formatted bytes. */
|
| 2169 | 450d4ff5 | ths | *tp = 0;
|
| 2170 | 450d4ff5 | ths | tp = temp; |
| 2171 | 450d4ff5 | ths | if (temp[0]) |
| 2172 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2173 | 450d4ff5 | ths | |
| 2174 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
| 2175 | 450d4ff5 | ths | |
| 2176 | 450d4ff5 | ths | info->target = number; |
| 2177 | 450d4ff5 | ths | } |
| 2178 | 450d4ff5 | ths | else
|
| 2179 | 450d4ff5 | ths | tp = format_hex (number, tp, disdata); |
| 2180 | 450d4ff5 | ths | } |
| 2181 | 450d4ff5 | ths | } |
| 2182 | 450d4ff5 | ths | else
|
| 2183 | 450d4ff5 | ths | {
|
| 2184 | 450d4ff5 | ths | /* Not an immediate number. Then this is a (possibly
|
| 2185 | 450d4ff5 | ths | prefixed) memory operand. */
|
| 2186 | 450d4ff5 | ths | if (info->insn_type != dis_nonbranch)
|
| 2187 | 450d4ff5 | ths | {
|
| 2188 | 450d4ff5 | ths | int mode_size
|
| 2189 | 450d4ff5 | ths | = 1 << ((insn >> 4) |
| 2190 | 450d4ff5 | ths | & (opcodep->args[0] == 'z' ? 1 : 3)); |
| 2191 | 450d4ff5 | ths | int size;
|
| 2192 | 450d4ff5 | ths | info->insn_type = dis_dref; |
| 2193 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEMREF; |
| 2194 | 450d4ff5 | ths | |
| 2195 | 450d4ff5 | ths | if (opcodep->imm_oprnd_size == SIZE_FIX_32)
|
| 2196 | 450d4ff5 | ths | size = 4;
|
| 2197 | 450d4ff5 | ths | else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) |
| 2198 | 450d4ff5 | ths | {
|
| 2199 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
| 2200 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
| 2201 | 450d4ff5 | ths | |
| 2202 | 450d4ff5 | ths | /* FIXME: Improve error handling; should have been caught
|
| 2203 | 450d4ff5 | ths | earlier. */
|
| 2204 | 450d4ff5 | ths | if (sregp == NULL) |
| 2205 | 450d4ff5 | ths | size = 4;
|
| 2206 | 450d4ff5 | ths | else
|
| 2207 | 450d4ff5 | ths | size = sregp->reg_size; |
| 2208 | 450d4ff5 | ths | } |
| 2209 | 450d4ff5 | ths | else
|
| 2210 | 450d4ff5 | ths | size = mode_size; |
| 2211 | 450d4ff5 | ths | |
| 2212 | 450d4ff5 | ths | info->data_size = size; |
| 2213 | 450d4ff5 | ths | } |
| 2214 | 450d4ff5 | ths | |
| 2215 | 450d4ff5 | ths | *tp++ = '[';
|
| 2216 | 450d4ff5 | ths | |
| 2217 | 450d4ff5 | ths | if (prefix_opcodep
|
| 2218 | 450d4ff5 | ths | /* We don't match dip with a postincremented field
|
| 2219 | 450d4ff5 | ths | as a side-effect address mode. */
|
| 2220 | 450d4ff5 | ths | && ((insn & 0x400) == 0 |
| 2221 | 450d4ff5 | ths | || prefix_opcodep->match != DIP_OPCODE)) |
| 2222 | 450d4ff5 | ths | {
|
| 2223 | 450d4ff5 | ths | if (insn & 0x400) |
| 2224 | 450d4ff5 | ths | {
|
| 2225 | 450d4ff5 | ths | tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
|
| 2226 | 450d4ff5 | ths | *tp++ = '=';
|
| 2227 | 450d4ff5 | ths | } |
| 2228 | 450d4ff5 | ths | |
| 2229 | 450d4ff5 | ths | |
| 2230 | 450d4ff5 | ths | /* We mainly ignore the prefix format string when the
|
| 2231 | 450d4ff5 | ths | address-mode syntax is output. */
|
| 2232 | 450d4ff5 | ths | switch (prefix_opcodep->match)
|
| 2233 | 450d4ff5 | ths | {
|
| 2234 | 450d4ff5 | ths | case DIP_OPCODE:
|
| 2235 | 450d4ff5 | ths | /* It's [r], [r+] or [pc+]. */
|
| 2236 | 450d4ff5 | ths | if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) |
| 2237 | 450d4ff5 | ths | {
|
| 2238 | 450d4ff5 | ths | /* It's [pc+]. This cannot possibly be anything
|
| 2239 | 450d4ff5 | ths | but an address. */
|
| 2240 | 450d4ff5 | ths | unsigned long number |
| 2241 | 450d4ff5 | ths | = prefix_buffer[2] + prefix_buffer[3] * 256 |
| 2242 | 450d4ff5 | ths | + prefix_buffer[4] * 65536 |
| 2243 | 450d4ff5 | ths | + prefix_buffer[5] * 0x1000000; |
| 2244 | 450d4ff5 | ths | |
| 2245 | 450d4ff5 | ths | info->target = (bfd_vma) number; |
| 2246 | 450d4ff5 | ths | |
| 2247 | 450d4ff5 | ths | /* Finish off and output previous formatted
|
| 2248 | 450d4ff5 | ths | data. */
|
| 2249 | 450d4ff5 | ths | *tp = 0;
|
| 2250 | 450d4ff5 | ths | tp = temp; |
| 2251 | 450d4ff5 | ths | if (temp[0]) |
| 2252 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2253 | 450d4ff5 | ths | |
| 2254 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
| 2255 | 450d4ff5 | ths | } |
| 2256 | 450d4ff5 | ths | else
|
| 2257 | 450d4ff5 | ths | {
|
| 2258 | 450d4ff5 | ths | /* For a memref in an address, we use target2.
|
| 2259 | 450d4ff5 | ths | In this case, target is zero. */
|
| 2260 | 450d4ff5 | ths | info->flags |
| 2261 | 450d4ff5 | ths | |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG |
| 2262 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET2_MEM); |
| 2263 | 450d4ff5 | ths | |
| 2264 | 450d4ff5 | ths | info->target2 = prefix_insn & 15;
|
| 2265 | 450d4ff5 | ths | |
| 2266 | 450d4ff5 | ths | *tp++ = '[';
|
| 2267 | 450d4ff5 | ths | tp = format_reg (disdata, prefix_insn & 15, tp,
|
| 2268 | 450d4ff5 | ths | with_reg_prefix); |
| 2269 | 450d4ff5 | ths | if (prefix_insn & 0x400) |
| 2270 | 450d4ff5 | ths | *tp++ = '+';
|
| 2271 | 450d4ff5 | ths | *tp++ = ']';
|
| 2272 | 450d4ff5 | ths | } |
| 2273 | 450d4ff5 | ths | break;
|
| 2274 | 450d4ff5 | ths | |
| 2275 | 450d4ff5 | ths | case BDAP_QUICK_OPCODE:
|
| 2276 | 450d4ff5 | ths | {
|
| 2277 | 450d4ff5 | ths | int number;
|
| 2278 | 450d4ff5 | ths | |
| 2279 | 450d4ff5 | ths | number = prefix_buffer[0];
|
| 2280 | 450d4ff5 | ths | if (number > 127) |
| 2281 | 450d4ff5 | ths | number -= 256;
|
| 2282 | 450d4ff5 | ths | |
| 2283 | 450d4ff5 | ths | /* Output "reg+num" or, if num < 0, "reg-num". */
|
| 2284 | 450d4ff5 | ths | tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, |
| 2285 | 450d4ff5 | ths | with_reg_prefix); |
| 2286 | 450d4ff5 | ths | if (number >= 0) |
| 2287 | 450d4ff5 | ths | *tp++ = '+';
|
| 2288 | 450d4ff5 | ths | tp = format_dec (number, tp, 1);
|
| 2289 | 450d4ff5 | ths | |
| 2290 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; |
| 2291 | 450d4ff5 | ths | info->target = (prefix_insn >> 12) & 15; |
| 2292 | 450d4ff5 | ths | info->target2 = (bfd_vma) number; |
| 2293 | 450d4ff5 | ths | break;
|
| 2294 | 450d4ff5 | ths | } |
| 2295 | 450d4ff5 | ths | |
| 2296 | 450d4ff5 | ths | case BIAP_OPCODE:
|
| 2297 | 450d4ff5 | ths | /* Output "r+R.m". */
|
| 2298 | 450d4ff5 | ths | tp = format_reg (disdata, prefix_insn & 15, tp,
|
| 2299 | 450d4ff5 | ths | with_reg_prefix); |
| 2300 | 450d4ff5 | ths | *tp++ = '+';
|
| 2301 | 450d4ff5 | ths | tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, |
| 2302 | 450d4ff5 | ths | with_reg_prefix); |
| 2303 | 450d4ff5 | ths | *tp++ = '.';
|
| 2304 | 450d4ff5 | ths | *tp++ = mode_char[(prefix_insn >> 4) & 3]; |
| 2305 | 450d4ff5 | ths | |
| 2306 | 450d4ff5 | ths | info->flags |
| 2307 | 450d4ff5 | ths | |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG |
| 2308 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET_IS_REG |
| 2309 | 450d4ff5 | ths | |
| 2310 | 450d4ff5 | ths | | ((prefix_insn & 0x8000)
|
| 2311 | 450d4ff5 | ths | ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 |
| 2312 | 450d4ff5 | ths | : ((prefix_insn & 0x8000)
|
| 2313 | 450d4ff5 | ths | ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
|
| 2314 | 450d4ff5 | ths | |
| 2315 | 450d4ff5 | ths | /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
|
| 2316 | 450d4ff5 | ths | if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f) |
| 2317 | 450d4ff5 | ths | /* Then start interpreting data as offsets. */
|
| 2318 | 450d4ff5 | ths | case_offset_counter = no_of_case_offsets; |
| 2319 | 450d4ff5 | ths | break;
|
| 2320 | 450d4ff5 | ths | |
| 2321 | 450d4ff5 | ths | case BDAP_INDIR_OPCODE:
|
| 2322 | 450d4ff5 | ths | /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
|
| 2323 | 450d4ff5 | ths | "r-s". */
|
| 2324 | 450d4ff5 | ths | tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, |
| 2325 | 450d4ff5 | ths | with_reg_prefix); |
| 2326 | 450d4ff5 | ths | |
| 2327 | 450d4ff5 | ths | if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) |
| 2328 | 450d4ff5 | ths | {
|
| 2329 | 450d4ff5 | ths | long number;
|
| 2330 | 450d4ff5 | ths | unsigned int nbytes; |
| 2331 | 450d4ff5 | ths | |
| 2332 | 450d4ff5 | ths | /* It's a value. Get its size. */
|
| 2333 | 450d4ff5 | ths | int mode_size = 1 << ((prefix_insn >> 4) & 3); |
| 2334 | 450d4ff5 | ths | |
| 2335 | 450d4ff5 | ths | if (mode_size == 1) |
| 2336 | 450d4ff5 | ths | nbytes = 2;
|
| 2337 | 450d4ff5 | ths | else
|
| 2338 | 450d4ff5 | ths | nbytes = mode_size; |
| 2339 | 450d4ff5 | ths | |
| 2340 | 450d4ff5 | ths | switch (nbytes)
|
| 2341 | 450d4ff5 | ths | {
|
| 2342 | 450d4ff5 | ths | case 1: |
| 2343 | 450d4ff5 | ths | number = prefix_buffer[2];
|
| 2344 | 450d4ff5 | ths | if (number > 127) |
| 2345 | 450d4ff5 | ths | number -= 256;
|
| 2346 | 450d4ff5 | ths | break;
|
| 2347 | 450d4ff5 | ths | |
| 2348 | 450d4ff5 | ths | case 2: |
| 2349 | 450d4ff5 | ths | number = prefix_buffer[2] + prefix_buffer[3] * 256; |
| 2350 | 450d4ff5 | ths | if (number > 32767) |
| 2351 | 450d4ff5 | ths | number -= 65536;
|
| 2352 | 450d4ff5 | ths | break;
|
| 2353 | 450d4ff5 | ths | |
| 2354 | 450d4ff5 | ths | case 4: |
| 2355 | 450d4ff5 | ths | number |
| 2356 | 450d4ff5 | ths | = prefix_buffer[2] + prefix_buffer[3] * 256 |
| 2357 | 450d4ff5 | ths | + prefix_buffer[4] * 65536 |
| 2358 | 450d4ff5 | ths | + prefix_buffer[5] * 0x1000000; |
| 2359 | 450d4ff5 | ths | break;
|
| 2360 | 450d4ff5 | ths | |
| 2361 | 450d4ff5 | ths | default:
|
| 2362 | 450d4ff5 | ths | strcpy (tp, "bug");
|
| 2363 | 450d4ff5 | ths | tp += 3;
|
| 2364 | 450d4ff5 | ths | number = 42;
|
| 2365 | 450d4ff5 | ths | } |
| 2366 | 450d4ff5 | ths | |
| 2367 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; |
| 2368 | 450d4ff5 | ths | info->target2 = (bfd_vma) number; |
| 2369 | 450d4ff5 | ths | |
| 2370 | 450d4ff5 | ths | /* If the size is dword, then assume it's an
|
| 2371 | 450d4ff5 | ths | address. */
|
| 2372 | 450d4ff5 | ths | if (nbytes == 4) |
| 2373 | 450d4ff5 | ths | {
|
| 2374 | 450d4ff5 | ths | /* Finish off and output previous formatted
|
| 2375 | 450d4ff5 | ths | bytes. */
|
| 2376 | 450d4ff5 | ths | *tp++ = '+';
|
| 2377 | 450d4ff5 | ths | *tp = 0;
|
| 2378 | 450d4ff5 | ths | tp = temp; |
| 2379 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2380 | 450d4ff5 | ths | |
| 2381 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
| 2382 | 450d4ff5 | ths | } |
| 2383 | 450d4ff5 | ths | else
|
| 2384 | 450d4ff5 | ths | {
|
| 2385 | 450d4ff5 | ths | if (number >= 0) |
| 2386 | 450d4ff5 | ths | *tp++ = '+';
|
| 2387 | 450d4ff5 | ths | tp = format_dec (number, tp, 1);
|
| 2388 | 450d4ff5 | ths | } |
| 2389 | 450d4ff5 | ths | } |
| 2390 | 450d4ff5 | ths | else
|
| 2391 | 450d4ff5 | ths | {
|
| 2392 | 450d4ff5 | ths | /* Output "r+[R].m" or "r+[R+].m". */
|
| 2393 | 450d4ff5 | ths | *tp++ = '+';
|
| 2394 | 450d4ff5 | ths | *tp++ = '[';
|
| 2395 | 450d4ff5 | ths | tp = format_reg (disdata, prefix_insn & 15, tp,
|
| 2396 | 450d4ff5 | ths | with_reg_prefix); |
| 2397 | 450d4ff5 | ths | if (prefix_insn & 0x400) |
| 2398 | 450d4ff5 | ths | *tp++ = '+';
|
| 2399 | 450d4ff5 | ths | *tp++ = ']';
|
| 2400 | 450d4ff5 | ths | *tp++ = '.';
|
| 2401 | 450d4ff5 | ths | *tp++ = mode_char[(prefix_insn >> 4) & 3]; |
| 2402 | 450d4ff5 | ths | |
| 2403 | 450d4ff5 | ths | info->flags |
| 2404 | 450d4ff5 | ths | |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG |
| 2405 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET2_MEM |
| 2406 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET_IS_REG |
| 2407 | 450d4ff5 | ths | |
| 2408 | 450d4ff5 | ths | | (((prefix_insn >> 4) == 2) |
| 2409 | 450d4ff5 | ths | ? 0
|
| 2410 | 450d4ff5 | ths | : (((prefix_insn >> 4) & 3) == 1 |
| 2411 | 450d4ff5 | ths | ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD |
| 2412 | 450d4ff5 | ths | : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); |
| 2413 | 450d4ff5 | ths | } |
| 2414 | 450d4ff5 | ths | break;
|
| 2415 | 450d4ff5 | ths | |
| 2416 | 450d4ff5 | ths | default:
|
| 2417 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "?prefix-bug");
|
| 2418 | 450d4ff5 | ths | } |
| 2419 | 450d4ff5 | ths | |
| 2420 | 450d4ff5 | ths | /* To mark that the prefix is used, reset it. */
|
| 2421 | 450d4ff5 | ths | prefix_opcodep = NULL;
|
| 2422 | 450d4ff5 | ths | } |
| 2423 | 450d4ff5 | ths | else
|
| 2424 | 450d4ff5 | ths | {
|
| 2425 | 450d4ff5 | ths | tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
|
| 2426 | 450d4ff5 | ths | |
| 2427 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; |
| 2428 | 450d4ff5 | ths | info->target = insn & 15;
|
| 2429 | 450d4ff5 | ths | |
| 2430 | 450d4ff5 | ths | if (insn & 0x400) |
| 2431 | 450d4ff5 | ths | *tp++ = '+';
|
| 2432 | 450d4ff5 | ths | } |
| 2433 | 450d4ff5 | ths | *tp++ = ']';
|
| 2434 | 450d4ff5 | ths | } |
| 2435 | 450d4ff5 | ths | break;
|
| 2436 | 450d4ff5 | ths | |
| 2437 | 450d4ff5 | ths | case 'x': |
| 2438 | 450d4ff5 | ths | tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); |
| 2439 | 450d4ff5 | ths | *tp++ = '.';
|
| 2440 | 450d4ff5 | ths | *tp++ = mode_char[(insn >> 4) & 3]; |
| 2441 | 450d4ff5 | ths | break;
|
| 2442 | 450d4ff5 | ths | |
| 2443 | 450d4ff5 | ths | case 'I': |
| 2444 | 450d4ff5 | ths | tp = format_dec (insn & 63, tp, 0); |
| 2445 | 450d4ff5 | ths | break;
|
| 2446 | 450d4ff5 | ths | |
| 2447 | 450d4ff5 | ths | case 'b': |
| 2448 | 450d4ff5 | ths | {
|
| 2449 | 450d4ff5 | ths | int where = buffer[2] + buffer[3] * 256; |
| 2450 | 450d4ff5 | ths | |
| 2451 | 450d4ff5 | ths | if (where > 32767) |
| 2452 | 450d4ff5 | ths | where -= 65536;
|
| 2453 | 450d4ff5 | ths | |
| 2454 | 450d4ff5 | ths | where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4); |
| 2455 | 450d4ff5 | ths | |
| 2456 | 450d4ff5 | ths | if (insn == BA_PC_INCR_OPCODE)
|
| 2457 | 450d4ff5 | ths | info->insn_type = dis_branch; |
| 2458 | 450d4ff5 | ths | else
|
| 2459 | 450d4ff5 | ths | info->insn_type = dis_condbranch; |
| 2460 | 450d4ff5 | ths | |
| 2461 | 450d4ff5 | ths | info->target = (bfd_vma) where; |
| 2462 | 450d4ff5 | ths | |
| 2463 | 450d4ff5 | ths | *tp = 0;
|
| 2464 | 450d4ff5 | ths | tp = temp; |
| 2465 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s%s ",
|
| 2466 | 450d4ff5 | ths | temp, cris_cc_strings[insn >> 12]);
|
| 2467 | 450d4ff5 | ths | |
| 2468 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) where, info); |
| 2469 | 450d4ff5 | ths | } |
| 2470 | 450d4ff5 | ths | break;
|
| 2471 | 450d4ff5 | ths | |
| 2472 | 450d4ff5 | ths | case 'c': |
| 2473 | 450d4ff5 | ths | tp = format_dec (insn & 31, tp, 0); |
| 2474 | 450d4ff5 | ths | break;
|
| 2475 | 450d4ff5 | ths | |
| 2476 | 450d4ff5 | ths | case 'C': |
| 2477 | 450d4ff5 | ths | tp = format_dec (insn & 15, tp, 0); |
| 2478 | 450d4ff5 | ths | break;
|
| 2479 | 450d4ff5 | ths | |
| 2480 | 450d4ff5 | ths | case 'o': |
| 2481 | 450d4ff5 | ths | {
|
| 2482 | 450d4ff5 | ths | long offset = insn & 0xfe; |
| 2483 | 450d4ff5 | ths | bfd_vma target; |
| 2484 | 450d4ff5 | ths | |
| 2485 | 450d4ff5 | ths | if (insn & 1) |
| 2486 | 450d4ff5 | ths | offset |= ~0xff;
|
| 2487 | 450d4ff5 | ths | |
| 2488 | 450d4ff5 | ths | if (opcodep->match == BA_QUICK_OPCODE)
|
| 2489 | 450d4ff5 | ths | info->insn_type = dis_branch; |
| 2490 | 450d4ff5 | ths | else
|
| 2491 | 450d4ff5 | ths | info->insn_type = dis_condbranch; |
| 2492 | 450d4ff5 | ths | |
| 2493 | 450d4ff5 | ths | target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset; |
| 2494 | 450d4ff5 | ths | info->target = target; |
| 2495 | 450d4ff5 | ths | *tp = 0;
|
| 2496 | 450d4ff5 | ths | tp = temp; |
| 2497 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2498 | 450d4ff5 | ths | (*info->print_address_func) (target, info); |
| 2499 | 450d4ff5 | ths | } |
| 2500 | 450d4ff5 | ths | break;
|
| 2501 | 450d4ff5 | ths | |
| 2502 | 450d4ff5 | ths | case 'Q': |
| 2503 | 450d4ff5 | ths | case 'O': |
| 2504 | 450d4ff5 | ths | {
|
| 2505 | 450d4ff5 | ths | long number = buffer[0]; |
| 2506 | 450d4ff5 | ths | |
| 2507 | 450d4ff5 | ths | if (number > 127) |
| 2508 | 450d4ff5 | ths | number = number - 256;
|
| 2509 | 450d4ff5 | ths | |
| 2510 | 450d4ff5 | ths | tp = format_dec (number, tp, 1);
|
| 2511 | 450d4ff5 | ths | *tp++ = ',';
|
| 2512 | 450d4ff5 | ths | tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); |
| 2513 | 450d4ff5 | ths | } |
| 2514 | 450d4ff5 | ths | break;
|
| 2515 | 450d4ff5 | ths | |
| 2516 | 450d4ff5 | ths | case 'f': |
| 2517 | 450d4ff5 | ths | tp = print_flags (disdata, insn, tp); |
| 2518 | 450d4ff5 | ths | break;
|
| 2519 | 450d4ff5 | ths | |
| 2520 | 450d4ff5 | ths | case 'i': |
| 2521 | 450d4ff5 | ths | tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1); |
| 2522 | 450d4ff5 | ths | break;
|
| 2523 | 450d4ff5 | ths | |
| 2524 | 450d4ff5 | ths | case 'P': |
| 2525 | 450d4ff5 | ths | {
|
| 2526 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
| 2527 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
| 2528 | 450d4ff5 | ths | |
| 2529 | 450d4ff5 | ths | if (sregp->name == NULL) |
| 2530 | 450d4ff5 | ths | /* Should have been caught as a non-match eariler. */
|
| 2531 | 450d4ff5 | ths | *tp++ = '?';
|
| 2532 | 450d4ff5 | ths | else
|
| 2533 | 450d4ff5 | ths | {
|
| 2534 | 450d4ff5 | ths | if (with_reg_prefix)
|
| 2535 | 450d4ff5 | ths | *tp++ = REGISTER_PREFIX_CHAR; |
| 2536 | 450d4ff5 | ths | strcpy (tp, sregp->name); |
| 2537 | 450d4ff5 | ths | tp += strlen (tp); |
| 2538 | 450d4ff5 | ths | } |
| 2539 | 450d4ff5 | ths | } |
| 2540 | 450d4ff5 | ths | break;
|
| 2541 | 450d4ff5 | ths | |
| 2542 | 450d4ff5 | ths | default:
|
| 2543 | 450d4ff5 | ths | strcpy (tp, "???");
|
| 2544 | 450d4ff5 | ths | tp += 3;
|
| 2545 | 450d4ff5 | ths | } |
| 2546 | 450d4ff5 | ths | } |
| 2547 | 450d4ff5 | ths | |
| 2548 | 450d4ff5 | ths | *tp = 0;
|
| 2549 | 450d4ff5 | ths | |
| 2550 | 450d4ff5 | ths | if (prefix_opcodep)
|
| 2551 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
|
| 2552 | 450d4ff5 | ths | prefix_opcodep->name, prefix_opcodep->args); |
| 2553 | 450d4ff5 | ths | |
| 2554 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
| 2555 | 450d4ff5 | ths | |
| 2556 | 450d4ff5 | ths | /* Get info for matching case-tables, if we don't have any active.
|
| 2557 | 450d4ff5 | ths | We assume that the last constant seen is used; either in the insn
|
| 2558 | 450d4ff5 | ths | itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
|
| 2559 | 450d4ff5 | ths | if (TRACE_CASE && case_offset_counter == 0) |
| 2560 | 450d4ff5 | ths | {
|
| 2561 | 450d4ff5 | ths | if (CONST_STRNEQ (opcodep->name, "sub")) |
| 2562 | 450d4ff5 | ths | case_offset = last_immediate; |
| 2563 | 450d4ff5 | ths | |
| 2564 | 450d4ff5 | ths | /* It could also be an "add", if there are negative case-values. */
|
| 2565 | 450d4ff5 | ths | else if (CONST_STRNEQ (opcodep->name, "add")) |
| 2566 | 450d4ff5 | ths | /* The first case is the negated operand to the add. */
|
| 2567 | 450d4ff5 | ths | case_offset = -last_immediate; |
| 2568 | 450d4ff5 | ths | |
| 2569 | 450d4ff5 | ths | /* A bound insn will tell us the number of cases. */
|
| 2570 | 450d4ff5 | ths | else if (CONST_STRNEQ (opcodep->name, "bound")) |
| 2571 | 450d4ff5 | ths | no_of_case_offsets = last_immediate + 1;
|
| 2572 | 450d4ff5 | ths | |
| 2573 | 450d4ff5 | ths | /* A jump or jsr or branch breaks the chain of insns for a
|
| 2574 | 450d4ff5 | ths | case-table, so assume default first-case again. */
|
| 2575 | 450d4ff5 | ths | else if (info->insn_type == dis_jsr |
| 2576 | 450d4ff5 | ths | || info->insn_type == dis_branch |
| 2577 | 450d4ff5 | ths | || info->insn_type == dis_condbranch) |
| 2578 | 450d4ff5 | ths | case_offset = 0;
|
| 2579 | 450d4ff5 | ths | } |
| 2580 | 450d4ff5 | ths | } |
| 2581 | 450d4ff5 | ths | |
| 2582 | 450d4ff5 | ths | |
| 2583 | 450d4ff5 | ths | /* Print the CRIS instruction at address memaddr on stream. Returns
|
| 2584 | 450d4ff5 | ths | length of the instruction, in bytes. Prefix register names with `$' if
|
| 2585 | 450d4ff5 | ths | WITH_REG_PREFIX. */
|
| 2586 | 450d4ff5 | ths | |
| 2587 | 450d4ff5 | ths | static int |
| 2588 | 450d4ff5 | ths | print_insn_cris_generic (bfd_vma memaddr, |
| 2589 | 450d4ff5 | ths | disassemble_info *info, |
| 2590 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
| 2591 | 450d4ff5 | ths | {
|
| 2592 | 450d4ff5 | ths | int nbytes;
|
| 2593 | 450d4ff5 | ths | unsigned int insn; |
| 2594 | 450d4ff5 | ths | const struct cris_opcode *matchedp; |
| 2595 | 450d4ff5 | ths | int advance = 0; |
| 2596 | 450d4ff5 | ths | struct cris_disasm_data *disdata
|
| 2597 | 450d4ff5 | ths | = (struct cris_disasm_data *) info->private_data;
|
| 2598 | 450d4ff5 | ths | |
| 2599 | 450d4ff5 | ths | /* No instruction will be disassembled as longer than this number of
|
| 2600 | 450d4ff5 | ths | bytes; stacked prefixes will not be expanded. */
|
| 2601 | 450d4ff5 | ths | unsigned char buffer[MAX_BYTES_PER_CRIS_INSN]; |
| 2602 | 450d4ff5 | ths | unsigned char *bufp; |
| 2603 | 450d4ff5 | ths | int status = 0; |
| 2604 | 450d4ff5 | ths | bfd_vma addr; |
| 2605 | 450d4ff5 | ths | |
| 2606 | 450d4ff5 | ths | /* There will be an "out of range" error after the last instruction.
|
| 2607 | 450d4ff5 | ths | Reading pairs of bytes in decreasing number, we hope that we will get
|
| 2608 | 450d4ff5 | ths | at least the amount that we will consume.
|
| 2609 | 450d4ff5 | ths | |
| 2610 | 450d4ff5 | ths | If we can't get any data, or we do not get enough data, we print
|
| 2611 | 450d4ff5 | ths | the error message. */
|
| 2612 | 450d4ff5 | ths | |
| 2613 | bfaf9a43 | edgar_igl | nbytes = info->buffer_length; |
| 2614 | bfaf9a43 | edgar_igl | if (nbytes > MAX_BYTES_PER_CRIS_INSN)
|
| 2615 | bfaf9a43 | edgar_igl | nbytes = MAX_BYTES_PER_CRIS_INSN; |
| 2616 | bfaf9a43 | edgar_igl | status = (*info->read_memory_func) (memaddr, buffer, nbytes, info); |
| 2617 | 450d4ff5 | ths | |
| 2618 | 450d4ff5 | ths | /* If we did not get all we asked for, then clear the rest.
|
| 2619 | 450d4ff5 | ths | Hopefully this makes a reproducible result in case of errors. */
|
| 2620 | 450d4ff5 | ths | if (nbytes != MAX_BYTES_PER_CRIS_INSN)
|
| 2621 | 450d4ff5 | ths | memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
|
| 2622 | 450d4ff5 | ths | |
| 2623 | 450d4ff5 | ths | addr = memaddr; |
| 2624 | 450d4ff5 | ths | bufp = buffer; |
| 2625 | 450d4ff5 | ths | |
| 2626 | 450d4ff5 | ths | /* Set some defaults for the insn info. */
|
| 2627 | 450d4ff5 | ths | info->insn_info_valid = 1;
|
| 2628 | 450d4ff5 | ths | info->branch_delay_insns = 0;
|
| 2629 | 450d4ff5 | ths | info->data_size = 0;
|
| 2630 | 450d4ff5 | ths | info->insn_type = dis_nonbranch; |
| 2631 | 450d4ff5 | ths | info->flags = 0;
|
| 2632 | 450d4ff5 | ths | info->target = 0;
|
| 2633 | 450d4ff5 | ths | info->target2 = 0;
|
| 2634 | 450d4ff5 | ths | |
| 2635 | 450d4ff5 | ths | /* If we got any data, disassemble it. */
|
| 2636 | 450d4ff5 | ths | if (nbytes != 0) |
| 2637 | 450d4ff5 | ths | {
|
| 2638 | 450d4ff5 | ths | matchedp = NULL;
|
| 2639 | 450d4ff5 | ths | |
| 2640 | 450d4ff5 | ths | insn = bufp[0] + bufp[1] * 256; |
| 2641 | 450d4ff5 | ths | |
| 2642 | 450d4ff5 | ths | /* If we're in a case-table, don't disassemble the offsets. */
|
| 2643 | 450d4ff5 | ths | if (TRACE_CASE && case_offset_counter != 0) |
| 2644 | 450d4ff5 | ths | {
|
| 2645 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
| 2646 | 450d4ff5 | ths | advance += 2;
|
| 2647 | 450d4ff5 | ths | |
| 2648 | 450d4ff5 | ths | /* If to print data as offsets, then shortcut here. */
|
| 2649 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
|
| 2650 | 450d4ff5 | ths | case_offset + no_of_case_offsets |
| 2651 | 450d4ff5 | ths | - case_offset_counter, |
| 2652 | 450d4ff5 | ths | case_offset_counter == 1 ? "/default" : |
| 2653 | 450d4ff5 | ths | "");
|
| 2654 | 450d4ff5 | ths | |
| 2655 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) |
| 2656 | 450d4ff5 | ths | ((short) (insn)
|
| 2657 | 450d4ff5 | ths | + (long) (addr
|
| 2658 | 450d4ff5 | ths | - (no_of_case_offsets |
| 2659 | 450d4ff5 | ths | - case_offset_counter) |
| 2660 | 450d4ff5 | ths | * 2)), info);
|
| 2661 | 450d4ff5 | ths | case_offset_counter--; |
| 2662 | 450d4ff5 | ths | |
| 2663 | 450d4ff5 | ths | /* The default case start (without a "sub" or "add") must be
|
| 2664 | 450d4ff5 | ths | zero. */
|
| 2665 | 450d4ff5 | ths | if (case_offset_counter == 0) |
| 2666 | 450d4ff5 | ths | case_offset = 0;
|
| 2667 | 450d4ff5 | ths | } |
| 2668 | 450d4ff5 | ths | else if (insn == 0) |
| 2669 | 450d4ff5 | ths | {
|
| 2670 | 450d4ff5 | ths | /* We're often called to disassemble zeroes. While this is a
|
| 2671 | 450d4ff5 | ths | valid "bcc .+2" insn, it is also useless enough and enough
|
| 2672 | 450d4ff5 | ths | of a nuiscance that we will just output "bcc .+2" for it
|
| 2673 | 450d4ff5 | ths | and signal it as a noninsn. */
|
| 2674 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, |
| 2675 | 450d4ff5 | ths | disdata->distype == cris_dis_v32 |
| 2676 | 450d4ff5 | ths | ? "bcc ." : "bcc .+2"); |
| 2677 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
| 2678 | 450d4ff5 | ths | advance += 2;
|
| 2679 | 450d4ff5 | ths | } |
| 2680 | 450d4ff5 | ths | else
|
| 2681 | 450d4ff5 | ths | {
|
| 2682 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep = NULL; |
| 2683 | 450d4ff5 | ths | unsigned char *prefix_buffer = bufp; |
| 2684 | 450d4ff5 | ths | unsigned int prefix_insn = insn; |
| 2685 | 450d4ff5 | ths | int prefix_size = 0; |
| 2686 | 450d4ff5 | ths | |
| 2687 | 450d4ff5 | ths | matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); |
| 2688 | 450d4ff5 | ths | |
| 2689 | 450d4ff5 | ths | /* Check if we're supposed to write out prefixes as address
|
| 2690 | 450d4ff5 | ths | modes and if this was a prefix. */
|
| 2691 | 450d4ff5 | ths | if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p') |
| 2692 | 450d4ff5 | ths | {
|
| 2693 | 450d4ff5 | ths | /* If it's a prefix, put it into the prefix vars and get the
|
| 2694 | 450d4ff5 | ths | main insn. */
|
| 2695 | 450d4ff5 | ths | prefix_size = bytes_to_skip (prefix_insn, matchedp, |
| 2696 | 450d4ff5 | ths | disdata->distype, NULL);
|
| 2697 | 450d4ff5 | ths | prefix_opcodep = matchedp; |
| 2698 | 450d4ff5 | ths | |
| 2699 | 450d4ff5 | ths | insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256; |
| 2700 | 450d4ff5 | ths | matchedp = get_opcode_entry (insn, prefix_insn, disdata); |
| 2701 | 450d4ff5 | ths | |
| 2702 | 450d4ff5 | ths | if (matchedp != NULL) |
| 2703 | 450d4ff5 | ths | {
|
| 2704 | 450d4ff5 | ths | addr += prefix_size; |
| 2705 | 450d4ff5 | ths | bufp += prefix_size; |
| 2706 | 450d4ff5 | ths | advance += prefix_size; |
| 2707 | 450d4ff5 | ths | } |
| 2708 | 450d4ff5 | ths | else
|
| 2709 | 450d4ff5 | ths | {
|
| 2710 | 450d4ff5 | ths | /* The "main" insn wasn't valid, at least not when
|
| 2711 | 450d4ff5 | ths | prefixed. Put back things enough to output the
|
| 2712 | 450d4ff5 | ths | prefix insn only, as a normal insn. */
|
| 2713 | 450d4ff5 | ths | matchedp = prefix_opcodep; |
| 2714 | 450d4ff5 | ths | insn = prefix_insn; |
| 2715 | 450d4ff5 | ths | prefix_opcodep = NULL;
|
| 2716 | 450d4ff5 | ths | } |
| 2717 | 450d4ff5 | ths | } |
| 2718 | 450d4ff5 | ths | |
| 2719 | 450d4ff5 | ths | if (matchedp == NULL) |
| 2720 | 450d4ff5 | ths | {
|
| 2721 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "??0x%x", insn);
|
| 2722 | 450d4ff5 | ths | advance += 2;
|
| 2723 | 450d4ff5 | ths | |
| 2724 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
| 2725 | 450d4ff5 | ths | } |
| 2726 | 450d4ff5 | ths | else
|
| 2727 | 450d4ff5 | ths | {
|
| 2728 | 450d4ff5 | ths | advance |
| 2729 | 450d4ff5 | ths | += bytes_to_skip (insn, matchedp, disdata->distype, |
| 2730 | 450d4ff5 | ths | prefix_opcodep); |
| 2731 | 450d4ff5 | ths | |
| 2732 | 450d4ff5 | ths | /* The info_type and assorted fields will be set according
|
| 2733 | 450d4ff5 | ths | to the operands. */
|
| 2734 | 450d4ff5 | ths | print_with_operands (matchedp, insn, bufp, addr, info, |
| 2735 | 450d4ff5 | ths | prefix_opcodep, prefix_insn, |
| 2736 | 450d4ff5 | ths | prefix_buffer, with_reg_prefix); |
| 2737 | 450d4ff5 | ths | } |
| 2738 | 450d4ff5 | ths | } |
| 2739 | 450d4ff5 | ths | } |
| 2740 | 450d4ff5 | ths | else
|
| 2741 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
| 2742 | 450d4ff5 | ths | |
| 2743 | 450d4ff5 | ths | /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
|
| 2744 | 450d4ff5 | ths | status when reading that much, and the insn decoding indicated a
|
| 2745 | 450d4ff5 | ths | length exceeding what we read, there is an error. */
|
| 2746 | 450d4ff5 | ths | if (status != 0 && (nbytes == 0 || advance > nbytes)) |
| 2747 | 450d4ff5 | ths | {
|
| 2748 | 450d4ff5 | ths | (*info->memory_error_func) (status, memaddr, info); |
| 2749 | 450d4ff5 | ths | return -1; |
| 2750 | 450d4ff5 | ths | } |
| 2751 | 450d4ff5 | ths | |
| 2752 | 450d4ff5 | ths | /* Max supported insn size with one folded prefix insn. */
|
| 2753 | 450d4ff5 | ths | info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN; |
| 2754 | 450d4ff5 | ths | |
| 2755 | 450d4ff5 | ths | /* I would like to set this to a fixed value larger than the actual
|
| 2756 | 450d4ff5 | ths | number of bytes to print in order to avoid spaces between bytes,
|
| 2757 | 450d4ff5 | ths | but objdump.c (2.9.1) does not like that, so we print 16-bit
|
| 2758 | 450d4ff5 | ths | chunks, which is the next choice. */
|
| 2759 | 450d4ff5 | ths | info->bytes_per_chunk = 2;
|
| 2760 | 450d4ff5 | ths | |
| 2761 | 450d4ff5 | ths | /* Printing bytes in order of increasing addresses makes sense,
|
| 2762 | 450d4ff5 | ths | especially on a little-endian target.
|
| 2763 | 450d4ff5 | ths | This is completely the opposite of what you think; setting this to
|
| 2764 | 450d4ff5 | ths | BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
|
| 2765 | 450d4ff5 | ths | we want. */
|
| 2766 | 450d4ff5 | ths | info->display_endian = BFD_ENDIAN_BIG; |
| 2767 | 450d4ff5 | ths | |
| 2768 | 450d4ff5 | ths | return advance;
|
| 2769 | 450d4ff5 | ths | } |
| 2770 | 450d4ff5 | ths | |
| 2771 | 450d4ff5 | ths | /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
|
| 2772 | 450d4ff5 | ths | #if 0
|
| 2773 | 450d4ff5 | ths | static int
|
| 2774 | 450d4ff5 | ths | print_insn_cris_with_register_prefix (bfd_vma vma,
|
| 2775 | 450d4ff5 | ths | disassemble_info *info)
|
| 2776 | 450d4ff5 | ths | {
|
| 2777 | 450d4ff5 | ths | if (info->private_data == NULL
|
| 2778 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
|
| 2779 | 450d4ff5 | ths | return -1;
|
| 2780 | 47cbc7aa | Juan Quintela | return print_insn_cris_generic (vma, info, true);
|
| 2781 | 450d4ff5 | ths | }
|
| 2782 | 450d4ff5 | ths | #endif
|
| 2783 | 450d4ff5 | ths | /* Disassemble, prefixing register names with `$'. CRIS v32. */
|
| 2784 | 450d4ff5 | ths | |
| 2785 | 450d4ff5 | ths | static int |
| 2786 | 450d4ff5 | ths | print_insn_crisv32_with_register_prefix (bfd_vma vma, |
| 2787 | 450d4ff5 | ths | disassemble_info *info) |
| 2788 | 450d4ff5 | ths | {
|
| 2789 | 450d4ff5 | ths | if (info->private_data == NULL |
| 2790 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v32)) |
| 2791 | 450d4ff5 | ths | return -1; |
| 2792 | 47cbc7aa | Juan Quintela | return print_insn_cris_generic (vma, info, true); |
| 2793 | 450d4ff5 | ths | } |
| 2794 | 450d4ff5 | ths | |
| 2795 | 450d4ff5 | ths | #if 0
|
| 2796 | 450d4ff5 | ths | /* Disassemble, prefixing register names with `$'.
|
| 2797 | 450d4ff5 | ths | Common v10 and v32 subset. */
|
| 2798 | 450d4ff5 | ths | |
| 2799 | 450d4ff5 | ths | static int
|
| 2800 | 450d4ff5 | ths | print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
|
| 2801 | 450d4ff5 | ths | disassemble_info *info)
|
| 2802 | 450d4ff5 | ths | {
|
| 2803 | 450d4ff5 | ths | if (info->private_data == NULL
|
| 2804 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
|
| 2805 | 450d4ff5 | ths | return -1;
|
| 2806 | 47cbc7aa | Juan Quintela | return print_insn_cris_generic (vma, info, true);
|
| 2807 | 450d4ff5 | ths | }
|
| 2808 | 450d4ff5 | ths | |
| 2809 | 450d4ff5 | ths | /* Disassemble, no prefixes on register names. CRIS v0..v10. */
|
| 2810 | 450d4ff5 | ths | |
| 2811 | 450d4ff5 | ths | static int
|
| 2812 | 450d4ff5 | ths | print_insn_cris_without_register_prefix (bfd_vma vma,
|
| 2813 | 450d4ff5 | ths | disassemble_info *info)
|
| 2814 | 450d4ff5 | ths | {
|
| 2815 | 450d4ff5 | ths | if (info->private_data == NULL
|
| 2816 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
|
| 2817 | 450d4ff5 | ths | return -1;
|
| 2818 | 47cbc7aa | Juan Quintela | return print_insn_cris_generic (vma, info, false);
|
| 2819 | 450d4ff5 | ths | }
|
| 2820 | 450d4ff5 | ths | |
| 2821 | 450d4ff5 | ths | /* Disassemble, no prefixes on register names. CRIS v32. */
|
| 2822 | 450d4ff5 | ths | |
| 2823 | 450d4ff5 | ths | static int
|
| 2824 | 450d4ff5 | ths | print_insn_crisv32_without_register_prefix (bfd_vma vma,
|
| 2825 | 450d4ff5 | ths | disassemble_info *info)
|
| 2826 | 450d4ff5 | ths | {
|
| 2827 | 450d4ff5 | ths | if (info->private_data == NULL
|
| 2828 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v32))
|
| 2829 | 450d4ff5 | ths | return -1;
|
| 2830 | 47cbc7aa | Juan Quintela | return print_insn_cris_generic (vma, info, false);
|
| 2831 | 450d4ff5 | ths | }
|
| 2832 | 450d4ff5 | ths | |
| 2833 | 450d4ff5 | ths | /* Disassemble, no prefixes on register names.
|
| 2834 | 450d4ff5 | ths | Common v10 and v32 subset. */
|
| 2835 | 450d4ff5 | ths | |
| 2836 | 450d4ff5 | ths | static int
|
| 2837 | 450d4ff5 | ths | print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
|
| 2838 | 450d4ff5 | ths | disassemble_info *info)
|
| 2839 | 450d4ff5 | ths | {
|
| 2840 | 450d4ff5 | ths | if (info->private_data == NULL
|
| 2841 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
|
| 2842 | 450d4ff5 | ths | return -1;
|
| 2843 | 47cbc7aa | Juan Quintela | return print_insn_cris_generic (vma, info, false);
|
| 2844 | 450d4ff5 | ths | }
|
| 2845 | 450d4ff5 | ths | #endif
|
| 2846 | 450d4ff5 | ths | |
| 2847 | 450d4ff5 | ths | int
|
| 2848 | 450d4ff5 | ths | print_insn_crisv32 (bfd_vma vma, |
| 2849 | 450d4ff5 | ths | disassemble_info *info) |
| 2850 | 450d4ff5 | ths | {
|
| 2851 | 450d4ff5 | ths | return print_insn_crisv32_with_register_prefix(vma, info);
|
| 2852 | 450d4ff5 | ths | } |
| 2853 | 450d4ff5 | ths | |
| 2854 | 450d4ff5 | ths | /* Return a disassembler-function that prints registers with a `$' prefix,
|
| 2855 | 450d4ff5 | ths | or one that prints registers without a prefix.
|
| 2856 | 450d4ff5 | ths | FIXME: We should improve the solution to avoid the multitude of
|
| 2857 | 450d4ff5 | ths | functions seen above. */
|
| 2858 | 450d4ff5 | ths | #if 0
|
| 2859 | 450d4ff5 | ths | disassembler_ftype
|
| 2860 | 450d4ff5 | ths | cris_get_disassembler (bfd *abfd)
|
| 2861 | 450d4ff5 | ths | {
|
| 2862 | 450d4ff5 | ths | /* If there's no bfd in sight, we return what is valid as input in all
|
| 2863 | 450d4ff5 | ths | contexts if fed back to the assembler: disassembly *with* register
|
| 2864 | 450d4ff5 | ths | prefix. Unfortunately this will be totally wrong for v32. */
|
| 2865 | 450d4ff5 | ths | if (abfd == NULL)
|
| 2866 | 450d4ff5 | ths | return print_insn_cris_with_register_prefix;
|
| 2867 | 450d4ff5 | ths | |
| 2868 | 450d4ff5 | ths | if (bfd_get_symbol_leading_char (abfd) == 0)
|
| 2869 | 450d4ff5 | ths | {
|
| 2870 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
|
| 2871 | 450d4ff5 | ths | return print_insn_crisv32_with_register_prefix;
|
| 2872 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
|
| 2873 | 450d4ff5 | ths | return print_insn_crisv10_v32_with_register_prefix;
|
| 2874 | 450d4ff5 | ths | |
| 2875 | 450d4ff5 | ths | /* We default to v10. This may be specifically specified in the
|
| 2876 | 450d4ff5 | ths | bfd mach, but is also the default setting. */
|
| 2877 | 450d4ff5 | ths | return print_insn_cris_with_register_prefix;
|
| 2878 | 450d4ff5 | ths | }
|
| 2879 | 450d4ff5 | ths | |
| 2880 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
|
| 2881 | 450d4ff5 | ths | return print_insn_crisv32_without_register_prefix;
|
| 2882 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
|
| 2883 | 450d4ff5 | ths | return print_insn_crisv10_v32_without_register_prefix;
|
| 2884 | 450d4ff5 | ths | return print_insn_cris_without_register_prefix;
|
| 2885 | 450d4ff5 | ths | }
|
| 2886 | 450d4ff5 | ths | #endif
|
| 2887 | 450d4ff5 | ths | /* Local variables:
|
| 2888 | 450d4ff5 | ths | eval: (c-set-style "gnu")
|
| 2889 | 450d4ff5 | ths | indent-tabs-mode: t
|
| 2890 | 450d4ff5 | ths | End: */ |