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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 7a3f1944 | bellard | */
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20 | 7a3f1944 | bellard | |
21 | 7a3f1944 | bellard | #include <stdarg.h> |
22 | 7a3f1944 | bellard | #include <stdlib.h> |
23 | 7a3f1944 | bellard | #include <stdio.h> |
24 | 7a3f1944 | bellard | #include <string.h> |
25 | 7a3f1944 | bellard | #include <inttypes.h> |
26 | 7a3f1944 | bellard | |
27 | 7a3f1944 | bellard | #include "cpu.h" |
28 | 7a3f1944 | bellard | #include "exec-all.h" |
29 | 7a3f1944 | bellard | #include "disas.h" |
30 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
31 | 57fec1fe | bellard | #include "tcg-op.h" |
32 | 7a3f1944 | bellard | |
33 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
34 | a7812ae4 | pbrook | #include "helper.h" |
35 | a7812ae4 | pbrook | |
36 | 7a3f1944 | bellard | #define DEBUG_DISAS
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37 | 7a3f1944 | bellard | |
38 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
39 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
40 | 72cbca10 | bellard | according to jump_pc[T2] */
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41 | 72cbca10 | bellard | |
42 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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43 | a7812ae4 | pbrook | static TCGv_ptr cpu_env, cpu_regwptr;
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44 | 25517f99 | Paul Brook | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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45 | 25517f99 | Paul Brook | static TCGv_i32 cpu_cc_op;
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46 | a7812ae4 | pbrook | static TCGv_i32 cpu_psr;
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47 | a7812ae4 | pbrook | static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
48 | 255e1fcb | blueswir1 | static TCGv cpu_y;
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49 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
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50 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
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51 | 255e1fcb | blueswir1 | #endif
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52 | 6ae20372 | blueswir1 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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53 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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54 | a7812ae4 | pbrook | static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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55 | a7812ae4 | pbrook | static TCGv cpu_gsr;
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56 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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57 | a7812ae4 | pbrook | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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58 | a7812ae4 | pbrook | static TCGv_i32 cpu_softint;
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59 | 255e1fcb | blueswir1 | #else
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60 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
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61 | dc99a3f2 | blueswir1 | #endif
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62 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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63 | a7812ae4 | pbrook | static TCGv cpu_tmp0;
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64 | a7812ae4 | pbrook | static TCGv_i32 cpu_tmp32;
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65 | a7812ae4 | pbrook | static TCGv_i64 cpu_tmp64;
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66 | 714547bb | blueswir1 | /* Floating point registers */
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67 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpr[TARGET_FPREGS];
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68 | 1a2fb1c0 | blueswir1 | |
69 | 2e70f6ef | pbrook | #include "gen-icount.h" |
70 | 2e70f6ef | pbrook | |
71 | 7a3f1944 | bellard | typedef struct DisasContext { |
72 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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73 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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74 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
75 | cf495bcf | bellard | int is_br;
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76 | e8af50a3 | bellard | int mem_idx;
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77 | a80dde08 | bellard | int fpu_enabled;
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78 | 2cade6a3 | blueswir1 | int address_mask_32bit;
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79 | 8393617c | Blue Swirl | uint32_t cc_op; /* current CC operation */
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80 | cf495bcf | bellard | struct TranslationBlock *tb;
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81 | 5578ceab | blueswir1 | sparc_def_t *def; |
82 | 7a3f1944 | bellard | } DisasContext; |
83 | 7a3f1944 | bellard | |
84 | 3475187d | bellard | // This function uses non-native bit order
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85 | dc1a6971 | Blue Swirl | #define GET_FIELD(X, FROM, TO) \
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86 | dc1a6971 | Blue Swirl | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
87 | 7a3f1944 | bellard | |
88 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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89 | dc1a6971 | Blue Swirl | #define GET_FIELD_SP(X, FROM, TO) \
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90 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
91 | 3475187d | bellard | |
92 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
93 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
94 | 3475187d | bellard | |
95 | 3475187d | bellard | #ifdef TARGET_SPARC64
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96 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
97 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
98 | 3475187d | bellard | #else
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99 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
100 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
101 | 3475187d | bellard | #endif
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102 | 3475187d | bellard | |
103 | b158a785 | blueswir1 | #define UA2005_HTRAP_MASK 0xff |
104 | b158a785 | blueswir1 | #define V8_TRAP_MASK 0x7f |
105 | b158a785 | blueswir1 | |
106 | 3475187d | bellard | static int sign_extend(int x, int len) |
107 | 3475187d | bellard | { |
108 | 3475187d | bellard | len = 32 - len;
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109 | 3475187d | bellard | return (x << len) >> len;
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110 | 3475187d | bellard | } |
111 | 3475187d | bellard | |
112 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
113 | 7a3f1944 | bellard | |
114 | ff07ec83 | blueswir1 | /* floating point registers moves */
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115 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
116 | ff07ec83 | blueswir1 | { |
117 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + |
118 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
119 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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120 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
121 | ff07ec83 | blueswir1 | } |
122 | ff07ec83 | blueswir1 | |
123 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
124 | ff07ec83 | blueswir1 | { |
125 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + |
126 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
127 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
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128 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
129 | ff07ec83 | blueswir1 | } |
130 | ff07ec83 | blueswir1 | |
131 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
132 | ff07ec83 | blueswir1 | { |
133 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + |
134 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
135 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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136 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
137 | ff07ec83 | blueswir1 | } |
138 | ff07ec83 | blueswir1 | |
139 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
140 | ff07ec83 | blueswir1 | { |
141 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
142 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
143 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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144 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
145 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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146 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
147 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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148 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
149 | ff07ec83 | blueswir1 | } |
150 | ff07ec83 | blueswir1 | |
151 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
152 | ff07ec83 | blueswir1 | { |
153 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
154 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
155 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
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156 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
157 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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158 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
159 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
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160 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
161 | ff07ec83 | blueswir1 | } |
162 | ff07ec83 | blueswir1 | |
163 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
164 | ff07ec83 | blueswir1 | { |
165 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
166 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
167 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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168 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
169 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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170 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
171 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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172 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
173 | ff07ec83 | blueswir1 | } |
174 | 1f587329 | blueswir1 | |
175 | 81ad8ba2 | blueswir1 | /* moves */
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176 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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177 | 3475187d | bellard | #define supervisor(dc) 0 |
178 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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179 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
180 | 81ad8ba2 | blueswir1 | #endif
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181 | 3475187d | bellard | #else
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182 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
183 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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184 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
185 | 6f27aba6 | blueswir1 | #else
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186 | 3475187d | bellard | #endif
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187 | 81ad8ba2 | blueswir1 | #endif
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188 | 81ad8ba2 | blueswir1 | |
189 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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190 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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191 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
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192 | 1a2fb1c0 | blueswir1 | #else
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193 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
194 | 2cade6a3 | blueswir1 | #endif
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195 | 1a2fb1c0 | blueswir1 | #endif
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196 | 3391c818 | blueswir1 | |
197 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
198 | 2cade6a3 | blueswir1 | { |
199 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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200 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
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201 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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202 | 2cade6a3 | blueswir1 | #endif
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203 | 2cade6a3 | blueswir1 | } |
204 | 2cade6a3 | blueswir1 | |
205 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
206 | 81ad8ba2 | blueswir1 | { |
207 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
208 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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209 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
210 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
211 | 1a2fb1c0 | blueswir1 | else {
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212 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
213 | 81ad8ba2 | blueswir1 | } |
214 | 81ad8ba2 | blueswir1 | } |
215 | 81ad8ba2 | blueswir1 | |
216 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
217 | 81ad8ba2 | blueswir1 | { |
218 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
219 | 1a2fb1c0 | blueswir1 | return;
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220 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
221 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
222 | 1a2fb1c0 | blueswir1 | else {
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223 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
224 | 81ad8ba2 | blueswir1 | } |
225 | 81ad8ba2 | blueswir1 | } |
226 | 81ad8ba2 | blueswir1 | |
227 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
228 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
229 | 6e256c93 | bellard | { |
230 | 6e256c93 | bellard | TranslationBlock *tb; |
231 | 6e256c93 | bellard | |
232 | 6e256c93 | bellard | tb = s->tb; |
233 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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234 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
235 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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236 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
237 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
238 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
239 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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240 | 6e256c93 | bellard | } else {
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241 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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242 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
243 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
244 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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245 | 6e256c93 | bellard | } |
246 | 6e256c93 | bellard | } |
247 | 6e256c93 | bellard | |
248 | 19f329ad | blueswir1 | // XXX suboptimal
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249 | a7812ae4 | pbrook | static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) |
250 | 19f329ad | blueswir1 | { |
251 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
252 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
253 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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254 | 19f329ad | blueswir1 | } |
255 | 19f329ad | blueswir1 | |
256 | a7812ae4 | pbrook | static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) |
257 | 19f329ad | blueswir1 | { |
258 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
259 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
260 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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261 | 19f329ad | blueswir1 | } |
262 | 19f329ad | blueswir1 | |
263 | a7812ae4 | pbrook | static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) |
264 | 19f329ad | blueswir1 | { |
265 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
266 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
267 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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268 | 19f329ad | blueswir1 | } |
269 | 19f329ad | blueswir1 | |
270 | a7812ae4 | pbrook | static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) |
271 | 19f329ad | blueswir1 | { |
272 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
273 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
274 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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275 | 19f329ad | blueswir1 | } |
276 | 19f329ad | blueswir1 | |
277 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
278 | dc99a3f2 | blueswir1 | { |
279 | a7812ae4 | pbrook | TCGv r_temp; |
280 | a7812ae4 | pbrook | TCGv_i32 r_const; |
281 | dc99a3f2 | blueswir1 | int l1;
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282 | dc99a3f2 | blueswir1 | |
283 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
284 | dc99a3f2 | blueswir1 | |
285 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
286 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
287 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
288 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
289 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
290 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
291 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
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292 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
293 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
294 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
295 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
296 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
297 | dc99a3f2 | blueswir1 | } |
298 | dc99a3f2 | blueswir1 | |
299 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
300 | dc99a3f2 | blueswir1 | { |
301 | dc99a3f2 | blueswir1 | int l1;
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302 | a7812ae4 | pbrook | TCGv_i32 r_const; |
303 | dc99a3f2 | blueswir1 | |
304 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
305 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
306 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
307 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
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308 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
309 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
310 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
311 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
312 | dc99a3f2 | blueswir1 | } |
313 | dc99a3f2 | blueswir1 | |
314 | 41d72852 | Blue Swirl | static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2) |
315 | 41d72852 | Blue Swirl | { |
316 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
317 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
318 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2); |
319 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
320 | 41d72852 | Blue Swirl | } |
321 | 41d72852 | Blue Swirl | |
322 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
323 | dc99a3f2 | blueswir1 | { |
324 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
325 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
326 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
327 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
328 | 41d72852 | Blue Swirl | } |
329 | 41d72852 | Blue Swirl | |
330 | 41d72852 | Blue Swirl | static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2) |
331 | dc99a3f2 | blueswir1 | { |
332 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
333 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
334 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
335 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
336 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
337 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
338 | 41d72852 | Blue Swirl | } |
339 | 41d72852 | Blue Swirl | |
340 | 41d72852 | Blue Swirl | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
341 | 41d72852 | Blue Swirl | { |
342 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
343 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
344 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
345 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
346 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
347 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
348 | dc99a3f2 | blueswir1 | } |
349 | dc99a3f2 | blueswir1 | |
350 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
351 | dc99a3f2 | blueswir1 | { |
352 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
353 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
354 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
355 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
356 | dc99a3f2 | blueswir1 | } |
357 | dc99a3f2 | blueswir1 | |
358 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
359 | dc99a3f2 | blueswir1 | { |
360 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
361 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
362 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
363 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
364 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
365 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
366 | dc99a3f2 | blueswir1 | } |
367 | dc99a3f2 | blueswir1 | |
368 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
369 | dc99a3f2 | blueswir1 | { |
370 | a7812ae4 | pbrook | TCGv r_temp; |
371 | a7812ae4 | pbrook | TCGv_i32 r_const; |
372 | dc99a3f2 | blueswir1 | int l1;
|
373 | dc99a3f2 | blueswir1 | |
374 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
375 | dc99a3f2 | blueswir1 | |
376 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
377 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
378 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
379 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
380 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
381 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
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382 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
383 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
384 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
385 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
386 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
387 | dc99a3f2 | blueswir1 | } |
388 | dc99a3f2 | blueswir1 | |
389 | d4b0d468 | Blue Swirl | static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc) |
390 | 41d72852 | Blue Swirl | { |
391 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
392 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
393 | 719f66a7 | Blue Swirl | if (src2 == 0) { |
394 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, src1); |
395 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
396 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
397 | 719f66a7 | Blue Swirl | } else {
|
398 | 719f66a7 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2); |
399 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
400 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
401 | 719f66a7 | Blue Swirl | } |
402 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
403 | 41d72852 | Blue Swirl | } |
404 | 41d72852 | Blue Swirl | |
405 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
406 | dc99a3f2 | blueswir1 | { |
407 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
408 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
409 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
410 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
411 | 41d72852 | Blue Swirl | } |
412 | 41d72852 | Blue Swirl | |
413 | 41d72852 | Blue Swirl | static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) |
414 | 41d72852 | Blue Swirl | { |
415 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
416 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
417 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
418 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
419 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
420 | 2ca1d92b | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
421 | 41d72852 | Blue Swirl | } |
422 | 41d72852 | Blue Swirl | |
423 | 41d72852 | Blue Swirl | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
424 | 41d72852 | Blue Swirl | { |
425 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
426 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
427 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
428 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
429 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
430 | 2ca1d92b | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
431 | dc99a3f2 | blueswir1 | } |
432 | dc99a3f2 | blueswir1 | |
433 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
434 | dc99a3f2 | blueswir1 | { |
435 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
436 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
437 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
438 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
439 | dc99a3f2 | blueswir1 | } |
440 | dc99a3f2 | blueswir1 | |
441 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
442 | dc99a3f2 | blueswir1 | { |
443 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
444 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
445 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
446 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
447 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
448 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
449 | dc99a3f2 | blueswir1 | } |
450 | dc99a3f2 | blueswir1 | |
451 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
452 | d9bdab86 | blueswir1 | { |
453 | 105a1f04 | blueswir1 | TCGv r_temp; |
454 | 6f551262 | blueswir1 | int l1;
|
455 | d9bdab86 | blueswir1 | |
456 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
457 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
458 | d9bdab86 | blueswir1 | |
459 | d9bdab86 | blueswir1 | /* old op:
|
460 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
461 | d9bdab86 | blueswir1 | T1 = 0;
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462 | d9bdab86 | blueswir1 | */
|
463 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
464 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
465 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
466 | 105a1f04 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
467 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
468 | 6f551262 | blueswir1 | gen_set_label(l1); |
469 | d9bdab86 | blueswir1 | |
470 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
471 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
472 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
473 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
474 | 255e1fcb | blueswir1 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
|
475 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
|
476 | 5068cbd9 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
477 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
478 | d9bdab86 | blueswir1 | |
479 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
480 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
481 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
482 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
483 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
484 | d9bdab86 | blueswir1 | |
485 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
486 | d9bdab86 | blueswir1 | // src1 = T0;
|
487 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
488 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
489 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
490 | d9bdab86 | blueswir1 | |
491 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
492 | d9bdab86 | blueswir1 | |
493 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
494 | d9bdab86 | blueswir1 | } |
495 | d9bdab86 | blueswir1 | |
496 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
497 | 8879d139 | blueswir1 | { |
498 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
499 | 8879d139 | blueswir1 | |
500 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
501 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
502 | 8879d139 | blueswir1 | |
503 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, src2); |
504 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, src1); |
505 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
506 | 8879d139 | blueswir1 | |
507 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
508 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
509 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
510 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
511 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
512 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
513 | 8879d139 | blueswir1 | #else
|
514 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
515 | 8879d139 | blueswir1 | #endif
|
516 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
517 | 8879d139 | blueswir1 | } |
518 | 8879d139 | blueswir1 | |
519 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
520 | 8879d139 | blueswir1 | { |
521 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
522 | 8879d139 | blueswir1 | |
523 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
524 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
525 | 8879d139 | blueswir1 | |
526 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, src2); |
527 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, src1); |
528 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
529 | 8879d139 | blueswir1 | |
530 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
531 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
532 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
533 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
534 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
535 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
536 | 8879d139 | blueswir1 | #else
|
537 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
538 | 8879d139 | blueswir1 | #endif
|
539 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
540 | 8879d139 | blueswir1 | } |
541 | 8879d139 | blueswir1 | |
542 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
543 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
544 | 1a7b60e7 | blueswir1 | { |
545 | a7812ae4 | pbrook | TCGv_i32 r_const; |
546 | 1a7b60e7 | blueswir1 | int l1;
|
547 | 1a7b60e7 | blueswir1 | |
548 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
549 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
550 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
551 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
552 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
553 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
554 | 1a7b60e7 | blueswir1 | } |
555 | 1a7b60e7 | blueswir1 | |
556 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
557 | 1a7b60e7 | blueswir1 | { |
558 | 1a7b60e7 | blueswir1 | int l1, l2;
|
559 | 1a7b60e7 | blueswir1 | |
560 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
561 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
562 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
563 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
564 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
565 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
566 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
567 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
568 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
569 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
570 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
571 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
572 | 1a7b60e7 | blueswir1 | } |
573 | 1a7b60e7 | blueswir1 | #endif
|
574 | 1a7b60e7 | blueswir1 | |
575 | 19f329ad | blueswir1 | // 1
|
576 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
577 | 19f329ad | blueswir1 | { |
578 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
579 | 19f329ad | blueswir1 | } |
580 | 19f329ad | blueswir1 | |
581 | 19f329ad | blueswir1 | // Z
|
582 | a7812ae4 | pbrook | static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) |
583 | 19f329ad | blueswir1 | { |
584 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
585 | 19f329ad | blueswir1 | } |
586 | 19f329ad | blueswir1 | |
587 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
588 | a7812ae4 | pbrook | static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) |
589 | 19f329ad | blueswir1 | { |
590 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
591 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
592 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
593 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
594 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
595 | 19f329ad | blueswir1 | } |
596 | 19f329ad | blueswir1 | |
597 | 19f329ad | blueswir1 | // N ^ V
|
598 | a7812ae4 | pbrook | static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) |
599 | 19f329ad | blueswir1 | { |
600 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
601 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
602 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
603 | 19f329ad | blueswir1 | } |
604 | 19f329ad | blueswir1 | |
605 | 19f329ad | blueswir1 | // C | Z
|
606 | a7812ae4 | pbrook | static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) |
607 | 19f329ad | blueswir1 | { |
608 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
609 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
610 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
611 | 19f329ad | blueswir1 | } |
612 | 19f329ad | blueswir1 | |
613 | 19f329ad | blueswir1 | // C
|
614 | a7812ae4 | pbrook | static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) |
615 | 19f329ad | blueswir1 | { |
616 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
617 | 19f329ad | blueswir1 | } |
618 | 19f329ad | blueswir1 | |
619 | 19f329ad | blueswir1 | // V
|
620 | a7812ae4 | pbrook | static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) |
621 | 19f329ad | blueswir1 | { |
622 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
623 | 19f329ad | blueswir1 | } |
624 | 19f329ad | blueswir1 | |
625 | 19f329ad | blueswir1 | // 0
|
626 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
627 | 19f329ad | blueswir1 | { |
628 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
629 | 19f329ad | blueswir1 | } |
630 | 19f329ad | blueswir1 | |
631 | 19f329ad | blueswir1 | // N
|
632 | a7812ae4 | pbrook | static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) |
633 | 19f329ad | blueswir1 | { |
634 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
635 | 19f329ad | blueswir1 | } |
636 | 19f329ad | blueswir1 | |
637 | 19f329ad | blueswir1 | // !Z
|
638 | a7812ae4 | pbrook | static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) |
639 | 19f329ad | blueswir1 | { |
640 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
641 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
642 | 19f329ad | blueswir1 | } |
643 | 19f329ad | blueswir1 | |
644 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
645 | a7812ae4 | pbrook | static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) |
646 | 19f329ad | blueswir1 | { |
647 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
648 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
649 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
650 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
651 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
652 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
653 | 19f329ad | blueswir1 | } |
654 | 19f329ad | blueswir1 | |
655 | 19f329ad | blueswir1 | // !(N ^ V)
|
656 | a7812ae4 | pbrook | static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) |
657 | 19f329ad | blueswir1 | { |
658 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
659 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
660 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
661 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
662 | 19f329ad | blueswir1 | } |
663 | 19f329ad | blueswir1 | |
664 | 19f329ad | blueswir1 | // !(C | Z)
|
665 | a7812ae4 | pbrook | static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) |
666 | 19f329ad | blueswir1 | { |
667 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
668 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
669 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
670 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
671 | 19f329ad | blueswir1 | } |
672 | 19f329ad | blueswir1 | |
673 | 19f329ad | blueswir1 | // !C
|
674 | a7812ae4 | pbrook | static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) |
675 | 19f329ad | blueswir1 | { |
676 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
677 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
678 | 19f329ad | blueswir1 | } |
679 | 19f329ad | blueswir1 | |
680 | 19f329ad | blueswir1 | // !N
|
681 | a7812ae4 | pbrook | static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) |
682 | 19f329ad | blueswir1 | { |
683 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
684 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
685 | 19f329ad | blueswir1 | } |
686 | 19f329ad | blueswir1 | |
687 | 19f329ad | blueswir1 | // !V
|
688 | a7812ae4 | pbrook | static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) |
689 | 19f329ad | blueswir1 | { |
690 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
691 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
692 | 19f329ad | blueswir1 | } |
693 | 19f329ad | blueswir1 | |
694 | 19f329ad | blueswir1 | /*
|
695 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
696 | 19f329ad | blueswir1 | 0 =
|
697 | 19f329ad | blueswir1 | 1 <
|
698 | 19f329ad | blueswir1 | 2 >
|
699 | 19f329ad | blueswir1 | 3 unordered
|
700 | 19f329ad | blueswir1 | */
|
701 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
702 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
703 | 19f329ad | blueswir1 | { |
704 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
705 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
706 | 19f329ad | blueswir1 | } |
707 | 19f329ad | blueswir1 | |
708 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
709 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
710 | 19f329ad | blueswir1 | { |
711 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
712 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
713 | 19f329ad | blueswir1 | } |
714 | 19f329ad | blueswir1 | |
715 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
716 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
717 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
718 | 19f329ad | blueswir1 | { |
719 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
720 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
721 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
722 | 19f329ad | blueswir1 | } |
723 | 19f329ad | blueswir1 | |
724 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
725 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
726 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
727 | 19f329ad | blueswir1 | { |
728 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
729 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
730 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
731 | 19f329ad | blueswir1 | } |
732 | 19f329ad | blueswir1 | |
733 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
734 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
735 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
736 | 19f329ad | blueswir1 | { |
737 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
738 | 19f329ad | blueswir1 | } |
739 | 19f329ad | blueswir1 | |
740 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
741 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
742 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
743 | 19f329ad | blueswir1 | { |
744 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
745 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
746 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
747 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
748 | 19f329ad | blueswir1 | } |
749 | 19f329ad | blueswir1 | |
750 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
751 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
752 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
753 | 19f329ad | blueswir1 | { |
754 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
755 | 19f329ad | blueswir1 | } |
756 | 19f329ad | blueswir1 | |
757 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
758 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
759 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
760 | 19f329ad | blueswir1 | { |
761 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
762 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
763 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
764 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
765 | 19f329ad | blueswir1 | } |
766 | 19f329ad | blueswir1 | |
767 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
768 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
769 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
770 | 19f329ad | blueswir1 | { |
771 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
772 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
773 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
774 | 19f329ad | blueswir1 | } |
775 | 19f329ad | blueswir1 | |
776 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
777 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
778 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
779 | 19f329ad | blueswir1 | { |
780 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
781 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
782 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
783 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
784 | 19f329ad | blueswir1 | } |
785 | 19f329ad | blueswir1 | |
786 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
787 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
788 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
789 | 19f329ad | blueswir1 | { |
790 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
791 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
792 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
793 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
794 | 19f329ad | blueswir1 | } |
795 | 19f329ad | blueswir1 | |
796 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
797 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
798 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
799 | 19f329ad | blueswir1 | { |
800 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
801 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
802 | 19f329ad | blueswir1 | } |
803 | 19f329ad | blueswir1 | |
804 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
805 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
806 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
807 | 19f329ad | blueswir1 | { |
808 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
809 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
810 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
811 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
812 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
813 | 19f329ad | blueswir1 | } |
814 | 19f329ad | blueswir1 | |
815 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
816 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
817 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
818 | 19f329ad | blueswir1 | { |
819 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
820 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
821 | 19f329ad | blueswir1 | } |
822 | 19f329ad | blueswir1 | |
823 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
824 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
825 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
826 | 19f329ad | blueswir1 | { |
827 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
828 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
829 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
830 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
831 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
832 | 19f329ad | blueswir1 | } |
833 | 19f329ad | blueswir1 | |
834 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
835 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
836 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
837 | 19f329ad | blueswir1 | { |
838 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
839 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
840 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
841 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
842 | 19f329ad | blueswir1 | } |
843 | 19f329ad | blueswir1 | |
844 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
845 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
846 | 83469015 | bellard | { |
847 | 83469015 | bellard | int l1;
|
848 | 83469015 | bellard | |
849 | 83469015 | bellard | l1 = gen_new_label(); |
850 | 83469015 | bellard | |
851 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
852 | 83469015 | bellard | |
853 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
854 | 83469015 | bellard | |
855 | 83469015 | bellard | gen_set_label(l1); |
856 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
857 | 83469015 | bellard | } |
858 | 83469015 | bellard | |
859 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
860 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
861 | 83469015 | bellard | { |
862 | 83469015 | bellard | int l1;
|
863 | 83469015 | bellard | |
864 | 83469015 | bellard | l1 = gen_new_label(); |
865 | 83469015 | bellard | |
866 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
867 | 83469015 | bellard | |
868 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
869 | 83469015 | bellard | |
870 | 83469015 | bellard | gen_set_label(l1); |
871 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
872 | 83469015 | bellard | } |
873 | 83469015 | bellard | |
874 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
875 | 19f329ad | blueswir1 | TCGv r_cond) |
876 | 83469015 | bellard | { |
877 | 83469015 | bellard | int l1, l2;
|
878 | 83469015 | bellard | |
879 | 83469015 | bellard | l1 = gen_new_label(); |
880 | 83469015 | bellard | l2 = gen_new_label(); |
881 | 19f329ad | blueswir1 | |
882 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
883 | 83469015 | bellard | |
884 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
885 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
886 | 83469015 | bellard | |
887 | 83469015 | bellard | gen_set_label(l1); |
888 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
889 | 83469015 | bellard | gen_set_label(l2); |
890 | 83469015 | bellard | } |
891 | 83469015 | bellard | |
892 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
893 | 4af984a7 | blueswir1 | have been set for a jump */
|
894 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
895 | 83469015 | bellard | { |
896 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
897 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
898 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
899 | 83469015 | bellard | } |
900 | 83469015 | bellard | } |
901 | 83469015 | bellard | |
902 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
903 | 72cbca10 | bellard | { |
904 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
905 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
906 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
907 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
908 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
909 | 72cbca10 | bellard | } |
910 | 72cbca10 | bellard | } |
911 | 72cbca10 | bellard | |
912 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
913 | 72cbca10 | bellard | { |
914 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
915 | cfa90513 | Blue Swirl | /* flush pending conditional evaluations before exposing cpu state */
|
916 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
917 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
918 | cfa90513 | Blue Swirl | gen_helper_compute_psr(); |
919 | cfa90513 | Blue Swirl | } |
920 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
921 | 72cbca10 | bellard | } |
922 | 72cbca10 | bellard | |
923 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
924 | 0bee699e | bellard | { |
925 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
926 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
927 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
928 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
929 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
930 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
931 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
932 | 0bee699e | bellard | } else {
|
933 | 0bee699e | bellard | dc->pc = dc->npc; |
934 | 0bee699e | bellard | } |
935 | 0bee699e | bellard | } |
936 | 0bee699e | bellard | |
937 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
938 | 38bc628b | blueswir1 | { |
939 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
940 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
941 | 38bc628b | blueswir1 | } |
942 | 38bc628b | blueswir1 | |
943 | 8393617c | Blue Swirl | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, |
944 | 8393617c | Blue Swirl | DisasContext *dc) |
945 | 19f329ad | blueswir1 | { |
946 | a7812ae4 | pbrook | TCGv_i32 r_src; |
947 | 3475187d | bellard | |
948 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
949 | 19f329ad | blueswir1 | if (cc)
|
950 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
951 | 19f329ad | blueswir1 | else
|
952 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
953 | 3475187d | bellard | #else
|
954 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
955 | 3475187d | bellard | #endif
|
956 | 8393617c | Blue Swirl | switch (dc->cc_op) {
|
957 | 8393617c | Blue Swirl | case CC_OP_FLAGS:
|
958 | 8393617c | Blue Swirl | break;
|
959 | 8393617c | Blue Swirl | default:
|
960 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
961 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
962 | 8393617c | Blue Swirl | break;
|
963 | 8393617c | Blue Swirl | } |
964 | 19f329ad | blueswir1 | switch (cond) {
|
965 | 19f329ad | blueswir1 | case 0x0: |
966 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
967 | 19f329ad | blueswir1 | break;
|
968 | 19f329ad | blueswir1 | case 0x1: |
969 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
970 | 19f329ad | blueswir1 | break;
|
971 | 19f329ad | blueswir1 | case 0x2: |
972 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
973 | 19f329ad | blueswir1 | break;
|
974 | 19f329ad | blueswir1 | case 0x3: |
975 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
976 | 19f329ad | blueswir1 | break;
|
977 | 19f329ad | blueswir1 | case 0x4: |
978 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
979 | 19f329ad | blueswir1 | break;
|
980 | 19f329ad | blueswir1 | case 0x5: |
981 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
982 | 19f329ad | blueswir1 | break;
|
983 | 19f329ad | blueswir1 | case 0x6: |
984 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
985 | 19f329ad | blueswir1 | break;
|
986 | 19f329ad | blueswir1 | case 0x7: |
987 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
988 | 19f329ad | blueswir1 | break;
|
989 | 19f329ad | blueswir1 | case 0x8: |
990 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
991 | 19f329ad | blueswir1 | break;
|
992 | 19f329ad | blueswir1 | case 0x9: |
993 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
994 | 19f329ad | blueswir1 | break;
|
995 | 19f329ad | blueswir1 | case 0xa: |
996 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
997 | 19f329ad | blueswir1 | break;
|
998 | 19f329ad | blueswir1 | case 0xb: |
999 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1000 | 19f329ad | blueswir1 | break;
|
1001 | 19f329ad | blueswir1 | case 0xc: |
1002 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1003 | 19f329ad | blueswir1 | break;
|
1004 | 19f329ad | blueswir1 | case 0xd: |
1005 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1006 | 19f329ad | blueswir1 | break;
|
1007 | 19f329ad | blueswir1 | case 0xe: |
1008 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1009 | 19f329ad | blueswir1 | break;
|
1010 | 19f329ad | blueswir1 | case 0xf: |
1011 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1012 | 19f329ad | blueswir1 | break;
|
1013 | 19f329ad | blueswir1 | } |
1014 | 19f329ad | blueswir1 | } |
1015 | 7a3f1944 | bellard | |
1016 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1017 | e8af50a3 | bellard | { |
1018 | 19f329ad | blueswir1 | unsigned int offset; |
1019 | 19f329ad | blueswir1 | |
1020 | 19f329ad | blueswir1 | switch (cc) {
|
1021 | 19f329ad | blueswir1 | default:
|
1022 | 19f329ad | blueswir1 | case 0x0: |
1023 | 19f329ad | blueswir1 | offset = 0;
|
1024 | 19f329ad | blueswir1 | break;
|
1025 | 19f329ad | blueswir1 | case 0x1: |
1026 | 19f329ad | blueswir1 | offset = 32 - 10; |
1027 | 19f329ad | blueswir1 | break;
|
1028 | 19f329ad | blueswir1 | case 0x2: |
1029 | 19f329ad | blueswir1 | offset = 34 - 10; |
1030 | 19f329ad | blueswir1 | break;
|
1031 | 19f329ad | blueswir1 | case 0x3: |
1032 | 19f329ad | blueswir1 | offset = 36 - 10; |
1033 | 19f329ad | blueswir1 | break;
|
1034 | 19f329ad | blueswir1 | } |
1035 | 19f329ad | blueswir1 | |
1036 | 19f329ad | blueswir1 | switch (cond) {
|
1037 | 19f329ad | blueswir1 | case 0x0: |
1038 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1039 | 19f329ad | blueswir1 | break;
|
1040 | 19f329ad | blueswir1 | case 0x1: |
1041 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1042 | 19f329ad | blueswir1 | break;
|
1043 | 19f329ad | blueswir1 | case 0x2: |
1044 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1045 | 19f329ad | blueswir1 | break;
|
1046 | 19f329ad | blueswir1 | case 0x3: |
1047 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1048 | 19f329ad | blueswir1 | break;
|
1049 | 19f329ad | blueswir1 | case 0x4: |
1050 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1051 | 19f329ad | blueswir1 | break;
|
1052 | 19f329ad | blueswir1 | case 0x5: |
1053 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1054 | 19f329ad | blueswir1 | break;
|
1055 | 19f329ad | blueswir1 | case 0x6: |
1056 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1057 | 19f329ad | blueswir1 | break;
|
1058 | 19f329ad | blueswir1 | case 0x7: |
1059 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1060 | 19f329ad | blueswir1 | break;
|
1061 | 19f329ad | blueswir1 | case 0x8: |
1062 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1063 | 19f329ad | blueswir1 | break;
|
1064 | 19f329ad | blueswir1 | case 0x9: |
1065 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1066 | 19f329ad | blueswir1 | break;
|
1067 | 19f329ad | blueswir1 | case 0xa: |
1068 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1069 | 19f329ad | blueswir1 | break;
|
1070 | 19f329ad | blueswir1 | case 0xb: |
1071 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1072 | 19f329ad | blueswir1 | break;
|
1073 | 19f329ad | blueswir1 | case 0xc: |
1074 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1075 | 19f329ad | blueswir1 | break;
|
1076 | 19f329ad | blueswir1 | case 0xd: |
1077 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1078 | 19f329ad | blueswir1 | break;
|
1079 | 19f329ad | blueswir1 | case 0xe: |
1080 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1081 | 19f329ad | blueswir1 | break;
|
1082 | 19f329ad | blueswir1 | case 0xf: |
1083 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1084 | 19f329ad | blueswir1 | break;
|
1085 | 19f329ad | blueswir1 | } |
1086 | e8af50a3 | bellard | } |
1087 | 00f219bf | blueswir1 | |
1088 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1089 | 00f219bf | blueswir1 | // Inverted logic
|
1090 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1091 | 00f219bf | blueswir1 | -1,
|
1092 | 00f219bf | blueswir1 | TCG_COND_NE, |
1093 | 00f219bf | blueswir1 | TCG_COND_GT, |
1094 | 00f219bf | blueswir1 | TCG_COND_GE, |
1095 | 00f219bf | blueswir1 | -1,
|
1096 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1097 | 00f219bf | blueswir1 | TCG_COND_LE, |
1098 | 00f219bf | blueswir1 | TCG_COND_LT, |
1099 | 00f219bf | blueswir1 | }; |
1100 | 19f329ad | blueswir1 | |
1101 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1102 | 19f329ad | blueswir1 | { |
1103 | 19f329ad | blueswir1 | int l1;
|
1104 | 19f329ad | blueswir1 | |
1105 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1106 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1107 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1108 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1109 | 19f329ad | blueswir1 | gen_set_label(l1); |
1110 | 19f329ad | blueswir1 | } |
1111 | 3475187d | bellard | #endif
|
1112 | cf495bcf | bellard | |
1113 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1114 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1115 | 4af984a7 | blueswir1 | TCGv r_cond) |
1116 | 7a3f1944 | bellard | { |
1117 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1118 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1119 | 5fafdf24 | ths | |
1120 | cf495bcf | bellard | if (cond == 0x0) { |
1121 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1122 | 0f8a249a | blueswir1 | if (a) {
|
1123 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1124 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1125 | 0f8a249a | blueswir1 | } else {
|
1126 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1127 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1128 | 0f8a249a | blueswir1 | } |
1129 | cf495bcf | bellard | } else if (cond == 0x8) { |
1130 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1131 | 0f8a249a | blueswir1 | if (a) {
|
1132 | 0f8a249a | blueswir1 | dc->pc = target; |
1133 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1134 | 0f8a249a | blueswir1 | } else {
|
1135 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1136 | 0f8a249a | blueswir1 | dc->npc = target; |
1137 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1138 | 0f8a249a | blueswir1 | } |
1139 | cf495bcf | bellard | } else {
|
1140 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1141 | 8393617c | Blue Swirl | gen_cond(r_cond, cc, cond, dc); |
1142 | 0f8a249a | blueswir1 | if (a) {
|
1143 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1144 | cf495bcf | bellard | dc->is_br = 1;
|
1145 | 0f8a249a | blueswir1 | } else {
|
1146 | cf495bcf | bellard | dc->pc = dc->npc; |
1147 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1148 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1149 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1150 | 0f8a249a | blueswir1 | } |
1151 | cf495bcf | bellard | } |
1152 | 7a3f1944 | bellard | } |
1153 | 7a3f1944 | bellard | |
1154 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1155 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1156 | 4af984a7 | blueswir1 | TCGv r_cond) |
1157 | e8af50a3 | bellard | { |
1158 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1159 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1160 | af7bf89b | bellard | |
1161 | e8af50a3 | bellard | if (cond == 0x0) { |
1162 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1163 | 0f8a249a | blueswir1 | if (a) {
|
1164 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1165 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1166 | 0f8a249a | blueswir1 | } else {
|
1167 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1168 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1169 | 0f8a249a | blueswir1 | } |
1170 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1171 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1172 | 0f8a249a | blueswir1 | if (a) {
|
1173 | 0f8a249a | blueswir1 | dc->pc = target; |
1174 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1175 | 0f8a249a | blueswir1 | } else {
|
1176 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1177 | 0f8a249a | blueswir1 | dc->npc = target; |
1178 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1179 | 0f8a249a | blueswir1 | } |
1180 | e8af50a3 | bellard | } else {
|
1181 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1182 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1183 | 0f8a249a | blueswir1 | if (a) {
|
1184 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1185 | e8af50a3 | bellard | dc->is_br = 1;
|
1186 | 0f8a249a | blueswir1 | } else {
|
1187 | e8af50a3 | bellard | dc->pc = dc->npc; |
1188 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1189 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1190 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1191 | 0f8a249a | blueswir1 | } |
1192 | e8af50a3 | bellard | } |
1193 | e8af50a3 | bellard | } |
1194 | e8af50a3 | bellard | |
1195 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1196 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1197 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1198 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1199 | 7a3f1944 | bellard | { |
1200 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1201 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1202 | 3475187d | bellard | |
1203 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1204 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1205 | 3475187d | bellard | if (a) {
|
1206 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1207 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1208 | 3475187d | bellard | } else {
|
1209 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1210 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1211 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1212 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1213 | 3475187d | bellard | } |
1214 | 7a3f1944 | bellard | } |
1215 | 7a3f1944 | bellard | |
1216 | a7812ae4 | pbrook | static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1217 | 7e8c2b6c | blueswir1 | { |
1218 | 714547bb | blueswir1 | switch (fccno) {
|
1219 | 714547bb | blueswir1 | case 0: |
1220 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1221 | 714547bb | blueswir1 | break;
|
1222 | 714547bb | blueswir1 | case 1: |
1223 | a7812ae4 | pbrook | gen_helper_fcmps_fcc1(r_rs1, r_rs2); |
1224 | 714547bb | blueswir1 | break;
|
1225 | 714547bb | blueswir1 | case 2: |
1226 | a7812ae4 | pbrook | gen_helper_fcmps_fcc2(r_rs1, r_rs2); |
1227 | 714547bb | blueswir1 | break;
|
1228 | 714547bb | blueswir1 | case 3: |
1229 | a7812ae4 | pbrook | gen_helper_fcmps_fcc3(r_rs1, r_rs2); |
1230 | 714547bb | blueswir1 | break;
|
1231 | 714547bb | blueswir1 | } |
1232 | 7e8c2b6c | blueswir1 | } |
1233 | 7e8c2b6c | blueswir1 | |
1234 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1235 | 7e8c2b6c | blueswir1 | { |
1236 | a7812ae4 | pbrook | switch (fccno) {
|
1237 | a7812ae4 | pbrook | case 0: |
1238 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1239 | a7812ae4 | pbrook | break;
|
1240 | a7812ae4 | pbrook | case 1: |
1241 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc1(); |
1242 | a7812ae4 | pbrook | break;
|
1243 | a7812ae4 | pbrook | case 2: |
1244 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc2(); |
1245 | a7812ae4 | pbrook | break;
|
1246 | a7812ae4 | pbrook | case 3: |
1247 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc3(); |
1248 | a7812ae4 | pbrook | break;
|
1249 | a7812ae4 | pbrook | } |
1250 | 7e8c2b6c | blueswir1 | } |
1251 | 7e8c2b6c | blueswir1 | |
1252 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1253 | 7e8c2b6c | blueswir1 | { |
1254 | a7812ae4 | pbrook | switch (fccno) {
|
1255 | a7812ae4 | pbrook | case 0: |
1256 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1257 | a7812ae4 | pbrook | break;
|
1258 | a7812ae4 | pbrook | case 1: |
1259 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc1(); |
1260 | a7812ae4 | pbrook | break;
|
1261 | a7812ae4 | pbrook | case 2: |
1262 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc2(); |
1263 | a7812ae4 | pbrook | break;
|
1264 | a7812ae4 | pbrook | case 3: |
1265 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc3(); |
1266 | a7812ae4 | pbrook | break;
|
1267 | a7812ae4 | pbrook | } |
1268 | 7e8c2b6c | blueswir1 | } |
1269 | 7e8c2b6c | blueswir1 | |
1270 | a7812ae4 | pbrook | static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1271 | 7e8c2b6c | blueswir1 | { |
1272 | 714547bb | blueswir1 | switch (fccno) {
|
1273 | 714547bb | blueswir1 | case 0: |
1274 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1275 | 714547bb | blueswir1 | break;
|
1276 | 714547bb | blueswir1 | case 1: |
1277 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc1(r_rs1, r_rs2); |
1278 | 714547bb | blueswir1 | break;
|
1279 | 714547bb | blueswir1 | case 2: |
1280 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc2(r_rs1, r_rs2); |
1281 | 714547bb | blueswir1 | break;
|
1282 | 714547bb | blueswir1 | case 3: |
1283 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc3(r_rs1, r_rs2); |
1284 | 714547bb | blueswir1 | break;
|
1285 | 714547bb | blueswir1 | } |
1286 | 7e8c2b6c | blueswir1 | } |
1287 | 7e8c2b6c | blueswir1 | |
1288 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1289 | 7e8c2b6c | blueswir1 | { |
1290 | a7812ae4 | pbrook | switch (fccno) {
|
1291 | a7812ae4 | pbrook | case 0: |
1292 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1293 | a7812ae4 | pbrook | break;
|
1294 | a7812ae4 | pbrook | case 1: |
1295 | a7812ae4 | pbrook | gen_helper_fcmped_fcc1(); |
1296 | a7812ae4 | pbrook | break;
|
1297 | a7812ae4 | pbrook | case 2: |
1298 | a7812ae4 | pbrook | gen_helper_fcmped_fcc2(); |
1299 | a7812ae4 | pbrook | break;
|
1300 | a7812ae4 | pbrook | case 3: |
1301 | a7812ae4 | pbrook | gen_helper_fcmped_fcc3(); |
1302 | a7812ae4 | pbrook | break;
|
1303 | a7812ae4 | pbrook | } |
1304 | 7e8c2b6c | blueswir1 | } |
1305 | 7e8c2b6c | blueswir1 | |
1306 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1307 | 7e8c2b6c | blueswir1 | { |
1308 | a7812ae4 | pbrook | switch (fccno) {
|
1309 | a7812ae4 | pbrook | case 0: |
1310 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1311 | a7812ae4 | pbrook | break;
|
1312 | a7812ae4 | pbrook | case 1: |
1313 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc1(); |
1314 | a7812ae4 | pbrook | break;
|
1315 | a7812ae4 | pbrook | case 2: |
1316 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc2(); |
1317 | a7812ae4 | pbrook | break;
|
1318 | a7812ae4 | pbrook | case 3: |
1319 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc3(); |
1320 | a7812ae4 | pbrook | break;
|
1321 | a7812ae4 | pbrook | } |
1322 | 7e8c2b6c | blueswir1 | } |
1323 | 7e8c2b6c | blueswir1 | |
1324 | 7e8c2b6c | blueswir1 | #else
|
1325 | 7e8c2b6c | blueswir1 | |
1326 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1327 | 7e8c2b6c | blueswir1 | { |
1328 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1329 | 7e8c2b6c | blueswir1 | } |
1330 | 7e8c2b6c | blueswir1 | |
1331 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1332 | 7e8c2b6c | blueswir1 | { |
1333 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1334 | 7e8c2b6c | blueswir1 | } |
1335 | 7e8c2b6c | blueswir1 | |
1336 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1337 | 7e8c2b6c | blueswir1 | { |
1338 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1339 | 7e8c2b6c | blueswir1 | } |
1340 | 7e8c2b6c | blueswir1 | |
1341 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1342 | 7e8c2b6c | blueswir1 | { |
1343 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1344 | 7e8c2b6c | blueswir1 | } |
1345 | 7e8c2b6c | blueswir1 | |
1346 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1347 | 7e8c2b6c | blueswir1 | { |
1348 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1349 | 7e8c2b6c | blueswir1 | } |
1350 | 7e8c2b6c | blueswir1 | |
1351 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1352 | 7e8c2b6c | blueswir1 | { |
1353 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1354 | 7e8c2b6c | blueswir1 | } |
1355 | 7e8c2b6c | blueswir1 | #endif
|
1356 | 7e8c2b6c | blueswir1 | |
1357 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1358 | 134d77a1 | blueswir1 | { |
1359 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1360 | 2ea815ca | blueswir1 | |
1361 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1362 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1363 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1364 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1365 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1366 | 134d77a1 | blueswir1 | } |
1367 | 134d77a1 | blueswir1 | |
1368 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1369 | a80dde08 | bellard | { |
1370 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1371 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1372 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1373 | 2ea815ca | blueswir1 | |
1374 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1375 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1376 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1377 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1378 | a80dde08 | bellard | dc->is_br = 1;
|
1379 | a80dde08 | bellard | return 1; |
1380 | a80dde08 | bellard | } |
1381 | a80dde08 | bellard | #endif
|
1382 | a80dde08 | bellard | return 0; |
1383 | a80dde08 | bellard | } |
1384 | a80dde08 | bellard | |
1385 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1386 | 7e8c2b6c | blueswir1 | { |
1387 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1388 | 7e8c2b6c | blueswir1 | } |
1389 | 7e8c2b6c | blueswir1 | |
1390 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1391 | 7e8c2b6c | blueswir1 | { |
1392 | a7812ae4 | pbrook | gen_helper_clear_float_exceptions(); |
1393 | 7e8c2b6c | blueswir1 | } |
1394 | 7e8c2b6c | blueswir1 | |
1395 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1396 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1397 | a7812ae4 | pbrook | static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) |
1398 | 1a2fb1c0 | blueswir1 | { |
1399 | 95f9397c | blueswir1 | int asi;
|
1400 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1401 | 1a2fb1c0 | blueswir1 | |
1402 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1403 | a7812ae4 | pbrook | r_asi = tcg_temp_new_i32(); |
1404 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1405 | 1a2fb1c0 | blueswir1 | } else {
|
1406 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1407 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1408 | 1a2fb1c0 | blueswir1 | } |
1409 | 0425bee5 | blueswir1 | return r_asi;
|
1410 | 0425bee5 | blueswir1 | } |
1411 | 0425bee5 | blueswir1 | |
1412 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1413 | 77f193da | blueswir1 | int sign)
|
1414 | 0425bee5 | blueswir1 | { |
1415 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1416 | 0425bee5 | blueswir1 | |
1417 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1418 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1419 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1420 | a7812ae4 | pbrook | gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign); |
1421 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1422 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1423 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1424 | 1a2fb1c0 | blueswir1 | } |
1425 | 1a2fb1c0 | blueswir1 | |
1426 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1427 | 1a2fb1c0 | blueswir1 | { |
1428 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1429 | 1a2fb1c0 | blueswir1 | |
1430 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1431 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1432 | a7812ae4 | pbrook | gen_helper_st_asi(addr, src, r_asi, r_size); |
1433 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1434 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1435 | 1a2fb1c0 | blueswir1 | } |
1436 | 1a2fb1c0 | blueswir1 | |
1437 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1438 | 1a2fb1c0 | blueswir1 | { |
1439 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1440 | 1a2fb1c0 | blueswir1 | |
1441 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1442 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1443 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1444 | a7812ae4 | pbrook | gen_helper_ldf_asi(addr, r_asi, r_size, r_rd); |
1445 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1446 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1447 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1448 | 1a2fb1c0 | blueswir1 | } |
1449 | 1a2fb1c0 | blueswir1 | |
1450 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1451 | 1a2fb1c0 | blueswir1 | { |
1452 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1453 | 1a2fb1c0 | blueswir1 | |
1454 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1455 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1456 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1457 | a7812ae4 | pbrook | gen_helper_stf_asi(addr, r_asi, r_size, r_rd); |
1458 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1459 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1460 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1461 | 1a2fb1c0 | blueswir1 | } |
1462 | 1a2fb1c0 | blueswir1 | |
1463 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1464 | 1a2fb1c0 | blueswir1 | { |
1465 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1466 | 1a2fb1c0 | blueswir1 | |
1467 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1468 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1469 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1470 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1471 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1472 | a7812ae4 | pbrook | gen_helper_st_asi(addr, dst, r_asi, r_size); |
1473 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1474 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1475 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1476 | 1a2fb1c0 | blueswir1 | } |
1477 | 1a2fb1c0 | blueswir1 | |
1478 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1479 | 1a2fb1c0 | blueswir1 | { |
1480 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_rd; |
1481 | 1a2fb1c0 | blueswir1 | |
1482 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1483 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1484 | a7812ae4 | pbrook | gen_helper_ldda_asi(addr, r_asi, r_rd); |
1485 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1486 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1487 | 0425bee5 | blueswir1 | } |
1488 | 0425bee5 | blueswir1 | |
1489 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1490 | 0425bee5 | blueswir1 | { |
1491 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1492 | a7ec4229 | blueswir1 | |
1493 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1494 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1495 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1496 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1497 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1498 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1499 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1500 | 1a2fb1c0 | blueswir1 | } |
1501 | 1a2fb1c0 | blueswir1 | |
1502 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1503 | 77f193da | blueswir1 | int rd)
|
1504 | 1a2fb1c0 | blueswir1 | { |
1505 | a7812ae4 | pbrook | TCGv r_val1; |
1506 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1507 | 1a2fb1c0 | blueswir1 | |
1508 | a7812ae4 | pbrook | r_val1 = tcg_temp_new(); |
1509 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1510 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1511 | a7812ae4 | pbrook | gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi); |
1512 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1513 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1514 | 1a2fb1c0 | blueswir1 | } |
1515 | 1a2fb1c0 | blueswir1 | |
1516 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1517 | 77f193da | blueswir1 | int rd)
|
1518 | 1a2fb1c0 | blueswir1 | { |
1519 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1520 | 1a2fb1c0 | blueswir1 | |
1521 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1522 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1523 | a7812ae4 | pbrook | gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi); |
1524 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1525 | 1a2fb1c0 | blueswir1 | } |
1526 | 1a2fb1c0 | blueswir1 | |
1527 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1528 | 1a2fb1c0 | blueswir1 | |
1529 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1530 | 77f193da | blueswir1 | int sign)
|
1531 | 1a2fb1c0 | blueswir1 | { |
1532 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1533 | 1a2fb1c0 | blueswir1 | |
1534 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1535 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1536 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1537 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1538 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1539 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1540 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1541 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1542 | 1a2fb1c0 | blueswir1 | } |
1543 | 1a2fb1c0 | blueswir1 | |
1544 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1545 | 1a2fb1c0 | blueswir1 | { |
1546 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1547 | 1a2fb1c0 | blueswir1 | |
1548 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1549 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1550 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1551 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1552 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1553 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1554 | 1a2fb1c0 | blueswir1 | } |
1555 | 1a2fb1c0 | blueswir1 | |
1556 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1557 | 1a2fb1c0 | blueswir1 | { |
1558 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1559 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1560 | 1a2fb1c0 | blueswir1 | |
1561 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1562 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1563 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1564 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1565 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1566 | a7812ae4 | pbrook | r_val = tcg_temp_new_i64(); |
1567 | a7812ae4 | pbrook | tcg_gen_extu_tl_i64(r_val, dst); |
1568 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1569 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1570 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1571 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1572 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1573 | 1a2fb1c0 | blueswir1 | } |
1574 | 1a2fb1c0 | blueswir1 | |
1575 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1576 | 1a2fb1c0 | blueswir1 | { |
1577 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1578 | 1a2fb1c0 | blueswir1 | |
1579 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1580 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1581 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1582 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1583 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1584 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1585 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1586 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1587 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1588 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1589 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1590 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1591 | 0425bee5 | blueswir1 | } |
1592 | 0425bee5 | blueswir1 | |
1593 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1594 | 0425bee5 | blueswir1 | { |
1595 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1596 | a7ec4229 | blueswir1 | |
1597 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1598 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1599 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1600 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1601 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1602 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1603 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1604 | 1a2fb1c0 | blueswir1 | } |
1605 | 1a2fb1c0 | blueswir1 | #endif
|
1606 | 1a2fb1c0 | blueswir1 | |
1607 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1608 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1609 | 1a2fb1c0 | blueswir1 | { |
1610 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1611 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1612 | 1a2fb1c0 | blueswir1 | |
1613 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1614 | 1a2fb1c0 | blueswir1 | |
1615 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1616 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1617 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1618 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1619 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1620 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1621 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1622 | 1a2fb1c0 | blueswir1 | } |
1623 | 1a2fb1c0 | blueswir1 | #endif
|
1624 | 1a2fb1c0 | blueswir1 | |
1625 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1626 | 9322a4bf | blueswir1 | { |
1627 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1628 | 9322a4bf | blueswir1 | unsigned int rs1; |
1629 | 9322a4bf | blueswir1 | |
1630 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1631 | 9322a4bf | blueswir1 | if (rs1 == 0) |
1632 | 5c6a0628 | blueswir1 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
1633 | 9322a4bf | blueswir1 | else if (rs1 < 8) |
1634 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1635 | 9322a4bf | blueswir1 | else
|
1636 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1637 | 9322a4bf | blueswir1 | return r_rs1;
|
1638 | 9322a4bf | blueswir1 | } |
1639 | 9322a4bf | blueswir1 | |
1640 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1641 | a49d9390 | blueswir1 | { |
1642 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1643 | a49d9390 | blueswir1 | |
1644 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1645 | 67526b20 | Blue Swirl | target_long simm; |
1646 | 67526b20 | Blue Swirl | |
1647 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
1648 | 67526b20 | Blue Swirl | r_rs2 = tcg_const_tl(simm); // XXX how to free?
|
1649 | a49d9390 | blueswir1 | } else { /* register */ |
1650 | 67526b20 | Blue Swirl | unsigned int rs2; |
1651 | 67526b20 | Blue Swirl | |
1652 | a49d9390 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1653 | a49d9390 | blueswir1 | if (rs2 == 0) |
1654 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
1655 | a49d9390 | blueswir1 | else if (rs2 < 8) |
1656 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1657 | a49d9390 | blueswir1 | else
|
1658 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1659 | a49d9390 | blueswir1 | } |
1660 | a49d9390 | blueswir1 | return r_rs2;
|
1661 | a49d9390 | blueswir1 | } |
1662 | a49d9390 | blueswir1 | |
1663 | 8194f35a | Igor Kovalenko | #ifdef TARGET_SPARC64
|
1664 | 8194f35a | Igor Kovalenko | static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env) |
1665 | 8194f35a | Igor Kovalenko | { |
1666 | b551ec04 | Jay Foad | TCGv_i32 r_tl = tcg_temp_new_i32(); |
1667 | 8194f35a | Igor Kovalenko | |
1668 | 8194f35a | Igor Kovalenko | /* load env->tl into r_tl */
|
1669 | b551ec04 | Jay Foad | tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); |
1670 | 8194f35a | Igor Kovalenko | |
1671 | 8194f35a | Igor Kovalenko | /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
|
1672 | b551ec04 | Jay Foad | tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); |
1673 | 8194f35a | Igor Kovalenko | |
1674 | 8194f35a | Igor Kovalenko | /* calculate offset to current trap state from env->ts, reuse r_tl */
|
1675 | b551ec04 | Jay Foad | tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
|
1676 | 8194f35a | Igor Kovalenko | tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts)); |
1677 | 8194f35a | Igor Kovalenko | |
1678 | 8194f35a | Igor Kovalenko | /* tsptr = env->ts[env->tl & MAXTL_MASK] */
|
1679 | b551ec04 | Jay Foad | { |
1680 | b551ec04 | Jay Foad | TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); |
1681 | b551ec04 | Jay Foad | tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); |
1682 | b551ec04 | Jay Foad | tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); |
1683 | bc57c114 | Stefan Weil | tcg_temp_free_ptr(r_tl_tmp); |
1684 | b551ec04 | Jay Foad | } |
1685 | 8194f35a | Igor Kovalenko | |
1686 | b551ec04 | Jay Foad | tcg_temp_free_i32(r_tl); |
1687 | 8194f35a | Igor Kovalenko | } |
1688 | 8194f35a | Igor Kovalenko | #endif
|
1689 | 8194f35a | Igor Kovalenko | |
1690 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1691 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1692 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1693 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1694 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1695 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1696 | 64a88d5d | blueswir1 | |
1697 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1698 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1699 | cf495bcf | bellard | { |
1700 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1701 | 67526b20 | Blue Swirl | target_long simm; |
1702 | 7a3f1944 | bellard | |
1703 | 8fec2b8c | aliguori | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1704 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1705 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1706 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1707 | 7a3f1944 | bellard | |
1708 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1709 | 6ae20372 | blueswir1 | |
1710 | a7812ae4 | pbrook | cpu_src1 = tcg_temp_new(); // const
|
1711 | a7812ae4 | pbrook | cpu_src2 = tcg_temp_new(); // const
|
1712 | 6ae20372 | blueswir1 | |
1713 | cf495bcf | bellard | switch (opc) {
|
1714 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1715 | 0f8a249a | blueswir1 | { |
1716 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1717 | 0f8a249a | blueswir1 | int32_t target; |
1718 | 0f8a249a | blueswir1 | switch (xop) {
|
1719 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1720 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1721 | 0f8a249a | blueswir1 | { |
1722 | 0f8a249a | blueswir1 | int cc;
|
1723 | 0f8a249a | blueswir1 | |
1724 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1725 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1726 | 0f8a249a | blueswir1 | target <<= 2;
|
1727 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1728 | 0f8a249a | blueswir1 | if (cc == 0) |
1729 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1730 | 0f8a249a | blueswir1 | else if (cc == 2) |
1731 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
1732 | 0f8a249a | blueswir1 | else
|
1733 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1734 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1735 | 0f8a249a | blueswir1 | } |
1736 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1737 | 0f8a249a | blueswir1 | { |
1738 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1739 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1740 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1741 | 0f8a249a | blueswir1 | target <<= 2;
|
1742 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1743 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
1744 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1745 | 0f8a249a | blueswir1 | } |
1746 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1747 | 0f8a249a | blueswir1 | { |
1748 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1749 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1750 | a80dde08 | bellard | goto jmp_insn;
|
1751 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1752 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1753 | 0f8a249a | blueswir1 | target <<= 2;
|
1754 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
1755 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1756 | 0f8a249a | blueswir1 | } |
1757 | a4d17f19 | blueswir1 | #else
|
1758 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1759 | 0f8a249a | blueswir1 | { |
1760 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1761 | 0f8a249a | blueswir1 | } |
1762 | 0f8a249a | blueswir1 | #endif
|
1763 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1764 | 0f8a249a | blueswir1 | { |
1765 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1766 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1767 | 0f8a249a | blueswir1 | target <<= 2;
|
1768 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1769 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1770 | 0f8a249a | blueswir1 | } |
1771 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1772 | 0f8a249a | blueswir1 | { |
1773 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1774 | a80dde08 | bellard | goto jmp_insn;
|
1775 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1776 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1777 | 0f8a249a | blueswir1 | target <<= 2;
|
1778 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
1779 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1780 | 0f8a249a | blueswir1 | } |
1781 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1782 | 0f8a249a | blueswir1 | if (rd) { // nop |
1783 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1784 | 2ea815ca | blueswir1 | TCGv r_const; |
1785 | 2ea815ca | blueswir1 | |
1786 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
1787 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1788 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1789 | 0f8a249a | blueswir1 | } |
1790 | 0f8a249a | blueswir1 | break;
|
1791 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1792 | 0f8a249a | blueswir1 | default:
|
1793 | 3475187d | bellard | goto illegal_insn;
|
1794 | 0f8a249a | blueswir1 | } |
1795 | 0f8a249a | blueswir1 | break;
|
1796 | 0f8a249a | blueswir1 | } |
1797 | 0f8a249a | blueswir1 | break;
|
1798 | dc1a6971 | Blue Swirl | case 1: /*CALL*/ |
1799 | dc1a6971 | Blue Swirl | { |
1800 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1801 | 2ea815ca | blueswir1 | TCGv r_const; |
1802 | cf495bcf | bellard | |
1803 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1804 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
1805 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1806 | 0f8a249a | blueswir1 | target += dc->pc; |
1807 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
1808 | 0f8a249a | blueswir1 | dc->npc = target; |
1809 | 0f8a249a | blueswir1 | } |
1810 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1811 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
1812 | 0f8a249a | blueswir1 | { |
1813 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
1814 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
1815 | cf495bcf | bellard | int cond;
|
1816 | 3475187d | bellard | |
1817 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1818 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
1819 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
1820 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
1821 | cf495bcf | bellard | } else {
|
1822 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
1823 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
1824 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
1825 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
1826 | 6f551262 | blueswir1 | } else
|
1827 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
1828 | cf495bcf | bellard | } |
1829 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
1830 | cf495bcf | bellard | if (cond == 0x8) { |
1831 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1832 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
1833 | b158a785 | blueswir1 | supervisor(dc)) |
1834 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
1835 | b158a785 | blueswir1 | else
|
1836 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
1837 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
1838 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
1839 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
1840 | af7bf89b | bellard | } else if (cond != 0) { |
1841 | a7812ae4 | pbrook | TCGv r_cond = tcg_temp_new(); |
1842 | b158a785 | blueswir1 | int l1;
|
1843 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1844 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
1845 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
1846 | 748b9d8e | blueswir1 | |
1847 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1848 | 0f8a249a | blueswir1 | if (cc == 0) |
1849 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
1850 | 0f8a249a | blueswir1 | else if (cc == 2) |
1851 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
1852 | 0f8a249a | blueswir1 | else
|
1853 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1854 | 3475187d | bellard | #else
|
1855 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1856 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
1857 | 3475187d | bellard | #endif
|
1858 | b158a785 | blueswir1 | l1 = gen_new_label(); |
1859 | b158a785 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1860 | b158a785 | blueswir1 | |
1861 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
1862 | b158a785 | blueswir1 | supervisor(dc)) |
1863 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
1864 | b158a785 | blueswir1 | else
|
1865 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
1866 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
1867 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
1868 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
1869 | b158a785 | blueswir1 | |
1870 | b158a785 | blueswir1 | gen_set_label(l1); |
1871 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
1872 | cf495bcf | bellard | } |
1873 | a80dde08 | bellard | gen_op_next_insn(); |
1874 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1875 | a80dde08 | bellard | dc->is_br = 1;
|
1876 | a80dde08 | bellard | goto jmp_insn;
|
1877 | cf495bcf | bellard | } else if (xop == 0x28) { |
1878 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1879 | cf495bcf | bellard | switch(rs1) {
|
1880 | cf495bcf | bellard | case 0: /* rdy */ |
1881 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
1882 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
1883 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
1884 | 65fe7b09 | blueswir1 | II */
|
1885 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
1886 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
1887 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
1888 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
1889 | 65fe7b09 | blueswir1 | microSPARC II */
|
1890 | 65fe7b09 | blueswir1 | #endif
|
1891 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_y); |
1892 | cf495bcf | bellard | break;
|
1893 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1894 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
1895 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1896 | a7812ae4 | pbrook | gen_helper_rdccr(cpu_dst); |
1897 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1898 | 3475187d | bellard | break;
|
1899 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
1900 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
1901 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1902 | 3475187d | bellard | break;
|
1903 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
1904 | ccd4a219 | blueswir1 | { |
1905 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
1906 | ccd4a219 | blueswir1 | |
1907 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
1908 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
1909 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
1910 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
1911 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
1912 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1913 | ccd4a219 | blueswir1 | } |
1914 | 3475187d | bellard | break;
|
1915 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
1916 | 2ea815ca | blueswir1 | { |
1917 | 2ea815ca | blueswir1 | TCGv r_const; |
1918 | 2ea815ca | blueswir1 | |
1919 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1920 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1921 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1922 | 2ea815ca | blueswir1 | } |
1923 | 0f8a249a | blueswir1 | break;
|
1924 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
1925 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
1926 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1927 | 3475187d | bellard | break;
|
1928 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
1929 | 65fe7b09 | blueswir1 | break; /* no effect */ |
1930 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
1931 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1932 | 725cb90b | bellard | goto jmp_insn;
|
1933 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_gsr); |
1934 | 725cb90b | bellard | break;
|
1935 | 9d926598 | blueswir1 | case 0x16: /* Softint */ |
1936 | 9d926598 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); |
1937 | 9d926598 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1938 | 9d926598 | blueswir1 | break;
|
1939 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
1940 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
1941 | 83469015 | bellard | break;
|
1942 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
1943 | ccd4a219 | blueswir1 | { |
1944 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
1945 | ccd4a219 | blueswir1 | |
1946 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
1947 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
1948 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
1949 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
1950 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
1951 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1952 | ccd4a219 | blueswir1 | } |
1953 | 83469015 | bellard | break;
|
1954 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
1955 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
1956 | 83469015 | bellard | break;
|
1957 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
1958 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
1959 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
1960 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
1961 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
1962 | 3475187d | bellard | #endif
|
1963 | 3475187d | bellard | default:
|
1964 | cf495bcf | bellard | goto illegal_insn;
|
1965 | cf495bcf | bellard | } |
1966 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1967 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
1968 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
1969 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1970 | 0f8a249a | blueswir1 | goto priv_insn;
|
1971 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1972 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1973 | a7812ae4 | pbrook | gen_helper_rdpsr(cpu_dst); |
1974 | e9ebed4d | blueswir1 | #else
|
1975 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
1976 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
1977 | e9ebed4d | blueswir1 | goto priv_insn;
|
1978 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1979 | e9ebed4d | blueswir1 | switch (rs1) {
|
1980 | e9ebed4d | blueswir1 | case 0: // hpstate |
1981 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
1982 | e9ebed4d | blueswir1 | break;
|
1983 | e9ebed4d | blueswir1 | case 1: // htstate |
1984 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
1985 | e9ebed4d | blueswir1 | break;
|
1986 | e9ebed4d | blueswir1 | case 3: // hintp |
1987 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
1988 | e9ebed4d | blueswir1 | break;
|
1989 | e9ebed4d | blueswir1 | case 5: // htba |
1990 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
1991 | e9ebed4d | blueswir1 | break;
|
1992 | e9ebed4d | blueswir1 | case 6: // hver |
1993 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
1994 | e9ebed4d | blueswir1 | break;
|
1995 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
1996 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
1997 | e9ebed4d | blueswir1 | break;
|
1998 | e9ebed4d | blueswir1 | default:
|
1999 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2000 | e9ebed4d | blueswir1 | } |
2001 | e9ebed4d | blueswir1 | #endif
|
2002 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2003 | e8af50a3 | bellard | break;
|
2004 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2005 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2006 | 0f8a249a | blueswir1 | goto priv_insn;
|
2007 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2008 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2009 | 0f8a249a | blueswir1 | switch (rs1) {
|
2010 | 0f8a249a | blueswir1 | case 0: // tpc |
2011 | 375ee38b | blueswir1 | { |
2012 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2013 | 375ee38b | blueswir1 | |
2014 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2015 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2016 | a7812ae4 | pbrook | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2017 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2018 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2019 | 375ee38b | blueswir1 | } |
2020 | 0f8a249a | blueswir1 | break;
|
2021 | 0f8a249a | blueswir1 | case 1: // tnpc |
2022 | 375ee38b | blueswir1 | { |
2023 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2024 | 375ee38b | blueswir1 | |
2025 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2026 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2027 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2028 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2029 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2030 | 375ee38b | blueswir1 | } |
2031 | 0f8a249a | blueswir1 | break;
|
2032 | 0f8a249a | blueswir1 | case 2: // tstate |
2033 | 375ee38b | blueswir1 | { |
2034 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2035 | 375ee38b | blueswir1 | |
2036 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2037 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2038 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2039 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2040 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2041 | 375ee38b | blueswir1 | } |
2042 | 0f8a249a | blueswir1 | break;
|
2043 | 0f8a249a | blueswir1 | case 3: // tt |
2044 | 375ee38b | blueswir1 | { |
2045 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2046 | 375ee38b | blueswir1 | |
2047 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2048 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2049 | a7812ae4 | pbrook | tcg_gen_ld_i32(cpu_tmp32, r_tsptr, |
2050 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2051 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2052 | a7812ae4 | pbrook | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2053 | 375ee38b | blueswir1 | } |
2054 | 0f8a249a | blueswir1 | break;
|
2055 | 0f8a249a | blueswir1 | case 4: // tick |
2056 | ccd4a219 | blueswir1 | { |
2057 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2058 | ccd4a219 | blueswir1 | |
2059 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2060 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2061 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2062 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
2063 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2064 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2065 | ccd4a219 | blueswir1 | } |
2066 | 0f8a249a | blueswir1 | break;
|
2067 | 0f8a249a | blueswir1 | case 5: // tba |
2068 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2069 | 0f8a249a | blueswir1 | break;
|
2070 | 0f8a249a | blueswir1 | case 6: // pstate |
2071 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2072 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2073 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2074 | 0f8a249a | blueswir1 | break;
|
2075 | 0f8a249a | blueswir1 | case 7: // tl |
2076 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2077 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2078 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2079 | 0f8a249a | blueswir1 | break;
|
2080 | 0f8a249a | blueswir1 | case 8: // pil |
2081 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2082 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2083 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2084 | 0f8a249a | blueswir1 | break;
|
2085 | 0f8a249a | blueswir1 | case 9: // cwp |
2086 | a7812ae4 | pbrook | gen_helper_rdcwp(cpu_tmp0); |
2087 | 0f8a249a | blueswir1 | break;
|
2088 | 0f8a249a | blueswir1 | case 10: // cansave |
2089 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2090 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2091 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2092 | 0f8a249a | blueswir1 | break;
|
2093 | 0f8a249a | blueswir1 | case 11: // canrestore |
2094 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2095 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2096 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2097 | 0f8a249a | blueswir1 | break;
|
2098 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2099 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2100 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2101 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2102 | 0f8a249a | blueswir1 | break;
|
2103 | 0f8a249a | blueswir1 | case 13: // otherwin |
2104 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2105 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2106 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2107 | 0f8a249a | blueswir1 | break;
|
2108 | 0f8a249a | blueswir1 | case 14: // wstate |
2109 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2110 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2111 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2112 | 0f8a249a | blueswir1 | break;
|
2113 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2114 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2115 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2116 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2117 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2118 | e9ebed4d | blueswir1 | break;
|
2119 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2120 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2121 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2122 | e9ebed4d | blueswir1 | goto priv_insn;
|
2123 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); |
2124 | e9ebed4d | blueswir1 | break;
|
2125 | 0f8a249a | blueswir1 | case 31: // ver |
2126 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2127 | 0f8a249a | blueswir1 | break;
|
2128 | 0f8a249a | blueswir1 | case 15: // fq |
2129 | 0f8a249a | blueswir1 | default:
|
2130 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2131 | 0f8a249a | blueswir1 | } |
2132 | 3475187d | bellard | #else
|
2133 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2134 | 3475187d | bellard | #endif
|
2135 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2136 | e8af50a3 | bellard | break;
|
2137 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2138 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2139 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2140 | a7812ae4 | pbrook | gen_helper_flushw(); |
2141 | 3475187d | bellard | #else
|
2142 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2143 | 0f8a249a | blueswir1 | goto priv_insn;
|
2144 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tbr); |
2145 | 3475187d | bellard | #endif
|
2146 | e8af50a3 | bellard | break;
|
2147 | e8af50a3 | bellard | #endif
|
2148 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2149 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2150 | a80dde08 | bellard | goto jmp_insn;
|
2151 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2152 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2153 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2154 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2155 | 0f8a249a | blueswir1 | switch (xop) {
|
2156 | dc1a6971 | Blue Swirl | case 0x1: /* fmovs */ |
2157 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2158 | dc1a6971 | Blue Swirl | break;
|
2159 | dc1a6971 | Blue Swirl | case 0x5: /* fnegs */ |
2160 | dc1a6971 | Blue Swirl | gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
2161 | dc1a6971 | Blue Swirl | break;
|
2162 | dc1a6971 | Blue Swirl | case 0x9: /* fabss */ |
2163 | dc1a6971 | Blue Swirl | gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
2164 | dc1a6971 | Blue Swirl | break;
|
2165 | dc1a6971 | Blue Swirl | case 0x29: /* fsqrts */ |
2166 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2167 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2168 | dc1a6971 | Blue Swirl | gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
2169 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2170 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2171 | dc1a6971 | Blue Swirl | break;
|
2172 | dc1a6971 | Blue Swirl | case 0x2a: /* fsqrtd */ |
2173 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2174 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2175 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2176 | dc1a6971 | Blue Swirl | gen_helper_fsqrtd(); |
2177 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2178 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2179 | dc1a6971 | Blue Swirl | break;
|
2180 | dc1a6971 | Blue Swirl | case 0x2b: /* fsqrtq */ |
2181 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2182 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2183 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2184 | dc1a6971 | Blue Swirl | gen_helper_fsqrtq(); |
2185 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2186 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2187 | dc1a6971 | Blue Swirl | break;
|
2188 | dc1a6971 | Blue Swirl | case 0x41: /* fadds */ |
2189 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2190 | dc1a6971 | Blue Swirl | gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2191 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2192 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2193 | dc1a6971 | Blue Swirl | break;
|
2194 | dc1a6971 | Blue Swirl | case 0x42: /* faddd */ |
2195 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2196 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2197 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2198 | dc1a6971 | Blue Swirl | gen_helper_faddd(); |
2199 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2200 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2201 | dc1a6971 | Blue Swirl | break;
|
2202 | dc1a6971 | Blue Swirl | case 0x43: /* faddq */ |
2203 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2204 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2205 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2206 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2207 | dc1a6971 | Blue Swirl | gen_helper_faddq(); |
2208 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2209 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2210 | dc1a6971 | Blue Swirl | break;
|
2211 | dc1a6971 | Blue Swirl | case 0x45: /* fsubs */ |
2212 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2213 | dc1a6971 | Blue Swirl | gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2214 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2215 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2216 | dc1a6971 | Blue Swirl | break;
|
2217 | dc1a6971 | Blue Swirl | case 0x46: /* fsubd */ |
2218 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2219 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2220 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2221 | dc1a6971 | Blue Swirl | gen_helper_fsubd(); |
2222 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2223 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2224 | dc1a6971 | Blue Swirl | break;
|
2225 | dc1a6971 | Blue Swirl | case 0x47: /* fsubq */ |
2226 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2227 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2228 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2229 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2230 | dc1a6971 | Blue Swirl | gen_helper_fsubq(); |
2231 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2232 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2233 | dc1a6971 | Blue Swirl | break;
|
2234 | dc1a6971 | Blue Swirl | case 0x49: /* fmuls */ |
2235 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2236 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2237 | dc1a6971 | Blue Swirl | gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2238 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2239 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2240 | dc1a6971 | Blue Swirl | break;
|
2241 | dc1a6971 | Blue Swirl | case 0x4a: /* fmuld */ |
2242 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2243 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2244 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2245 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2246 | dc1a6971 | Blue Swirl | gen_helper_fmuld(); |
2247 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2248 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2249 | dc1a6971 | Blue Swirl | break;
|
2250 | dc1a6971 | Blue Swirl | case 0x4b: /* fmulq */ |
2251 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2252 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2253 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2254 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2255 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2256 | dc1a6971 | Blue Swirl | gen_helper_fmulq(); |
2257 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2258 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2259 | dc1a6971 | Blue Swirl | break;
|
2260 | dc1a6971 | Blue Swirl | case 0x4d: /* fdivs */ |
2261 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2262 | dc1a6971 | Blue Swirl | gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2263 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2264 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2265 | dc1a6971 | Blue Swirl | break;
|
2266 | dc1a6971 | Blue Swirl | case 0x4e: /* fdivd */ |
2267 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2268 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2269 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2270 | dc1a6971 | Blue Swirl | gen_helper_fdivd(); |
2271 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2272 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2273 | dc1a6971 | Blue Swirl | break;
|
2274 | dc1a6971 | Blue Swirl | case 0x4f: /* fdivq */ |
2275 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2276 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2277 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2278 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2279 | dc1a6971 | Blue Swirl | gen_helper_fdivq(); |
2280 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2281 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2282 | dc1a6971 | Blue Swirl | break;
|
2283 | dc1a6971 | Blue Swirl | case 0x69: /* fsmuld */ |
2284 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSMULD); |
2285 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2286 | dc1a6971 | Blue Swirl | gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
2287 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2288 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2289 | dc1a6971 | Blue Swirl | break;
|
2290 | dc1a6971 | Blue Swirl | case 0x6e: /* fdmulq */ |
2291 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2292 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2293 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2294 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2295 | dc1a6971 | Blue Swirl | gen_helper_fdmulq(); |
2296 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2297 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2298 | dc1a6971 | Blue Swirl | break;
|
2299 | dc1a6971 | Blue Swirl | case 0xc4: /* fitos */ |
2300 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2301 | dc1a6971 | Blue Swirl | gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
2302 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2303 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2304 | dc1a6971 | Blue Swirl | break;
|
2305 | dc1a6971 | Blue Swirl | case 0xc6: /* fdtos */ |
2306 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2307 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2308 | dc1a6971 | Blue Swirl | gen_helper_fdtos(cpu_tmp32); |
2309 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2310 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2311 | dc1a6971 | Blue Swirl | break;
|
2312 | dc1a6971 | Blue Swirl | case 0xc7: /* fqtos */ |
2313 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2314 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2315 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2316 | dc1a6971 | Blue Swirl | gen_helper_fqtos(cpu_tmp32); |
2317 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2318 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2319 | dc1a6971 | Blue Swirl | break;
|
2320 | dc1a6971 | Blue Swirl | case 0xc8: /* fitod */ |
2321 | dc1a6971 | Blue Swirl | gen_helper_fitod(cpu_fpr[rs2]); |
2322 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2323 | dc1a6971 | Blue Swirl | break;
|
2324 | dc1a6971 | Blue Swirl | case 0xc9: /* fstod */ |
2325 | dc1a6971 | Blue Swirl | gen_helper_fstod(cpu_fpr[rs2]); |
2326 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2327 | dc1a6971 | Blue Swirl | break;
|
2328 | dc1a6971 | Blue Swirl | case 0xcb: /* fqtod */ |
2329 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2330 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2331 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2332 | dc1a6971 | Blue Swirl | gen_helper_fqtod(); |
2333 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2334 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2335 | dc1a6971 | Blue Swirl | break;
|
2336 | dc1a6971 | Blue Swirl | case 0xcc: /* fitoq */ |
2337 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2338 | dc1a6971 | Blue Swirl | gen_helper_fitoq(cpu_fpr[rs2]); |
2339 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2340 | dc1a6971 | Blue Swirl | break;
|
2341 | dc1a6971 | Blue Swirl | case 0xcd: /* fstoq */ |
2342 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2343 | dc1a6971 | Blue Swirl | gen_helper_fstoq(cpu_fpr[rs2]); |
2344 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2345 | dc1a6971 | Blue Swirl | break;
|
2346 | dc1a6971 | Blue Swirl | case 0xce: /* fdtoq */ |
2347 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2348 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2349 | dc1a6971 | Blue Swirl | gen_helper_fdtoq(); |
2350 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2351 | dc1a6971 | Blue Swirl | break;
|
2352 | dc1a6971 | Blue Swirl | case 0xd1: /* fstoi */ |
2353 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2354 | dc1a6971 | Blue Swirl | gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
2355 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2356 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2357 | dc1a6971 | Blue Swirl | break;
|
2358 | dc1a6971 | Blue Swirl | case 0xd2: /* fdtoi */ |
2359 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2360 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2361 | dc1a6971 | Blue Swirl | gen_helper_fdtoi(cpu_tmp32); |
2362 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2363 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2364 | dc1a6971 | Blue Swirl | break;
|
2365 | dc1a6971 | Blue Swirl | case 0xd3: /* fqtoi */ |
2366 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2367 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2368 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2369 | dc1a6971 | Blue Swirl | gen_helper_fqtoi(cpu_tmp32); |
2370 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2371 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2372 | dc1a6971 | Blue Swirl | break;
|
2373 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2374 | dc1a6971 | Blue Swirl | case 0x2: /* V9 fmovd */ |
2375 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2376 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
2377 | dc1a6971 | Blue Swirl | cpu_fpr[DFPREG(rs2) + 1]);
|
2378 | dc1a6971 | Blue Swirl | break;
|
2379 | dc1a6971 | Blue Swirl | case 0x3: /* V9 fmovq */ |
2380 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2381 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2382 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
|
2383 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 1]);
|
2384 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
|
2385 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 2]);
|
2386 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
|
2387 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 3]);
|
2388 | dc1a6971 | Blue Swirl | break;
|
2389 | dc1a6971 | Blue Swirl | case 0x6: /* V9 fnegd */ |
2390 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2391 | dc1a6971 | Blue Swirl | gen_helper_fnegd(); |
2392 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2393 | dc1a6971 | Blue Swirl | break;
|
2394 | dc1a6971 | Blue Swirl | case 0x7: /* V9 fnegq */ |
2395 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2396 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2397 | dc1a6971 | Blue Swirl | gen_helper_fnegq(); |
2398 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2399 | dc1a6971 | Blue Swirl | break;
|
2400 | dc1a6971 | Blue Swirl | case 0xa: /* V9 fabsd */ |
2401 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2402 | dc1a6971 | Blue Swirl | gen_helper_fabsd(); |
2403 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2404 | dc1a6971 | Blue Swirl | break;
|
2405 | dc1a6971 | Blue Swirl | case 0xb: /* V9 fabsq */ |
2406 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2407 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2408 | dc1a6971 | Blue Swirl | gen_helper_fabsq(); |
2409 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2410 | dc1a6971 | Blue Swirl | break;
|
2411 | dc1a6971 | Blue Swirl | case 0x81: /* V9 fstox */ |
2412 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2413 | dc1a6971 | Blue Swirl | gen_helper_fstox(cpu_fpr[rs2]); |
2414 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2415 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2416 | dc1a6971 | Blue Swirl | break;
|
2417 | dc1a6971 | Blue Swirl | case 0x82: /* V9 fdtox */ |
2418 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2419 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2420 | dc1a6971 | Blue Swirl | gen_helper_fdtox(); |
2421 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2422 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2423 | dc1a6971 | Blue Swirl | break;
|
2424 | dc1a6971 | Blue Swirl | case 0x83: /* V9 fqtox */ |
2425 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2426 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2427 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2428 | dc1a6971 | Blue Swirl | gen_helper_fqtox(); |
2429 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2430 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2431 | dc1a6971 | Blue Swirl | break;
|
2432 | dc1a6971 | Blue Swirl | case 0x84: /* V9 fxtos */ |
2433 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2434 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2435 | dc1a6971 | Blue Swirl | gen_helper_fxtos(cpu_tmp32); |
2436 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2437 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2438 | dc1a6971 | Blue Swirl | break;
|
2439 | dc1a6971 | Blue Swirl | case 0x88: /* V9 fxtod */ |
2440 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2441 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2442 | dc1a6971 | Blue Swirl | gen_helper_fxtod(); |
2443 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2444 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2445 | dc1a6971 | Blue Swirl | break;
|
2446 | dc1a6971 | Blue Swirl | case 0x8c: /* V9 fxtoq */ |
2447 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2448 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2449 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2450 | dc1a6971 | Blue Swirl | gen_helper_fxtoq(); |
2451 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2452 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2453 | dc1a6971 | Blue Swirl | break;
|
2454 | 1f587329 | blueswir1 | #endif
|
2455 | dc1a6971 | Blue Swirl | default:
|
2456 | dc1a6971 | Blue Swirl | goto illegal_insn;
|
2457 | 0f8a249a | blueswir1 | } |
2458 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2459 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2460 | 0f8a249a | blueswir1 | int cond;
|
2461 | 3475187d | bellard | #endif
|
2462 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2463 | a80dde08 | bellard | goto jmp_insn;
|
2464 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2465 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2466 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2467 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2468 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2469 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2470 | dcf24905 | blueswir1 | int l1;
|
2471 | dcf24905 | blueswir1 | |
2472 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2473 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2474 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2475 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2476 | cb63669a | pbrook | 0, l1);
|
2477 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2478 | dcf24905 | blueswir1 | gen_set_label(l1); |
2479 | 0f8a249a | blueswir1 | break;
|
2480 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2481 | dcf24905 | blueswir1 | int l1;
|
2482 | dcf24905 | blueswir1 | |
2483 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2484 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2485 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2486 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2487 | cb63669a | pbrook | 0, l1);
|
2488 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2489 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
2490 | dcf24905 | blueswir1 | gen_set_label(l1); |
2491 | 0f8a249a | blueswir1 | break;
|
2492 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2493 | dcf24905 | blueswir1 | int l1;
|
2494 | dcf24905 | blueswir1 | |
2495 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2496 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2497 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2498 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2499 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2500 | cb63669a | pbrook | 0, l1);
|
2501 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2502 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
2503 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
2504 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
2505 | dcf24905 | blueswir1 | gen_set_label(l1); |
2506 | 1f587329 | blueswir1 | break;
|
2507 | 0f8a249a | blueswir1 | } |
2508 | 0f8a249a | blueswir1 | #endif
|
2509 | 0f8a249a | blueswir1 | switch (xop) {
|
2510 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2511 | 714547bb | blueswir1 | #define FMOVSCC(fcc) \
|
2512 | 19f329ad | blueswir1 | { \ |
2513 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2514 | 19f329ad | blueswir1 | int l1; \
|
2515 | 19f329ad | blueswir1 | \ |
2516 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2517 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2518 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2519 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2520 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2521 | cb63669a | pbrook | 0, l1); \
|
2522 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2523 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2524 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2525 | 714547bb | blueswir1 | } |
2526 | 714547bb | blueswir1 | #define FMOVDCC(fcc) \
|
2527 | 714547bb | blueswir1 | { \ |
2528 | 714547bb | blueswir1 | TCGv r_cond; \ |
2529 | 714547bb | blueswir1 | int l1; \
|
2530 | 714547bb | blueswir1 | \ |
2531 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2532 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2533 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2534 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2535 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2536 | 714547bb | blueswir1 | 0, l1); \
|
2537 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2538 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2539 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2540 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2541 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2542 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2543 | 714547bb | blueswir1 | } |
2544 | 714547bb | blueswir1 | #define FMOVQCC(fcc) \
|
2545 | 714547bb | blueswir1 | { \ |
2546 | 714547bb | blueswir1 | TCGv r_cond; \ |
2547 | 714547bb | blueswir1 | int l1; \
|
2548 | 714547bb | blueswir1 | \ |
2549 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2550 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2551 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2552 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2553 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2554 | 714547bb | blueswir1 | 0, l1); \
|
2555 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2556 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2557 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2558 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2559 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2560 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2561 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2562 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2563 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2564 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2565 | 19f329ad | blueswir1 | } |
2566 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2567 | 714547bb | blueswir1 | FMOVSCC(0);
|
2568 | 0f8a249a | blueswir1 | break;
|
2569 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2570 | 714547bb | blueswir1 | FMOVDCC(0);
|
2571 | 0f8a249a | blueswir1 | break;
|
2572 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2573 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2574 | 714547bb | blueswir1 | FMOVQCC(0);
|
2575 | 1f587329 | blueswir1 | break;
|
2576 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2577 | 714547bb | blueswir1 | FMOVSCC(1);
|
2578 | 0f8a249a | blueswir1 | break;
|
2579 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2580 | 714547bb | blueswir1 | FMOVDCC(1);
|
2581 | 0f8a249a | blueswir1 | break;
|
2582 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2583 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2584 | 714547bb | blueswir1 | FMOVQCC(1);
|
2585 | 1f587329 | blueswir1 | break;
|
2586 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2587 | 714547bb | blueswir1 | FMOVSCC(2);
|
2588 | 0f8a249a | blueswir1 | break;
|
2589 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2590 | 714547bb | blueswir1 | FMOVDCC(2);
|
2591 | 0f8a249a | blueswir1 | break;
|
2592 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2593 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2594 | 714547bb | blueswir1 | FMOVQCC(2);
|
2595 | 1f587329 | blueswir1 | break;
|
2596 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2597 | 714547bb | blueswir1 | FMOVSCC(3);
|
2598 | 0f8a249a | blueswir1 | break;
|
2599 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2600 | 714547bb | blueswir1 | FMOVDCC(3);
|
2601 | 0f8a249a | blueswir1 | break;
|
2602 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2603 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2604 | 714547bb | blueswir1 | FMOVQCC(3);
|
2605 | 1f587329 | blueswir1 | break;
|
2606 | 714547bb | blueswir1 | #undef FMOVSCC
|
2607 | 714547bb | blueswir1 | #undef FMOVDCC
|
2608 | 714547bb | blueswir1 | #undef FMOVQCC
|
2609 | 714547bb | blueswir1 | #define FMOVSCC(icc) \
|
2610 | 714547bb | blueswir1 | { \ |
2611 | 714547bb | blueswir1 | TCGv r_cond; \ |
2612 | 714547bb | blueswir1 | int l1; \
|
2613 | 714547bb | blueswir1 | \ |
2614 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2615 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2616 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2617 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2618 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2619 | 714547bb | blueswir1 | 0, l1); \
|
2620 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2621 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2622 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2623 | 714547bb | blueswir1 | } |
2624 | 714547bb | blueswir1 | #define FMOVDCC(icc) \
|
2625 | 714547bb | blueswir1 | { \ |
2626 | 714547bb | blueswir1 | TCGv r_cond; \ |
2627 | 714547bb | blueswir1 | int l1; \
|
2628 | 714547bb | blueswir1 | \ |
2629 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2630 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2631 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2632 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2633 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2634 | 714547bb | blueswir1 | 0, l1); \
|
2635 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2636 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2637 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2638 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2639 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2640 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2641 | 714547bb | blueswir1 | } |
2642 | 714547bb | blueswir1 | #define FMOVQCC(icc) \
|
2643 | 714547bb | blueswir1 | { \ |
2644 | 714547bb | blueswir1 | TCGv r_cond; \ |
2645 | 714547bb | blueswir1 | int l1; \
|
2646 | 714547bb | blueswir1 | \ |
2647 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2648 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2649 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2650 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2651 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2652 | 714547bb | blueswir1 | 0, l1); \
|
2653 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2654 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2655 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2656 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2657 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2658 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2659 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2660 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2661 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2662 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2663 | 714547bb | blueswir1 | } |
2664 | 19f329ad | blueswir1 | |
2665 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2666 | 714547bb | blueswir1 | FMOVSCC(0);
|
2667 | 0f8a249a | blueswir1 | break;
|
2668 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2669 | 714547bb | blueswir1 | FMOVDCC(0);
|
2670 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2671 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2672 | 714547bb | blueswir1 | FMOVQCC(0);
|
2673 | 1f587329 | blueswir1 | break;
|
2674 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2675 | 714547bb | blueswir1 | FMOVSCC(1);
|
2676 | 0f8a249a | blueswir1 | break;
|
2677 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2678 | 714547bb | blueswir1 | FMOVDCC(1);
|
2679 | 0f8a249a | blueswir1 | break;
|
2680 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2681 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2682 | 714547bb | blueswir1 | FMOVQCC(1);
|
2683 | 1f587329 | blueswir1 | break;
|
2684 | 714547bb | blueswir1 | #undef FMOVSCC
|
2685 | 714547bb | blueswir1 | #undef FMOVDCC
|
2686 | 714547bb | blueswir1 | #undef FMOVQCC
|
2687 | 1f587329 | blueswir1 | #endif
|
2688 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2689 | 714547bb | blueswir1 | gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2690 | 0f8a249a | blueswir1 | break;
|
2691 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2692 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2693 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2694 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2695 | 0f8a249a | blueswir1 | break;
|
2696 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2697 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2698 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2699 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2700 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2701 | 1f587329 | blueswir1 | break;
|
2702 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2703 | 714547bb | blueswir1 | gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2704 | 0f8a249a | blueswir1 | break;
|
2705 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2706 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2707 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2708 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2709 | 0f8a249a | blueswir1 | break;
|
2710 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2711 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2712 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2713 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2714 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2715 | 1f587329 | blueswir1 | break;
|
2716 | 0f8a249a | blueswir1 | default:
|
2717 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2718 | 0f8a249a | blueswir1 | } |
2719 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2720 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2721 | e80cfcfc | bellard | |
2722 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2723 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2724 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2725 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2726 | 2ea815ca | blueswir1 | TCGv r_const; |
2727 | 2ea815ca | blueswir1 | |
2728 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2729 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
2730 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2731 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2732 | 0f8a249a | blueswir1 | } else { /* register */ |
2733 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2734 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
2735 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2736 | 0f8a249a | blueswir1 | } |
2737 | 0f8a249a | blueswir1 | } else {
|
2738 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2739 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2740 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2741 | 67526b20 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2742 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2743 | 0f8a249a | blueswir1 | } else { /* register */ |
2744 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2745 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2746 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2747 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2748 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2749 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2750 | 6f551262 | blueswir1 | } else
|
2751 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
2752 | 0f8a249a | blueswir1 | } |
2753 | 0f8a249a | blueswir1 | } |
2754 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2755 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2756 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2757 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2758 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2759 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2760 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2761 | 1a2fb1c0 | blueswir1 | } else {
|
2762 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
|
2763 | 1a2fb1c0 | blueswir1 | } |
2764 | 0f8a249a | blueswir1 | } else { /* register */ |
2765 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2766 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2767 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2768 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2769 | 1a2fb1c0 | blueswir1 | } else {
|
2770 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2771 | 1a2fb1c0 | blueswir1 | } |
2772 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2773 | 83469015 | bellard | } |
2774 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2775 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2776 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2777 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2778 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2779 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2780 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2781 | 1a2fb1c0 | blueswir1 | } else {
|
2782 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2783 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2784 | 1a2fb1c0 | blueswir1 | } |
2785 | 0f8a249a | blueswir1 | } else { /* register */ |
2786 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2787 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2788 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2789 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2790 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2791 | 1a2fb1c0 | blueswir1 | } else {
|
2792 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2793 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2794 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2795 | 1a2fb1c0 | blueswir1 | } |
2796 | 83469015 | bellard | } |
2797 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2798 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2799 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2800 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2801 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2802 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2803 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2804 | 1a2fb1c0 | blueswir1 | } else {
|
2805 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2806 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2807 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2808 | 1a2fb1c0 | blueswir1 | } |
2809 | 0f8a249a | blueswir1 | } else { /* register */ |
2810 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2811 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2812 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2813 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2814 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2815 | 1a2fb1c0 | blueswir1 | } else {
|
2816 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2817 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2818 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2819 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2820 | 1a2fb1c0 | blueswir1 | } |
2821 | 83469015 | bellard | } |
2822 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2823 | 83469015 | bellard | #endif
|
2824 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
2825 | cf495bcf | bellard | if (xop < 0x20) { |
2826 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
2827 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
2828 | cf495bcf | bellard | switch (xop & ~0x10) { |
2829 | b89e94af | Blue Swirl | case 0x0: /* add */ |
2830 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2831 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2832 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2833 | 41d72852 | Blue Swirl | gen_op_addi_cc(cpu_dst, cpu_src1, simm); |
2834 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
2835 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
2836 | 41d72852 | Blue Swirl | } else {
|
2837 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
2838 | 41d72852 | Blue Swirl | } |
2839 | 41d72852 | Blue Swirl | } else {
|
2840 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2841 | 41d72852 | Blue Swirl | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
2842 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
2843 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
2844 | 41d72852 | Blue Swirl | } else {
|
2845 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2846 | 41d72852 | Blue Swirl | } |
2847 | 41d72852 | Blue Swirl | } |
2848 | cf495bcf | bellard | break;
|
2849 | b89e94af | Blue Swirl | case 0x1: /* and */ |
2850 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2851 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2852 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); |
2853 | 41d72852 | Blue Swirl | } else {
|
2854 | 41d72852 | Blue Swirl | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
2855 | 41d72852 | Blue Swirl | } |
2856 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2857 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2858 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2859 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2860 | 41d72852 | Blue Swirl | } |
2861 | cf495bcf | bellard | break;
|
2862 | b89e94af | Blue Swirl | case 0x2: /* or */ |
2863 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2864 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2865 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2866 | 41d72852 | Blue Swirl | } else {
|
2867 | 41d72852 | Blue Swirl | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2868 | 41d72852 | Blue Swirl | } |
2869 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2870 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2871 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2872 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2873 | 8393617c | Blue Swirl | } |
2874 | 0f8a249a | blueswir1 | break;
|
2875 | b89e94af | Blue Swirl | case 0x3: /* xor */ |
2876 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2877 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2878 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); |
2879 | 41d72852 | Blue Swirl | } else {
|
2880 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
2881 | 41d72852 | Blue Swirl | } |
2882 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2883 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2884 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2885 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2886 | 8393617c | Blue Swirl | } |
2887 | cf495bcf | bellard | break;
|
2888 | b89e94af | Blue Swirl | case 0x4: /* sub */ |
2889 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2890 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2891 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2892 | d4b0d468 | Blue Swirl | gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc); |
2893 | 41d72852 | Blue Swirl | } else {
|
2894 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_dst, cpu_src1, simm); |
2895 | 41d72852 | Blue Swirl | } |
2896 | 41d72852 | Blue Swirl | } else {
|
2897 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2898 | 41d72852 | Blue Swirl | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
2899 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
2900 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
2901 | 41d72852 | Blue Swirl | } else {
|
2902 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
2903 | 41d72852 | Blue Swirl | } |
2904 | 41d72852 | Blue Swirl | } |
2905 | cf495bcf | bellard | break;
|
2906 | b89e94af | Blue Swirl | case 0x5: /* andn */ |
2907 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2908 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2909 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); |
2910 | 41d72852 | Blue Swirl | } else {
|
2911 | 41d72852 | Blue Swirl | tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
2912 | 41d72852 | Blue Swirl | } |
2913 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2914 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2915 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2916 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2917 | 8393617c | Blue Swirl | } |
2918 | cf495bcf | bellard | break;
|
2919 | b89e94af | Blue Swirl | case 0x6: /* orn */ |
2920 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2921 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2922 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); |
2923 | 41d72852 | Blue Swirl | } else {
|
2924 | 41d72852 | Blue Swirl | tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
2925 | 41d72852 | Blue Swirl | } |
2926 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2927 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2928 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2929 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2930 | 8393617c | Blue Swirl | } |
2931 | cf495bcf | bellard | break;
|
2932 | b89e94af | Blue Swirl | case 0x7: /* xorn */ |
2933 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2934 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2935 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); |
2936 | 41d72852 | Blue Swirl | } else {
|
2937 | 41d72852 | Blue Swirl | tcg_gen_not_tl(cpu_tmp0, cpu_src2); |
2938 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2939 | 41d72852 | Blue Swirl | } |
2940 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2941 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2942 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2943 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2944 | 8393617c | Blue Swirl | } |
2945 | cf495bcf | bellard | break;
|
2946 | b89e94af | Blue Swirl | case 0x8: /* addx, V9 addc */ |
2947 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2948 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2949 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2950 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2951 | 41d72852 | Blue Swirl | gen_op_addxi_cc(cpu_dst, cpu_src1, simm); |
2952 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
2953 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
2954 | 8393617c | Blue Swirl | } else {
|
2955 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2956 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2957 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
2958 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2959 | 41d72852 | Blue Swirl | } |
2960 | 41d72852 | Blue Swirl | } else {
|
2961 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2962 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2963 | 41d72852 | Blue Swirl | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
2964 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
2965 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
2966 | 8393617c | Blue Swirl | } else {
|
2967 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2968 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2969 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
2970 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2971 | 41d72852 | Blue Swirl | } |
2972 | 38bc628b | blueswir1 | } |
2973 | cf495bcf | bellard | break;
|
2974 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
2975 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
2976 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2977 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2978 | 41d72852 | Blue Swirl | tcg_gen_muli_i64(cpu_dst, cpu_src1, simm); |
2979 | 41d72852 | Blue Swirl | } else {
|
2980 | 41d72852 | Blue Swirl | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
2981 | 41d72852 | Blue Swirl | } |
2982 | ded3ab80 | pbrook | break;
|
2983 | ded3ab80 | pbrook | #endif
|
2984 | b89e94af | Blue Swirl | case 0xa: /* umul */ |
2985 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
2986 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
2987 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2988 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2989 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2990 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2991 | 8393617c | Blue Swirl | } |
2992 | cf495bcf | bellard | break;
|
2993 | b89e94af | Blue Swirl | case 0xb: /* smul */ |
2994 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
2995 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
2996 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2997 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2998 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2999 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3000 | 8393617c | Blue Swirl | } |
3001 | cf495bcf | bellard | break;
|
3002 | b89e94af | Blue Swirl | case 0xc: /* subx, V9 subc */ |
3003 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3004 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3005 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3006 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3007 | 41d72852 | Blue Swirl | gen_op_subxi_cc(cpu_dst, cpu_src1, simm); |
3008 | 2ca1d92b | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
3009 | 2ca1d92b | Blue Swirl | dc->cc_op = CC_OP_SUBX; |
3010 | 41d72852 | Blue Swirl | } else {
|
3011 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3012 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3013 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
3014 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3015 | 41d72852 | Blue Swirl | } |
3016 | 41d72852 | Blue Swirl | } else {
|
3017 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3018 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3019 | 41d72852 | Blue Swirl | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
3020 | 2ca1d92b | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
3021 | 2ca1d92b | Blue Swirl | dc->cc_op = CC_OP_SUBX; |
3022 | 41d72852 | Blue Swirl | } else {
|
3023 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3024 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3025 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3026 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3027 | 41d72852 | Blue Swirl | } |
3028 | 38bc628b | blueswir1 | } |
3029 | cf495bcf | bellard | break;
|
3030 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3031 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3032 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3033 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3034 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3035 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3036 | ded3ab80 | pbrook | break;
|
3037 | ded3ab80 | pbrook | #endif
|
3038 | b89e94af | Blue Swirl | case 0xe: /* udiv */ |
3039 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3040 | a7812ae4 | pbrook | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
3041 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3042 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3043 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3044 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3045 | 8393617c | Blue Swirl | } |
3046 | cf495bcf | bellard | break;
|
3047 | b89e94af | Blue Swirl | case 0xf: /* sdiv */ |
3048 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3049 | a7812ae4 | pbrook | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
3050 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3051 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3052 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3053 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3054 | 8393617c | Blue Swirl | } |
3055 | cf495bcf | bellard | break;
|
3056 | cf495bcf | bellard | default:
|
3057 | cf495bcf | bellard | goto illegal_insn;
|
3058 | cf495bcf | bellard | } |
3059 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3060 | cf495bcf | bellard | } else {
|
3061 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
3062 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
3063 | cf495bcf | bellard | switch (xop) {
|
3064 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3065 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3066 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3067 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); |
3068 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADD; |
3069 | 0f8a249a | blueswir1 | break;
|
3070 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3071 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3072 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3073 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); |
3074 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUB; |
3075 | 0f8a249a | blueswir1 | break;
|
3076 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3077 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3078 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3079 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3080 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV); |
3081 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADDTV; |
3082 | 0f8a249a | blueswir1 | break;
|
3083 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3084 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3085 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3086 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3087 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV); |
3088 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUBTV; |
3089 | 0f8a249a | blueswir1 | break;
|
3090 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3091 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3092 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3093 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3094 | d084469c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3095 | d084469c | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3096 | cf495bcf | bellard | break;
|
3097 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3098 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3099 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3100 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3101 | 67526b20 | Blue Swirl | tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3102 | e35298cd | blueswir1 | } else { /* register */ |
3103 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3104 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3105 | e35298cd | blueswir1 | } |
3106 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3107 | cf495bcf | bellard | break;
|
3108 | 83469015 | bellard | case 0x26: /* srl */ |
3109 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3110 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3111 | 67526b20 | Blue Swirl | tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3112 | e35298cd | blueswir1 | } else { /* register */ |
3113 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3114 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3115 | e35298cd | blueswir1 | } |
3116 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3117 | cf495bcf | bellard | break;
|
3118 | 83469015 | bellard | case 0x27: /* sra */ |
3119 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3120 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3121 | 67526b20 | Blue Swirl | tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3122 | e35298cd | blueswir1 | } else { /* register */ |
3123 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3124 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3125 | e35298cd | blueswir1 | } |
3126 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3127 | cf495bcf | bellard | break;
|
3128 | 83469015 | bellard | #endif
|
3129 | cf495bcf | bellard | case 0x30: |
3130 | cf495bcf | bellard | { |
3131 | cf495bcf | bellard | switch(rd) {
|
3132 | 3475187d | bellard | case 0: /* wry */ |
3133 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3134 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3135 | cf495bcf | bellard | break;
|
3136 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3137 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3138 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3139 | 65fe7b09 | blueswir1 | on the microSPARC
|
3140 | 65fe7b09 | blueswir1 | II */
|
3141 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3142 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3143 | 65fe7b09 | blueswir1 | manual, nop on the
|
3144 | 65fe7b09 | blueswir1 | microSPARC II */
|
3145 | 65fe7b09 | blueswir1 | break;
|
3146 | 65fe7b09 | blueswir1 | #else
|
3147 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3148 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3149 | a7812ae4 | pbrook | gen_helper_wrccr(cpu_dst); |
3150 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3151 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3152 | 0f8a249a | blueswir1 | break;
|
3153 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3154 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3155 | 01b5d4e5 | Igor V. Kovalenko | tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
|
3156 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
3157 | 0f8a249a | blueswir1 | break;
|
3158 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3159 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3160 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
3161 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3162 | 3299908c | blueswir1 | gen_op_next_insn(); |
3163 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3164 | 3299908c | blueswir1 | dc->is_br = 1;
|
3165 | 0f8a249a | blueswir1 | break;
|
3166 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3167 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3168 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3169 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3170 | 3475187d | bellard | #endif
|
3171 | 0f8a249a | blueswir1 | break;
|
3172 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3173 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3174 | 725cb90b | bellard | goto jmp_insn;
|
3175 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3176 | 0f8a249a | blueswir1 | break;
|
3177 | 9d926598 | blueswir1 | case 0x14: /* Softint set */ |
3178 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3179 | 9d926598 | blueswir1 | goto illegal_insn;
|
3180 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3181 | a7812ae4 | pbrook | gen_helper_set_softint(cpu_tmp64); |
3182 | 9d926598 | blueswir1 | break;
|
3183 | 9d926598 | blueswir1 | case 0x15: /* Softint clear */ |
3184 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3185 | 9d926598 | blueswir1 | goto illegal_insn;
|
3186 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3187 | a7812ae4 | pbrook | gen_helper_clear_softint(cpu_tmp64); |
3188 | 9d926598 | blueswir1 | break;
|
3189 | 9d926598 | blueswir1 | case 0x16: /* Softint write */ |
3190 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3191 | 9d926598 | blueswir1 | goto illegal_insn;
|
3192 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3193 | a7812ae4 | pbrook | gen_helper_write_softint(cpu_tmp64); |
3194 | 9d926598 | blueswir1 | break;
|
3195 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3196 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3197 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3198 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3199 | 83469015 | bellard | #endif
|
3200 | ccd4a219 | blueswir1 | { |
3201 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3202 | ccd4a219 | blueswir1 | |
3203 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3204 | 6ae20372 | blueswir1 | cpu_src2); |
3205 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3206 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3207 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3208 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3209 | a7812ae4 | pbrook | cpu_tick_cmpr); |
3210 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3211 | ccd4a219 | blueswir1 | } |
3212 | 0f8a249a | blueswir1 | break;
|
3213 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3214 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3215 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3216 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3217 | 83469015 | bellard | #endif
|
3218 | ccd4a219 | blueswir1 | { |
3219 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3220 | ccd4a219 | blueswir1 | |
3221 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3222 | 6ae20372 | blueswir1 | cpu_src2); |
3223 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3224 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3225 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3226 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3227 | a7812ae4 | pbrook | cpu_dst); |
3228 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3229 | ccd4a219 | blueswir1 | } |
3230 | 0f8a249a | blueswir1 | break;
|
3231 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3232 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3233 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3234 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3235 | 3475187d | bellard | #endif
|
3236 | ccd4a219 | blueswir1 | { |
3237 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3238 | ccd4a219 | blueswir1 | |
3239 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3240 | 6ae20372 | blueswir1 | cpu_src2); |
3241 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3242 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3243 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3244 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3245 | a7812ae4 | pbrook | cpu_stick_cmpr); |
3246 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3247 | ccd4a219 | blueswir1 | } |
3248 | 0f8a249a | blueswir1 | break;
|
3249 | 83469015 | bellard | |
3250 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3251 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3252 | 77f193da | blueswir1 | Counter */
|
3253 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3254 | 83469015 | bellard | #endif
|
3255 | 3475187d | bellard | default:
|
3256 | cf495bcf | bellard | goto illegal_insn;
|
3257 | cf495bcf | bellard | } |
3258 | cf495bcf | bellard | } |
3259 | cf495bcf | bellard | break;
|
3260 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3261 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3262 | e8af50a3 | bellard | { |
3263 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3264 | 0f8a249a | blueswir1 | goto priv_insn;
|
3265 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3266 | 0f8a249a | blueswir1 | switch (rd) {
|
3267 | 0f8a249a | blueswir1 | case 0: |
3268 | a7812ae4 | pbrook | gen_helper_saved(); |
3269 | 0f8a249a | blueswir1 | break;
|
3270 | 0f8a249a | blueswir1 | case 1: |
3271 | a7812ae4 | pbrook | gen_helper_restored(); |
3272 | 0f8a249a | blueswir1 | break;
|
3273 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3274 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3275 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3276 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3277 | e9ebed4d | blueswir1 | // XXX
|
3278 | 0f8a249a | blueswir1 | default:
|
3279 | 3475187d | bellard | goto illegal_insn;
|
3280 | 3475187d | bellard | } |
3281 | 3475187d | bellard | #else
|
3282 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3283 | a7812ae4 | pbrook | gen_helper_wrpsr(cpu_dst); |
3284 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3285 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3286 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3287 | 9e61bde5 | bellard | gen_op_next_insn(); |
3288 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3289 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3290 | 3475187d | bellard | #endif
|
3291 | e8af50a3 | bellard | } |
3292 | e8af50a3 | bellard | break;
|
3293 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3294 | e8af50a3 | bellard | { |
3295 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3296 | 0f8a249a | blueswir1 | goto priv_insn;
|
3297 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3298 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3299 | 0f8a249a | blueswir1 | switch (rd) {
|
3300 | 0f8a249a | blueswir1 | case 0: // tpc |
3301 | 375ee38b | blueswir1 | { |
3302 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3303 | 375ee38b | blueswir1 | |
3304 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3305 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3306 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3307 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3308 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3309 | 375ee38b | blueswir1 | } |
3310 | 0f8a249a | blueswir1 | break;
|
3311 | 0f8a249a | blueswir1 | case 1: // tnpc |
3312 | 375ee38b | blueswir1 | { |
3313 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3314 | 375ee38b | blueswir1 | |
3315 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3316 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3317 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3318 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3319 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3320 | 375ee38b | blueswir1 | } |
3321 | 0f8a249a | blueswir1 | break;
|
3322 | 0f8a249a | blueswir1 | case 2: // tstate |
3323 | 375ee38b | blueswir1 | { |
3324 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3325 | 375ee38b | blueswir1 | |
3326 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3327 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3328 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3329 | 77f193da | blueswir1 | offsetof(trap_state, |
3330 | 77f193da | blueswir1 | tstate)); |
3331 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3332 | 375ee38b | blueswir1 | } |
3333 | 0f8a249a | blueswir1 | break;
|
3334 | 0f8a249a | blueswir1 | case 3: // tt |
3335 | 375ee38b | blueswir1 | { |
3336 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3337 | 375ee38b | blueswir1 | |
3338 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3339 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3340 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3341 | 527067d8 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, r_tsptr, |
3342 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3343 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3344 | 375ee38b | blueswir1 | } |
3345 | 0f8a249a | blueswir1 | break;
|
3346 | 0f8a249a | blueswir1 | case 4: // tick |
3347 | ccd4a219 | blueswir1 | { |
3348 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3349 | ccd4a219 | blueswir1 | |
3350 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3351 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3352 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3353 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3354 | a7812ae4 | pbrook | cpu_tmp0); |
3355 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3356 | ccd4a219 | blueswir1 | } |
3357 | 0f8a249a | blueswir1 | break;
|
3358 | 0f8a249a | blueswir1 | case 5: // tba |
3359 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3360 | 0f8a249a | blueswir1 | break;
|
3361 | 0f8a249a | blueswir1 | case 6: // pstate |
3362 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3363 | a7812ae4 | pbrook | gen_helper_wrpstate(cpu_tmp0); |
3364 | ded3ab80 | pbrook | gen_op_next_insn(); |
3365 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3366 | ded3ab80 | pbrook | dc->is_br = 1;
|
3367 | 0f8a249a | blueswir1 | break;
|
3368 | 0f8a249a | blueswir1 | case 7: // tl |
3369 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3370 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3371 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3372 | 0f8a249a | blueswir1 | break;
|
3373 | 0f8a249a | blueswir1 | case 8: // pil |
3374 | 1fae7b70 | Igor V. Kovalenko | gen_helper_wrpil(cpu_tmp0); |
3375 | 0f8a249a | blueswir1 | break;
|
3376 | 0f8a249a | blueswir1 | case 9: // cwp |
3377 | a7812ae4 | pbrook | gen_helper_wrcwp(cpu_tmp0); |
3378 | 0f8a249a | blueswir1 | break;
|
3379 | 0f8a249a | blueswir1 | case 10: // cansave |
3380 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3381 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3382 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3383 | 77f193da | blueswir1 | cansave)); |
3384 | 0f8a249a | blueswir1 | break;
|
3385 | 0f8a249a | blueswir1 | case 11: // canrestore |
3386 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3387 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3388 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3389 | 77f193da | blueswir1 | canrestore)); |
3390 | 0f8a249a | blueswir1 | break;
|
3391 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3392 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3393 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3394 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3395 | 77f193da | blueswir1 | cleanwin)); |
3396 | 0f8a249a | blueswir1 | break;
|
3397 | 0f8a249a | blueswir1 | case 13: // otherwin |
3398 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3399 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3400 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3401 | 77f193da | blueswir1 | otherwin)); |
3402 | 0f8a249a | blueswir1 | break;
|
3403 | 0f8a249a | blueswir1 | case 14: // wstate |
3404 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3405 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3406 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3407 | 77f193da | blueswir1 | wstate)); |
3408 | 0f8a249a | blueswir1 | break;
|
3409 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3410 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3411 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3412 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3413 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3414 | e9ebed4d | blueswir1 | break;
|
3415 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3416 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3417 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3418 | e9ebed4d | blueswir1 | goto priv_insn;
|
3419 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); |
3420 | e9ebed4d | blueswir1 | break;
|
3421 | 0f8a249a | blueswir1 | default:
|
3422 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3423 | 0f8a249a | blueswir1 | } |
3424 | 3475187d | bellard | #else
|
3425 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3426 | c93e7817 | blueswir1 | if (dc->def->nwindows != 32) |
3427 | c93e7817 | blueswir1 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
3428 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3429 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3430 | 3475187d | bellard | #endif
|
3431 | e8af50a3 | bellard | } |
3432 | e8af50a3 | bellard | break;
|
3433 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3434 | e8af50a3 | bellard | { |
3435 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3436 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3437 | 0f8a249a | blueswir1 | goto priv_insn;
|
3438 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3439 | e9ebed4d | blueswir1 | #else
|
3440 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3441 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3442 | e9ebed4d | blueswir1 | goto priv_insn;
|
3443 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3444 | e9ebed4d | blueswir1 | switch (rd) {
|
3445 | e9ebed4d | blueswir1 | case 0: // hpstate |
3446 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3447 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3448 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3449 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3450 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3451 | e9ebed4d | blueswir1 | break;
|
3452 | e9ebed4d | blueswir1 | case 1: // htstate |
3453 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3454 | e9ebed4d | blueswir1 | break;
|
3455 | e9ebed4d | blueswir1 | case 3: // hintp |
3456 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3457 | e9ebed4d | blueswir1 | break;
|
3458 | e9ebed4d | blueswir1 | case 5: // htba |
3459 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3460 | e9ebed4d | blueswir1 | break;
|
3461 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3462 | ccd4a219 | blueswir1 | { |
3463 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3464 | ccd4a219 | blueswir1 | |
3465 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3466 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3467 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3468 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3469 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3470 | a7812ae4 | pbrook | cpu_hstick_cmpr); |
3471 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3472 | ccd4a219 | blueswir1 | } |
3473 | e9ebed4d | blueswir1 | break;
|
3474 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3475 | e9ebed4d | blueswir1 | default:
|
3476 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3477 | e9ebed4d | blueswir1 | } |
3478 | e9ebed4d | blueswir1 | #endif
|
3479 | e8af50a3 | bellard | } |
3480 | e8af50a3 | bellard | break;
|
3481 | e8af50a3 | bellard | #endif
|
3482 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3483 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3484 | 0f8a249a | blueswir1 | { |
3485 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3486 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3487 | 748b9d8e | blueswir1 | TCGv r_cond; |
3488 | 00f219bf | blueswir1 | int l1;
|
3489 | 00f219bf | blueswir1 | |
3490 | a7812ae4 | pbrook | r_cond = tcg_temp_new(); |
3491 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3492 | 0f8a249a | blueswir1 | if (cc == 0) |
3493 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
3494 | 0f8a249a | blueswir1 | else if (cc == 2) |
3495 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
3496 | 0f8a249a | blueswir1 | else
|
3497 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3498 | 0f8a249a | blueswir1 | } else {
|
3499 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3500 | 0f8a249a | blueswir1 | } |
3501 | 00f219bf | blueswir1 | |
3502 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3503 | 00f219bf | blueswir1 | |
3504 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3505 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3506 | 2ea815ca | blueswir1 | TCGv r_const; |
3507 | 2ea815ca | blueswir1 | |
3508 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 10); |
3509 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3510 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3511 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3512 | 00f219bf | blueswir1 | } else {
|
3513 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3514 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3515 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3516 | 00f219bf | blueswir1 | } |
3517 | 00f219bf | blueswir1 | gen_set_label(l1); |
3518 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3519 | 0f8a249a | blueswir1 | break;
|
3520 | 0f8a249a | blueswir1 | } |
3521 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3522 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3523 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3524 | 0f8a249a | blueswir1 | break;
|
3525 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3526 | 0f8a249a | blueswir1 | { |
3527 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3528 | a7812ae4 | pbrook | gen_helper_popc(cpu_dst, cpu_src2); |
3529 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3530 | 0f8a249a | blueswir1 | } |
3531 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3532 | 0f8a249a | blueswir1 | { |
3533 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3534 | 00f219bf | blueswir1 | int l1;
|
3535 | 00f219bf | blueswir1 | |
3536 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3537 | 00f219bf | blueswir1 | |
3538 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3539 | 00f219bf | blueswir1 | |
3540 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3541 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3542 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3543 | 2ea815ca | blueswir1 | TCGv r_const; |
3544 | 2ea815ca | blueswir1 | |
3545 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 9); |
3546 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3547 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3548 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3549 | 00f219bf | blueswir1 | } else {
|
3550 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3551 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3552 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3553 | 0f8a249a | blueswir1 | } |
3554 | 00f219bf | blueswir1 | gen_set_label(l1); |
3555 | 0f8a249a | blueswir1 | break;
|
3556 | 0f8a249a | blueswir1 | } |
3557 | 0f8a249a | blueswir1 | #endif
|
3558 | 0f8a249a | blueswir1 | default:
|
3559 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3560 | 0f8a249a | blueswir1 | } |
3561 | 0f8a249a | blueswir1 | } |
3562 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3563 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3564 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3565 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3566 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3567 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3568 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3569 | 3299908c | blueswir1 | |
3570 | 3299908c | blueswir1 | switch (opf) {
|
3571 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3572 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3573 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3574 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3575 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3576 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3577 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3578 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3579 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3580 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3581 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3582 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3583 | e9ebed4d | blueswir1 | // XXX
|
3584 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3585 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3586 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3587 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3588 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3589 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3590 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3591 | e9ebed4d | blueswir1 | break;
|
3592 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3593 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3594 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3595 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3596 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3597 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3598 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3599 | e9ebed4d | blueswir1 | break;
|
3600 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3601 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3602 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3603 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3604 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3605 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3606 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3607 | e9ebed4d | blueswir1 | break;
|
3608 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3609 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3610 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3611 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3612 | a7812ae4 | pbrook | gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); |
3613 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3614 | 3299908c | blueswir1 | break;
|
3615 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3616 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3617 | 3299908c | blueswir1 | // XXX
|
3618 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3619 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3620 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3621 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3622 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3623 | a7812ae4 | pbrook | gen_helper_fcmple16(); |
3624 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3625 | e9ebed4d | blueswir1 | break;
|
3626 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3627 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3628 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3629 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3630 | a7812ae4 | pbrook | gen_helper_fcmpne16(); |
3631 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3632 | 3299908c | blueswir1 | break;
|
3633 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3634 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3635 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3636 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3637 | a7812ae4 | pbrook | gen_helper_fcmple32(); |
3638 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3639 | e9ebed4d | blueswir1 | break;
|
3640 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3641 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3642 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3643 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3644 | a7812ae4 | pbrook | gen_helper_fcmpne32(); |
3645 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3646 | e9ebed4d | blueswir1 | break;
|
3647 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3648 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3649 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3650 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3651 | a7812ae4 | pbrook | gen_helper_fcmpgt16(); |
3652 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3653 | e9ebed4d | blueswir1 | break;
|
3654 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3655 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3656 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3657 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3658 | a7812ae4 | pbrook | gen_helper_fcmpeq16(); |
3659 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3660 | e9ebed4d | blueswir1 | break;
|
3661 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3662 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3663 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3664 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3665 | a7812ae4 | pbrook | gen_helper_fcmpgt32(); |
3666 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3667 | e9ebed4d | blueswir1 | break;
|
3668 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3669 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3670 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3671 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3672 | a7812ae4 | pbrook | gen_helper_fcmpeq32(); |
3673 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3674 | e9ebed4d | blueswir1 | break;
|
3675 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3676 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3677 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3678 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3679 | a7812ae4 | pbrook | gen_helper_fmul8x16(); |
3680 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3681 | e9ebed4d | blueswir1 | break;
|
3682 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3683 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3684 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3685 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3686 | a7812ae4 | pbrook | gen_helper_fmul8x16au(); |
3687 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3688 | e9ebed4d | blueswir1 | break;
|
3689 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3690 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3691 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3692 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3693 | a7812ae4 | pbrook | gen_helper_fmul8x16al(); |
3694 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3695 | e9ebed4d | blueswir1 | break;
|
3696 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3697 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3698 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3699 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3700 | a7812ae4 | pbrook | gen_helper_fmul8sux16(); |
3701 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3702 | e9ebed4d | blueswir1 | break;
|
3703 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3704 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3705 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3706 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3707 | a7812ae4 | pbrook | gen_helper_fmul8ulx16(); |
3708 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3709 | e9ebed4d | blueswir1 | break;
|
3710 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3711 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3712 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3713 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3714 | a7812ae4 | pbrook | gen_helper_fmuld8sux16(); |
3715 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3716 | e9ebed4d | blueswir1 | break;
|
3717 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3718 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3719 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3720 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3721 | a7812ae4 | pbrook | gen_helper_fmuld8ulx16(); |
3722 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3723 | e9ebed4d | blueswir1 | break;
|
3724 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3725 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3726 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3727 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3728 | e9ebed4d | blueswir1 | // XXX
|
3729 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3730 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3731 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3732 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3733 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3734 | a7812ae4 | pbrook | gen_helper_faligndata(); |
3735 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3736 | 3299908c | blueswir1 | break;
|
3737 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3738 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3739 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3740 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3741 | a7812ae4 | pbrook | gen_helper_fpmerge(); |
3742 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3743 | e9ebed4d | blueswir1 | break;
|
3744 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3745 | e9ebed4d | blueswir1 | // XXX
|
3746 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3747 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3748 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3749 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3750 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3751 | a7812ae4 | pbrook | gen_helper_fexpand(); |
3752 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3753 | e9ebed4d | blueswir1 | break;
|
3754 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3755 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3756 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3757 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3758 | a7812ae4 | pbrook | gen_helper_fpadd16(); |
3759 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3760 | e9ebed4d | blueswir1 | break;
|
3761 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3762 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3763 | a7812ae4 | pbrook | gen_helper_fpadd16s(cpu_fpr[rd], |
3764 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3765 | e9ebed4d | blueswir1 | break;
|
3766 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3767 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3768 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3769 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3770 | a7812ae4 | pbrook | gen_helper_fpadd32(); |
3771 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3772 | e9ebed4d | blueswir1 | break;
|
3773 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3774 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3775 | a7812ae4 | pbrook | gen_helper_fpadd32s(cpu_fpr[rd], |
3776 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3777 | e9ebed4d | blueswir1 | break;
|
3778 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3779 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3780 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3781 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3782 | a7812ae4 | pbrook | gen_helper_fpsub16(); |
3783 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3784 | e9ebed4d | blueswir1 | break;
|
3785 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3786 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3787 | a7812ae4 | pbrook | gen_helper_fpsub16s(cpu_fpr[rd], |
3788 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3789 | e9ebed4d | blueswir1 | break;
|
3790 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3791 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3792 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3793 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3794 | a7812ae4 | pbrook | gen_helper_fpsub32(); |
3795 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3796 | e9ebed4d | blueswir1 | break;
|
3797 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3798 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3799 | a7812ae4 | pbrook | gen_helper_fpsub32s(cpu_fpr[rd], |
3800 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3801 | e9ebed4d | blueswir1 | break;
|
3802 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3803 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3804 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
3805 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
3806 | 3299908c | blueswir1 | break;
|
3807 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3808 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3809 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], 0);
|
3810 | 3299908c | blueswir1 | break;
|
3811 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3812 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3813 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3814 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3815 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3816 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3817 | e9ebed4d | blueswir1 | break;
|
3818 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3819 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3820 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3821 | e9ebed4d | blueswir1 | break;
|
3822 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3823 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3824 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3825 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3826 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3827 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3828 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3829 | e9ebed4d | blueswir1 | break;
|
3830 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3831 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3832 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3833 | e9ebed4d | blueswir1 | break;
|
3834 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3835 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3836 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
3837 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3838 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3839 | e9ebed4d | blueswir1 | break;
|
3840 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3841 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3842 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3843 | e9ebed4d | blueswir1 | break;
|
3844 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3845 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3846 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3847 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3848 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3849 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3850 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3851 | e9ebed4d | blueswir1 | break;
|
3852 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3853 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3854 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3855 | e9ebed4d | blueswir1 | break;
|
3856 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3857 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3858 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3859 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3860 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3861 | e9ebed4d | blueswir1 | break;
|
3862 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3863 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3864 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3865 | e9ebed4d | blueswir1 | break;
|
3866 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3867 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3868 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3869 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3870 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
|
3871 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3872 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3873 | e9ebed4d | blueswir1 | break;
|
3874 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3875 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3876 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3877 | e9ebed4d | blueswir1 | break;
|
3878 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3879 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3880 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3881 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3882 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3883 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3884 | e9ebed4d | blueswir1 | break;
|
3885 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3886 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3887 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3888 | e9ebed4d | blueswir1 | break;
|
3889 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3890 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3891 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3892 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3893 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
|
3894 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3895 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3896 | e9ebed4d | blueswir1 | break;
|
3897 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3898 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3899 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3900 | e9ebed4d | blueswir1 | break;
|
3901 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3902 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3903 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
3904 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
3905 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3906 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
3907 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
3908 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3909 | e9ebed4d | blueswir1 | break;
|
3910 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3911 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3912 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
3913 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
3914 | e9ebed4d | blueswir1 | break;
|
3915 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3916 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3917 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3918 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
3919 | 1d01299d | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3920 | 3299908c | blueswir1 | break;
|
3921 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3922 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3923 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3924 | 3299908c | blueswir1 | break;
|
3925 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3926 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3927 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3928 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3929 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3930 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3931 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3932 | e9ebed4d | blueswir1 | break;
|
3933 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
3934 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3935 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3936 | e9ebed4d | blueswir1 | break;
|
3937 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
3938 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3939 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3940 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3941 | 3299908c | blueswir1 | break;
|
3942 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
3943 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3944 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3945 | 3299908c | blueswir1 | break;
|
3946 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
3947 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3948 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3949 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3950 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3951 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3952 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3953 | e9ebed4d | blueswir1 | break;
|
3954 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
3955 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3956 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3957 | e9ebed4d | blueswir1 | break;
|
3958 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
3959 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3960 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3961 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3962 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
|
3963 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3964 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3965 | e9ebed4d | blueswir1 | break;
|
3966 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
3967 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3968 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3969 | e9ebed4d | blueswir1 | break;
|
3970 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
3971 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3972 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
3973 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
3974 | 3299908c | blueswir1 | break;
|
3975 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
3976 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3977 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], -1);
|
3978 | 3299908c | blueswir1 | break;
|
3979 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
3980 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
3981 | e9ebed4d | blueswir1 | // XXX
|
3982 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3983 | 3299908c | blueswir1 | default:
|
3984 | 3299908c | blueswir1 | goto illegal_insn;
|
3985 | 3299908c | blueswir1 | } |
3986 | 3299908c | blueswir1 | #else
|
3987 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3988 | 3299908c | blueswir1 | #endif
|
3989 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
3990 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
3991 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3992 | fcc72045 | blueswir1 | #else
|
3993 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3994 | fcc72045 | blueswir1 | #endif
|
3995 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3996 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
3997 | a7812ae4 | pbrook | TCGv_i32 r_const; |
3998 | 2ea815ca | blueswir1 | |
3999 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4000 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4001 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4002 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4003 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4004 | 0f8a249a | blueswir1 | } else { /* register */ |
4005 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4006 | 0f8a249a | blueswir1 | if (rs2) {
|
4007 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4008 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4009 | 6f551262 | blueswir1 | } else
|
4010 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4011 | 3475187d | bellard | } |
4012 | a7812ae4 | pbrook | gen_helper_restore(); |
4013 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4014 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4015 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4016 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4017 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4018 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4019 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4020 | 3475187d | bellard | #endif
|
4021 | 0f8a249a | blueswir1 | } else {
|
4022 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4023 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4024 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4025 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4026 | 0f8a249a | blueswir1 | } else { /* register */ |
4027 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4028 | 0f8a249a | blueswir1 | if (rs2) {
|
4029 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4030 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4031 | 6f551262 | blueswir1 | } else
|
4032 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4033 | cf495bcf | bellard | } |
4034 | 0f8a249a | blueswir1 | switch (xop) {
|
4035 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4036 | 0f8a249a | blueswir1 | { |
4037 | a7812ae4 | pbrook | TCGv r_pc; |
4038 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4039 | 2ea815ca | blueswir1 | |
4040 | a7812ae4 | pbrook | r_pc = tcg_const_tl(dc->pc); |
4041 | a7812ae4 | pbrook | gen_movl_TN_reg(rd, r_pc); |
4042 | a7812ae4 | pbrook | tcg_temp_free(r_pc); |
4043 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4044 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4045 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4046 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4047 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4048 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4049 | 0f8a249a | blueswir1 | } |
4050 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4051 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4052 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4053 | 0f8a249a | blueswir1 | { |
4054 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4055 | 2ea815ca | blueswir1 | |
4056 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4057 | 0f8a249a | blueswir1 | goto priv_insn;
|
4058 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4059 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4060 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4061 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4062 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4063 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4064 | a7812ae4 | pbrook | gen_helper_rett(); |
4065 | 0f8a249a | blueswir1 | } |
4066 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4067 | 0f8a249a | blueswir1 | #endif
|
4068 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4069 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4070 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4071 | a7812ae4 | pbrook | gen_helper_flush(cpu_dst); |
4072 | 0f8a249a | blueswir1 | break;
|
4073 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4074 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4075 | a7812ae4 | pbrook | gen_helper_save(); |
4076 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4077 | 0f8a249a | blueswir1 | break;
|
4078 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4079 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4080 | a7812ae4 | pbrook | gen_helper_restore(); |
4081 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4082 | 0f8a249a | blueswir1 | break;
|
4083 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4084 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4085 | 0f8a249a | blueswir1 | { |
4086 | 0f8a249a | blueswir1 | switch (rd) {
|
4087 | 0f8a249a | blueswir1 | case 0: |
4088 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4089 | 0f8a249a | blueswir1 | goto priv_insn;
|
4090 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4091 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4092 | a7812ae4 | pbrook | gen_helper_done(); |
4093 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4094 | 0f8a249a | blueswir1 | case 1: |
4095 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4096 | 0f8a249a | blueswir1 | goto priv_insn;
|
4097 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4098 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4099 | a7812ae4 | pbrook | gen_helper_retry(); |
4100 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4101 | 0f8a249a | blueswir1 | default:
|
4102 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4103 | 0f8a249a | blueswir1 | } |
4104 | 0f8a249a | blueswir1 | } |
4105 | 0f8a249a | blueswir1 | break;
|
4106 | 0f8a249a | blueswir1 | #endif
|
4107 | 0f8a249a | blueswir1 | default:
|
4108 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4109 | 0f8a249a | blueswir1 | } |
4110 | cf495bcf | bellard | } |
4111 | 0f8a249a | blueswir1 | break;
|
4112 | 0f8a249a | blueswir1 | } |
4113 | 0f8a249a | blueswir1 | break;
|
4114 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4115 | 0f8a249a | blueswir1 | { |
4116 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4117 | 9322a4bf | blueswir1 | |
4118 | cfa90513 | Blue Swirl | /* flush pending conditional evaluations before exposing
|
4119 | cfa90513 | Blue Swirl | cpu state */
|
4120 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
4121 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
4122 | cfa90513 | Blue Swirl | gen_helper_compute_psr(); |
4123 | cfa90513 | Blue Swirl | } |
4124 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4125 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4126 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4127 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4128 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4129 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4130 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4131 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_addr, cpu_src1, simm); |
4132 | 0f8a249a | blueswir1 | } else { /* register */ |
4133 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4134 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4135 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4136 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4137 | 6f551262 | blueswir1 | } else
|
4138 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4139 | 0f8a249a | blueswir1 | } |
4140 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4141 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4142 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4143 | 0f8a249a | blueswir1 | switch (xop) {
|
4144 | b89e94af | Blue Swirl | case 0x0: /* ld, V9 lduw, load unsigned word */ |
4145 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4146 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4147 | 0f8a249a | blueswir1 | break;
|
4148 | b89e94af | Blue Swirl | case 0x1: /* ldub, load unsigned byte */ |
4149 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4150 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4151 | 0f8a249a | blueswir1 | break;
|
4152 | b89e94af | Blue Swirl | case 0x2: /* lduh, load unsigned halfword */ |
4153 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4154 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4155 | 0f8a249a | blueswir1 | break;
|
4156 | b89e94af | Blue Swirl | case 0x3: /* ldd, load double word */ |
4157 | 0f8a249a | blueswir1 | if (rd & 1) |
4158 | d4218d99 | blueswir1 | goto illegal_insn;
|
4159 | 1a2fb1c0 | blueswir1 | else {
|
4160 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4161 | 2ea815ca | blueswir1 | |
4162 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4163 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4164 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4165 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4166 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4167 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4168 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4169 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4170 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4171 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4172 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4173 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4174 | 1a2fb1c0 | blueswir1 | } |
4175 | 0f8a249a | blueswir1 | break;
|
4176 | b89e94af | Blue Swirl | case 0x9: /* ldsb, load signed byte */ |
4177 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4178 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4179 | 0f8a249a | blueswir1 | break;
|
4180 | b89e94af | Blue Swirl | case 0xa: /* ldsh, load signed halfword */ |
4181 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4182 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4183 | 0f8a249a | blueswir1 | break;
|
4184 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4185 | 2ea815ca | blueswir1 | { |
4186 | 2ea815ca | blueswir1 | TCGv r_const; |
4187 | 2ea815ca | blueswir1 | |
4188 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4189 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4190 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4191 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4192 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4193 | 2ea815ca | blueswir1 | } |
4194 | 0f8a249a | blueswir1 | break;
|
4195 | b89e94af | Blue Swirl | case 0x0f: /* swap, swap register with memory. Also |
4196 | 77f193da | blueswir1 | atomically */
|
4197 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4198 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4199 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4200 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4201 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4202 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_val, cpu_tmp0); |
4203 | 0f8a249a | blueswir1 | break;
|
4204 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4205 | b89e94af | Blue Swirl | case 0x10: /* lda, V9 lduwa, load word alternate */ |
4206 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4207 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4208 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4209 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4210 | 0f8a249a | blueswir1 | goto priv_insn;
|
4211 | 6ea4a6c8 | blueswir1 | #endif
|
4212 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4213 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4214 | 0f8a249a | blueswir1 | break;
|
4215 | b89e94af | Blue Swirl | case 0x11: /* lduba, load unsigned byte alternate */ |
4216 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4217 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4218 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4219 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4220 | 0f8a249a | blueswir1 | goto priv_insn;
|
4221 | 0f8a249a | blueswir1 | #endif
|
4222 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4223 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4224 | 0f8a249a | blueswir1 | break;
|
4225 | b89e94af | Blue Swirl | case 0x12: /* lduha, load unsigned halfword alternate */ |
4226 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4227 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4228 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4229 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4230 | 0f8a249a | blueswir1 | goto priv_insn;
|
4231 | 6ea4a6c8 | blueswir1 | #endif
|
4232 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4233 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4234 | 0f8a249a | blueswir1 | break;
|
4235 | b89e94af | Blue Swirl | case 0x13: /* ldda, load double word alternate */ |
4236 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4237 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4238 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4239 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4240 | 0f8a249a | blueswir1 | goto priv_insn;
|
4241 | 3475187d | bellard | #endif
|
4242 | 0f8a249a | blueswir1 | if (rd & 1) |
4243 | d4218d99 | blueswir1 | goto illegal_insn;
|
4244 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4245 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4246 | db166940 | blueswir1 | goto skip_move;
|
4247 | b89e94af | Blue Swirl | case 0x19: /* ldsba, load signed byte alternate */ |
4248 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4249 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4250 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4251 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4252 | 0f8a249a | blueswir1 | goto priv_insn;
|
4253 | 0f8a249a | blueswir1 | #endif
|
4254 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4255 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4256 | 0f8a249a | blueswir1 | break;
|
4257 | b89e94af | Blue Swirl | case 0x1a: /* ldsha, load signed halfword alternate */ |
4258 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4259 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4260 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4261 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4262 | 0f8a249a | blueswir1 | goto priv_insn;
|
4263 | 6ea4a6c8 | blueswir1 | #endif
|
4264 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4265 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4266 | 0f8a249a | blueswir1 | break;
|
4267 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4268 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4269 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4270 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4271 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4272 | 0f8a249a | blueswir1 | goto priv_insn;
|
4273 | 0f8a249a | blueswir1 | #endif
|
4274 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4275 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4276 | 0f8a249a | blueswir1 | break;
|
4277 | b89e94af | Blue Swirl | case 0x1f: /* swapa, swap reg with alt. memory. Also |
4278 | 77f193da | blueswir1 | atomically */
|
4279 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4280 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4281 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4282 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4283 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4284 | 0f8a249a | blueswir1 | goto priv_insn;
|
4285 | 6ea4a6c8 | blueswir1 | #endif
|
4286 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4287 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4288 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4289 | 0f8a249a | blueswir1 | break;
|
4290 | 3475187d | bellard | |
4291 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4292 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4293 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4294 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4295 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4296 | 3475187d | bellard | #endif
|
4297 | 3475187d | bellard | #endif
|
4298 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4299 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4300 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4301 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4302 | 0f8a249a | blueswir1 | break;
|
4303 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4304 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4305 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4306 | 0f8a249a | blueswir1 | break;
|
4307 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4308 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4309 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4310 | 0f8a249a | blueswir1 | break;
|
4311 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4312 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4313 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4314 | 0f8a249a | blueswir1 | break;
|
4315 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4316 | 0f8a249a | blueswir1 | goto skip_move;
|
4317 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4318 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4319 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4320 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4321 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4322 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4323 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4324 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4325 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4326 | 0f8a249a | blueswir1 | goto skip_move;
|
4327 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4328 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4329 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4330 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4331 | 1f587329 | blueswir1 | goto skip_move;
|
4332 | 1f587329 | blueswir1 | #endif
|
4333 | 0f8a249a | blueswir1 | default:
|
4334 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4335 | 0f8a249a | blueswir1 | } |
4336 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4337 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4338 | 0f8a249a | blueswir1 | skip_move: ;
|
4339 | 3475187d | bellard | #endif
|
4340 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4341 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4342 | a80dde08 | bellard | goto jmp_insn;
|
4343 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4344 | 0f8a249a | blueswir1 | switch (xop) {
|
4345 | b89e94af | Blue Swirl | case 0x20: /* ldf, load fpreg */ |
4346 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4347 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4348 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
4349 | 0f8a249a | blueswir1 | break;
|
4350 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4351 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4352 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4353 | 3a3b925d | blueswir1 | if (rd == 1) { |
4354 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4355 | a7812ae4 | pbrook | gen_helper_ldxfsr(cpu_tmp64); |
4356 | 3a3b925d | blueswir1 | } else
|
4357 | 3a3b925d | blueswir1 | #else
|
4358 | 3a3b925d | blueswir1 | { |
4359 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4360 | a7812ae4 | pbrook | gen_helper_ldfsr(cpu_tmp32); |
4361 | 3a3b925d | blueswir1 | } |
4362 | 3a3b925d | blueswir1 | #endif
|
4363 | 0f8a249a | blueswir1 | break;
|
4364 | b89e94af | Blue Swirl | case 0x22: /* ldqf, load quad fpreg */ |
4365 | 2ea815ca | blueswir1 | { |
4366 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4367 | 2ea815ca | blueswir1 | |
4368 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4369 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4370 | a7812ae4 | pbrook | gen_helper_ldqf(cpu_addr, r_const); |
4371 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4372 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4373 | 2ea815ca | blueswir1 | } |
4374 | 1f587329 | blueswir1 | break;
|
4375 | b89e94af | Blue Swirl | case 0x23: /* lddf, load double fpreg */ |
4376 | 2ea815ca | blueswir1 | { |
4377 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4378 | 2ea815ca | blueswir1 | |
4379 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4380 | a7812ae4 | pbrook | gen_helper_lddf(cpu_addr, r_const); |
4381 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4382 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4383 | 2ea815ca | blueswir1 | } |
4384 | 0f8a249a | blueswir1 | break;
|
4385 | 0f8a249a | blueswir1 | default:
|
4386 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4387 | 0f8a249a | blueswir1 | } |
4388 | dc1a6971 | Blue Swirl | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || |
4389 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4390 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4391 | 0f8a249a | blueswir1 | switch (xop) {
|
4392 | b89e94af | Blue Swirl | case 0x4: /* st, store word */ |
4393 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4394 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4395 | 0f8a249a | blueswir1 | break;
|
4396 | b89e94af | Blue Swirl | case 0x5: /* stb, store byte */ |
4397 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4398 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4399 | 0f8a249a | blueswir1 | break;
|
4400 | b89e94af | Blue Swirl | case 0x6: /* sth, store halfword */ |
4401 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4402 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4403 | 0f8a249a | blueswir1 | break;
|
4404 | b89e94af | Blue Swirl | case 0x7: /* std, store double word */ |
4405 | 0f8a249a | blueswir1 | if (rd & 1) |
4406 | d4218d99 | blueswir1 | goto illegal_insn;
|
4407 | 1a2fb1c0 | blueswir1 | else {
|
4408 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4409 | 1a2fb1c0 | blueswir1 | |
4410 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4411 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4412 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4413 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4414 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4415 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
4416 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); |
4417 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4418 | 7fa76c0b | blueswir1 | } |
4419 | 0f8a249a | blueswir1 | break;
|
4420 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4421 | b89e94af | Blue Swirl | case 0x14: /* sta, V9 stwa, store word alternate */ |
4422 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4423 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4424 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4425 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4426 | 0f8a249a | blueswir1 | goto priv_insn;
|
4427 | 3475187d | bellard | #endif
|
4428 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4429 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4430 | d39c0b99 | bellard | break;
|
4431 | b89e94af | Blue Swirl | case 0x15: /* stba, store byte alternate */ |
4432 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4433 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4434 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4435 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4436 | 0f8a249a | blueswir1 | goto priv_insn;
|
4437 | 3475187d | bellard | #endif
|
4438 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4439 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4440 | d39c0b99 | bellard | break;
|
4441 | b89e94af | Blue Swirl | case 0x16: /* stha, store halfword alternate */ |
4442 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4443 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4444 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4445 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4446 | 0f8a249a | blueswir1 | goto priv_insn;
|
4447 | 3475187d | bellard | #endif
|
4448 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4449 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4450 | d39c0b99 | bellard | break;
|
4451 | b89e94af | Blue Swirl | case 0x17: /* stda, store double word alternate */ |
4452 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4453 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4454 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4455 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4456 | 0f8a249a | blueswir1 | goto priv_insn;
|
4457 | 3475187d | bellard | #endif
|
4458 | 0f8a249a | blueswir1 | if (rd & 1) |
4459 | d4218d99 | blueswir1 | goto illegal_insn;
|
4460 | 1a2fb1c0 | blueswir1 | else {
|
4461 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4462 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4463 | 1a2fb1c0 | blueswir1 | } |
4464 | d39c0b99 | bellard | break;
|
4465 | e80cfcfc | bellard | #endif
|
4466 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4467 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4468 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4469 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4470 | 0f8a249a | blueswir1 | break;
|
4471 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4472 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4473 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4474 | 0f8a249a | blueswir1 | break;
|
4475 | 3475187d | bellard | #endif
|
4476 | 0f8a249a | blueswir1 | default:
|
4477 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4478 | 0f8a249a | blueswir1 | } |
4479 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4480 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4481 | a80dde08 | bellard | goto jmp_insn;
|
4482 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4483 | 0f8a249a | blueswir1 | switch (xop) {
|
4484 | b89e94af | Blue Swirl | case 0x24: /* stf, store fpreg */ |
4485 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4486 | 527067d8 | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); |
4487 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); |
4488 | 0f8a249a | blueswir1 | break;
|
4489 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4490 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4491 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4492 | 3a3b925d | blueswir1 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4493 | 3a3b925d | blueswir1 | if (rd == 1) |
4494 | 3a3b925d | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4495 | 527067d8 | blueswir1 | else
|
4496 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx); |
4497 | 3a3b925d | blueswir1 | #else
|
4498 | 3a3b925d | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); |
4499 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4500 | 3a3b925d | blueswir1 | #endif
|
4501 | 0f8a249a | blueswir1 | break;
|
4502 | 1f587329 | blueswir1 | case 0x26: |
4503 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4504 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4505 | 2ea815ca | blueswir1 | { |
4506 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4507 | 2ea815ca | blueswir1 | |
4508 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4509 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4510 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4511 | a7812ae4 | pbrook | gen_helper_stqf(cpu_addr, r_const); |
4512 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4513 | 2ea815ca | blueswir1 | } |
4514 | 1f587329 | blueswir1 | break;
|
4515 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4516 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4517 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4518 | 1f587329 | blueswir1 | goto illegal_insn;
|
4519 | 1f587329 | blueswir1 | #else
|
4520 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4521 | 0f8a249a | blueswir1 | goto priv_insn;
|
4522 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4523 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4524 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4525 | 0f8a249a | blueswir1 | #endif
|
4526 | 1f587329 | blueswir1 | #endif
|
4527 | b89e94af | Blue Swirl | case 0x27: /* stdf, store double fpreg */ |
4528 | 2ea815ca | blueswir1 | { |
4529 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4530 | 2ea815ca | blueswir1 | |
4531 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4532 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4533 | a7812ae4 | pbrook | gen_helper_stdf(cpu_addr, r_const); |
4534 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4535 | 2ea815ca | blueswir1 | } |
4536 | 0f8a249a | blueswir1 | break;
|
4537 | 0f8a249a | blueswir1 | default:
|
4538 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4539 | 0f8a249a | blueswir1 | } |
4540 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4541 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4542 | 0f8a249a | blueswir1 | switch (xop) {
|
4543 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4544 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4545 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4546 | 0f8a249a | blueswir1 | break;
|
4547 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4548 | 2ea815ca | blueswir1 | { |
4549 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4550 | 2ea815ca | blueswir1 | |
4551 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4552 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4553 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); |
4554 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4555 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4556 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4557 | 2ea815ca | blueswir1 | } |
4558 | 1f587329 | blueswir1 | break;
|
4559 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4560 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4561 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4562 | 0f8a249a | blueswir1 | break;
|
4563 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4564 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4565 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4566 | 0f8a249a | blueswir1 | break;
|
4567 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4568 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4569 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4570 | 0f8a249a | blueswir1 | break;
|
4571 | a4d17f19 | blueswir1 | #else
|
4572 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4573 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4574 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4575 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4576 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4577 | 0f8a249a | blueswir1 | #endif
|
4578 | 0f8a249a | blueswir1 | default:
|
4579 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4580 | 0f8a249a | blueswir1 | } |
4581 | dc1a6971 | Blue Swirl | } else
|
4582 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4583 | 0f8a249a | blueswir1 | } |
4584 | 0f8a249a | blueswir1 | break;
|
4585 | cf495bcf | bellard | } |
4586 | cf495bcf | bellard | /* default case for non jump instructions */
|
4587 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4588 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4589 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4590 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4591 | 72cbca10 | bellard | /* we can do a static jump */
|
4592 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4593 | 72cbca10 | bellard | dc->is_br = 1;
|
4594 | 72cbca10 | bellard | } else {
|
4595 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4596 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4597 | cf495bcf | bellard | } |
4598 | e80cfcfc | bellard | jmp_insn:
|
4599 | cf495bcf | bellard | return;
|
4600 | cf495bcf | bellard | illegal_insn:
|
4601 | 2ea815ca | blueswir1 | { |
4602 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4603 | 2ea815ca | blueswir1 | |
4604 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4605 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4606 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4607 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4608 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4609 | 2ea815ca | blueswir1 | } |
4610 | e8af50a3 | bellard | return;
|
4611 | 64a88d5d | blueswir1 | unimp_flush:
|
4612 | 2ea815ca | blueswir1 | { |
4613 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4614 | 2ea815ca | blueswir1 | |
4615 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4616 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4617 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4618 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4619 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4620 | 2ea815ca | blueswir1 | } |
4621 | 64a88d5d | blueswir1 | return;
|
4622 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4623 | e8af50a3 | bellard | priv_insn:
|
4624 | 2ea815ca | blueswir1 | { |
4625 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4626 | 2ea815ca | blueswir1 | |
4627 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4628 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4629 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4630 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4631 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4632 | 2ea815ca | blueswir1 | } |
4633 | e80cfcfc | bellard | return;
|
4634 | 64a88d5d | blueswir1 | #endif
|
4635 | e80cfcfc | bellard | nfpu_insn:
|
4636 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4637 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4638 | e80cfcfc | bellard | dc->is_br = 1;
|
4639 | fcc72045 | blueswir1 | return;
|
4640 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4641 | 9143e598 | blueswir1 | nfq_insn:
|
4642 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4643 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4644 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4645 | 9143e598 | blueswir1 | return;
|
4646 | 9143e598 | blueswir1 | #endif
|
4647 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4648 | fcc72045 | blueswir1 | ncp_insn:
|
4649 | 2ea815ca | blueswir1 | { |
4650 | 2ea815ca | blueswir1 | TCGv r_const; |
4651 | 2ea815ca | blueswir1 | |
4652 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4653 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4654 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4655 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4656 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4657 | 2ea815ca | blueswir1 | } |
4658 | fcc72045 | blueswir1 | return;
|
4659 | fcc72045 | blueswir1 | #endif
|
4660 | 7a3f1944 | bellard | } |
4661 | 7a3f1944 | bellard | |
4662 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4663 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4664 | 7a3f1944 | bellard | { |
4665 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4666 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4667 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4668 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
4669 | e8af50a3 | bellard | int j, lj = -1; |
4670 | 2e70f6ef | pbrook | int num_insns;
|
4671 | 2e70f6ef | pbrook | int max_insns;
|
4672 | cf495bcf | bellard | |
4673 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4674 | cf495bcf | bellard | dc->tb = tb; |
4675 | 72cbca10 | bellard | pc_start = tb->pc; |
4676 | cf495bcf | bellard | dc->pc = pc_start; |
4677 | e80cfcfc | bellard | last_pc = dc->pc; |
4678 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4679 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_DYNAMIC; |
4680 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4681 | 5578ceab | blueswir1 | dc->def = env->def; |
4682 | 5578ceab | blueswir1 | if ((dc->def->features & CPU_FEATURE_FLOAT))
|
4683 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4684 | 5578ceab | blueswir1 | else
|
4685 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4686 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4687 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4688 | 2cade6a3 | blueswir1 | #endif
|
4689 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4690 | cf495bcf | bellard | |
4691 | a7812ae4 | pbrook | cpu_tmp0 = tcg_temp_new(); |
4692 | a7812ae4 | pbrook | cpu_tmp32 = tcg_temp_new_i32(); |
4693 | a7812ae4 | pbrook | cpu_tmp64 = tcg_temp_new_i64(); |
4694 | d987963a | blueswir1 | |
4695 | a7812ae4 | pbrook | cpu_dst = tcg_temp_local_new(); |
4696 | d987963a | blueswir1 | |
4697 | d987963a | blueswir1 | // loads and stores
|
4698 | a7812ae4 | pbrook | cpu_val = tcg_temp_local_new(); |
4699 | a7812ae4 | pbrook | cpu_addr = tcg_temp_local_new(); |
4700 | 1a2fb1c0 | blueswir1 | |
4701 | 2e70f6ef | pbrook | num_insns = 0;
|
4702 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4703 | 2e70f6ef | pbrook | if (max_insns == 0) |
4704 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4705 | 2e70f6ef | pbrook | gen_icount_start(); |
4706 | cf495bcf | bellard | do {
|
4707 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
4708 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
4709 | a1d1bb31 | aliguori | if (bp->pc == dc->pc) {
|
4710 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4711 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4712 | a7812ae4 | pbrook | gen_helper_debug(); |
4713 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4714 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4715 | e80cfcfc | bellard | goto exit_gen_loop;
|
4716 | e8af50a3 | bellard | } |
4717 | e8af50a3 | bellard | } |
4718 | e8af50a3 | bellard | } |
4719 | e8af50a3 | bellard | if (spc) {
|
4720 | 93fcfe39 | aliguori | qemu_log("Search PC...\n");
|
4721 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4722 | e8af50a3 | bellard | if (lj < j) {
|
4723 | e8af50a3 | bellard | lj++; |
4724 | e8af50a3 | bellard | while (lj < j)
|
4725 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4726 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4727 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4728 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4729 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
4730 | e8af50a3 | bellard | } |
4731 | e8af50a3 | bellard | } |
4732 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4733 | 2e70f6ef | pbrook | gen_io_start(); |
4734 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4735 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4736 | 2e70f6ef | pbrook | num_insns++; |
4737 | 0f8a249a | blueswir1 | |
4738 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4739 | 0f8a249a | blueswir1 | break;
|
4740 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4741 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4742 | 0f8a249a | blueswir1 | break;
|
4743 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4744 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4745 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4746 | d39c0b99 | bellard | break;
|
4747 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4748 | e80cfcfc | bellard | generate an exception */
|
4749 | 1b530a6d | aurel32 | if (env->singlestep_enabled || singlestep) {
|
4750 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4751 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4752 | e80cfcfc | bellard | break;
|
4753 | e80cfcfc | bellard | } |
4754 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4755 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
4756 | 2e70f6ef | pbrook | num_insns < max_insns); |
4757 | e80cfcfc | bellard | |
4758 | e80cfcfc | bellard | exit_gen_loop:
|
4759 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
4760 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
4761 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
4762 | a7812ae4 | pbrook | tcg_temp_free_i64(cpu_tmp64); |
4763 | a7812ae4 | pbrook | tcg_temp_free_i32(cpu_tmp32); |
4764 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
4765 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
4766 | 2e70f6ef | pbrook | gen_io_end(); |
4767 | 72cbca10 | bellard | if (!dc->is_br) {
|
4768 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4769 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4770 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4771 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
4772 | 72cbca10 | bellard | } else {
|
4773 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4774 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4775 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
4776 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4777 | 72cbca10 | bellard | } |
4778 | 72cbca10 | bellard | } |
4779 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
4780 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4781 | e8af50a3 | bellard | if (spc) {
|
4782 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4783 | e8af50a3 | bellard | lj++; |
4784 | e8af50a3 | bellard | while (lj <= j)
|
4785 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4786 | e8af50a3 | bellard | #if 0
|
4787 | 93fcfe39 | aliguori | log_page_dump();
|
4788 | e8af50a3 | bellard | #endif
|
4789 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4790 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4791 | e8af50a3 | bellard | } else {
|
4792 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4793 | 2e70f6ef | pbrook | tb->icount = num_insns; |
4794 | e8af50a3 | bellard | } |
4795 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4796 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
4797 | 93fcfe39 | aliguori | qemu_log("--------------\n");
|
4798 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
4799 | 93fcfe39 | aliguori | log_target_disas(pc_start, last_pc + 4 - pc_start, 0); |
4800 | 93fcfe39 | aliguori | qemu_log("\n");
|
4801 | cf495bcf | bellard | } |
4802 | 7a3f1944 | bellard | #endif
|
4803 | 7a3f1944 | bellard | } |
4804 | 7a3f1944 | bellard | |
4805 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4806 | 7a3f1944 | bellard | { |
4807 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
4808 | 7a3f1944 | bellard | } |
4809 | 7a3f1944 | bellard | |
4810 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4811 | 7a3f1944 | bellard | { |
4812 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
4813 | 7a3f1944 | bellard | } |
4814 | 7a3f1944 | bellard | |
4815 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
4816 | e80cfcfc | bellard | { |
4817 | f5069b26 | blueswir1 | unsigned int i; |
4818 | c48fcb47 | blueswir1 | static int inited; |
4819 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4820 | f5069b26 | blueswir1 | NULL, // g0 not used |
4821 | f5069b26 | blueswir1 | "g1",
|
4822 | f5069b26 | blueswir1 | "g2",
|
4823 | f5069b26 | blueswir1 | "g3",
|
4824 | f5069b26 | blueswir1 | "g4",
|
4825 | f5069b26 | blueswir1 | "g5",
|
4826 | f5069b26 | blueswir1 | "g6",
|
4827 | f5069b26 | blueswir1 | "g7",
|
4828 | f5069b26 | blueswir1 | }; |
4829 | 714547bb | blueswir1 | static const char * const fregnames[64] = { |
4830 | 714547bb | blueswir1 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
4831 | 714547bb | blueswir1 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
4832 | 714547bb | blueswir1 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
4833 | 714547bb | blueswir1 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
4834 | 714547bb | blueswir1 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
4835 | 714547bb | blueswir1 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
4836 | 714547bb | blueswir1 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
4837 | 714547bb | blueswir1 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
4838 | 714547bb | blueswir1 | }; |
4839 | aaed909a | bellard | |
4840 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4841 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4842 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4843 | 1a2fb1c0 | blueswir1 | |
4844 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
4845 | a7812ae4 | pbrook | cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, |
4846 | a7812ae4 | pbrook | offsetof(CPUState, regwptr), |
4847 | a7812ae4 | pbrook | "regwptr");
|
4848 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4849 | a7812ae4 | pbrook | cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc), |
4850 | a7812ae4 | pbrook | "xcc");
|
4851 | a7812ae4 | pbrook | cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi), |
4852 | a7812ae4 | pbrook | "asi");
|
4853 | a7812ae4 | pbrook | cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs), |
4854 | a7812ae4 | pbrook | "fprs");
|
4855 | a7812ae4 | pbrook | cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr), |
4856 | 255e1fcb | blueswir1 | "gsr");
|
4857 | a7812ae4 | pbrook | cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4858 | 255e1fcb | blueswir1 | offsetof(CPUState, tick_cmpr), |
4859 | 255e1fcb | blueswir1 | "tick_cmpr");
|
4860 | a7812ae4 | pbrook | cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4861 | 255e1fcb | blueswir1 | offsetof(CPUState, stick_cmpr), |
4862 | 255e1fcb | blueswir1 | "stick_cmpr");
|
4863 | a7812ae4 | pbrook | cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4864 | 255e1fcb | blueswir1 | offsetof(CPUState, hstick_cmpr), |
4865 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
4866 | a7812ae4 | pbrook | cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp), |
4867 | 255e1fcb | blueswir1 | "hintp");
|
4868 | a7812ae4 | pbrook | cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba), |
4869 | a7812ae4 | pbrook | "htba");
|
4870 | a7812ae4 | pbrook | cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver), |
4871 | a7812ae4 | pbrook | "hver");
|
4872 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new(TCG_AREG0, |
4873 | 255e1fcb | blueswir1 | offsetof(CPUState, ssr), "ssr");
|
4874 | a7812ae4 | pbrook | cpu_ver = tcg_global_mem_new(TCG_AREG0, |
4875 | 255e1fcb | blueswir1 | offsetof(CPUState, version), "ver");
|
4876 | a7812ae4 | pbrook | cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, |
4877 | a7812ae4 | pbrook | offsetof(CPUState, softint), |
4878 | a7812ae4 | pbrook | "softint");
|
4879 | 255e1fcb | blueswir1 | #else
|
4880 | a7812ae4 | pbrook | cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), |
4881 | 255e1fcb | blueswir1 | "wim");
|
4882 | 1a2fb1c0 | blueswir1 | #endif
|
4883 | a7812ae4 | pbrook | cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), |
4884 | 77f193da | blueswir1 | "cond");
|
4885 | a7812ae4 | pbrook | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), |
4886 | dc99a3f2 | blueswir1 | "cc_src");
|
4887 | a7812ae4 | pbrook | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, |
4888 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4889 | d9bdab86 | blueswir1 | "cc_src2");
|
4890 | a7812ae4 | pbrook | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), |
4891 | dc99a3f2 | blueswir1 | "cc_dst");
|
4892 | 8393617c | Blue Swirl | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), |
4893 | 8393617c | Blue Swirl | "cc_op");
|
4894 | a7812ae4 | pbrook | cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr), |
4895 | a7812ae4 | pbrook | "psr");
|
4896 | a7812ae4 | pbrook | cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr), |
4897 | 87e92502 | blueswir1 | "fsr");
|
4898 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc), |
4899 | 48d5c82b | blueswir1 | "pc");
|
4900 | a7812ae4 | pbrook | cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc), |
4901 | a7812ae4 | pbrook | "npc");
|
4902 | a7812ae4 | pbrook | cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
|
4903 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
4904 | a7812ae4 | pbrook | cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr), |
4905 | 255e1fcb | blueswir1 | "tbr");
|
4906 | 255e1fcb | blueswir1 | #endif
|
4907 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
4908 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, |
4909 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
4910 | f5069b26 | blueswir1 | gregnames[i]); |
4911 | 714547bb | blueswir1 | for (i = 0; i < TARGET_FPREGS; i++) |
4912 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, |
4913 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), |
4914 | a7812ae4 | pbrook | fregnames[i]); |
4915 | 714547bb | blueswir1 | |
4916 | c9e03d8f | blueswir1 | /* register helpers */
|
4917 | c9e03d8f | blueswir1 | |
4918 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
4919 | c9e03d8f | blueswir1 | #include "helper.h" |
4920 | 1a2fb1c0 | blueswir1 | } |
4921 | 658138bc | bellard | } |
4922 | d2856f1a | aurel32 | |
4923 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
4924 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
4925 | d2856f1a | aurel32 | { |
4926 | d2856f1a | aurel32 | target_ulong npc; |
4927 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
4928 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
4929 | d2856f1a | aurel32 | if (npc == 1) { |
4930 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
4931 | d2856f1a | aurel32 | } else if (npc == 2) { |
4932 | d2856f1a | aurel32 | target_ulong t2 = (target_ulong)(unsigned long)puc; |
4933 | d2856f1a | aurel32 | /* jump PC: use T2 and the jump targets of the translation */
|
4934 | d2856f1a | aurel32 | if (t2)
|
4935 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
4936 | d2856f1a | aurel32 | else
|
4937 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
4938 | d2856f1a | aurel32 | } else {
|
4939 | d2856f1a | aurel32 | env->npc = npc; |
4940 | d2856f1a | aurel32 | } |
4941 | 14ed7adc | Igor Kovalenko | |
4942 | 14ed7adc | Igor Kovalenko | /* flush pending conditional evaluations before exposing cpu state */
|
4943 | 14ed7adc | Igor Kovalenko | if (CC_OP != CC_OP_FLAGS) {
|
4944 | 14ed7adc | Igor Kovalenko | helper_compute_psr(); |
4945 | 14ed7adc | Igor Kovalenko | } |
4946 | d2856f1a | aurel32 | } |