Revision 3c9a8f17

b/tcg/mips/tcg-target.c
1423 1423 
        tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
1424 1424 
        tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);
1425 1425 
        break;
1426 
    case INDEX_op_mulsh_i32:
1427 
        tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]);
1428 
        tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
1429 
        break;
1430 
    case INDEX_op_muluh_i32:
1431 
        tcg_out_opc_reg(s, OPC_MULTU, 0, args[1], args[2]);
1432 
        tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
1433 
        break;
1426 1434 
    case INDEX_op_div_i32:
1427 1435 
        tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]);
1428 1436 
        tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
......
1602 1610 
    { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
1603 1611 
    { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
1604 1612 
    { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
1613 
    { INDEX_op_mulsh_i32, { "r", "rZ", "rZ" } },
1614 
    { INDEX_op_muluh_i32, { "r", "rZ", "rZ" } },
1605 1615 
    { INDEX_op_div_i32, { "r", "rZ", "rZ" } },
1606 1616 
    { INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
1607 1617 
    { INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
b/tcg/mips/tcg-target.h
89 89 
#define TCG_TARGET_HAS_eqv_i32          0
90 90 
#define TCG_TARGET_HAS_nand_i32         0
91 91 
#define TCG_TARGET_HAS_muls2_i32        1
92 
#define TCG_TARGET_HAS_muluh_i32        0
93 
#define TCG_TARGET_HAS_mulsh_i32        0
92 
#define TCG_TARGET_HAS_muluh_i32        1
93 
#define TCG_TARGET_HAS_mulsh_i32        1
94 94 

  		





  95
  95
  
    
/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */


  		





  96
  96
  
    
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \


  		












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