root / target-ppc / cpu.h @ 3cc62370
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/*
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* PPC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#define TARGET_LONG_BITS 32 |
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#include "cpu-defs.h" |
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#include "config.h" |
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#include <setjmp.h> |
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/* Instruction types */
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enum {
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PPC_NONE = 0x0000,
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PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */ |
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PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */ |
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PPC_FLOW = 0x0004, /* CPU has flow control instructions */ |
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PPC_MEM = 0x0008, /* CPU has virtual memory instructions */ |
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PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */ |
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PPC_CACHE = 0x0020, /* CPU has cache control instructions */ |
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PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */ |
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PPC_EXTERN = 0x0080, /* CPU has external control instructions */ |
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PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */ |
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PPC_CACHE_OPT= 0x0200,
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PPC_FLOAT_OPT= 0x0400,
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PPC_MEM_OPT = 0x0800,
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}; |
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#define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT) |
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/* PPC 604 */
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#define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT \ |
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PPC_MEM_OPT) |
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/* PPC 740/745/750/755 (aka G3) has external access instructions */
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#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT) |
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typedef struct ppc_tb_t ppc_tb_t; |
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/* Supervisor mode registers */
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/* Machine state register */
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#define MSR_POW 18 |
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#define MSR_ILE 16 |
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#define MSR_EE 15 |
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#define MSR_PR 14 |
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#define MSR_FP 13 |
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#define MSR_ME 12 |
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#define MSR_FE0 11 |
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#define MSR_SE 10 |
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#define MSR_BE 9 |
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#define MSR_FE1 8 |
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#define MSR_IP 6 |
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#define MSR_IR 5 |
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#define MSR_DR 4 |
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#define MSR_RI 1 |
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#define MSR_LE 0 |
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#define msr_pow env->msr[MSR_POW]
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#define msr_ile env->msr[MSR_ILE]
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#define msr_ee env->msr[MSR_EE]
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#define msr_pr env->msr[MSR_PR]
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#define msr_fp env->msr[MSR_FP]
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#define msr_me env->msr[MSR_ME]
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#define msr_fe0 env->msr[MSR_FE0]
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#define msr_se env->msr[MSR_SE]
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#define msr_be env->msr[MSR_BE]
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#define msr_fe1 env->msr[MSR_FE1]
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#define msr_ip env->msr[MSR_IP]
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#define msr_ir env->msr[MSR_IR]
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#define msr_dr env->msr[MSR_DR]
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#define msr_ri env->msr[MSR_RI]
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#define msr_le env->msr[MSR_LE]
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/* Segment registers */
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typedef struct CPUPPCState { |
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/* general purpose registers */
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uint32_t gpr[32];
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/* floating point registers */
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double fpr[32]; |
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/* segment registers */
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uint32_t sdr1; |
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uint32_t sr[16];
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/* XER */
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uint8_t xer[4];
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/* Reservation address */
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uint32_t reserve; |
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/* machine state register */
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uint8_t msr[32];
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/* condition register */
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uint8_t crf[8];
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/* floating point status and control register */
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uint8_t fpscr[8];
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uint32_t nip; |
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/* special purpose registers */
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uint32_t lr; |
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uint32_t ctr; |
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/* BATs */
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uint32_t DBAT[2][8]; |
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uint32_t IBAT[2][8]; |
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/* all others */
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uint32_t spr[1024];
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/* qemu dedicated */
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/* temporary float registers */
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double ft0;
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double ft1;
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double ft2;
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int interrupt_request;
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jmp_buf jmp_env; |
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int exception_index;
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int error_code;
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int access_type; /* when a memory exception occurs, the access |
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type is stored here */
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int user_mode_only; /* user mode only simulation */ |
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struct TranslationBlock *current_tb; /* currently executing TB */ |
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/* soft mmu support */
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/* in order to avoid passing too many arguments to the memory
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write helpers, we store some rarely used information in the CPU
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context) */
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unsigned long mem_write_pc; /* host pc at which the memory was |
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written */
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unsigned long mem_write_vaddr; /* target virtual addr at which the |
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memory was written */
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/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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/* ice debug support */
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uint32_t breakpoints[MAX_BREAKPOINTS]; |
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int nb_breakpoints;
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int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
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/* Time base and decrementer */
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ppc_tb_t *tb_env; |
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/* Power management */
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int power_mode;
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/* user data */
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void *opaque;
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} CPUPPCState; |
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CPUPPCState *cpu_ppc_init(void);
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int cpu_ppc_exec(CPUPPCState *s);
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void cpu_ppc_close(CPUPPCState *s);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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struct siginfo;
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int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
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void *puc);
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void do_interrupt (CPUPPCState *env);
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void cpu_loop_exit(void); |
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void dump_stack (CPUPPCState *env);
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uint32_t _load_xer (CPUPPCState *env); |
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void _store_xer (CPUPPCState *env, uint32_t value);
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uint32_t _load_msr (CPUPPCState *env); |
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void _store_msr (CPUPPCState *env, uint32_t value);
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int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
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/* Time-base and decrementer management */
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#ifndef NO_CPU_IO_DEFS
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uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
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uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
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void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
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uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
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void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
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#endif
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#define TARGET_PAGE_BITS 12 |
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#include "cpu-all.h" |
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#define ugpr(n) (env->gpr[n])
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#define fprd(n) (env->fpr[n])
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#define fprs(n) ((float)env->fpr[n]) |
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#define fpru(n) ((uint32_t)env->fpr[n])
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#define fpri(n) ((int32_t)env->fpr[n])
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#define SPR_ENCODE(sprn) \
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(((sprn) >> 5) | (((sprn) & 0x1F) << 5)) |
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/* User mode SPR */
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#define spr(n) env->spr[n]
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#define XER_SO 31 |
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#define XER_OV 30 |
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#define XER_CA 29 |
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#define XER_BC 0 |
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#define xer_so env->xer[3] |
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#define xer_ov env->xer[2] |
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#define xer_ca env->xer[1] |
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#define xer_bc env->xer[0] |
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#define MQ SPR_ENCODE(0) |
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#define XER SPR_ENCODE(1) |
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#define RTCUR SPR_ENCODE(4) |
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#define RTCLR SPR_ENCODE(5) |
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#define LR SPR_ENCODE(8) |
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#define CTR SPR_ENCODE(9) |
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/* VEA mode SPR */
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#define V_TBL SPR_ENCODE(268) |
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#define V_TBU SPR_ENCODE(269) |
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/* supervisor mode SPR */
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#define DSISR SPR_ENCODE(18) |
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#define DAR SPR_ENCODE(19) |
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#define RTCUW SPR_ENCODE(20) |
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#define RTCLW SPR_ENCODE(21) |
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#define DECR SPR_ENCODE(22) |
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#define SDR1 SPR_ENCODE(25) |
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#define SRR0 SPR_ENCODE(26) |
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#define SRR1 SPR_ENCODE(27) |
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#define SPRG0 SPR_ENCODE(272) |
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#define SPRG1 SPR_ENCODE(273) |
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#define SPRG2 SPR_ENCODE(274) |
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#define SPRG3 SPR_ENCODE(275) |
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#define SPRG4 SPR_ENCODE(276) |
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#define SPRG5 SPR_ENCODE(277) |
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#define SPRG6 SPR_ENCODE(278) |
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#define SPRG7 SPR_ENCODE(279) |
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#define ASR SPR_ENCODE(280) |
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#define EAR SPR_ENCODE(282) |
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#define O_TBL SPR_ENCODE(284) |
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#define O_TBU SPR_ENCODE(285) |
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#define PVR SPR_ENCODE(287) |
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#define IBAT0U SPR_ENCODE(528) |
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#define IBAT0L SPR_ENCODE(529) |
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#define IBAT1U SPR_ENCODE(530) |
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#define IBAT1L SPR_ENCODE(531) |
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#define IBAT2U SPR_ENCODE(532) |
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#define IBAT2L SPR_ENCODE(533) |
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#define IBAT3U SPR_ENCODE(534) |
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#define IBAT3L SPR_ENCODE(535) |
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#define DBAT0U SPR_ENCODE(536) |
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#define DBAT0L SPR_ENCODE(537) |
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#define DBAT1U SPR_ENCODE(538) |
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#define DBAT1L SPR_ENCODE(539) |
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#define DBAT2U SPR_ENCODE(540) |
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#define DBAT2L SPR_ENCODE(541) |
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#define DBAT3U SPR_ENCODE(542) |
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#define DBAT3L SPR_ENCODE(543) |
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#define IBAT4U SPR_ENCODE(560) |
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#define IBAT4L SPR_ENCODE(561) |
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#define IBAT5U SPR_ENCODE(562) |
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#define IBAT5L SPR_ENCODE(563) |
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#define IBAT6U SPR_ENCODE(564) |
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#define IBAT6L SPR_ENCODE(565) |
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#define IBAT7U SPR_ENCODE(566) |
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#define IBAT7L SPR_ENCODE(567) |
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#define DBAT4U SPR_ENCODE(568) |
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#define DBAT4L SPR_ENCODE(569) |
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#define DBAT5U SPR_ENCODE(570) |
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#define DBAT5L SPR_ENCODE(571) |
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#define DBAT6U SPR_ENCODE(572) |
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#define DBAT6L SPR_ENCODE(573) |
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#define DBAT7U SPR_ENCODE(574) |
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#define DBAT7L SPR_ENCODE(575) |
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#define UMMCR0 SPR_ENCODE(936) |
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#define UPMC1 SPR_ENCODE(937) |
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#define UPMC2 SPR_ENCODE(938) |
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#define USIA SPR_ENCODE(939) |
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#define UMMCR1 SPR_ENCODE(940) |
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#define UPMC3 SPR_ENCODE(941) |
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#define UPMC4 SPR_ENCODE(942) |
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#define MMCR0 SPR_ENCODE(952) |
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#define PMC1 SPR_ENCODE(953) |
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#define PMC2 SPR_ENCODE(954) |
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#define SIA SPR_ENCODE(955) |
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#define MMCR1 SPR_ENCODE(956) |
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#define PMC3 SPR_ENCODE(957) |
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#define PMC4 SPR_ENCODE(958) |
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#define SDA SPR_ENCODE(959) |
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#define DMISS SPR_ENCODE(976) |
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#define DCMP SPR_ENCODE(977) |
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#define DHASH1 SPR_ENCODE(978) |
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#define DHASH2 SPR_ENCODE(979) |
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#define IMISS SPR_ENCODE(980) |
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#define ICMP SPR_ENCODE(981) |
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#define RPA SPR_ENCODE(982) |
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#define TCR SPR_ENCODE(984) |
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#define IBR SPR_ENCODE(986) |
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#define ESASRR SPR_ENCODE(987) |
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#define SEBR SPR_ENCODE(990) |
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#define SER SPR_ENCODE(991) |
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#define HID0 SPR_ENCODE(1008) |
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#define HID1 SPR_ENCODE(1009) |
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#define IABR SPR_ENCODE(1010) |
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#define HID2 SPR_ENCODE(1011) |
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#define DABR SPR_ENCODE(1013) |
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#define L2PM SPR_ENCODE(1016) |
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#define L2CR SPR_ENCODE(1017) |
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#define ICTC SPR_ENCODE(1019) |
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#define THRM1 SPR_ENCODE(1020) |
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#define THRM2 SPR_ENCODE(1021) |
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#define THRM3 SPR_ENCODE(1022) |
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#define SP SPR_ENCODE(1021) |
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#define SPR_LP SPR_ENCODE(1022) |
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#define DABR_MASK 0xFFFFFFF8 |
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#define FPECR SPR_ENCODE(1022) |
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#define PIR SPR_ENCODE(1023) |
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/* Memory access type :
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* may be needed for precise access rights control and precise exceptions.
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*/
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enum {
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/* 1 bit to define user level / supervisor access */
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ACCESS_USER = 0x00,
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ACCESS_SUPER = 0x01,
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/* Type of instruction that generated the access */
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ACCESS_CODE = 0x10, /* Code fetch access */ |
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ACCESS_INT = 0x20, /* Integer load/store access */ |
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ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
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ACCESS_RES = 0x40, /* load/store with reservation */ |
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ACCESS_EXT = 0x50, /* external access */ |
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ACCESS_CACHE = 0x60, /* Cache manipulation */ |
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}; |
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/*****************************************************************************/
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/* Exceptions */
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enum {
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EXCP_NONE = -1,
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/* PPC hardware exceptions : exception vector / 0x100 */
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EXCP_RESET = 0x01, /* System reset */ |
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EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
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EXCP_DSI = 0x03, /* Impossible memory access */ |
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EXCP_ISI = 0x04, /* Impossible instruction fetch */ |
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EXCP_EXTERNAL = 0x05, /* External interruption */ |
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EXCP_ALIGN = 0x06, /* Alignment exception */ |
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EXCP_PROGRAM = 0x07, /* Program exception */ |
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EXCP_NO_FP = 0x08, /* No floating point */ |
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EXCP_DECR = 0x09, /* Decrementer exception */ |
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EXCP_RESA = 0x0A, /* Implementation specific */ |
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EXCP_RESB = 0x0B, /* Implementation specific */ |
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EXCP_SYSCALL = 0x0C, /* System call */ |
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EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
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EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
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/* MPC740/745/750 & IBM 750 */
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EXCP_PERF = 0x0F, /* Performance monitor */ |
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EXCP_IABR = 0x13, /* Instruction address breakpoint */ |
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EXCP_SMI = 0x14, /* System management interrupt */ |
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EXCP_THRM = 0x15, /* Thermal management interrupt */ |
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/* MPC755 */
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EXCP_TLBMISS = 0x10, /* Instruction TLB miss */ |
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EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */ |
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EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */ |
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EXCP_PPC_MAX = 0x16,
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/* Qemu exception */
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EXCP_OFCALL = 0x20, /* Call open-firmware emulator */ |
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EXCP_RTASCALL = 0x21, /* Call RTAS emulator */ |
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/* Special cases where we want to stop translation */
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EXCP_MTMSR = 0x104, /* mtmsr instruction: */ |
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/* may change privilege level */
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EXCP_BRANCH = 0x108, /* branch instruction */ |
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EXCP_RFI = 0x10C, /* return from interrupt */ |
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EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
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}; |
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/* Error codes */
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enum {
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/* Exception subtypes for EXCP_DSI */
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EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */ |
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EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */ |
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EXCP_DSI_PROT = 0x03, /* Memory protection violation */ |
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EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */ |
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EXCP_DSI_DABR = 0x05, /* Data address breakpoint */ |
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/* flags for EXCP_DSI */
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EXCP_DSI_DIRECT = 0x10,
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EXCP_DSI_STORE = 0x20,
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EXCP_DSI_ECXW = 0x40,
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/* Exception subtypes for EXCP_ISI */
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EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */ |
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EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */ |
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EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */ |
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EXCP_ISI_PROT = 0x04, /* Memory protection violation */ |
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EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from * |
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* a direct store segment */
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/* Exception subtypes for EXCP_ALIGN */
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EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
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EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
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EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
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EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
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EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
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EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
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/* Exception subtypes for EXCP_PROGRAM */
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/* FP exceptions */
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EXCP_FP = 0x10,
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EXCP_FP_OX = 0x01, /* FP overflow */ |
| 407 |
EXCP_FP_UX = 0x02, /* FP underflow */ |
| 408 |
EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
| 409 |
EXCP_FP_XX = 0x04, /* FP inexact */ |
| 410 |
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
| 411 |
EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
| 412 |
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
| 413 |
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
| 414 |
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
| 415 |
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
| 416 |
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
| 417 |
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
| 418 |
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
| 419 |
/* Invalid instruction */
|
| 420 |
EXCP_INVAL = 0x20,
|
| 421 |
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
| 422 |
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
| 423 |
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
| 424 |
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
| 425 |
/* Privileged instruction */
|
| 426 |
EXCP_PRIV = 0x30,
|
| 427 |
EXCP_PRIV_OPC = 0x01,
|
| 428 |
EXCP_PRIV_REG = 0x02,
|
| 429 |
/* Trap */
|
| 430 |
EXCP_TRAP = 0x40,
|
| 431 |
}; |
| 432 |
|
| 433 |
/*****************************************************************************/
|
| 434 |
|
| 435 |
#endif /* !defined (__CPU_PPC_H__) */ |